memory

Abstract

Embodiments of the present application relate to the field of memories, and provide a memory, comprising a first chip, a second chip, a third chip and a fourth chip stacked in a first direction in sequence, wherein a logic circuit is formed on the first chip, a first memory array is formed on the second chip, a core area circuit is formed on the third chip, and a second memory array is formed on the fourth chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of memory, and in particular to a semiconductor memory. Background Art

[0002] Traditional memory chips are fabricated on a two-dimensional plane, with memory cells arranged on a single plane. However, with the increasing demand for higher capacity and smaller size memory, traditional two-dimensional planar memory technology faces physical and performance limitations.

[0003] To address these issues, three-dimensional memory technology has emerged. It achieves higher storage density by stacking multiple layers of memory cells vertically. This stacking structure can significantly increase the storage capacity of memory chips while keeping the chip size relatively small. Furthermore, 3D memory utilizes advanced manufacturing processes and materials to improve data transmission speed and energy efficiency.

[0004] Existing three-dimensional memories place all memory cells on one chip and all circuit structures on another chip. However, this design wastes area due to the drive capability requirements of the memory cells and the circuit layout requirements. Summary of the Invention

[0005] The embodiments of the present application provide a memory that at least helps to solve the problem of wasted storage array chip area in a three-dimensional memory.

[0006] According to some embodiments of the present application, on the one hand, an embodiment of the present application provides a memory, comprising a first chip, a second chip, a third chip and a fourth chip stacked in sequence along a first direction, wherein a logic circuit is formed on the first chip, a first memory array is formed on the second chip, a core area circuit is formed on the third chip, and a second memory array is formed on the fourth chip.

[0007] In some embodiments, the core circuit includes a sense amplifier.

[0008] In some embodiments, the sense amplifier is connected to the first memory array through a first bit line, and the sense amplifier is connected to the second memory array through a first complementary bit line.

[0009] In some embodiments, the sense amplifier has different driving capabilities for the first bit line and the first complementary bit line.

[0010] In some embodiments, the sense amplifier includes a first inverter and a second inverter connected end to end, and the first inverter and the second inverter have different driving capabilities.

[0011] In some embodiments, the core area circuit includes a sub-word line driver array, the sub-word line driver array includes a first sub-word line driver and a second sub-word line driver, the first sub-word line driver is connected to the first storage array through a first sub-word line, and the second sub-word line driver is connected to the second storage array through a second sub-word line.

[0012] In some embodiments, the first sub-word line driver and the second sub-word line driver have different driving capabilities.

[0013] In some embodiments, the core area circuit further includes a row decoder, a column decoder, and a low-dropout linear regulator.

[0014] In some embodiments, the core area circuit is arranged on the side of the third chip facing the fourth chip, and the electrical connection path between the core area circuit and the first chip includes: a through hole passing through the third chip, a hybrid bonding between the third chip and the second chip, a through hole passing through the second chip, and a hybrid bonding between the second chip and the first chip.

[0015] In some embodiments, the core area circuit is arranged on a side of the third chip facing the second chip, and the electrical connection path between the core area circuit and the first chip includes: hybrid bonding between the third chip and the second chip, a through hole passing through the second chip, and hybrid bonding between the second chip and the first chip.

[0016] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0017] Since the memory includes a first chip, a second chip, a third chip and a fourth chip stacked in sequence along a first direction, wherein a logic circuit is formed on the first chip, a first memory array is formed on the second chip, a core area circuit is formed on the third chip, and a second memory array is formed on the fourth chip, a four-layer chip stacking method of "memory array-core area circuit-memory array-logic circuit" is formed. Compared with the traditional "memory array-circuit" two-layer chip stacking structure, the present application places the core area circuit closely related to reading and writing memory array data information separately in an independent chip for driving or reading data information stored in the memory arrays on both sides thereof, and places the logic circuit of the peripheral area in a separate chip located on the other side. As a result, the memory array chip does not need to be provided with an invalid area corresponding to the peripheral area circuit, thereby achieving a memory array chip with nearly 100% utilization and a higher number of chips per wafer (die per wafer, DPW).

[0018] In addition, since the sense amplifier can sense and amplify the memory cells on the chips on both sides, it can solve the problem of edge memory array (edge ​​MAT) and improve the utilization of the memory array and the sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0020] Figure 1 A schematic diagram of the layout of a two-layer chip stacking structure;

[0021] Figure 2 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram of a detailed layout of a memory provided in an embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of the connection relationship between a sense amplifier array and a memory array provided in an embodiment of the present disclosure;

[0024] Figure 5 A schematic structural diagram of an asymmetric sense amplifier provided in an embodiment of the present disclosure;

[0025] Figure 6 A schematic diagram of the detailed layout of another memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways, all without departing from the spirit or scope of the present invention. For example, the exemplary embodiments provided herein are considered to be capable of being combined with each other in whole or in part to achieve this. Specifically, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless a contrary or contradictory description is provided therein.

[0027] Throughout this specification, when any part is referred to as being “connected” to another part, this includes both the case where the part and the other part are “indirectly connected” to each other due to another part being interposed therebetween, and the case where the part and the other part are “directly connected” to each other. For example, it should be understood that when an element is referred to as being “connected” or “coupled” or “on” another element, it can be directly connected or coupled to or on the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as being “in contact with” or “in contact with” another element, there are no intervening elements at the point of contact.

[0028] Furthermore, "electrically connected" conceptually includes both physical connections and physical disconnections. It will be understood that when terms such as "first" and "second" are used to refer to an element, the element is not limited thereto. They may serve only to distinguish the element from other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

[0029] Figure 1 A schematic layout diagram of a two-layer chip stacking structure of "memory array-circuit" in the prior art is provided. In the structure of a three-dimensional memory, wafer-on-wafer (WoW) bonding technology is used to bond a chip having a memory array composed of memory cells and a chip having a circuit for performing data reading and writing operations on the memory array together by, for example, hybrid bonding, to achieve high-density storage. The charge information stored in the memory cells in the memory array chip requires the operation of circuits such as a sense amplifier (SA) and a sub-wordline driver (SWD) before it can be written and read. To ensure that the stored information can be read correctly and quickly, the sense amplifier and the sub-wordline driver circuit are placed directly above each memory pad (Memory Array Tile, MAT) in the memory array, that is, at the position corresponding to the memory pad on the circuit chip. Since the area of ​​the sense amplifier and the sub-wordline driver circuit is smaller than the area of ​​the corresponding memory pad, many fragmented blank areas (such as ) will be left on the circuit chip after the sense amplifier and the sub-wordline driver circuit are arranged. Figure 1As shown). Due to its fragmented area, it is difficult to place a relatively complete circuit, resulting in this part of the area being wasted. The characteristic of the core area circuit on this circuit chip and the storage pad of the memory array chip being set one-to-one requires that the circuit chip of the three-dimensional memory also requires additional area for placing modules such as the row decoder (XDEC), column decoder (YDEC), memory body processing logic (Bank Logic) circuit and data channel (Channel) circuit. Therefore, in this "memory array-circuit" two-layer chip stacking structure, the area occupied by the circuit chip cannot be placed 100% above the storage pad. The memory array chip needs to reserve additional area to correspond to the area of ​​the row decoder, column decoder, memory body processing logic circuit and data channel circuit modules, resulting in waste of area of ​​the memory array chip and reduced wafer utilization.

[0030] Based on this, the present application provides a memory, comprising a first chip, a second chip, a third chip and a fourth chip stacked in sequence along a first direction, wherein a logic circuit is formed on the first chip, a first memory array is formed on the second chip, a core area circuit is formed on the third chip, and a second memory array is formed on the fourth chip, forming a four-layer chip stacking method of "memory array-core area circuit-memory array-logic circuit". Compared with the traditional "memory array-circuit" two-layer chip stacking structure, the present application places the core area circuit closely related to reading and writing memory array data information separately in an independent chip for driving or reading data information stored in the memory arrays on both sides thereof, and places the logic circuit of the peripheral area in a separate chip located on the other side. As a result, the memory array chip does not need to be provided with an invalid area corresponding to the peripheral area circuit, thereby achieving a memory array chip with nearly 100% utilization and a higher number of chips per wafer (die per wafer, DPW).

[0031] In addition, since the sense amplifier can sense and amplify the memory cells on the chips on both sides, it can solve the problem of edge memory array (edge ​​MAT) and improve the utilization of the memory array and the sense amplifier.

[0032] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0033] Figure 2 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure. Figure 2 A memory includes a first chip 100, a second chip 200, a third chip 300 and a fourth chip 400 stacked in sequence along a first direction Z, wherein a logic circuit is formed on the first chip 100, a first memory array is formed on the second chip, a core area circuit is formed on the third chip, and a second memory array is formed on the fourth chip.

[0034] Thus, a four-layer chip stack structure of "storage array-core area circuit-storage array-logic circuit" is formed. Compared with the traditional two-layer chip stack structure of "storage array-circuit", this embodiment places the core area circuit closely related to reading and writing storage array data information separately in an independent chip for driving or reading data information stored in the storage arrays on both sides, while placing the logic circuit of the peripheral area in a separate chip located on the other side. As a result, the storage array chip does not need to be provided with an inactive area corresponding to the peripheral area circuit, thereby achieving nearly 100% utilization of the storage array chip and improving wafer utilization.

[0035] Figure 2 In the embodiment, each of the first to fourth chips extends along the second direction X and the third direction Y. The first direction Z, the second direction X, and the third direction Y are perpendicular to each other.

[0036] In the following examples, dynamic random access memory (DRAM) is used as an example, but it should be understood that the present application is also applicable to other types of memory such as static random access memory (SRAM), magnetic random access memory (MRAM), phase change memory (PRAM), ferroelectric random access memory (FeRAM), flash memory (such as NAND Flash and Nor Flash), etc.

[0037] In some embodiments, Figure 2 The circuit details of each chip can be as follows Figure 3 Reference Figure 3The logic circuit formed on the first chip 100 includes a data channel circuit Channel and a memory bank logic circuit Bank Logic. The data channel circuit Channel includes circuits such as a data receiving circuit, a parallel-to-serial conversion circuit, a data driving circuit, a data sending circuit, and a control circuit. The memory bank logic circuit Bank Logic includes logic circuits for controlling each memory bank, such as a refresh-related control circuit and an error checking and correction circuit (ECC). The surface of the first chip 100 also has input and output pads PAD1 for signals such as data signals DQ, instruction address signals CA, and data selection signals DQS. It should be noted that PAD1 here only represents one type of pad, not just one pad. There can be multiple PAD1s. The surface of the first chip 100 also has input and output pads PAD2 for power supply signals. It should be understood that there can also be multiple PAD2s here, depending on the actual number required. For example, PAD2 can include pads for connecting power supplies for multiple high-level signals, and can also include pads for connecting power supplies for low-level signals.

[0038] Figure 3 In the embodiment of the present invention, the logic circuit is formed on the surface of the first chip 100 on the side close to the second chip 200, and a surface electrical connection circuit is also formed on the surface of the first chip 100 on the side close to the second chip 200, for electrically connecting the surface of the first chip 100 to other chips in the stacked structure. Through-hole vias (TSVs) are also formed in the first chip 100, and pads PAD1 and PAD2 are formed on the surface of the first chip 100 on the side away from the second chip 200. The through-hole vias (TSVs) are used to electrically connect the logic circuit on the surface of the first chip 100 to the pads PAD1 and PAD2 on the other side, thereby electrically leading out the logic circuit of the first chip 100 and the circuit electrically connected to the logic circuit of the first chip 100 through the pads PAD1 and PAD2.

[0039] The second chip 200 and the fourth chip 400 can be identical, and thus can be manufactured using the same process, reducing process complexity and saving process steps. In other embodiments, the second chip 200 and the fourth chip 400 can also adopt different structures to be compatible with different storage capacities and increase flexibility.

[0040] refer to Figure 3 , a memory array is formed on the second chip 200 and the fourth chip 400, Figure 3In the figure, Bottom Array represents the first storage array in the second chip 200, and Top Array represents the second storage array in the fourth chip 400. The storage array is composed of an array of storage cells. The storage pad MAT and the storage body Bank are both storage arrays. For DRAM, a storage cell can be composed of one transistor and one capacitor (1T1C). In other embodiments, the storage cell can also be composed of 2 transistors and 0 capacitors (2T0C), or one transistor and 0 capacitors (1T0C). This application does not make specific limitations for comparison.

[0041] refer to Figure 3 A capacitor Cap may also be formed in the memory array to serve as a power supply terminal for receiving and outputting power.

[0042] Continue to refer Figure 3 The core circuitry is formed on the third chip 300. The core circuitry may include a sense amplifier SA, a sub-wordline driver SWD, a row decoder XDEC, and a column decoder YDEC. Specifically, the core circuitry may include a sense amplifier array comprising multiple sense amplifiers, with each sense amplifier array corresponding one-to-one to the memory array. Considering the area ratio of the memory array to the sense amplifier, by placing the sense amplifiers on the third chip and amplifying the memory arrays on both sides, the memory array area on the second and fourth chips can be fully utilized.

[0043] Figure 4 This diagram illustrates the connection relationship between a sense amplifier array and a memory array according to an embodiment of the present disclosure. The third chip 300 is provided with sense amplifiers SA, which are arranged in an array. The sense amplifiers SA are connected to the first memory array (Bottom Array) on the second chip 200 via first bit lines BLa. The sense amplifiers SA are also connected to the second memory array (Top Array) on the fourth chip 400 via first complementary bit lines BLb.

[0044] Figure 4 In the embodiment, memory cells are arranged in an array of rows and columns. Each row of memory cells is driven by the same word line WL, and the memory cells in the same column are read by the same bit line BL. Each memory cell Cell includes, for example, a transistor and a capacitor structure.

[0045] The first bit line BLa and the first complementary bit line BLb are two bit lines whose charge differences are sensed and amplified by the same sense amplifier SA. Specifically, the memory cells in the first memory array are connected to the sense amplifier SA via the first bit line BLa, while the memory cells in the second memory array are connected to the same sense amplifier SA via the first complementary bit line BLb. When reading data stored in the memory cells in the first memory array, the charge on the first bit line BLa changes. The sense amplifier uses the voltage level on the first complementary bit line BLb as a reference value to detect the slight signal change on the first bit line BLa and amplify it to a readable level, thereby reading the data stored in the memory cells in the first memory array. Conversely, when reading data stored in the memory cells in the second memory array, the charge on the first complementary bit line BLb changes. The sense amplifier uses the voltage level on the first bit line BLa as a reference value to detect the slight signal change on the first complementary bit line BLb and amplify it to a readable level, thereby reading the data stored in the memory cells in the second memory array.

[0046] As a result, since the sense amplifiers can sense and amplify the memory cells on the second and fourth chips, and the second and fourth chips are located on either side of the sense amplifiers, forming a natural pairing, this can solve the problem of bit lines in the edge memory array (edge ​​MAT) not having corresponding complementary bit lines, thereby improving the utilization of the memory array and sense amplifiers. Furthermore, since the sense amplifier array is located between the second and fourth chips, the second chip and the third chip, as well as the third chip and the fourth chip, can use the same hybrid bonding method, improving the path matching between the sense amplifier and the second chip, and between the sense amplifier and the fourth chip, thereby reducing asymmetry.

[0047] In other embodiments, the sense amplifier SA may also sense and amplify charge differences only on two bit lines on the second chip 200 or two bit lines on the fourth chip 400. That is, the sense amplifier SA is connected to a memory cell on the second chip 200 via a first bit line and also to another memory cell on the second chip 400 via a first complementary bit line. Alternatively, the sense amplifier SA is connected to a memory cell on the fourth chip 400 via a first bit line and also to another memory cell on the fourth chip 400 via a first complementary bit line. When the storage capacities of the second chip 200 and the fourth chip 400 are unequal, some sense amplifiers SA may be connected to only one side of the chip, sensing and amplifying data only on that side. For example, if the storage capacity of the fourth chip 400 is greater than that of the second chip 200, for the portion with equal storage capacity, the sense amplifier SA is connected to the first bit line and the first complementary bit line from the second chip 200 and the fourth chip 400, respectively. For the portion of the fourth chip 400 that exceeds the storage capacity of the second chip 200, the sense amplifier is connected to both the first bit line and the first complementary bit line from the fourth chip 400.

[0048] In some embodiments, to further improve symmetry, the sense amplifier SA has different driving capabilities for the first bit line BLa and the first complementary bit line BLb.

[0049] exist Figure 3 In the example, the sense amplifier SA is formed on the side of the third chip 300 facing the fourth chip 400. For the convenience of description, the upper surface and the lower surface are described below. Figure 3The side of the third chip 300 facing the fourth chip 400 is the upper surface of the third chip 300, and the side of the third chip 300 facing the second chip 200 is the upper surface of the third chip 300. Since the third chip 300 has a certain thickness, the circuit on the upper surface needs to be electrically connected to the lower surface of the chip through the through-hole via TSV, so as to be electrically connected to the second chip 200 on the lower surface. That is, when the sense amplifier SA is formed on the upper surface of the chip, the sense amplifier SA can be directly connected to the second storage array Top Array on the upper surface through hybrid bonding, but the sense amplifier needs to be routed to the lower surface through the through-hole via TSV first, and then connected to the first storage array Bottom Array on the lower surface through hybrid bonding on the lower surface. In some embodiments, the sense amplifier SA also needs to be connected to the through-hole via TSV through the interconnect metal line layer on the upper surface before it can be connected to the lower surface through the through-hole via TSV. Since the first bit line BLa needs to pass through at least one additional layer of through-hole via TSV, a bit line load mismatch occurs between the bit line and the complementary bit line. Therefore, by providing an asymmetric sense amplifier, the sense amplifier has different driving capabilities for the first bit line BLa and the first complementary bit line BLb, so that the load mismatch between the bit line and the complementary bit line can be compensated as needed.

[0050] Figure 5 Schematic diagram of the structure of an asymmetric sense amplifier provided by an embodiment of the present disclosure. Figure 5 As shown, the sense amplifier includes a first inverter Inv1 and a second inverter Inv2 connected end to end. The first inverter Inv1 and the second inverter Inv2 have different driving capabilities. For example, the driving capability of the first inverter Inv1 can be weaker than that of the second inverter Inv2. The first inverter Inv1 with the weaker driving capability can be used to drive a bit line with a smaller load, while the second inverter Inv2 with the stronger driving capability can be used to drive a bit line with a larger load.

[0051] for Figure 3 In an embodiment, the sense amplifier SA is located on the top surface of the third chip 300 and requires connection to the first storage array Bottom Array through a through-hole via (TSV). The load on the first bit line BLa is greater than the load on the first complementary bit line BLb. Accordingly, the driving capability of the first inverter Inv1 is weaker than that of the second inverter Inv2. The first inverter Inv1 with the weaker driving capability is used to drive the first complementary bit line BLb with the smaller load, while the second inverter Inv2 with the stronger driving capability can drive the first bit line BLa with the larger load.

[0052] Figure 6 Another schematic diagram showing the detailed layout of a memory provided in an embodiment of the present disclosure. Figure 6In the embodiment, the sense amplifier SA is formed on the lower surface of the third chip 300. In the case where the sense amplifier SA is still required to be connected to the second memory array Top Array through a through-hole via (TSV), the load on the first complementary bit line BLb is greater than the load on the first bit line BLa. Accordingly, the driving capability of the first inverter Inv1 can be set to be stronger than the driving capability of the second inverter Inv2. The first inverter Inv1 with a stronger driving capability is used to drive the first complementary bit line BLb with a larger load, and the second inverter Inv2 with a weaker driving capability can be used to drive the first bit line BLa with a smaller load.

[0053] Therefore, through the asymmetric inverter design, bit lines with different loads can be driven to different degrees, thereby compensating for load mismatch, improving circuit symmetry, and facilitating correct sensing and amplification by the sense amplifier.

[0054] There are two types of through-hole vias: regular-sized through-hole vias (TSVs) and nano-sized through-hole vias (Nano-TSVs). Regular-sized through-hole vias are larger than nano-sized through-hole vias. In some embodiments, TSVs may cause bit line load mismatch, such as Figure 3 As shown, the through-hole vias (TSVs) on the third chip 300 may be fine TSVs to reduce the load caused by them and further reduce the bit line load mismatch.

[0055] In some embodiments, the drive capability of an asymmetric inverter can be designed using asymmetric transistors. An inverter with a stronger drive capability can be realized by having a larger W / L (width / length) ratio. In other embodiments, an asymmetric inverter can also be realized by having an asymmetric power supply voltage. An inverter with a stronger drive capability receives a higher power supply voltage VDD.

[0056] In other embodiments, asymmetric routing lengths may be used to match the loads on different bit lines. For example, for bit lines that do not include TSV loads, longer routing lengths may be used to increase the load to match the loads introduced by the TSVs.

[0057] In some embodiments, the core area circuit on the third chip 300 further includes a sub-word line driver array, which is formed by arranging a plurality of sub-word line drivers SWD. Figure 3 The sub-word line driver array includes a first sub-word line driver SWD1 and a second sub-word line driver SWD2. The first sub-word line driver SWD1 is connected to the first memory array Bottom Array through a first sub-word line WL1, and the second sub-word line driver SWD2 is connected to the second memory array Top Array through a second sub-word line WL2.

[0058] That is, different sub-word line drivers are used for the first memory array and the second memory array, so that the corresponding sub-word line drivers can be specifically adjusted and designed according to the positions of the first memory array and the second memory array, thereby flexibly controlling the reading and writing of the first memory array and the second memory array.

[0059] In some embodiments, the first sub-word line driver SWD1 and the second sub-word line driver SWD2 have different driving capabilities.

[0060] Specifically, for Figure 3 In this embodiment, the sub-wordline driver array, like the sense amplifier SA, is formed on the top surface of the third chip 300. The sub-wordline driver array also requires through-hole vias (TSVs) (or Nano-TSVs) to connect to the first memory array, the Bottom Array. The load on the first wordline WL1 is greater than that on the second wordline WL2. Therefore, the required driving capability of the first wordline WL1 is greater than that of the second wordline WL2. Therefore, the driving capability of the first sub-wordline driver SWD1 can be designed to be greater than that of the second sub-wordline driver SWD2, thereby balancing the read and write timings of the first and second memory arrays.

[0061] Figure 6 Another schematic diagram showing the detailed layout of a memory provided in an embodiment of the present disclosure. Figure 6 In the embodiment, the sub-wordline driver array, like the sense amplifier SA, is formed on the lower surface of the third chip 300. The sub-wordline driver array also requires through-hole vias (TSVs) (or Nano-TSVs) to connect to the second memory array, Top Array. The load on the first wordline WL1 is smaller than that on the second wordline WL2. Therefore, the required driving capability of the first wordline WL1 is smaller than that of the second wordline WL2. Therefore, the driving capability of the first sub-wordline driver SWD1 can be designed to be smaller than that of the second sub-wordline driver SWD2, thereby balancing the read and write timings of the first and second memory arrays.

[0062] The sub-wordline driver SWD can adopt the structure of a conventional sub-wordline driver SWD. The first sub-wordline driver SWD1 and the second sub-wordline driver SWD2 only need to be designed with different sizes or different power supply voltages to adjust their driving capabilities. The sub-wordline driver SWD with stronger driving capability is larger in size or receives a higher power supply voltage VDD.

[0063] Continue to refer Figure 3 and Figure 6, the core area circuit also includes a row decoder XDEC and a column decoder YDEC, and a low-voltage dropout linear regulator LDO. The row decoder XDEC is used to decode the row address and provide the row address for activating the first storage array and the second storage array. The column decoder YDEC is used to decode the column address and provide the column address for activating the first storage array and the second storage array. The low-voltage dropout linear regulator LDO steps down and removes the noise of the received external voltage to provide an internal power supply for the internal core area circuit. The low-voltage dropout linear regulator LDO is connected to the capacitor Cap on the second chip 200 and the fourth chip 400, and uses the capacitor Cap as a terminal to provide a power supply voltage for the second chip 200 and the fourth chip 400.

[0064] The core area circuit on the third chip 300 serves as an intermediate circuit between the logic circuit on the first chip 100 and the first and second storage arrays. The core area circuit is different from the logic circuit. The core area circuit transmits the power and signals sent by the logic circuit to the storage array, and transmits the data information read out from the storage array to the logic circuit.

[0065] Continue to refer Figure 3 The core area circuit is arranged on the side of the third chip 300 facing the fourth chip 400. The electrical connection path between the core area circuit and the first chip 100 includes: a through-hole Nano-TSV passing through the third chip 300, a hybrid bond between the third chip 300 and the second chip 200, a through-hole Nano-TSV passing through the second chip 200, and a hybrid bond between the second chip 200 and the first chip 100.

[0066] In some embodiments, the electrical connection path also includes a metal wiring layer on the chip surface. For example, the core area circuit is connected to the Nano-TSV through the third chip 300 via the metal wiring layer on the surface of the third chip 300. The Nano-TSV through the third chip 300 is connected to the metal wiring layer on the surface of the second chip via hybrid bonding on the back side. The metal wiring layer on the surface of the second chip is connected to the Nano-TSV through the second chip 200. The Nano-TSV through the second chip 200 is then connected to the front side of the first chip via hybrid bonding.

[0067] Thus, an electrical path is formed from the core area circuit of the third chip 300 to the lead pads PAD1 and PAD2 of the first chip 100, and data information stored in the first and second memory arrays is read out or data information is written into the first and second memory arrays.

[0068] Continue to refer Figure 6 In some other embodiments, the core area circuit is arranged on the side of the third chip 300 facing the second chip 200, and the electrical connection path between the core area circuit and the first chip 100 includes: a hybrid bond between the third chip 300 and the second chip 200, a through-hole Nano-TSV penetrating the second chip 200, and a hybrid bond between the second chip 200 and the first chip 100.

[0069] In some embodiments, the electrical connection path also includes a metal wiring layer on the chip surface. For example, the core area circuit is connected to the metal wiring layer on the second chip surface via a hybrid bond between the front surface of the third chip 300 and the second chip 200. The metal wiring layer on the second chip surface is connected to a through-hole via (Nano-TSV) penetrating the second chip 200. The through-hole via (Nano-TSV) penetrating the second chip 200 is then connected to the front surface of the first chip via a hybrid bond.

[0070] Thus, an electrical path is formed from the core area circuit of the third chip 300 to the lead pads PAD1 and PAD2 of the first chip 100, and the data information stored in the first memory array and the second memory array is read out, or the data information is written into the first memory array and the second memory array. Figure 6 In the embodiment of the present invention, the front side of the third chip 300 faces the second chip 200, and the signal transmission path between the core circuit and the logic circuit is shorter than that of the Figure 3 The embodiment of the present invention eliminates the need for Nano-TSVs, thereby reducing the electrical connection load from the core area circuit to the logic circuit, thereby achieving a better chip read and write delay.

[0071] See attached Figure 3 and Figure 6 There are two types of electrical connection paths: signal paths and power paths. Signal paths include undecoded row and column address information, test modes, read and write control signals, and more. Power paths include power control signals. This figure shows only one example; however, it is understood that the number of these signal paths can be customized based on actual needs.

[0072] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A memory, characterized in that: The device comprises a first chip, a second chip, a third chip, and a fourth chip stacked in sequence along a first direction, wherein the first chip has a logic circuit formed thereon, the second chip has a first memory array formed thereon, the third chip has a core area circuit formed thereon, and the fourth chip has a second memory array formed thereon; The core area circuit includes a sense amplifier; the sense amplifier is connected to the first storage array through a first bit line, and the sense amplifier is connected to the second storage array through a first complementary bit line.

2. The memory according to claim 1, wherein The sense amplifier has different driving capabilities for the first bit line and the first complementary bit line.

3. The memory according to claim 2, wherein: The sense amplifier includes a first inverter and a second inverter connected end to end, and the first inverter and the second inverter have different driving capabilities.

4. A memory, characterized in that: The invention comprises a first chip, a second chip, a third chip and a fourth chip stacked in sequence along a first direction, wherein the first chip is provided with a logic circuit, the second chip is provided with a first memory array, the third chip is provided with a core area circuit, and the fourth chip is provided with a second memory array. Among them, the core area circuit includes a sub-word line driver array, and the sub-word line driver array includes a first sub-word line driver and a second sub-word line driver. The first sub-word line driver is connected to the first storage array through a first sub-word line, and the second sub-word line driver is connected to the second storage array through a second sub-word line.

5. The memory according to claim 4, wherein: The first sub-word line driver and the second sub-word line driver have different driving capabilities.

6. The memory according to any one of claims 1 to 5, characterized in that The core area circuit further includes a row decoder, a column decoder, and a low voltage dropout linear regulator.

7. The memory according to any one of claims 1 to 5, characterized in that: The core area circuit is arranged on the side of the third chip facing the fourth chip, and the electrical connection path between the core area circuit and the first chip includes: a through hole passing through the third chip, a hybrid bonding between the third chip and the second chip, a through hole passing through the second chip, and a hybrid bonding between the second chip and the first chip.

8. The memory according to any one of claims 1 to 5, characterized in that: The core area circuit is set on the side of the third chip facing the second chip, and the electrical connection path between the core area circuit and the first chip includes: hybrid bonding between the third chip and the second chip, a through hole passing through the second chip, and hybrid bonding between the second chip and the first chip.

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