Method of forming a semiconductor structure

Abstract

The embodiment of the present application provides a forming method of a semiconductor structure, which comprises the following steps: providing a substrate, wherein a dielectric layer is formed on the substrate; forming an initial groove in the dielectric layer; performing at least one etching treatment on the dielectric layer exposed by the initial groove until a target groove with a set depth is formed in the dielectric layer; wherein each etching treatment comprises the following steps: forming a planarization coating with a mask opening on the dielectric layer, wherein the mask opening exposes the initial groove; taking the planarization coating as a mask, and removing the dielectric layer exposed by the initial groove in the depth direction by using a directional etching process. By using the technical scheme, the electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor technology, the performance requirements of semiconductor devices are getting higher and higher, the integration of semiconductor devices is getting higher and higher, and correspondingly, the size of individual devices is getting smaller and smaller.

[0003] Given that deep trench structures can expand the chip area vertically, they are widely used in various semiconductor devices to improve the integration density of semiconductor devices.

[0004] However, the electrical performance of currently developed semiconductor devices still needs improvement. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure and improve the electrical performance of the semiconductor structure.

[0006] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate on which a dielectric layer is formed; forming an initial trench within the dielectric layer; performing at least one etching process on the dielectric layer exposed by the initial trench until a target trench with a predetermined depth is formed within the dielectric layer; wherein any one etching process comprises: forming a planarization coating with a mask opening on the dielectric layer, the mask opening exposing the initial trench; and using the planarization coating as a mask, employing a directional etching process to remove the dielectric layer exposed along the depth direction of the initial trench.

[0007] Optionally, the directional etching process includes a gas etching process;

[0008] During the process of removing the dielectric layer exposed along the depth direction of the initial trench using the gas etching process, the polymer remaining on the sidewall of the initial trench serves as an etching barrier layer.

[0009] Optionally, the etching gas in the gas etching process includes C4F8, CHF3, Ar and O2; the etching power is 2200 to 2600 W; the etching time is 700 to 900 s; and the pressure is 200 mT to 250 mT.

[0010] Optionally, the step of forming a planarization coating with mask openings on the dielectric layer includes:

[0011] A planarization coating is formed on the dielectric layer, the planarization coating filling the initial trench;

[0012] A first barrier layer with a first opening is formed on the planarization coating, the first opening exposing the top of the planarization coating, and the position of the first opening is opposite to the position of the initial trench;

[0013] Along the sidewall of the first barrier layer, the planarization coating exposed by the first opening is removed, and the mask opening is formed within the planarization coating.

[0014] Optionally, the material of the planarization coating includes at least one of SiON, Si3N4, SiC, SOC, and TiO2;

[0015] The material of the first barrier layer includes at least one of photoresist and titanium nitride.

[0016] Optionally, the method for forming the semiconductor structure further includes:

[0017] Prior to the step of forming a first barrier layer with a first opening on the planarization coating, a protective layer is formed on the planarization coating; wherein the first barrier layer is located above the protective layer, and the first opening exposes the top of the protective layer;

[0018] In the step of removing the planarization coating exposed by the first opening along the sidewall of the first barrier layer, the protective layer exposed by the first opening is also removed.

[0019] Optionally, a low-temperature oxidation process is used to form the protective layer on the planarization coating.

[0020] Optionally, a dry etching process is used to remove the protective layer exposed by the first opening, as well as the planarization coating located below the protective layer.

[0021] Optionally, the material of the protective layer includes silicon oxide.

[0022] Optionally, any of the etching processes further includes:

[0023] After removing the dielectric layer exposed along the depth direction of the initial trench using a directional etching process, the planarization coating on the dielectric layer is removed.

[0024] Optionally, an ashing process is used to remove the planarization coating on the dielectric layer.

[0025] Optionally, the step of forming the initial trench within the dielectric layer includes:

[0026] A second barrier layer with a second opening is formed on the dielectric layer, the second opening exposing the top of the dielectric layer;

[0027] Along the sidewall of the second barrier layer, a portion of the dielectric layer exposed by the second opening is removed to form the initial trench within the dielectric layer.

[0028] Optionally, the set depth is greater than 10 micrometers.

[0029] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0030] In the semiconductor structure formation method provided by this invention, an initial trench is formed within a dielectric layer. By performing at least one etching process on the dielectric layer exposed by the initial trench, a target trench with a set depth can be formed within the dielectric layer. For any etching process, when using a planarization coating as a mask and employing a directional etching process, the dielectric layer exposed along the depth direction of the initial trench can be removed, reducing damage to the sidewalls of the initial trench, improving the flatness of the sidewalls of the target trench, and reducing or avoiding the probability of subsequent void formation, thereby improving the electrical performance of the semiconductor structure. Attached Figure Description

[0031] Figures 1 to 8 This is a schematic diagram of the structure corresponding to each step of a semiconductor structure. Detailed Implementation

[0032] The performance of current semiconductor structures needs improvement. This is because isotropic etching is used when forming deep trench structures. During the etching of the dielectric layer along the depth direction, the sidewalls of the dielectric layer are also etched, causing scalping on the sidewalls and creating edge-wall ripples. Currently, these edge-wall ripples can create surface roughness exceeding 100 nm. This will create voids when filling the deep trench structure later, thus reducing the electrical performance of the semiconductor structure.

[0033] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate on which a dielectric layer is formed; forming an initial trench within the dielectric layer; performing at least one etching process on the dielectric layer exposed by the initial trench until a target trench with a predetermined depth is formed within the dielectric layer; wherein any one etching process comprises: forming a planarization coating with a mask opening on the dielectric layer, the mask opening exposing the initial trench; and using the planarization coating as a mask, employing a directional etching process to remove the dielectric layer exposed along the depth direction of the initial trench.

[0034] By adopting the above scheme, for any etching process, when using a planarization coating as a mask and employing a directional etching process, the dielectric layer exposed along the depth direction of the initial trench can be removed, the damage to the sidewalls of the initial trench can be reduced, the flatness of the sidewalls of the target trench can be improved, and the probability of subsequent hole generation can be reduced or avoided, thereby improving the electrical performance of the semiconductor structure.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0036] See Figure 1 A substrate 100 is provided, on which a dielectric layer 102 is formed.

[0037] In this embodiment, the substrate 100 can provide the basis for the process operation of forming a semiconductor structure. The semiconductor structure may include complementary metal-oxide-semiconductor (CMOS), integrated circuit (IC), microelectromechanical system (MEMS), any other electronic component, or a combination of electronic components.

[0038] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0039] In some embodiments, the substrate may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate exposed by the fins, the isolation structure covering a portion of the sidewalls of the fins, and the top of the isolation structure being lower than the top of the fins.

[0040] In this embodiment, the isolation structure serves to electrically isolate adjacent fins.

[0041] In some embodiments, the material of the isolation structure can be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.

[0042] In this embodiment, the material of the isolation structure can be silicon oxide.

[0043] The dielectric layer 102 can provide spatial location for the initial trench and target trench that are subsequently formed.

[0044] In this embodiment, a chemical vapor deposition process can be used to form a dielectric layer 102 on the substrate 100.

[0045] In this embodiment, the material of the dielectric layer 102 may include low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0046] In one specific embodiment, the material of the dielectric layer 102 may include silicon oxide.

[0047] See Figure 2 and Figure 3 An initial trench 106 is formed within the dielectric layer 102.

[0048] The initial trench 106 is used to provide a process window for forming the target trench.

[0049] In this embodiment, the step of forming the initial trench 106 in the dielectric layer 102 includes:

[0050] See Figure 2 A second barrier layer 104 with a second opening K1 is formed on the dielectric layer 102, the second opening K1 being exposed at the top of the dielectric layer 102.

[0051] The second barrier layer 104 can protect the dielectric layer 102 and prevent damage to other parts of the dielectric layer 102 during the formation of the second opening K1.

[0052] In this embodiment, a second barrier layer 104 with a second opening K1 is formed using a photolithography process.

[0053] Specifically, a second barrier material layer (not shown) is formed on the dielectric layer 102, a photoresist with patterned openings (not shown) is formed on the second barrier material layer, and the second barrier material layer is patterned to form a second barrier layer 104.

[0054] In this embodiment, chemical vapor deposition (e.g., plasma-enhanced PECVD, ion beam deposition (IBD), sputtering, etc.) is used to deposit and form the second barrier material layer.

[0055] In this embodiment, the material of the second barrier layer 104 may include at least one of photoresist, silicon nitride, titanium nitride, and titanium oxide.

[0056] In one specific embodiment, the material of the second barrier layer 104 includes photoresist. The photoresist may include positive photoresist or negative photoresist, and the present invention does not specifically limit it.

[0057] See Figure 3Along the sidewall of the second barrier layer 104, a portion of the thickness of the dielectric layer 102 exposed by the second opening K1 is removed, and an initial trench 106 is formed in the dielectric layer 102. The initial trench 106 is formed by the bottom of the dielectric layer 102 and the sidewall of the dielectric layer 102.

[0058] In this embodiment, a dry etching method is used to remove the dielectric layer 102 of a portion of the thickness exposed by the second opening K1.

[0059] In this embodiment, the depth of the initial trench 106 should not be too large, otherwise it may affect the formation quality of the target trench. For example, if the depth of the initial trench 106 is too large, it means that the thickness of the removed dielectric layer 102 is too thick, which may damage the sidewalls of the dielectric layer 102, easily leading to poor smoothness of the sidewalls of the final target trench. If the depth of the initial trench 106 is too small, the time required to form the target trench will be too long. Therefore, in this embodiment, the depth of the initial trench 106 is 5 micrometers to 8 micrometers.

[0060] It should be noted that after the initial trench 106 is formed, the second barrier layer 104 is also removed; or, during the process of forming the initial trench 106, the second barrier layer 104 is also consumed (for example, when the material of the second barrier layer 104 is photoresist). When the initial trench 106 is formed, the second barrier layer 104 is completely consumed.

[0061] See Figures 4 to 8 At least one etching process is performed on the dielectric layer 102 exposed by the initial trench 106 until a target trench 120 with a set depth is formed in the dielectric layer 102; wherein any etching process includes: forming a planarization coating 108 with a mask opening K2 on the dielectric layer 102, the mask opening K2 exposing the initial trench 106; using the planarization coating 108 as a mask, a directional etching process is used to remove the dielectric layer 102 exposed along the depth direction of the initial trench 106.

[0062] In this embodiment of the invention, by performing at least one etching process on the dielectric layer 102 exposed in the initial trench 106, and by employing a directional etching process during the etching process, the dielectric layer 102 exposed in the depth direction of the initial trench 106 can be removed, thereby reducing damage to the sidewalls of the dielectric layer 102, improving the flatness of the sidewalls of the target trench, reducing or avoiding the probability of subsequent hole formation, and thus improving the electrical performance of the semiconductor structure.

[0063] The steps for forming the target trench 120 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0064] See Figures 4 to 6 The step of forming a planarization coating 108 with a mask opening K2 on the dielectric layer 102 includes:

[0065] See Figure 4 A planarization coating 108 is formed on the dielectric layer 102, and the planarization coating 108 fills the initial trench 106.

[0066] The planarization coating 108 can be used as a mask to remove the dielectric layer 102 exposed by the initial trench 106 to form a deeper trench.

[0067] In this embodiment, a chemical vapor deposition process is used to form a planarization coating 108 on the dielectric layer 102 that fills the initial trench 106.

[0068] In this embodiment, the planarization coating 108 may include a bottom anti-reflective layer Barc, and the material of the bottom anti-reflective layer may include at least one of SiON, Si3N4, SiC, SOC and TiO2.

[0069] See Figure 5 A first barrier layer 112 with a first opening K3 is formed on the planarization coating 108. The first opening K3 exposes the top of the planarization coating 108, and the position of the first opening K3 is opposite to the position of the initial trench 106.

[0070] The first barrier layer 112 can protect the planarization coating 108 and prevent damage to other parts of the planarization coating 108 during the formation of the first opening K3.

[0071] In this embodiment, a first barrier layer 112 with a first opening K3 is formed using a photolithography process.

[0072] Specifically, a first barrier material layer (not shown) is formed on the planarization coating 108, a photoresist (not shown) is formed on the first barrier material layer, and the first barrier material layer is patterned to form a first barrier layer 112 with a first opening K3.

[0073] In this embodiment, chemical vapor deposition (e.g., plasma-enhanced PECVD, ion beam deposition (IBD), sputtering, etc.) is used to form the first barrier material layer.

[0074] In this embodiment, the material of the first barrier layer 112 includes at least one of photoresist, silicon nitride, titanium nitride, and titanium oxide.

[0075] In one specific embodiment, the material of the first barrier layer 112 includes photoresist. The photoresist may include positive photoresist or negative photoresist, and the present invention does not specifically limit it.

[0076] In this embodiment, the width of the first opening K3 parallel to the surface of the substrate 100 is the same as the width of the initial trench 106 parallel to the surface of the substrate 100, and the sidewall of the first opening K3 is collinear with the sidewall of the initial trench 106 along the normal direction of the surface of the substrate 100.

[0077] See Figure 6 Along the sidewall of the first barrier layer 112, the planarization coating 108 exposed by the first opening K3 is removed, and a mask opening K2 is formed in the planarization coating 108.

[0078] The mask opening K2 provides a process window for removing the dielectric layer 102.

[0079] In this embodiment, a dry etching method is used to remove the planarization coating 108 exposed by the first opening K3. The etching gases used in the dry etching method include CF4, CHF3, Ar and O2; the etching power is 2200 to 2600 W; the etching time is 250 s to 350 s; and the pressure is 200 mT to 250 mT.

[0080] It should be noted that after the mask opening K2 is formed, the first barrier layer 112 can be removed; or, the first barrier layer 112 can be consumed during the process of forming the mask opening K2 (for example, when the material of the first barrier layer 112 is photoresist). When the mask opening K2 is formed, the first barrier layer 112 is completely consumed.

[0081] See next Figure 5 and Figure 6 Before the step of forming a first barrier layer 112 with a first opening K3 on the planarization coating 108, a protective layer 110 is formed on the planarization coating 108.

[0082] The protective layer 110 is used to protect the planarization coating 108 and prevent damage to the surface of the planarization coating 108 during the formation of the mask opening K2, as the first barrier layer 112 is consumed.

[0083] In this case, the first barrier layer 112 can be located above the protective layer 110, and the first opening K3 exposes the protective layer 110.

[0084] In this embodiment, a low-temperature oxidation process can be used to form a protective layer 110 on the planarization coating 108.

[0085] Accordingly, the material of the protective layer 110 may include silicon oxide. By selecting silicon oxide as the material of the protective layer 110, process compatibility can be improved and process risks can be reduced; moreover, compared with organic materials, silicon oxide materials have greater hardness and density, which is beneficial to improving the protective effect of the protective layer 110 on the surface of the planarization coating 108.

[0086] In one specific embodiment, the material of the protective layer 110 may include silicon oxide. Silicon oxide has good adhesion to the substrate 100, which is beneficial to improving the stability and processing effect of subsequent processes; moreover, silicon oxide is a commonly used silicon oxide in semiconductor processes, which can reduce the difficulty and process cost of forming the protective layer 110 and improve process compatibility.

[0087] In the step of removing the planarization coating 108 exposed by the first opening K3 along the sidewall of the first barrier layer 112, the protective layer 110 exposed by the first opening K3 is also removed.

[0088] That is, the protective layer 110 exposed by the first opening K3 is removed first, and then the planarization coating 108 below the protective layer 110 is removed. Correspondingly, the sidewall of the mask opening K2 may include the sidewall of the protective layer 110 and the planarization coating 108.

[0089] In this embodiment, a dry etching process is used to remove the protective layer 110 exposed by the first opening K3, as well as the planarization coating 108 located below the protective layer 110.

[0090] See Figure 7 After forming a planarization coating 108 with a mask opening K2 on the dielectric layer 102, the dielectric layer 102 exposed along the depth direction of the initial trench 106 is removed by using the planarization coating 108 as a mask and a directional etching process to form the trench 114.

[0091] In this embodiment, the directional etching process includes a gas etching process. During the process of removing the dielectric layer 102 exposed along the depth direction of the initial trench 106 using the gas etching process, polymers are also generated. The polymers remaining on the sidewalls of the initial trench 106 can serve as an etching barrier layer to protect the sidewalls of the initial trench 106.

[0092] Specifically, during the process of removing the dielectric layer 102 exposed along the depth direction of the initial trench 106 using gas etching, the sidewalls of the initial trench 106 may also be etched. Since the polymer located in the initial trench 106 serves as a protective layer, and this solution uses a multi-stage etching process to form the target trench, the thickness of the dielectric layer 102 removed in a single gas etching process is relatively small, the etching time is short, and the damage to the sidewalls of the dielectric layer 102 is minimal, resulting in good smoothness of the sidewalls.

[0093] In this embodiment, the etching gas in the gas etching process includes C4F8, CHF3, Ar and O2; the etching power is 2200 to 2600 W; the etching time is 700 to 900 s; and the pressure is 200 mT to 250 mT.

[0094] See next Figure 7 Each etching process also includes: after removing the dielectric layer 102 exposed along the depth direction of the initial trench 106 using a directional etching process, removing the planarization coating 108 on the dielectric layer 102.

[0095] In this embodiment, an ashing process is used to remove the planarization coating 108 on the dielectric layer 102. The ashing process can remove the planarization coating 108 in a timely manner, making it less likely for the organic material of the planarization coating 108 to contaminate the machine.

[0096] See also Figures 3 to 7 In this embodiment, during the first etching process, the dielectric layer 102 exposed in the initial trench 106 is removed. The thickness of the removed dielectric layer 102 is relatively small, and the depth of the formed trench 114 has not yet reached the set depth. Therefore, another etching process can be used... Figures 3 to 7 In the steps shown, the dielectric layer 102 is removed.

[0097] For example, see Figure 8 Continue etching the dielectric layer 102 exposed in the trench 114 until a target trench 120 with a set depth is formed in the dielectric layer 102.

[0098] It should be noted that as the trench depth gradually increases, the etching depth gradually decreases during the etching process, which helps to reduce the operational difficulty and improve the smoothness of the sidewalls. In this embodiment, the depth is set to be greater than 10 micrometers, meaning that the above method can be used to form a target trench 120 with a depth greater than 10 micrometers.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The application relates to a method for forming a target trench in a medium layer. The method comprises the following steps: providing a substrate, on which a medium layer is formed; forming an initial trench in the medium layer; 2. The method of forming a semiconductor structure of claim 1, wherein, performing at least one etching treatment on the medium layer exposed by the initial trench until a target trench with a set depth is formed in the medium layer; wherein each etching treatment comprises: forming a planarization coating with a mask opening on the medium layer, the mask opening exposing the initial trench; using the planarization coating as a mask, removing the medium layer exposed by the initial trench in the depth direction by using a directional etching process. The directional etching process comprises a gas etching process.

3. The method of forming a semiconductor structure of claim 2, wherein, During the process of removing the medium layer exposed by the initial trench in the depth direction by using the gas etching process, the polymer remaining on the sidewall of the initial trench acts as an etching barrier.

4. The method of forming a semiconductor structure of claim 1, wherein, The etching gas of the gas etching process comprises C4F8, CHF3, Ar and O2; the etching power is 2200-2600 W; the etching time is 700-900 s; and the pressure is 200-250 mT. The step of forming the planarization coating with the mask opening on the medium layer comprises: forming a planarization coating on the medium layer, the planarization coating filling the initial trench; forming a first barrier layer with a first opening on the planarization coating, the first opening exposing the top of the planarization coating, and the position of the first opening is opposite to the position of the initial trench; 5. The method of forming a semiconductor structure of claim 4, wherein, removing the planarization coating exposed by the first opening along the sidewall of the first barrier layer to form the mask opening in the planarization coating. The material of the planarization coating comprises at least one of SiON, Si3N4, SiC, SOC and TiO2; 6. The method of forming a semiconductor structure of claim 4, wherein, The material of the first barrier layer comprises at least one of photoresist and titanium nitride. The method further comprises: forming a protection layer on the planarization coating before the step of forming the first barrier layer with the first opening on the planarization coating; wherein the first barrier layer is located above the protection layer, and the first opening exposes the top of the protection layer; 7. The method of forming a semiconductor structure of claim 6, wherein, in the step of removing the planarization coating exposed by the first opening along the sidewall of the first barrier layer, the protection layer exposed by the first opening is also removed.

8. The method of forming a semiconductor structure of claim 6, wherein, The protection layer is formed on the planarization coating by using a low-temperature oxidation process.

9. The method of forming a semiconductor structure of claim 6, wherein, The protection layer exposed by the first opening and the planarization coating located below the protection layer are removed by using a dry etching process.

10. The method of forming a semiconductor structure of claim 1, wherein, The material of the protection layer comprises silicon oxide. The method further comprises:

11. The method of forming a semiconductor structure of claim 10, wherein, after the step of removing the medium layer exposed by the initial trench in the depth direction by using the directional etching process, the planarization coating on the medium layer is removed.

12. The method of forming a semiconductor structure of claim 1, wherein, The planarization coating on the medium layer is removed by using a gray etching process. The step of forming the initial trench in the medium layer comprises: forming a second barrier layer with a second opening on the medium layer, the second opening exposing the top of the medium layer; removing the medium layer with a partial thickness exposed by the second opening along the sidewall of the second barrier layer to form the initial trench in the medium layer.

13. The method of forming a semiconductor structure of claim 1, wherein, The set depth is greater than 10 microns. The set depth is greater than 10 microns.

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