An IO multiplexing circuit with anti-backflow function

Abstract

The present invention discloses an IO multiplexing circuit with an anti-backflow function. When port P is used as an output terminal, the enable signal EN is at a high level, and the IO multiplexing circuit can realize a data transmission function. When port P is used as an input terminal, the enable signal EN is at a low level, and the pull-up branch and the pull-down branch in the anti-backflow circuit are both turned off. Port P of the IO multiplexing circuit is used as an input terminal. If port P inputs a low level, the internal power supply voltage of the IO multiplexing circuit is not lower than the port P voltage, and there will be no backflow current. If port P inputs a high level, and the voltage of port P is higher than the internal power supply voltage of the IO multiplexing circuit, the parasitic diode in the pull-up branch is reverse biased, preventing current from flowing back from port P into the internal power supply of the IO multiplexing circuit. The present invention solves the current backflow risk during IO port multiplexing, and has the advantages of simple structure and low power consumption, effectively reducing chip design costs.

Description

Technical Field

[0001] The present invention relates to an IO multiplexing circuit, and in particular to an IO multiplexing circuit with an anti-backflow function. Background Art

[0002] IO (Input / Output) ports are a crucial component of chips, serving as the interface between the chip core and external circuits for data transmission. Due to their bidirectional nature, IO ports can be reused to save chip area and cost. For example, control signals can be used to enable IO ports to serve as inputs for external signals when the chip is in normal operating mode, while in test mode, they can function as outputs to detect signals such as voltage and current at key nodes within the chip.

[0003] In actual applications, when the IO port works in input port mode, the internal power supply of the chip is in the power-off process, and the IO port is connected to the external input signal at a high level, there is a risk of current backflow. Since the pull-up PMOS body diode in the IO circuit is turned on, there is a current path from the IO port through the PMOS body diode to the internal power supply of the chip, charging the internal power supply, causing the chip to be in an abnormal working state.

[0004] In the prior art, the anti-backflow function processing for IO multiplexing circuits is often achieved by adding large resistors, capacitors or diodes. The use of large resistors and capacitors will occupy a large chip area, while the use of diodes has high process requirements and increases the design cost of the chip. Summary of the Invention

[0005] In response to the problems existing in the prior art, the present invention provides an IO multiplexing circuit with an anti-backflow function, which solves the risk of current backflow during IO port multiplexing and has the advantages of simple structure and low power consumption, effectively reducing chip design costs.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solutions: an IO multiplexing circuit with anti-backflow function, consisting of a logic control circuit and an anti-backflow circuit;

[0007] When the logic control circuit is used as the output end of port P, when the enable signal EN and the digital logic signal D are both at a high level, the pull-up branch in the anti-backflow circuit is controlled to be turned on and the pull-down branch is turned off, and the port P of the IO multiplexing circuit outputs a high level as the output end to realize the data transmission function; when the enable signal EN is at a high level and the digital logic signal D is at a low level, the pull-up branch in the anti-backflow circuit is controlled to be turned off and the pull-down branch is turned on, and the port P of the IO multiplexing circuit outputs a low level as the output end to realize the data transmission function;

[0008] When the logic control circuit uses port P as an input terminal, the enable signal EN is at a low level, and the pull-up branch and the pull-down branch in the anti-backflow circuit are controlled to be turned off. Port P of the IO multiplexing circuit serves as an input terminal. If a low level is input to port P, the internal power supply voltage of the IO multiplexing circuit is not lower than the voltage of port P, and there will be no backflow current; if a high level is input to port P, and the voltage of port P is higher than the internal power supply voltage of the IO multiplexing circuit, the parasitic diode in the pull-up branch is reverse biased, thereby preventing current from flowing back from port P into the internal power supply of the IO multiplexing circuit.

[0009] Furthermore, the logic control circuit includes: a first inverter, a first logic level conversion circuit, a second logic level conversion circuit, a second inverter, a third inverter, a fourth inverter, a NAND gate, and a NOR gate, wherein the input end of the first inverter serves as the input end of the enable signal EN, the output end of the first inverter is connected to the input end of the first logic level conversion circuit, the Q output end of the first logic level conversion circuit is respectively connected to the input end of the second inverter and the first input port of the NOR gate, the output end of the second inverter is connected to the first input end of the NAND gate, and the output end of the NAND gate is connected to the input end of the third inverter; the input end of the second logic level conversion circuit serves as the input end of the digital logic signal D, the Q output end of the second logic level conversion circuit is respectively connected to the second input end of the NAND gate and the second input end of the NOR gate, and the output end of the NOR gate is connected to the input end of the fourth inverter; The output end, the output end of the third inverter and the output end of the fourth inverter are all connected to the anti-backflow circuit.

[0010] Furthermore, the first logic level conversion circuit and the second logic level conversion circuit each include: a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, an eighth NMOS tube M13, a ninth NMOS tube M14, a sixth PMOS tube M15, and a seventh PMOS tube M16. The output end of the fifth inverter is respectively connected to the input end of the sixth inverter and the gate of the ninth NMOS tube M14. The output end of the sixth inverter is connected to the gate of the eighth NMOS tube M13. The drain of the eighth NMOS tube M13 is respectively connected to the drain of the sixth PMOS tube M15 and the gate of the seventh PMOS tube M16. The gate of the sixth PMOS tube M15, the drain of the seventh PMOS tube M16, and the drain of the ninth NMOS tube M14 are all connected to the input end of the seventh inverter. The output end of the seventh inverter serves as The output end of the seventh inverter is connected to the input end of the eighth inverter, and the output end of the eighth inverter serves as the Q output end; the source of the sixth PMOS tube M15 and the source of the seventh PMOS tube M16 are both connected to the power supply voltage, and the source of the eighth NMOS tube M13 and the source of the ninth NMOS tube M14 are both grounded.

[0011] Furthermore, in the first logic level conversion circuit, the input end of the fifth inverter is connected to the output end of the first inverter; in the second logic level conversion circuit, the input end of the fifth inverter serves as the input end of the digital logic signal D.

[0012] Furthermore, the anti-backflow circuit includes: a first NMOS transistor M1, a first PMOS transistor M2, a second NMOS transistor M3, a third NMOS transistor M4, a pull-up branch composed of a second PMOS transistor M5 and a third PMOS transistor M6, a fourth PMOS transistor M7, a fourth NMOS transistor M8, a fifth NMOS transistor M9, a sixth NMOS transistor M10 as a pull-down branch, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The gate of the first NMOS transistor M1 is connected to the logic control circuit, the source of the first NMOS transistor M1 is grounded, and the The drain of the first NMOS transistor M1 is connected to one end of the first resistor R1 and the gate of the third PMOS transistor M6 respectively. The other end of the first resistor R1 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 serves as the port P of the IO multiplexing circuit. The gate of the first PMOS transistor M2 and the gate of the second NMOS transistor M3 are both connected to the logic control circuit. The source of the first PMOS transistor M2 is connected to the power supply voltage. The drain of the first PMOS transistor M2 is connected to one end of the second resistor R2, the gate of the third NMOS transistor M4, and the gate of the second PMOS transistor M5 respectively. The other end of the second resistor R2 is connected to the drain of the second NMOS transistor M3, the source of the second NMOS transistor M3 is grounded, the substrate and source of the second PMOS transistor M5 are both connected to the power supply voltage, the drain of the second PMOS transistor M5 is connected to the source of the third PMOS transistor M6, the substrate of the third PMOS transistor M6, the drain of the third PMOS transistor M6, the source of the third NMOS transistor M4, and the drain of the third NMOS transistor M4 are all connected to one end of the fourth resistor R4; the gate of the fourth PMOS transistor M7 and the gate of the fourth NMOS transistor M8 are both connected to the logic In the logic control circuit, the source of the fourth PMOS transistor M7 is connected to the power supply voltage, the drain of the fourth PMOS transistor M7 is respectively connected to one end of the third resistor R3, the source of the fifth NMOS transistor M9, the drain of the fifth NMOS transistor M9, and the gate of the sixth NMOS transistor M10, the gate of the fifth NMOS transistor M9 and the drain of the sixth NMOS transistor M10 are both connected to one end of the fourth resistor R4, the source of the sixth NMOS transistor M10 is grounded, the other end of the third resistor R3 is connected to the drain of the fourth NMOS transistor M8, and the source of the fourth NMOS transistor M8 is grounded.

[0013] Furthermore, the gate of the first NMOS tube M1 is connected to the gate of the first logic level conversion circuit. Output connection.

[0014] Furthermore, the gate of the first PMOS transistor M2 and the gate of the second NMOS transistor M3 are both connected to the output end of the third inverter.

[0015] Furthermore, the gate of the fourth PMOS transistor M7 and the gate of the fourth NMOS transistor M8 are both connected to the output end of the fourth inverter.

[0016] Furthermore, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter are all composed of a fifth PMOS transistor M11 and a seventh NMOS transistor M12. The gate of the fifth PMOS transistor M11 and the gate of the seventh NMOS transistor M12 serve as input ends of the inverters, the drain of the fifth PMOS transistor M11 and the drain of the seventh NMOS transistor M12 serve as output ends of the inverters, the source of the fifth PMOS transistor M11 is connected to the power supply voltage, and the source of the seventh NMOS transistor M12 is grounded.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] (1) The IO multiplexing circuit with anti-backflow function of the present invention controls the IO multiplexing circuit to work in the input or output state through an enable signal, thereby realizing bi-phase transmission of signals from the IO port, reducing the number of IOs and reducing chip costs;

[0019] (2) The pull-up branch of the anti-backflow circuit in the IO multiplexing circuit with an anti-backflow function of the present invention has two control paths: when the port P is used as an output terminal, the state of the pull-up branch is controlled by the first NMOS tube M1 in the anti-backflow circuit to realize the data transmission function; when the port P is used as an input terminal, the state of the pull-up branch is controlled by the voltage of the port P of the IO multiplexing circuit. When the voltage of the port P is higher than the internal power supply voltage of the IO multiplexing circuit, the parasitic diode in the pull-up branch is reverse biased to prevent the current from flowing back from the port P into the internal power supply of the IO multiplexing circuit, thereby realizing the anti-backflow function and having the advantages of simple circuit structure and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the logic control circuit of the IO multiplexing circuit with anti-backflow function of the present invention;

[0021] Figure 2 Schematic diagram of an anti-backflow circuit of an IO multiplexing circuit with an anti-backflow function according to the present invention;

[0022] Figure 3 Schematic diagram of the inverter circuit involved in the present invention;

[0023] Figure 4 Schematic diagram of the logic level conversion circuit in the present invention. DETAILED DESCRIPTION

[0024] The technical solution of the present invention will be further explained below with reference to the accompanying drawings.

[0025] The present invention provides an IO multiplexing circuit with an anti-backflow function, which is composed of a logic control circuit and an anti-backflow circuit; when the logic control circuit is used as an output end, when the enable signal EN and the digital logic signal D are both high, the pull-up branch in the anti-backflow circuit is controlled to be turned on and the pull-down branch is turned off, and the port P of the IO multiplexing circuit outputs a high level as the output end to realize the data transmission function; when the enable signal EN is high and the digital logic signal D is low, the pull-up branch in the anti-backflow circuit is controlled to be turned off and the pull-down branch is turned on, and the port P of the IO multiplexing circuit outputs a low level as the output end to realize the data transmission function. Output function; when the logic control circuit uses port P as the input terminal, the enable signal EN is low, and the pull-up branch and the pull-down branch in the anti-backflow circuit are both turned off. The port P of the IO multiplexing circuit is used as the input terminal. If the port P input is low, the internal power supply voltage of the IO multiplexing circuit is not lower than the port P voltage, and the pull-up branch is turned off, and there will be no backflow current; if the port P input is high, and the port P terminal voltage is higher than the internal power supply voltage of the IO multiplexing circuit, the parasitic diode in the pull-up branch is reverse biased, which can prevent the current from flowing back from port P into the internal power supply of the chip, thereby realizing the anti-backflow function when the external input signal is too high.

[0026] like Figure 1 The logic control circuit of the present invention includes: a first inverter, a first logic level conversion circuit, a second logic level conversion circuit, a second inverter, a third inverter, a fourth inverter, a NAND gate, and a NOR gate. The input end of the first inverter serves as the input end of the enable signal EN, the output end of the first inverter is connected to the input end of the first logic level conversion circuit, the Q output end of the first logic level conversion circuit is respectively connected to the input end of the second inverter and the first input port of the NOR gate, the output end of the second inverter is connected to the first input end of the NAND gate, and the output end of the NAND gate is connected to the input end of the third inverter; the input end of the second logic level conversion circuit serves as the input end of the digital logic signal D, the Q output end of the second logic level conversion circuit is respectively connected to the second input end of the NAND gate and the second input end of the NOR gate, and the output end of the NOR gate is connected to the input end of the fourth inverter; the first logic level conversion circuit The output terminal, the output terminal of the third inverter, and the output terminal of the fourth inverter are all connected to the anti-backflow circuit. The logic control circuit of the present invention uses an inverter, a logic level conversion circuit, a NAND gate, and a NOR gate to perform a logical operation on the enable signal EN and the digital logic signal D, converting the result into an output signal that serves as a control signal for the subsequent anti-backflow circuit.

[0027] like Figure 4In the present invention, the first logic level conversion circuit and the second logic level conversion circuit both include: a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, an eighth NMOS transistor M13, a ninth NMOS transistor M14, a sixth PMOS transistor M15, and a seventh PMOS transistor M16. The output end of the fifth inverter is respectively connected to the input end of the sixth inverter and the gate of the ninth NMOS transistor M14. The output end of the sixth inverter is connected to the gate of the eighth NMOS transistor M13. The drain of the eighth NMOS transistor M13 is respectively connected to the drain of the sixth PMOS transistor M15 and the gate of the seventh PMOS transistor M16. The gate of the sixth PMOS transistor M15, the drain of the seventh PMOS transistor M16, and the drain of the ninth NMOS transistor M14 are all connected to the input end of the seventh inverter. The output end of the seventh inverter serves as a gate. The output terminal of the seventh inverter is connected to the input terminal of the eighth inverter, and the output terminal of the eighth inverter serves as the Q output terminal; the source of the sixth PMOS transistor M15 and the source of the seventh PMOS transistor M16 are both connected to the power supply voltage, and the source of the eighth NMOS transistor M13 and the source of the ninth NMOS transistor M14 are both grounded. The present invention completes the conversion from the digital domain power supply to the analog domain power supply through the first logic level conversion circuit and the second logic level conversion circuit.

[0028] In the first logic level conversion circuit, the input end of the fifth inverter is connected to the output end of the first inverter; in the second logic level conversion circuit, the input end of the fifth inverter serves as the input end of the digital logic signal D.

[0029] like Figure 2 The anti-backflow circuit of the present invention includes: a first NMOS transistor M1, a first PMOS transistor M2, a second NMOS transistor M3, a third NMOS transistor M4, a pull-up branch composed of a second PMOS transistor M5 and a third PMOS transistor M6, a fourth PMOS transistor M7, a fourth NMOS transistor M8, a fifth NMOS transistor M9, a sixth NMOS transistor M10 as a pull-down branch, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The gate of the first NMOS transistor M1 is connected to the logic control circuit. Specifically, the gate of the first NMOS transistor M1 is connected to the first logic level conversion circuit. The output end is connected and the control signal F1 is input; the source of the first NMOS transistor M1 is grounded, the drain of the first NMOS transistor M1 is respectively connected to one end of the first resistor R1 and the gate of the third PMOS transistor M6, the other end of the first resistor R1 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 serves as the port P of the IO multiplexing circuit; the gate of the first PMOS transistor M2 and the gate of the second NMOS transistor M3 are both connected to the logic control circuit. Specifically, the gate of the first PMOS transistor M2 and the gate of the second NMOS transistor M3 are both connected to the output end of the third inverter and the control signal F2 is input; the source of the first PMOS transistor M2 is connected to the power supply voltage, the drain of the first PMOS transistor M2 is respectively connected to one end of the second resistor R2, the gate of the third NMOS transistor M4, and the gate of the second PMOS transistor M5, the other end of the second resistor R2 is connected to the drain of the second NMOS transistor M3, the source of the second NMOS transistor M3 is grounded, the substrate and source of the second PMOS transistor M5 are both connected to the power supply voltage, and the drain of the second PMOS transistor M5 is connected to the power supply voltage. The source of the third PMOS transistor M6 is connected to the substrate of the third PMOS transistor M6, the drain of the third PMOS transistor M6, the source of the third NMOS transistor M4, and the drain of the third NMOS transistor M4 are all connected to one end of the fourth resistor R4; the gate of the fourth PMOS transistor M7 and the gate of the fourth NMOS transistor M8 are both connected to the logic control circuit. Specifically, the gate of the fourth PMOS transistor M7 and the gate of the fourth NMOS transistor M8 are both connected to the output end of the fourth inverter and input the control signal F3; the fourth PMOS transistor The source of M7 is connected to the power supply voltage. The drain of the fourth PMOS transistor M7 is respectively connected to one end of the third resistor R3, the source of the fifth NMOS transistor M9, the drain of the fifth NMOS transistor M9, and the gate of the sixth NMOS transistor M10. The gate of the fifth NMOS transistor M9 and the drain of the sixth NMOS transistor M10 are both connected to one end of the fourth resistor R4. The source of the sixth NMOS transistor M10 is grounded. The other end of the third resistor R3 is connected to the drain of the fourth NMOS transistor M8. The source of the fourth NMOS transistor M8 is grounded.

[0030] When port P is used as an output terminal, that is, when the enable signal EN=1 and the digital logic signal D=1, the logic control circuit outputs signals F1=1, F2=D=1, and F3=D=1. After the control signals F1, F2, and F3 are transmitted to the anti-backflow circuit, the control signal F1 is 1, turning on the first NMOS transistor M1, thereby turning on the third PMOS transistor M6; the control signal F2 is 1, turning on the second NMOS transistor M3, turning off the first PMOS transistor M2, and pulling the gate of the second PMOS transistor M5 to the ground potential, thereby turning on the second PMOS transistor M5; the control signal F3 is 1, turning on the fourth NMOS transistor M8, turning off the fourth PMOS transistor M7, and pulling the gate of the sixth NMOS transistor M10 to the ground potential, thereby turning off the sixth NMOS transistor M10. Since the pull-up branch is turned on and the pull-down branch is turned off, port P outputs a high level. When the enable signal EN=1 and the digital logic signal D=0, the logic control circuit outputs signals F1=1, F2=D=0, and F3=D=0. After the control signals F1, F2, and F3 are transmitted to the backflow prevention circuit, the control signal F1 is 1, turning on the first NMOS transistor M1, and then turning on the third PMOS transistor M6; the control signal F2 is 0, turning on the first PMOS transistor M2, turning off the second NMOS transistor M3, and pulling the gate of the second PMOS transistor M5 to the power supply potential, turning off the second PMOS transistor M5; the control signal F3 is 0, turning on the fourth PMOS transistor M7, turning off the fourth NMOS transistor M8, and pulling the gate of the sixth NMOS transistor M10 to the power supply potential, turning on the sixth NMOS transistor M10. At this time, the pull-up branch is turned off, the pull-down branch is turned on, and the port P outputs a low level. In summary, when the IO multiplexing circuit is used as an output terminal, the output voltage of port P changes with the digital logic signal D. When D is high, port P outputs a high level; when D is low, port P outputs a low level, realizing the data transmission function. Among them, 1 represents a high level, and 0 represents a low level.

[0031] When the port P is used as an input terminal and the enable signal EN=0, no matter whether the digital logic signal D is 1 or 0, the output of the logic control circuit is always F1=0, F2=0, and F3=1. After the control signals F1, F2, and F3 are transmitted to the anti-backflow circuit, F1=0 turns off the first NMOS transistor M1, and the state of the third PMOS transistor M6 is controlled by the voltage of the port P; F2=0 turns on the first PMOS transistor M2, turns off the second NMOS transistor M3, and pulls the gate of the second PMOS transistor M5 to a high level to turn off the second PMOS transistor M5; F3=1 turns on the fourth NMOS transistor M8, turns off the fourth PMOS transistor M7, and pulls the gate of the sixth NMOS transistor M10 to a low potential to turn off the sixth NMOS transistor M10. The MOS transistor M10 is turned off. At this time, both the pull-up branch and the pull-down branch are turned off. The circuit no longer has the signal transmission function, but needs to prevent current from flowing back from port P to the power supply voltage through the pull-up branch. The specific implementation logic is discussed in two cases: when port P is at a low level, the internal power supply voltage of the chip is not lower than the voltage of port P, and there is no possibility of current flowing back from port P to the internal power supply of the IO multiplexing circuit; the gate and drain voltages of the third PMOS transistor M6 are both at a low level, the third PMOS transistor M6 is turned on, and the source voltage of the third PMOS transistor M6 drops to a low potential. However, since the second PMOS transistor M5 is in the off state, no current will flow from the internal power supply voltage of the IO multiplexing circuit to port P. When port P is at a high level, the gate voltage and drain voltage of the third PMOS transistor M6 are both at a high level. Since the substrate of the third PMOS transistor M6 is connected to the drain, the body diode of the third PMOS transistor M6 is in a reverse biased state. Even if the internal chip power supply is in a power-off process or the chip voltage is lower than the IO voltage, there is no conductive branch from the IO to the internal chip power supply, and there is no backflow current from the IO. At the same time, since the parasitic body diode of the third PMOS transistor M6 is used to implement the backflow prevention function, compared with adding additional diodes and other devices, no additional voltage margin is occupied, the circuit structure is simpler, the dependence on the process is reduced, and the chip area and cost are saved. Therefore, the present invention realizes an IO multiplexing circuit with backflow prevention protection.

[0032] like Figure 3 In the present invention, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter are all composed of a fifth PMOS transistor M11 and a seventh NMOS transistor M12. The gate of the fifth PMOS transistor M11 and the gate of the seventh NMOS transistor M12 serve as input terminals of the inverters. The drain of the fifth PMOS transistor M11 and the drain of the seventh NMOS transistor M12 serve as output terminals of the inverters. The source of the fifth PMOS transistor M11 is connected to the power supply voltage, and the source of the seventh NMOS transistor M12 is grounded.

[0033] The IO multiplexing circuit with anti-backflow function of the present invention solves the risk of current backflow when IO ports are multiplexed, and has the advantages of simple structure and low power consumption, effectively reducing chip design costs.

[0034] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. An IO multiplexing circuit with anti-backflow function, characterized in that: It consists of a logic control circuit and an anti-backflow circuit; When the logic control circuit is used as the output end of port P, when the enable signal EN and the digital logic signal D are both at a high level, the pull-up branch in the anti-backflow circuit is controlled to be turned on and the pull-down branch is turned off, and the port P of the IO multiplexing circuit outputs a high level as the output end to realize the data transmission function; when the enable signal EN is at a high level and the digital logic signal D is at a low level, the pull-up branch in the anti-backflow circuit is controlled to be turned off and the pull-down branch is turned on, and the port P of the IO multiplexing circuit outputs a low level as the output end to realize the data transmission function; When the logic control circuit uses port P as an input terminal, the enable signal EN is at a low level, and the pull-up branch and the pull-down branch in the anti-backflow circuit are controlled to be turned off. Port P of the IO multiplexing circuit serves as an input terminal. If a low level is input to port P, the internal power supply voltage of the IO multiplexing circuit is not lower than the voltage of port P, and there will be no backflow current; if a high level is input to port P, and the voltage of port P is higher than the internal power supply voltage of the IO multiplexing circuit, the parasitic diode in the pull-up branch is reverse biased, thereby preventing current from flowing back from port P into the internal power supply of the IO multiplexing circuit; The logic control circuit includes: a first inverter, a first logic level conversion circuit, a second logic level conversion circuit, a second inverter, a third inverter, a fourth inverter, a NAND gate and a NOR gate, wherein the input end of the first inverter serves as the input end of the enable signal EN, the output end of the first inverter is connected to the input end of the first logic level conversion circuit, the Q output end of the first logic level conversion circuit is respectively connected to the input end of the second inverter and the first input port of the NOR gate, the output end of the second inverter is connected to the first input end of the NAND gate, and the output end of the NAND gate is connected to the input end of the third inverter; the input end of the second logic level conversion circuit serves as the input end of the digital logic signal D, the Q output end of the second logic level conversion circuit is respectively connected to the second input end of the NAND gate and the second input end of the NOR gate, and the output end of the NOR gate is connected to the input end of the fourth inverter; The output end, the output end of the third inverter and the output end of the fourth inverter are all connected to the anti-backflow circuit.

2. The IO multiplexing circuit with anti-backflow function according to claim 1, characterized in that: The first logic level conversion circuit and the second logic level conversion circuit both include: a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, an eighth NMOS transistor M13, a ninth NMOS transistor M14, a sixth PMOS transistor M15, and a seventh PMOS transistor M16. The output end of the fifth inverter is respectively connected to the input end of the sixth inverter and the gate of the ninth NMOS transistor M14. The output end of the sixth inverter is connected to the gate of the eighth NMOS transistor M13. The drain of the eighth NMOS transistor M13 is respectively connected to the drain of the sixth PMOS transistor M15 and the gate of the seventh PMOS transistor M16. The gate of the sixth PMOS transistor M15, the drain of the seventh PMOS transistor M16, and the drain of the ninth NMOS transistor M14 are all connected to the input end of the seventh inverter. The output end of the seventh inverter serves as a gate. The output end of the seventh inverter is connected to the input end of the eighth inverter, and the output end of the eighth inverter serves as the Q output end; the source of the sixth PMOS tube M15 and the source of the seventh PMOS tube M16 are both connected to the power supply voltage, and the source of the eighth NMOS tube M13 and the source of the ninth NMOS tube M14 are both grounded.

3. The IO multiplexing circuit with anti-backflow function according to claim 2, characterized in that: In the first logic level conversion circuit, the input terminal of the fifth inverter is connected to the output terminal of the first inverter; In the second logic level conversion circuit, the input terminal of the fifth inverter serves as the input terminal of the digital logic signal D.

4. The IO multiplexing circuit with anti-backflow function according to claim 3, characterized in that: The anti-backflow circuit includes: a first NMOS transistor M1, a first PMOS transistor M2, a second NMOS transistor M3, a third NMOS transistor M4, a pull-up branch composed of a second PMOS transistor M5 and a third PMOS transistor M6, a fourth PMOS transistor M7, a fourth NMOS transistor M8, a fifth NMOS transistor M9, a sixth NMOS transistor M10 as a pull-down branch, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The gate of the first NMOS transistor M1 is connected to the logic control circuit, the source of the first NMOS transistor M1 is grounded, and the first NMOS transistor M1 is connected to the logic control circuit. The drain of the OS transistor M1 is connected to one end of the first resistor R1 and the gate of the third PMOS transistor M6 respectively. The other end of the first resistor R1 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 serves as the port P of the IO multiplexing circuit. The gate of the first PMOS transistor M2 and the gate of the second NMOS transistor M3 are both connected to the logic control circuit. The source of the first PMOS transistor M2 is connected to the power supply voltage. The drain of the first PMOS transistor M2 is connected to one end of the second resistor R2, the gate of the third NMOS transistor M4, and the gate of the second PMOS transistor M5 respectively. The other end of the second resistor R2 is connected to the drain of the second NMOS transistor M3, the source of the second NMOS transistor M3 is grounded, the substrate and source of the second PMOS transistor M5 are both connected to the power supply voltage, the drain of the second PMOS transistor M5 is connected to the source of the third PMOS transistor M6, the substrate of the third PMOS transistor M6, the drain of the third PMOS transistor M6, the source of the third NMOS transistor M4, and the drain of the third NMOS transistor M4 are all connected to one end of the fourth resistor R4; the gate of the fourth PMOS transistor M7 and the gate of the fourth NMOS transistor M8 are both connected to the logic control In the control circuit, the source of the fourth PMOS transistor M7 is connected to the power supply voltage, the drain of the fourth PMOS transistor M7 is respectively connected to one end of the third resistor R3, the source of the fifth NMOS transistor M9, the drain of the fifth NMOS transistor M9, and the gate of the sixth NMOS transistor M10, the gate of the fifth NMOS transistor M9 and the drain of the sixth NMOS transistor M10 are both connected to one end of the fourth resistor R4, the source of the sixth NMOS transistor M10 is grounded, the other end of the third resistor R3 is connected to the drain of the fourth NMOS transistor M8, and the source of the fourth NMOS transistor M8 is grounded.

5. The IO multiplexing circuit with anti-backflow function according to claim 4, characterized in that: The gate of the first NMOS tube M1 is connected to the gate of the first logic level conversion circuit. Output connection.

6. The IO multiplexing circuit with anti-backflow function according to claim 4, characterized in that: The gate of the first PMOS transistor M2 and the gate of the second NMOS transistor M3 are both connected to the output end of the third inverter.

7. The IO multiplexing circuit with anti-backflow function according to claim 4, characterized in that: The gate of the fourth PMOS transistor M7 and the gate of the fourth NMOS transistor M8 are both connected to the output end of the fourth inverter.

8. The IO multiplexing circuit with anti-backflow function according to claim 4, characterized in that: The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter are all composed of a fifth PMOS transistor M11 and a seventh NMOS transistor M12. The gate of the fifth PMOS transistor M11 and the gate of the seventh NMOS transistor M12 serve as input ends of the inverters, the drain of the fifth PMOS transistor M11 and the drain of the seventh NMOS transistor M12 serve as output ends of the inverters, the source of the fifth PMOS transistor M11 is connected to the power supply voltage, and the source of the seventh NMOS transistor M12 is grounded.

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