Ultra-low phase noise frequency source circuit and frequency planning method based on YTO

Abstract

The present application provides an ultra-low phase noise frequency source circuit and frequency planning method based on YTO, which belongs to the field of microwave radio frequency and frequency source technology. The frequency source circuit includes a main loop circuit, a first offset loop circuit, a second offset loop circuit, a clock circuit, a YTO drive circuit, a control circuit, etc.; the main loop circuit includes a first phase detector module U1, a first loop module U2, a YTO module U3, a first coupler module U4, a first mixer module U5, a first filter module U6, an amplifier module U7, a second mixer module U8, etc. The method is implemented based on the frequency source circuit. The scheme of the present application generates a frequency signal with low phase noise by adopting a multi-stage conversion loop, and gradually widens the frequency, so that the YTO module can finally output a frequency signal with low phase noise. At the same time, the spectrum is planned according to the frequency range output by the YTO module, so that the final output spectrum of the YTO module is pure and the spurious is low.

Description

Technical Field

[0001] The present application belongs to the field of microwave radio frequency technology and relates to a frequency source, and specifically to an ultra-low phase noise frequency source circuit and a frequency planning method based on YTO. Background Art

[0002] Modern high-performance broadband spectrum analyzers often use superheterodyne frequency sweeping schemes. The measured signal undergoes multiple frequency conversions to the intermediate frequency, and finally obtains the signal spectrum through digital signal processing. The first-stage scanning local oscillator in a broadband spectrum analyzer is often composed of a YTO (YIG tuned oscillator). YTO has the characteristics of wide tuning frequency bandwidth, good linearity, pure spectrum, and high reliability, and has become a core component of many modern military electronic equipment and microwave instruments.

[0003] For broadband analog signal sources, using YTO as the main oscillator not only makes the spectrum pure, but also has better phase noise indicators than VCO (voltage-controlled oscillator). Therefore, the frequency source circuit composed of YTO has excellent performance. However, YTO also has its own shortcomings. Due to the influence of hysteresis, eddy current, etc., the response speed of YTO is far inferior to that of VCO. In addition, the traditional YTO frequency source circuit adopts a two-stage frequency division or mixing method, and the coarse adjustment coil is used for frequency preset. The driving local oscillator of the mixer adopts a comb spectrum generator to achieve down-conversion, and then the fine adjustment coil is locked through a fractional phase-locked loop, such as Figure 1 As shown. This method will generate a lot of spurious frequencies and has high requirements for the filter. At the same time, because of the use of an integrated fractional phase-locked loop and a comb spectrum generator, the phase noise will deteriorate and the debugging is also complicated. The prior art with publication number CN115622556A discloses a multi-stage down-conversion frequency synthesis device and method, which achieves the low phase noise performance of YTO through multi-stage down-conversion. However, the phase noise of this circuit will put forward higher requirements on the far-end phase noise of the VCO, especially when using a wide-band VCO to meet the wide-band characteristics of the YTO, that is, the phase noise of the wide-band output VCO itself is very poor, which ultimately results in the phase noise of the YTO output not being particularly low. Summary of the invention

[0004] In order to solve the deficiencies of the above-mentioned prior art, the present application provides an ultra-low phase noise frequency source circuit and frequency planning method based on YTO, which generates a frequency signal with low phase noise by adopting a multi-stage conversion loop, and gradually widens the frequency, so that the YTO module can eventually output a frequency signal with low phase noise. At the same time, spectrum planning is performed according to the frequency range output by the YTO module, so that the final output spectrum of the YTO module is pure and the spurious signal is low.

[0005] In order to achieve the above object, the present invention adopts the following technologies:

[0006] An ultra-low phase noise frequency source circuit based on YTO includes a main loop circuit, a first offset loop circuit, a second offset loop circuit, a clock circuit, and a YTO driving circuit;

[0007] The main loop circuit includes:

[0008] The first phase detector module U1 has a first input terminal connected to a reference signal provided by a clock circuit. Fref , the output end is connected to the input end of the first loop module U2;

[0009] A YTO module U3, whose fine tuning input terminal is connected to the output terminal of the first loop module U2, and whose coarse tuning input terminal is connected to the YTO driving circuit;

[0010] A first coupler module U4, whose input end is connected to the output end of the YTO module U3, and whose first output end is a radio frequency output end;

[0011] The first mixer module U5 has a first input terminal connected to a reference signal provided by a clock circuit. Fs 1. The second input end is connected to the second output end of the first coupler module U4, and the output end of the first mixer module U5 is connected to the input end of the first filter module U6;

[0012] A second mixer module U8, wherein a first input end thereof is connected to the output of the second offset loop circuit, a second input end thereof is connected to the output end of the first filter module U6, and an output end of the second mixer module U8 is connected to a second input end of the first phase detector module U1;

[0013] The first offset loop circuit is used to provide a reference signal according to the reference signal provided by the clock circuit. Fs 5 and reference signal Fs 4. Form and output a predetermined narrowband low phase noise frequency signal Fs 3 to the second offset loop circuit;

[0014] The second offset loop circuit is used to generate a reference signal according to the reference signal provided by the clock circuit. Ff and the first offset loop circuit delivers a signal Fs 3. Form and output a frequency range wider than the signal Fs Low phase noise frequency signal of 3 Fs 2 to the first input terminal of the second mixer module U8;

[0015] The first phase detector module U1 is used to obtain the phase difference of the signals at its two input terminals and output it. The first loop module U2 is used to convert the phase difference output by the first phase detector module U1 into a fixed voltage value and provide it to the fine tuning input terminal of the YTO module U3. The YTO module U3 is used to adjust the phase difference according to the control current of the YTO drive circuit. I Output at locked frequency FoThe first coupler module U4 is used to divide the output signal of the YTO module U3 into two signals with equal frequencies and output them from the first output end and the second output end. The first mixer module U5 is used to generate a reference signal according to the reference signal. Fs 1 and the signal output from the second output end of the first coupler module U4 are mixed to generate an intermediate frequency signal, the first filter U6 is used to filter out the intermodulation signal in the intermediate frequency signal and then output it, and the second mixer U8 is used to generate an intermediate frequency signal according to the signal Fs 2 and the first filter U6 output signal are mixed to form a signal IF 2 is input to the second input terminal of the first phase detector module U1; when the signal IF 2 has a frequency equal to the reference signal Fref When the frequency is , the output signal frequency of the YTO module U3 is locked at the locking frequency Fo , the RF output terminal outputs the locking frequency Fo signal.

[0016] Furthermore, the main loop circuit also includes an amplifier module U7 connected between the first filter module U6 and the second mixer module U8, the output end of the first filter module U6 is connected to the input end of the amplifier module U7, the output end of the amplifier module U7 is connected to the second input end of the second mixer module U8, and the amplifier module U7 is used to amplify the filtered signal to form a signal IF 1. The second mixer U8 is used to Fs 2 and signal IF 1 Mixing to form a signal IF 2 is input to the second input terminal of the first phase detector module U1.

[0017] Further, the second offset loop circuit includes:

[0018] Attenuator module U9, whose input is connected to the reference signal provided by the clock circuit Ff , used for the reference signal Ff After the predetermined attenuation amount is attenuated, the signal is formed. Fs 6 and output;

[0019] The second phase detector module U10 has a first input end connected to the output end of the attenuator module U9 and a second input end connected to the output end of the second filter U15, for obtaining a signal Fs 6 and the signal output after filtering by the second filter U15 IF 3 phase difference and output;

[0020] A second loop module U11, whose input end is connected to the output end of the second phase detector module U10, is used to convert the phase difference output by the second phase detector module U10 into a fixed voltage value;

[0021] A first VCO module U12, whose input end is connected to the output end of the second loop module U11, and is used to lock the frequency of the output signal according to the voltage value provided by the second loop module U11;

[0022] The second coupler module U13 has an input end connected to the output end of the first VCO module U12, and a first output end of the second coupler module U13 is connected to a first input end of the second mixer module U8, and is used to divide the signal output by the first VCO module U12 into two paths with equal frequencies, one of which is used as a signal Fs 2 is sent to the second mixer module U8;

[0023] The third mixer module U14 has a first input end connected to the second output end of the second coupler module U13, and a second input end of the third mixer module U14 is connected to the frequency signal output by the first offset loop circuit. Fs 3. The output end of the third mixer module U14 is connected to the input end of the second filter U15, and is used to output the signal according to the other output signal of the second coupler module U13 and the signal Fs 3 is mixed and then input to the second filter U15, the second filter U15 is used to filter the signal mixed by the third mixer module U14 to form a signal IF 3 output to the second phase detector module U10;

[0024] when signal IF The frequency of 3 is equal to the signal Fs 6, the signal Fs 2 frequency lock.

[0025] Further, the first offset loop circuit includes:

[0026] The DDS module U16 has its input connected to the reference signal provided by the clock circuit. Fs 5, used to output signals according to the following formula IF 4:

[0027]

[0028] In the formula, FTW is the frequency control word sent externally, and N is the number of bits of the frequency control word of the DDS module U16;

[0029] The third phase detector module U17 has a first input terminal connected to the output terminal of the DDS module U16, and a second input terminal connected to the output terminal of the third filter module U22, for obtaining a signal IF 4 and the signal output after filtering by the third filtering module U22 IF 5 phase difference and output;

[0030] A third loop module U18, whose input end is connected to the output end of the third phase detector module U17, is used to convert the phase difference output by the third phase detector module U17 into a fixed voltage value;

[0031] A second VCO module U19, whose input end is connected to the output end of the third loop module U18, is used to lock the frequency of the output signal according to the voltage value provided by the third loop module U18;

[0032] The third coupler module U20, whose input end is connected to the output end of the second VCO module U19, is used to divide the signal output by the second VCO module U19 into two paths with equal frequencies, one of which is used as the signal Fs 3 is sent to the second offset loop circuit;

[0033] The fourth mixer module U21 has a first input end connected to the second output end of the third coupler module U20, and a second input end of the fourth mixer module U21 is connected to the reference signal provided by the clock circuit. Fs 4. The output end of the fourth mixer module U21 is connected to the input end of the third filter module U22, and is used to output the signal according to the other output signal of the third coupler module U20 and the signal Fs 4 is mixed and then input to the third filter module U22, the third filter module U22 is used to filter the signal mixed by the third coupler module U20 to form a signal IF 5 is output to the third phase detector module U17;

[0034] when signal IF The frequency of 5 is equal to the signal IF 4 frequency, the signal Fs 3 frequency lock.

[0035] Furthermore, it also includes a control circuit connected to the YTO drive circuit, the clock circuit, the first offset loop circuit, and the second offset loop circuit respectively, and the control circuit is used to control the YTO drive circuit to adjust the control current I , and is used to switch the frequency of the reference signal provided by the clock circuit.

[0036] Furthermore, the reference signal Ff , reference signal Fref The reference signal is generated by the nonlinear transmission line NLTL of the clock circuit. Fs 1. Reference signal Fs 4. Reference signal Fs 5 is generated by the phase-locked dielectric oscillator PDRO of the clock circuit.

[0037] A frequency planning method is implemented using an ultra-low phase noise frequency source circuit based on YTO, the method comprising the steps of:

[0038] Generate reference signal through clock circuit Ff , reference signal Fref , reference signal Fs 1. Reference signal Fs 4. Reference signal Fs 5; where the reference signal Fs The number of frequency points NFs1 of 1 is determined by the following formula:

[0039]

[0040] In the formula, Fo MAX Indicates the maximum frequency output by the YTO module. Fo MIN Indicates the minimum frequency output by the YTO module, in MHz;

[0041] According to the locking frequency to be output by YTO module U3 Fo Calculate the control current input to the coarse tuning input of the YTO module U3 through the YTO drive circuit I , so that the frequency of the output signal of the YTO module U3 is at the locking frequency Fo within the preset range;

[0042] The first offset loop circuit is used to adjust the reference signal Fs 5 and reference signal Fs 4. Form and output a predetermined narrowband low phase noise frequency signal Fs 3 to the second offset loop circuit;

[0043] The second offset loop circuit is used to adjust the reference signal Ff and the first offset loop circuit delivers a signal Fs 3. Form and output a frequency range wider than the signal Fs Low phase noise frequency signal of 3 Fs 2 to the first input terminal of the second mixer module U8;

[0044] When the YTO module U3 is unlocked, it will be controlled by the control current of the coarse tuning input terminal. I The output is locked at the frequency Fo The first coupler module U4 divides the output signal of the YTO module into two signals with equal frequencies, one of which is used as the signal output from the final RF output terminal, and the other output signal enters the first mixer module U5. The first mixer module U5 generates a reference signal according to the reference signal. Fs 1 and another output signal of the first coupler module U4 are mixed to generate an intermediate frequency signal, the first filter module U6 filters out the intermodulation signal in the intermediate frequency signal and then outputs it, and the second mixer module U8 generates an intermediate frequency signal according to the signal Fs2 and the first filter U6 output signal are mixed to form a signal IF 2 is input to the second input terminal of the first phase detector module U1. Preferably, when the main loop circuit also includes an amplifier module U7, the output signal of the first filter module U6 is amplified by the amplifier module U7 to form a signal IF 1 and then sent to the second mixer module U8, the second mixer module U8 then Fs 2 and signal IF 1 Mixing to form a signal IF 2; The first phase detector module U1 obtains the reference signal Fref and signal IF 2 and outputs it, the first loop module U2 converts the phase difference output by the first phase detector module U1 into a fixed voltage value and provides it to the fine tuning input terminal of the YTO module;

[0045] Until the signal IF 2 has a frequency equal to the reference signal Fref When the frequency is , the output signal frequency of the YTO module U3 is locked at the locking frequency Fo , the RF output terminal outputs the locking frequency Fo signal.

[0046] The beneficial effects of the present invention are:

[0047] 1. Compared with the traditional YTO frequency source circuit, the present invention does not use a comb spectrum generator to perform loop conversion phase locking, thus avoiding the situation where the use of a comb spectrum generator will produce deteriorated phase noise; instead, a multi-stage conversion loop is used to generate a frequency signal with low phase noise, and the frequency is gradually widened, so that the YTO module can eventually output a frequency signal with low phase noise. At the same time, spectrum planning is performed according to the frequency range output by the YTO module, so that the final output spectrum of the YTO module is pure and the spurious is low;

[0048] 2. The ultra-low phase noise reference signal generated by the clock circuit is generated by PDRO and NLTL frequency multiplication. Not only is the phase noise better than that of the comb spectrum generator, but the spectrum is also pure;

[0049] 3. The control circuit can be used to control the DDS module to output different frequencies and realize the output of the entire wide-band YTO. At the same time, by selecting the appropriate offset local oscillator signal, the entire frequency coverage can be achieved more perfectly, and the spurious signals generated by the mixer can be effectively filtered out according to the frequency planning. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 The invention is a schematic diagram of a YTO frequency source circuit in the prior art.

[0051] Figure 2It is a block diagram of the overall circuit structure of the frequency source circuit of an embodiment of the present application.

[0052] Figure 3 This is an example schematic diagram of the main loop circuit of an embodiment of the present application.

[0053] Figure 4 It is a preferred example schematic diagram of the main loop circuit of the embodiment of the present application.

[0054] Figure 5 It is an example schematic diagram of the second offset loop circuit of an embodiment of the present application.

[0055] Figure 6 This is an example schematic diagram of the first offset loop circuit of the embodiment of the present application.

[0056] Figure 7 This is an example circuit diagram of the overall circuit of the frequency source circuit of an embodiment of the present application.

[0057] Figure 8 This is a schematic diagram of a conversion loop phase-locked loop circuit according to an embodiment of the present application.

[0058] Figure 9 It is a schematic diagram of phase noise of a conversion loop phase-locked loop according to an embodiment of the present application. DETAILED DESCRIPTION

[0059] To make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the implementation modes of the present invention are described in detail below with reference to the accompanying drawings. However, the embodiments described in the present invention are only part of the embodiments of the present invention, rather than all the embodiments.

[0060] From the basic YTO phase-locked circuit, we can know that YTO is often used in frequency source circuits due to its advantages such as wide output frequency band, pure spectrum, and good far-end phase noise. Since YTO is a magnetic device, it needs a constant current source to drive it, and in the frequency source circuit, YTO needs to use a phase-locked loop to lock the frequency.

[0061] In such Figure 8 In the conversion circuit shown in FIG. 1 , the in-band phase noise of the basic phase-locked loop is calculated as follows:

[0062] PN = PN SYNTH +10 logF PD +20 logN

[0063] in, PN SYNTH is the phase noise floor of the phase detector in the phase-locked loop, F PD is the reference frequency of the phase detector in the phase-locked loop,N The value is the frequency division ratio in the phase-locked loop, that is, N The larger the value, the worse the phase noise in the phase-locked loop. In order to reduce the deterioration of phase noise, the phase detection frequency can be increased and the N value, a mixer is used to convert the output signal to an intermediate frequency (IF) that matches the reference frequency, instead of dividing the output frequency by a large divider value, which can reduce the divider value to 1, thereby eliminating the noise generated when a traditional phase-locked loop uses a large divider. Of course, this will cause the phase noise of the LO (local oscillator signal) to appear in the loop, so the close-in carrier phase noise of the LO is particularly important. In the conversion loop, since the close-in phase noise of the carrier is extremely low, a large loop filter bandwidth can be selected, while speeding up the locking time. Within the loop bandwidth, the RF (radio frequency signal) output tracks the LO phase noise. Outside the loop bandwidth, because the LO close-in phase noise is excellent, but the far-end noise floor is high, the phase noise outside the loop bandwidth is determined by the master oscillator (VCO), such as Figure 9 shown.

[0064] The present application embodiment provides an ultra-low phase noise frequency source circuit and a frequency planning method based on YTO, such as Figure 2 As shown, it includes a main loop circuit, a first offset loop circuit, a second offset loop circuit, a clock circuit, a YTO drive circuit, a control circuit, etc.

[0065] The first offset loop circuit is based on the reference signal provided by the clock circuit Fs 5 and reference signal Fs 4. Form and output a predetermined narrowband low phase noise frequency signal Fs 3 to the second offset loop circuit.

[0066] The second offset loop circuit is based on the reference signal provided by the clock circuit Ff and the first offset loop circuit delivers a signal Fs 3. Form and output a frequency range wider than the signal Fs Low phase noise frequency signal of 3 Fs 2 to the first input terminal of the second mixer module U8.

[0067] Among them, Figure 3 As shown, the main loop circuit includes a first phase detector module U1, a first loop module U2, a YTO module U3, a first coupler module U4, a first mixer module U5, a first filter module U6, a second mixer module U8, etc.

[0068] The first input terminal of the first phase detector module U1 is connected to the reference signal provided by the clock circuit Fref, the output end is connected to the input end of the first loop module U2; the fine tuning input end of the YTO module U3 is connected to the output end of the first loop module U2, and the coarse tuning input end is connected to the YTO drive circuit; the input end of the first coupler module U4 is connected to the output end of the YTO module U3, and the first output end is the RF output end; the first input end of the first mixer module U5 is connected to the reference signal provided by the clock circuit Fs 1, the second input end is connected to the second output end of the first coupler module U4, the output end of the first mixer module U5 is connected to the input end of the first filter module U6, the first input end of the second mixer module U8 is connected to the output of the second offset loop circuit, the second input end is connected to the output end of the first filter module U6, and the output end of the second mixer module U8 is connected to the second input end of the first phase detector module U1.

[0069] The control circuit is connected to the YTO drive circuit, the clock circuit, the first offset loop circuit, and the second offset loop circuit respectively, and is used to control the YTO drive circuit to adjust the control current. I , and is used to switch the frequency of the reference signal provided by the clock circuit.

[0070] The YTO drive circuit is mainly used to preset the output frequency of the YTO module U3 in the main loop circuit. Before the YTO module U3 phase locks, the main coil needs to be preset so that the output frequency is close to the locking frequency. The implementation method is to adjust the coarse control current I It is connected to the main coil of the YTO module U3 and then locked through the transfer loop. The fine tuning coil of the YTO module U3 is fed with voltage through the first loop module U2. The voltage is converted into current through resistance inside, and then the YTO module U3 outputs the locked frequency.

[0071] The first phase detector module U1 is used to obtain the phase difference of the signals at its two input terminals and output it. The first loop module U2 is used to convert the phase difference output by the first phase detector module U1 into a fixed voltage value and provide it to the fine tuning input terminal of the YTO module U3. The YTO module U3 is used to adjust the phase difference according to the control current of the YTO drive circuit. I Output at locked frequency Fo The first coupler module U4 is used to divide the output signal of the YTO module U3 into two signals with equal frequencies and output them from the first output end and the second output end. The first mixer module U5 is used to generate a reference signal according to the reference signal. Fs 1 and the signal output from the second output end of the first coupler module U4 are mixed to generate an intermediate frequency signal, the first filter U6 is used to filter out the intermodulation signal in the intermediate frequency signal and then output it, and the second mixer U8 is used to generate an intermediate frequency signal according to the signal Fs 2 and the first filter U6 output signal are mixed to form a signal IF2 is input to the second input terminal of the first phase detector module U1; when the signal IF 2 has a frequency equal to the reference signal Fref When the frequency is , the output signal frequency of the YTO module U3 is locked at the locking frequency Fo , the RF output terminal outputs the locking frequency Fo signal.

[0072] Preferably, Figure 4 As shown, the main loop circuit includes an amplifier module U7 connected between the first filter module U6 and the second mixer module U8, the output end of the first filter module U6 is connected to the input end of the amplifier module U7, the output end of the amplifier module U7 is connected to the second input end of the second mixer module U8, and the amplifier module U7 is used to amplify the filtered signal to form a signal IF 1. The second mixer U8 is used to Fs 2 and signal IF 1 Mixing to form a signal IF 2 is input to the second input terminal of the first phase detector module U1.

[0073] In this example, the first-stage offset loop circuit realizes a low-phase noise, low-spurious, high-frequency resolution signal with a certain bandwidth. Its main function is to shift the output frequency spectrum, and then continue to shift the signal spectrum through the second-stage offset loop circuit. The purpose of the second-stage offset loop circuit is also to achieve a frequency signal with low phase noise, but the bandwidth of the output frequency is widened, that is, the frequency coverage achieved by the second-stage offset loop circuit is wider than that of the first-stage offset loop circuit. Then, it is changed to a fixed frequency in the main loop circuit for phase detection to achieve YTO loop locking. The YTO module U3 is generally a broadband oscillator greater than one octave. Through this multi-stage spectrum shifting, without using a frequency divider, the purpose is to minimize the phase noise deterioration and realize the entire YTO output of a low phase noise and wide frequency range signal. Among them, the local oscillator signal of the second offset loop circuit is provided by the clock circuit as a reference signal, and the reference signal will also determine the final phase noise output of the YTO. Therefore, the reference signal is also an ultra-low phase noise reference signal, and according to the output frequency range of the YTO, the number of local oscillator frequencies can be appropriately increased to achieve the purpose of frequency coverage.

[0074] As an optional implementation of the second offset loop circuit, Figure 5 As shown, it includes an attenuator module U9, a second phase detector module U10, a second loop module U11, a first VCO module U12, a second coupler module U13, a third mixer module U14, a second filter U15, etc. Specifically, the control circuit is connected to the attenuator module U9 in the second offset loop circuit, and is used to control the attenuation of the attenuator module U9, that is, to control the reference signal Ff of power.

[0075] Among them, the input end of the attenuator module U9 is connected to the reference signal provided by the clock circuit Ff , used for the reference signal Ff After the predetermined attenuation amount is attenuated, the signal is formed. Fs 6 and output; the first input end of the second phase detector module U10 is connected to the output end of the attenuator module U9, and the second input end is connected to the output end of the second filter U15, for obtaining a signal Fs 6 and the signal output after filtering by the second filter U15 IF 3 phase difference and output.

[0076] The input end of the second loop module U11 is connected to the output end of the second phase detector module U10, and is used to convert the phase difference output by the second phase detector module U10 into a fixed voltage value; the input end of the first VCO module U12 is connected to the output end of the second loop module U11, and is used to lock the frequency of the output signal according to the voltage value provided by the second loop module U11; the input end of the second coupler module U13 is connected to the output end of the first VCO module U12, and the first output end of the second coupler module U13 is connected to the first input end of the second mixer module U8, and is used to divide the signal output by the first VCO module U12 into two paths with equal frequencies, one path being used as the signal Fs 2 is sent to the second mixer module U8; the first input end of the third mixer module U14 is connected to the second output end of the second coupler module U13, and the second input end of the third mixer module U14 is connected to the frequency signal output by the first offset loop circuit Fs 3. The output end of the third mixer module U14 is connected to the input end of the second filter U15, and is used to output the signal according to the other output signal of the second coupler module U13 and the signal Fs 3 is mixed and then input to the second filter U15, the second filter U15 is used to filter the signal mixed by the third mixer module U14 to form a signal IF 3 is output to the second phase detector module U10; when the signal IF The frequency of 3 is equal to the signal Fs 6, the signal Fs 2 frequency lock.

[0077] As an optional implementation of the first offset loop circuit, Figure 6 As shown, the first offset loop circuit includes a DDS module U16, a third phase detector module U17, a third loop module U18, a second VCO module U19, a third coupler module U20, a fourth mixer module U21, a third filter module U22, etc.

[0078] The input of DDS module U16 is connected to the reference signal provided by the clock circuit Fs5, used to output signals according to the following formula IF 4:

[0079] ;

[0080] In the formula, FTW is the frequency control word sent externally, and N is the number of bits of the frequency control word of the DDS module U16. Specifically, the control circuit is connected to the DDS module U16 in the first offset loop circuit, and is used to control the DDS module U16 to generate a signal of a required frequency.

[0081] The first input end of the third phase detector module U17 is connected to the output end of the DDS module U16, and the second input end is connected to the output end of the third filter module U22, so as to obtain the signal IF 4 and the signal output after filtering by the third filtering module U22 IF 5 and output it; the input end of the third loop module U18 is connected to the output end of the third phase detector module U17, and is used to convert the phase difference output by the third phase detector module U17 into a fixed voltage value; the input end of the second VCO module U19 is connected to the output end of the third loop module U18, and is used to lock the frequency of the output signal according to the voltage value provided by the third loop module U18.

[0082] The input end of the third coupler module U20 is connected to the output end of the second VCO module U19, and is used to divide the signal output by the second VCO module U19 into two paths with equal frequencies, one of which is used as the signal Fs 3 is sent to the second offset loop circuit; the first input end of the fourth mixer module U21 is connected to the second output end of the third coupler module U20, and the second input end of the fourth mixer module U21 is connected to the reference signal provided by the clock circuit Fs 4. The output end of the fourth mixer module U21 is connected to the input end of the third filter module U22, and is used to output the signal according to the other output signal of the third coupler module U20 and the signal Fs 4 is mixed and then input to the third filter module U22, the third filter module U22 is used to filter the signal mixed by the third coupler module U20 to form a signal IF 5 is output to the third phase detector module U17; when the signal IF The frequency of 5 is equal to the signal IF 4 frequency, the signal Fs 3 frequency lock.

[0083] The main purpose of the first offset loop circuit is to achieve a low-phase noise, low-spurious, high-frequency resolution signal with a certain bandwidth through a conversion loop. By utilizing the excellent near-end phase noise of the local oscillator port of the mixer (fourth mixer module U21), the far-end phase noise performance of the master oscillator (second VCO module U19) is brought into play by selecting a large loop bandwidth, while avoiding the phase noise degradation caused by the use of an N-divider. The loop bandwidth is only related to the near-end phase noise of the local oscillator port of the mixer (fourth mixer module U21). This method solves the problems related to the entire phase noise area and achieves extremely low output phase noise within the entire frequency deviation range. The DDS module U16 has a relatively high frequency resolution and good near-end phase noise. Therefore, through the mixer conversion loop in the first offset loop circuit, the second VCO module U19 finally outputs a certain narrowband high-frequency resolution, low phase noise signal. Fs 3 is given to the second offset loop circuit.

[0084] The second offset loop circuit has a similar function to the first offset loop circuit, and its purpose is also to achieve a frequency signal with low phase noise, but the bandwidth of the output frequency is widened by changing the reference phase detection frequency, that is, the frequency coverage achieved by the second offset loop circuit is wider than that of the first offset loop circuit. That is, the signal with low phase noise and high frequency resolution generated by the first offset loop circuit Fs 3 is used as the offset local oscillator in the second offset loop circuit, that is, the local oscillator signal of the third mixer module U14 in the second offset loop circuit, by changing the reference phase detection frequency (that is, by changing the reference signal output by the clock circuit through the control circuit of Ff frequency), the output frequency range of the first VCO module U12 in the second offset loop circuit is widened. At the same time, because the near-end phase noise of the reference signal is good, the local oscillator signal phase noise of the local oscillator port of the third mixer module U14 is good, and the far-end phase noise of the first VCO module U12 is good, the output signal of the second offset loop circuit is realized. Fs 2. The phase noise is good and the frequency range is wide. This signal continues to be used as the offset loop local oscillator signal to be given to the conversion loop in the main loop circuit as a reference.

[0085] Specifically, Figure 7 The figure shows an example of the overall scheme of the frequency source circuit of this embodiment, in which the main loop circuit adopts the following Figure 4 In the preferred example shown, the first offset loop adopts the following Figure 6 In the example shown, the second offset loop uses Figure 5 In the example shown, the signal output by the third coupler module U20 of the first offset loop circuit Fs 3 is fed to the second input end of the third mixer module U14 of the second offset loop circuit, and the signal output by the second coupler module U13 of the second offset loop circuit Fs2 is fed to the first input terminal of the second mixer module U8 of the main loop circuit.

[0086] The frequency planning method based on this circuit is as follows:

[0087] (1) Generate reference signal through clock circuit Ff , reference signal Fref , reference signal Fs 1. Reference signal Fs 4. Reference signal Fs 5.

[0088] As a preferred embodiment of this invention, for a low-frequency clock reference signal, such as a reference signal Ff , reference signal Fref , generated by the nonlinear transmission line NLTL frequency multiplication of the clock circuit, the phase noise degradation is lower than that of the diode frequency multiplication, and the spurious and harmonics are filtered out by the corresponding filter, so the output low-frequency clock reference signal has lower phase noise and a purer spectrum. For high-frequency clock reference signals, such as reference signals Fs 1. Reference signal Fs 4. Reference signal Fs 5, generated by the phase-locked dielectric oscillator PDRO of the clock circuit. PDRO has a higher Q value, lower phase noise and purer spectrum than the traditional point frequency signal, so it is most suitable as a point frequency reference signal.

[0089] The clock circuit is controlled by the control circuit to change the frequency of the low-frequency clock reference signal, that is, the reference signal Ff The output frequency can be changed by the control circuit, that is, the low-frequency reference frequency can be switched. The high-frequency clock reference signal can also be switched, that is, the reference signal Fs The output of 1 can be frequency-changed by the control circuit, that is, the high-frequency reference frequency can be switched.

[0090] In order to maximize the frequency utilization of the conversion loop of the main loop circuit and prevent the local oscillator signal of the first mixer module U5 from leaking to the final RF output end to cause spurious deterioration, and at the same time, the general narrowband VCO has better far-end phase noise, so the required bandwidth can be determined according to the bandwidth of the first VCO module U12 Fs 1, so the bandwidth of the first VCO module U12 is set to 1000MHz, that is, Fs 2 output bandwidth is 1GHz. When mixing, the characteristics of the two sidebands of the corresponding mixer can be used to reduce the number of local oscillator frequencies. Therefore, the second mixer module U8 can be driven by either high local oscillator or low local oscillator. Fs The number of frequency points NFs1 of 1 is determined by the following formula:

[0091]

[0092] In the formula, Fo MAX Indicates the maximum frequency output by the YTO module. Fo MIN Indicates the minimum frequency output by the YTO module U3, in MHz. That is, by rounding up, it can be concluded that when the frequency output by the YTO module U3 is 4GHz~8GHz, NFs 1=2, that is, at least 2 reference signals are required Fs 1. If it is not rounded, calculate NFs 1 is a decimal. When rounded up, it means that the frequency range of the required frequency points is greater than the frequency range of the YTO module U3 output. NFs For example, 1=2, the two frequency points of the first reference frequency Fs 1_1 and Fs 1_2 is:

[0093]

[0094] Reference signal Fs 1 needs to set two frequency points, 3 GHz and 5 GHz. Since the phase noise of the conversion loop phase-locked loop output is mainly affected by the phase noise of the local oscillator port of the first mixer module U5, for the first mixer module U5, the reference signal Fs 1 The corresponding 5GHz and 3GHz far-end phase noise should be good. Then confirm that the intermediate frequency range of the first mixer module U5 after down-conversion is 1GHz~3GHz, that is, the signal IF 1. Reference frequency Fref The frequency of the second mixer module U8 is set to 500MHz, and the local oscillator frequency of the second mixer module U8 is 1.5GHz~2.5GHz, that is, the signal Fs 2 frequency range. Since DDS has low spurious and good phase noise when outputting narrowband signals, DDS is generally used only with narrowband signals. When the second offset loop circuit in this example uses a 100MHz bandwidth signal, it is necessary to switch the phase detector frequency to convert the 100MHz bandwidth signal into a 1GHz bandwidth signal. That is, the reference frequency of the second phase detector module U10 requires several frequency points to widen the 100MHz bandwidth signal to 1GHz bandwidth, and the reference signal can be obtained. Ff The minimum frequency required is 5 frequency points. Fs 3 is 1.9GHz~2GHz. The performance is best when the DDS module U16 outputs 100MHz~200MHz. At this time, the output frequency phase noise is good and the spurious is also low, so the reference signal can be determined. Fs4 is 2.1GHz, the output of the second VCO module U19 is 1.9GHz~2GHz, and through the conversion loop, the frequency 100MHz~200MHz output by the DDS module U16 corresponds to the output 1.9GHz~2GHz of the second VCO module U19.

[0095] like Figure 6 In the example shown, the implementation process is that the clock circuit first generates a reference signal Fref 500MHz, reference signal Fs 4 is 2.1GHz, reference signal Fs 5 is 1GHz signal, reference signal Fs 1 is 3GHz / 5GHz, when the YTO module U3 needs to output a signal greater than 6GHz, the reference signal Fs 1 frequency = 5GHz, when the YTO module U3 output frequency is less than or equal to 6GHz signal, the reference signal Fs 1 frequency = 3GHz, specific reference signal Fs 1 The frequency switching is generated by the control circuit and the clock circuit.

[0096] (2) According to the locking frequency to be output by the YTO module Fo Calculate the control current input to the coarse tuning input of the YTO module through the YTO drive circuit I , so that the frequency of the YTO module output signal is at the locked frequency Fo Nearby / preset range.

[0097] Specifically, the control circuit controls the YTO drive circuit to give the YTO module U3 a corresponding locking frequency Fo Control current under I , and at the same time control the attenuator module U9 to open the channel of the corresponding frequency band, and control the DDS module U16 to output a specific frequency, and control the reference signal provided by the clock circuit Fs 1Specific frequency, specific output formula is as follows:

[0098]

[0099] Among them, ± represents the values ​​of different frequency bands.

[0100] (3) The first offset loop circuit is used according to the reference signal Fs 5 and reference signal Fs 4. Form and output a predetermined narrowband low phase noise frequency signal Fs 3 to the second offset loop circuit.

[0101] Reference signal Fs 5 1GHz enters DDS module U16, calculates the output signal required by DDS module U16IF 4, and then calculate the frequency control word according to the following formula FTW , through the control circuit to send the specific frequency control word to the DDS module U16 FTW , so that the DDS module U16 outputs the signal of the required frequency IF 4:

[0102]

[0103] In this formula, N The number of bits of the frequency control word of the DDS module U16. IF 4 Enter the third phase detector module U17, reference signal Fs 4 2.1GHz enters the fourth mixer module U21. The second VCO module U19 will output a frequency signal when it is not locked and enter the input end of the third coupler U20. The frequencies of the two output signals of the third coupler U20 are equal. One way is used to transmit to the second offset loop, and the other way enters the fourth mixer module U21 and the reference signal. Fs 4 is mixed to generate an intermediate frequency signal, which is then filtered out by the third filter module U22 to form a signal after the intermodulation signal generated by the mixing is removed. IF 5. The output frequency of the second VCO module U19 is adjusted by the phase-locked loop feedback structure formed by the third coupler module U20, the fourth mixer module U21, the third filter module U22, and the third phase detector module U17 in the first offset loop circuit until the signal IF 4Frequency equals signal IF 5 frequency, 100MHz~200MHz, the third phase detector module U17 output signal IF 4 and signal IF 5 phase difference to the third loop module U18, converted into a fixed voltage value and provided to the input end of the second VCO module U19. At this time, the phase-locked loop in the first offset loop circuit is locked. At this time, the second VCO module U19 outputs a signal Fs 3 The frequency is fixed to 1.9GHz~2GHz, and enters the third mixer module U14 in the second offset loop circuit after passing through the third coupler module U20. Fs The phase noise of 3 is very low, and the phase noise within the loop bandwidth is close to the reference signal Fs 4 phase noise, and the far-end phase noise of the second VCO module U19 outside the loop bandwidth, so the signal Fs 3 is a signal with low phase noise, low spurious and high frequency accuracy.

[0104] (4) The second offset loop circuit is used according to the reference signal Ff and the first offset loop circuit delivers a signal Fs3. Form and output a frequency range wider than the signal Fs Low phase noise frequency signal of 3 Fs 2 to the first input terminal of the second mixer module U8.

[0105] Signal Fs 3 1.9GHz~2GHz is used as the reference signal of the third mixer module U14. The clock circuit pre-sets the reference signal through the control circuit. Ff Switch to the required frequency and output the signal after passing through the attenuator module U9 Fs 6. Reference signal Ff and signal Fs 6Equal frequency, signal Fs 6 enters the input end of the second phase detector module U10. The first VCO module U12 outputs a frequency signal when unlocked / locked, and enters the input end of the second coupler U13. The frequencies of the two output signals of the second coupler U13 are equal. One path is used to transmit to the second mixer module U8 of the main loop, and the other path enters the third mixer module U14 and the signal Fs 3 is mixed to generate an intermediate frequency signal, which is then filtered out by the second filter module U15 to form a signal after the intermodulation signal generated by the mixing is removed. IF 3. The output signal frequency of the first VCO module U12 is adjusted by the phase-locked loop feedback structure formed by the second coupler module U13, the third mixer module U14, the second filter module U15, and the second phase detector module U10 in the second offset loop circuit until the signal IF 3 Frequency and Signal Fs 6 The frequencies are equal, and the second phase detector module U10 outputs a signal IF 3 and signal Fs The second loop module U11 converts the phase difference into a fixed voltage value and gives it to the input end of the first VCO module U12. At this time, the phase-locked loop is locked. At this time, the output signal of the first VCO module U12 is Fs 2 is locked to 1.5GHz~2.5GHz. At this point, the frequency of the second offset loop circuit is locked. Due to the use of a conversion loop, the output signal is Fs 2 The phase noise of the output is very low, and the phase noise within the loop bandwidth is close to the reference signal Fs 3 Phase noise, outside the loop bandwidth is the far-end phase noise of the first VCO module U12, so the signal Fs 2 is a high frequency precision signal with ultra-low phase noise and ultra-low spurious.

[0106] (5) When the YTO module is unlocked, the control current of the coarse tuning input terminal is I The output is locked at the frequency FoThe first coupler module U4 divides the output signal of the YTO module into two signals with equal frequencies, one of which is used as the signal output from the final RF output terminal, and the other output signal enters the first mixer module U5. The first mixer module U5 generates a reference signal according to the reference signal. Fs 1 and another output signal of the first coupler module U4 are mixed to generate an intermediate frequency signal, the first filter U6 filters out the intermodulation signal in the intermediate frequency signal and then outputs it, and the amplifier module U7 is used to amplify the signal output by the first filter U6 to form a signal IF 1 1GHz~3GHz, the second mixer U8 according to the signal Fs 2 and signal IF 1 Mixing to form a signal IF 2 500MHz is input to the second input terminal of the first phase detector module U1, and the first phase detector module U1 obtains the reference signal Fref and signal IF 2 and outputs it. The first loop module U2 converts the phase difference output by the first phase detector module U1 into a fixed voltage value and provides it to the fine tuning input of the YTO module. The output frequency of the YTO module U3 is adjusted through the phase-locked loop feedback structure formed by the first coupler module U4, the first mixer module U5, the first filter module U6, the amplifier module U7, the second mixer module U8, and the first phase detector module U1 in the main loop circuit until the signal IF 2 has a frequency equal to the reference signal Fref When the frequency is , the output signal frequency of the YTO module U3 is locked at the locking frequency Fo , 4GHz~8GHz, the RF output output lock frequency Fo The phase noise of the final output signal is very low, and the phase noise within the loop bandwidth is close to the reference signal. Fs 1 and signal Fs 2 phase noise value, the loop bandwidth is the far-end phase noise of the YTO module U3, so the locked frequency Fo The signal is an ultra-low phase noise, low spurious and high frequency accuracy signal.

[0107] In this embodiment, the phase detector module can be replaced by an analog phase detector, that is, the analog phase detector has low additional phase noise. At the same time, the high-frequency clock reference signal is generated by the PDRO in the clock circuit, and the low-frequency clock reference signal is generated by the NLTL frequency multiplication. Therefore, these clock reference signals have ultra-low phase noise. Ultimately, after the YTO frequency source is locked, the overall phase noise reaches the best, which is also within the scope of protection of the present invention.

[0108] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application.

Claims

1. Ultra-low phase noise frequency source circuit based on YTO, characterized in that: It includes a main loop circuit, a first offset loop circuit, a second offset loop circuit, a clock circuit, and a YTO driving circuit; The main loop circuit includes: The first phase detector module U1 has a first input terminal connected to a reference signal provided by a clock circuit. Fref , the output end is connected to the input end of the first loop module U2; A YTO module U3, whose fine tuning input terminal is connected to the output terminal of the first loop module U2, and whose coarse tuning input terminal is connected to the YTO driving circuit; A first coupler module U4, whose input end is connected to the output end of the YTO module U3, and whose first output end is a radio frequency output end; The first mixer module U5 has a first input terminal connected to a reference signal provided by a clock circuit. F 1. The second input end is connected to the second output end of the first coupler module U4, and the output end of the first mixer module U5 is connected to the input end of the first filter module U6; A second mixer module U8, wherein a first input end thereof is connected to the output of the second offset loop circuit, a second input end thereof is connected to the output end of the first filter module U6, and an output end of the second mixer module U8 is connected to a second input end of the first phase detector module U1; The first offset loop circuit is used to provide a reference signal according to the reference signal provided by the clock circuit. F 5 and reference signal F 4. Form and output a predetermined narrowband low phase noise frequency signal F 3 to the second offset loop circuit; The second offset loop circuit is used to generate a reference signal according to the reference signal provided by the clock circuit. F and the first offset loop circuit delivers a signal F 3. Form and output a frequency range wider than the signal F Low phase noise frequency signal of 3 F 2 to the first input terminal of the second mixer module U8; The first phase detector module U1 is used to obtain the phase difference of the signals at its two input terminals and output it. The first loop module U2 is used to convert the phase difference output by the first phase detector module U1 into a fixed voltage value and provide it to the fine tuning input terminal of the YTO module U3. The YTO module U3 is used to adjust the phase difference according to the control current of the YTO drive circuit. I Output at locked frequency Fo The first coupler module U4 is used to divide the output signal of the YTO module U3 into two signals with equal frequencies and output them from the first output end and the second output end. The first mixer module U5 is used to generate a reference signal according to the reference signal. F 1 and the signal output from the second output end of the first coupler module U4 are mixed to generate an intermediate frequency signal, the first filter U6 is used to filter out the intermodulation signal in the intermediate frequency signal and then output it, and the second mixer U8 is used to generate an intermediate frequency signal according to the signal F 2 and the first filter U6 output signal are mixed to form a signal IF 2 is input to the second input terminal of the first phase detector module U1; when the signal IF 2 has a frequency equal to the reference signal Fref When the frequency is , the output signal frequency of the YTO module U3 is locked at the locking frequency Fo , the RF output output lock frequency Fo signal.

2. The YTO-based ultra-low phase noise frequency source circuit according to claim 1, characterized in that: The main loop circuit also includes an amplifier module U7 connected between the first filter module U6 and the second mixer module U8. The output end of the first filter module U6 is connected to the input end of the amplifier module U7. The output end of the amplifier module U7 is connected to the second input end of the second mixer module U8. The amplifier module U7 is used to amplify the filtered signal to form a signal IF 1. The second mixer U8 is used to F 2 and signal IF 1 Mixing to form a signal IF 2 is input to the second input terminal of the first phase detector module U1.

3. The YTO-based ultra-low phase noise frequency source circuit according to claim 1, characterized in that: The second offset loop circuit includes: Attenuator module U9, whose input is connected to the reference signal provided by the clock circuit F , used for the reference signal F After the predetermined attenuation amount is attenuated, the signal is formed. F 6 and output; The second phase detector module U10 has a first input end connected to the output end of the attenuator module U9 and a second input end connected to the output end of the second filter U15, for obtaining a signal F 6 and the signal output after filtering by the second filter U15 IF 3 phase difference and output; The second loop module U11, whose input end is connected to the output end of the second phase detector module U10, is used to convert the phase difference output by the second phase detector module U10 into a fixed voltage value; A first VCO module U12, whose input end is connected to the output end of the second loop module U11, and is used to lock the frequency of the output signal according to the voltage value provided by the second loop module U11; The second coupler module U13 has an input end connected to the output end of the first VCO module U12, and a first output end of the second coupler module U13 is connected to a first input end of the second mixer module U8, and is used to divide the signal output by the first VCO module U12 into two paths with equal frequencies, one of which is used as a signal F 2 is sent to the second mixer module U8; The third mixer module U14 has a first input end connected to the second output end of the second coupler module U13, and a second input end of the third mixer module U14 is connected to the frequency signal output by the first offset loop circuit. F 3. The output end of the third mixer module U14 is connected to the input end of the second filter U15, and is used to output the signal according to the other output signal of the second coupler module U13 and the signal F 3 is mixed and then input to the second filter U15, the second filter U15 is used to filter the signal mixed by the third mixer module U14 to form a signal IF 3 output to the second phase detector module U10; when signal IF The frequency of 3 is equal to the signal F 6, the signal F 2 frequency lock.

4. The YTO-based ultra-low phase noise frequency source circuit according to claim 1, characterized in that: The first offset loop circuit includes: The DDS module U16 has its input connected to the reference signal provided by the clock circuit. F 5, used according to the formula Output signal IF 4, where FTW It is the frequency control word sent externally. N The number of bits of the frequency control word of the DDS module U16; The third phase detector module U17 has a first input terminal connected to the output terminal of the DDS module U16, and a second input terminal connected to the output terminal of the third filter module U22, for obtaining a signal IF 4 and the signal output after filtering by the third filtering module U22 IF 5 phase difference and output; A third loop module U18, whose input end is connected to the output end of the third phase detector module U17, is used to convert the phase difference output by the third phase detector module U17 into a fixed voltage value; A second VCO module U19, whose input end is connected to the output end of the third loop module U18, is used to lock the frequency of the output signal according to the voltage value provided by the third loop module U18; The third coupler module U20, whose input end is connected to the output end of the second VCO module U19, is used to divide the signal output by the second VCO module U19 into two paths with equal frequencies, one of which is used as the signal F 3 is sent to the second offset loop circuit; The fourth mixer module U21 has a first input end connected to the second output end of the third coupler module U20, and a second input end of the fourth mixer module U21 is connected to the reference signal provided by the clock circuit. F 4. The output end of the fourth mixer module U21 is connected to the input end of the third filter module U22, and is used to output the signal according to the other output signal of the third coupler module U20 and the signal F 4 is mixed and then input to the third filter module U22, the third filter module U22 is used to filter the signal mixed by the third coupler module U20 to form a signal IF 5 is output to the third phase detector module U17; when signal IF The frequency of 5 is equal to the signal IF 4, the signal F 3 frequency lock.

5. The YTO-based ultra-low phase noise frequency source circuit according to claim 1, characterized in that: The invention also includes a control circuit connected to the YTO drive circuit, the clock circuit, the first offset loop circuit, and the second offset loop circuit respectively, and the control circuit is used to control the YTO drive circuit to adjust the control current I , and is used to switch the frequency of the reference signal provided by the clock circuit.

6. The YTO-based ultra-low phase noise frequency source circuit according to claim 1, characterized in that: Reference signal F , reference signal Fref The reference signal is generated by the nonlinear transmission line NLTL of the clock circuit. F 1. Reference signal F 4. Reference signal F 5 is generated by the phase-locked dielectric oscillator PDRO of the clock circuit.

7. A frequency planning method, characterized in that: The method is implemented by using the YTO-based ultra-low phase noise frequency source circuit as described in any one of claims 1 to 6, and the method comprises the steps of: Generate reference signal through clock circuit F , reference signal Fref , reference signal F 1. Reference signal F 4. Reference signal F 5; According to the locking frequency to be output by YTO module U3 Fo Calculate the control current input to the coarse tuning input of the YTO module U3 through the YTO drive circuit I , so that the frequency of the output signal of the YTO module U3 is at the locking frequency Fo within the preset range; The first offset loop circuit is used to adjust the reference signal F 5 and reference signal F 4. Form and output a predetermined narrowband low phase noise frequency signal F 3 to the second offset loop circuit; The second offset loop circuit is used to adjust the reference signal F and the first offset loop circuit delivers a signal F 3. Form and output a frequency range wider than the signal F Low phase noise frequency signal of 3 F 2 to the first input terminal of the second mixer module U8; The YTO module U3 is controlled by the coarse tuning input when it is unlocked. I The output is locked at the frequency Fo The first coupler module U4 divides the output signal of the YTO module U3 into two signals with equal frequencies, one of which is used as the signal output from the final RF output terminal, and the other output signal enters the first mixer module U5. The first mixer module U5 generates a reference signal according to the reference signal. F 1 and another output signal of the first coupler module U4 are mixed to generate an intermediate frequency signal, the first filter U6 filters out the intermodulation signal in the intermediate frequency signal and then outputs it, and the second mixer U8 generates an intermediate frequency signal according to the signal F 2 and the first filter U6 output signal are mixed to form a signal IF 2 is input to the second input terminal of the first phase detector module U1, and the first phase detector module U1 obtains the reference signal Fref and signal IF 2 and outputs it, the first loop module U2 converts the phase difference output by the first phase detector module U1 into a fixed voltage value and provides it to the fine tuning input terminal of the YTO module U3; Until the signal IF 2 has a frequency equal to the reference signal Fref When the frequency is , the output signal frequency of the YTO module U3 is locked at the locking frequency Fo , the RF output output lock frequency Fo signal.

8. The frequency planning method according to claim 7, characterized in that: Reference signal F The number of frequencies of 1 NFs 1 is determined by the following formula: In the formula, Fo MAX Indicates the maximum frequency output by the YTO module U3, Fo MIN Indicates the minimum frequency output by the YTO module U3, in MHz.

9. The frequency planning method according to claim 8, characterized in that: When the frequency of the YTO module output U3 is 4GHz~8GHz, NFs 1=2, that is, at least 2 reference signals are required F The frequency of 1 is expressed as F 1_1 and F 1_2: 。

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