Signal decoding method and system, medium, equipment and program product

Abstract

The invention provides a signal decoding method and system, a computer readable storage medium, electronic equipment and a computer program product, and relates to the technical field of communication, and the method comprises the steps: obtaining a received signal, and carrying out the modulation and demodulation of the received signal, and obtaining soft bit information; the received signal is a signal generated through finite field linear block code coding and low-density parity check coding cascade coding; performing belief propagation iterative decoding of new air interface low-density parity check on the soft bit information to obtain a code word corresponding to a low-density parity check mother code; performing bit flipping hard decision decoding on the codeword corresponding to the low-density parity check mother code to obtain a finite field linear block code codeword; and performing finite field linear block code hard decision decoding on the finite field linear block code codeword to obtain information bits after receiving signal decoding. According to the method, the success rate of finite field linear block code hard decision decoding can be increased, an error code platform in a short code scene is remarkably reduced, and decoding time delay is effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a signal decoding method, system, medium, device and program product. Background Art

[0002] Currently, satellite communication technology plays a key role in the global communication network due to its wide coverage and accessibility to remote areas. Geostationary satellite (GEO) satellites can provide stable communication coverage due to their fixed position relative to the earth's surface.

[0003] In the GEO satellite communication system, since the GEO satellite is about 35,786 kilometers away from the earth's surface, there is a significant propagation delay in the signal in the uplink (ground to satellite) and downlink (satellite to ground), which seriously affects the performance of the real-time communication system. This delay is particularly prominent in application scenarios that require fast response, such as voice communication, video conferencing, etc. For the Hybrid Automatic Repeat reQuest (HARQ) mechanism, they correct errors in transmission by requesting retransmission, which is particularly important for maintaining the reliability of communication. However, the GEO satellite communication system can only transmit once when the HARQ mechanism is disabled. At present, there is an error platform problem in the single transmission of the short code scenario (the error platform refers to the error rate in the low error rate area no longer significantly decreases with the increase of the signal-to-noise ratio), that is, in the low error rate area, the error rate no longer significantly decreases with the increase of the signal-to-noise ratio. Therefore, how to achieve high-reliability satellite communication is a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0004] The purpose of the present application is to provide a signal decoding method, system, computer-readable storage medium, electronic device and computer program product, which significantly alleviate the error platform problem.

[0005] In order to solve the above technical problems, the present application provides a signal decoding method, and the specific technical solution is as follows:

[0006] Acquire a received signal, and obtain soft bit information after modulating and demodulating the received signal; the received signal is a signal generated by concatenating finite field linear block code encoding and low density parity check code encoding;

[0007] Performing a belief propagation iterative decoding of a new air interface low-density parity check on the soft bit information to obtain a codeword corresponding to a low-density parity check mother code;

[0008] Performing bit-flip hard decision decoding on the codeword corresponding to the low-density parity check mother code to obtain a finite field linear block code codeword;

[0009] Finite field linear block code hard decision decoding is performed on the finite field linear block code codeword to obtain decoded information bits of the received signal.

[0010] Optionally, performing confidence propagation iterative decoding of a new air interface low-density parity check on the soft bit information to obtain a codeword corresponding to a low-density parity check mother code includes:

[0011] A check matrix is ​​represented by a bipartite graph including variable nodes and check nodes; for each non-zero element in the check matrix, an edge is added to the bipartite graph to connect the corresponding check node and variable node;

[0012] Initializing the variable node using the soft bit information;

[0013] Passing the information of the variable node to the check node, and updating the check node information of the check node;

[0014] The check node information of the check node is transferred to the variable node to update the information of the variable node, thereby completing one iteration;

[0015] The soft bit information in the variable node is verified by using a hard decision check equation; wherein each row of the check matrix represents one of the check equations;

[0016] If all the check equations pass, the codeword corresponding to the low-density parity check mother code is output;

[0017] If the check equations are not all passed, the information between the variable node and the check node is updated until the maximum number of iterations is met or the check equations are all passed, and the codeword corresponding to the low-density parity check mother code is output.

[0018] Optionally, performing bit-flip hard decision decoding on the codeword corresponding to the low-density parity check mother code to obtain a finite field linear block code codeword includes:

[0019] Step 1: Obtain a mother code matrix corresponding to a mother code from the check matrix;

[0020] Step 2: calculating a syndrome according to the codeword and the mother code matrix, and applying the syndrome to calculate the number of bits of the codeword that do not satisfy the check equation;

[0021] Step 3: If the number of bits is not less than the set value, flip the bits in the codeword that do not satisfy the check equation to obtain a new codeword, and complete an iteration; if the number of bits is less than the set value, proceed to step 6;

[0022] Step 4: Determine whether the current number of iterations meets the maximum number of iterations; if not, proceed to step 5; if yes, proceed to step 6;

[0023] Step 5: Use the new codeword to replace the codeword and execute step 2;

[0024] Step 6: Output the finite field linear block code codeword corresponding to the bit length in the codeword.

[0025] Optionally, calculating a syndrome according to the codeword and the mother code matrix, and applying the syndrome to calculate the number of bits of the codeword that do not satisfy the check equation includes:

[0026] Calculate a syndrome according to the codeword and a transposed matrix of the mother code matrix;

[0027] The number of bits of the codeword that do not satisfy the check equation is calculated according to the product of the syndrome and the mother code matrix.

[0028] Optionally, before flipping the bits in the codeword that do not satisfy the check equation to obtain a new codeword, the method further includes:

[0029] The set value is configured according to a set error correction amount.

[0030] Optionally, performing finite field linear block code hard decision decoding on the finite field linear block code codeword to obtain decoded information bits of the received signal includes:

[0031] The finite field linear block code codeword is subjected to finite field linear block code hard decision decoding using the generating polynomial used in the encoding process of the received signal, and when the number of bit errors in the finite field linear block code codeword is less than the set value, the decoded information bits of the received signal are obtained.

[0032] Optionally, the encoding process of the information bits includes:

[0033] Get information bits;

[0034] Determine the check bit length according to the length of the information bit and the finite field linear block code parameters; the finite field linear block code parameters include the total length of the finite field linear block code codeword, the information bit length and the maximum number of correctable error bits;

[0035] Obtaining a generating polynomial according to the check bit length;

[0036] Using the generator polynomial to perform finite field linear block code encoding on the information bits to obtain a finite field linear block code codeword;

[0037] The finite field linear block code codeword is NR low density parity check encoded to obtain a second codeword; the second codeword is used to generate the received signal.

[0038] The present application also provides a signal decoding system, comprising:

[0039] A signal receiving module, used for acquiring a received signal, modulating and demodulating the received signal to obtain soft bit information; the received signal is a signal generated by finite field linear block code encoding and low density parity check code concatenation encoding;

[0040] A first decoding module is used to perform a belief propagation iterative decoding of a new air interface low-density parity check on the soft bit information to obtain a codeword corresponding to a low-density parity check mother code;

[0041] A bit flip module, used for performing bit flip hard decision decoding on the codeword corresponding to the low-density parity check mother code to obtain a finite field linear block code codeword;

[0042] The second decoding module is used to perform finite field linear block code hard decision decoding on the finite field linear block code codeword to obtain the decoded information bits of the received signal.

[0043] The present application also provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the steps of the above-mentioned method when executed by a processor.

[0044] The present application also provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps of the above-mentioned method when calling the computer program in the memory.

[0045] The present application also provides a computer program product, including a computer program, which implements the steps of the signal decoding method described above when the computer program is executed.

[0046] The present application provides a signal decoding method, comprising: obtaining a received signal, modulating and demodulating the received signal to obtain soft bit information; the received signal is a signal generated by finite field linear block code encoding and low-density parity check code concatenation encoding; performing new air interface low-density parity check confidence propagation iterative decoding on the soft bit information to obtain a codeword corresponding to a low-density parity check mother code; performing bit flip hard decision decoding on the codeword corresponding to the low-density parity check mother code to obtain a finite field linear block code codeword; performing finite field linear block code hard decision decoding on the finite field linear block code codeword to obtain information bits after decoding of the received signal.

[0047] The present application performs bit-flip hard decision decoding on the codeword corresponding to the low-density parity check mother code during the decoding process, and the bit-flip hard decision decoding is performed before the hard decision decoding of the finite field linear block code, which can increase the success rate of the hard decision decoding of the finite field linear block code and significantly reduce the error platform in the short code scenario, so that it can achieve quasi-error-free performance, that is, 10^(-5) packet error rate. At the same time, the bit-flip hard decision decoding has a faster decoding convergence speed, can achieve better decoding performance within a smaller number of iterations, effectively reduce the decoding delay, and is suitable for communication systems with higher real-time requirements. At the same time, the flip hard decision decoding process has low implementation complexity, is easy to implement in hardware, and has good application prospects.

[0048] The present application also provides a signal decoding system, a computer-readable storage medium, an electronic device and a computer program product, which have the above-mentioned beneficial effects and are not described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0050] Figure 1 A schematic diagram of a base diagram provided in an embodiment of the present application;

[0051] Figure 2 A schematic diagram of a base graph BG#2 used in the NR LDPC encoding process provided in an embodiment of the present application;

[0052] Figure 3 A flow chart of a signal decoding method provided in an embodiment of the present application;

[0053] Figure 4 A schematic diagram of a bipartite graph provided in an embodiment of the present application;

[0054] Figure 5 Schematic diagram of performance curves of three encoding and decoding methods provided in the embodiments of the present application;

[0055] Figure 6 A schematic diagram of the structure of a signal decoding system provided in an embodiment of the present application;

[0056] Figure 7 A structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0058] The object information involved in this application, including but not limited to the object device information, object personal information, etc., and data, including but not limited to data used for analysis, stored data, displayed data, etc., are all information and data authorized by the object or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the laws, regulations and standards of relevant countries and regions.

[0059] The signal decoding method proposed in the present application can be used in the short code scenario of GEO (Geostationary satellite) satellite communication. In order to better understand the signal decoding process of the present application, the decoding object of the present application, that is, the encoding process of the received signal is first described below, which may include the following steps:

[0060] Step 1: Get information bits;

[0061] Step 2: Encode the information bits by finite field linear block code to obtain finite field linear block code codewords;

[0062] Step 3: Perform new air interface low density parity check encoding on the finite field linear block code to obtain a second codeword.

[0063] An information bit is the smallest unit used to represent information in data communication. Each bit represents a binary digit, that is, 0 or 1. When acquiring information bits, this embodiment continuously acquires information bits to meet communication transmission. For ease of understanding, this embodiment uses a k Represents information bits.

[0064] In the second step, the information bit a k Finite field linear block code encoding, namely BCH encoding (Bose-Chaudhuri-Hocquenghem code, finite field linear block code, an important type of error correction code). BCH code uses a specific generating polynomial to make the minimum Hamming distance of the encoded codeword d min =2t-1, so that t errors can be detected and corrected. Specifically, the following steps can be included:

[0065] A1: Determine the check bit length according to the length of the information bit and the finite field linear block code parameter;

[0066] A2: Obtaining a generating polynomial according to the check bit length;

[0067] A3: Using the generating polynomial to perform finite field linear block code encoding on the information bits to obtain finite field linear block code codewords.

[0068] The parameters of finite field linear block codes include the total length of the finite field linear block code codeword, the information bit length, and the maximum number of correctable error bits. The check bit length directly affects the selection of the generator polynomial. Different check bit lengths correspond to different generator polynomials. Information bit a k The length is k bits, the total length of the bit after BCH encoding is L bits, and the selected check bit length is Lk. The selected check bit length is about 6% of the BCH code length. Then the generating polynomial g(x) is obtained based on the check bit length. Finally, the generating polynomial g(x) is used to generate the information bit a with a length of k bits. k Perform BCH encoding to obtain a finite field linear block code word b with a length of L bits L .

[0069] For example, assuming that the information bit length is 924 bits, according to the BCH coding rule, some selectable check bit lengths Lk and the corresponding correctable error numbers t are shown in Table 1.

[0070] Table 1 Some selectable check bit lengths and correctable error numbers for 924 information bits

[0071]

[0072]

[0073] The selected check bit length accounts for about 6% of the total code length. In this embodiment, the check bit length is selected as 60 bits. Then, the corresponding generating polynomial g(x) can be obtained. The generating polynomial can be expressed as a binary sequence as follows: [1101101100100001010111011100101010000010001011100010010101101];

[0075] After that, the 924-bit information bit a can be converted into k Perform BCH encoding to obtain a finite field linear block code word b with a length of 984 bits L .

[0076] The parity check matrix of the New Radio Low-Density Parity-Check (NR LDPC) has a quasi-cyclic property and is constructed by a base graph (BG) and a corresponding shift factor. The base graph is also called a base matrix. The base matrix is ​​a smaller matrix that usually contains -1, 0, and positive integer elements. Among them, -1 represents an all-zero submatrix, indicating that in the corresponding parity-check matrix (PCM), this part is a submatrix composed entirely of zeros without any non-zero elements; 0 represents a unit matrix; and the positive integer p represents a unit matrix that is cyclically shifted right by p bits. The expansion factor Z is a positive integer used to expand the base matrix to the required size of the parity check matrix. Specifically, each element in the base matrix will be expanded into a Z×Z submatrix.

[0077] NR LDPC has two BGs such as Figure 1 See Figure 1 According to the BG division, NR LDPC can be regarded as a high-rate LDPC code, that is, the mother code is extended by parity check, where the O matrix is ​​an all-zero matrix, the I matrix is ​​a unit matrix, the A matrix corresponds to the system information bits, the B matrix corresponds to the system check bits, the matrix [AB] corresponds to the mother code, and the matrix [EI] corresponds to the extended parity check redundant bits.

[0078] The finite field linear block code codeword b L Through the new low-density parity check coding, a second codeword with a length of 2952 bits can be obtained, and the code rate of the NR LDPC code is R = 984 / 2952 = 1 / 3. At this time, according to the BG selection rule, if any of the following three conditions is met, BG#2 is selected, otherwise BG#1 is selected:

[0079] Condition 1: The length before encoding is no more than 3824 and the code rate R ≤ 0.67;

[0080] Condition 2: The length before encoding is not greater than 292;

[0081] Condition three: Bit rate R ≤ 0.25.

[0082] There is no limitation on how to obtain the check matrix. The check matrix can be obtained by first determining a base image and an extension factor, and then determining the check matrix according to the base image and the extension factor.

[0083] Specifically, the -1 element in the base graph is replaced by a zero matrix Z*Z, and the element p greater than or equal to 0 is replaced by a unit matrix Z*Z that is cyclically right shifted by p bits to obtain the NR LDPC check matrix H.

[0084] When performing NR LDPC coding, the selection of the base graph and the size of the expansion factor Z are determined according to the code rate R and the length of the codeword before coding L, where the code rate is the ratio of the length of the codeword before coding to the length of the final coded codeword, that is, R = L / N, where N is the final coded codeword length. According to the selection of BG and the size of Z, the check matrix H for this coding can be obtained. Finally, the codeword b of the finite field linear block code is converted into L After performing new air interface low-density parity check coding and code rate matching, a second codeword c having a length of N bits is obtained. N , and the second codeword is used to generate the received signal. Rate matching is used to adjust the number of encoded data bits to match the code rate of the transmission channel, including but not limited to duplication or deletion of bits to ensure that the number of transmitted data bits matches the code rate of the channel. Rate matching is usually performed after low-density parity check encoding to ensure that the encoding can adapt to different transmission conditions.

[0085] Select BG#2 and get the expansion factor Z as 104. The obtained BG#2 is as follows Figure 2 As shown. Figure 2 The check matrix H can be obtained by performing cyclic shift matrix expansion on BG#2 in the finite field linear block code. L Perform NR LDPC encoding to obtain a second codeword c with a length of 2952 bits N .

[0086] NR LDPC determines the size of the check matrix through the base graph and the expansion factor Z. The -1 element in BG is replaced by a Z*Z zero matrix, and the element p greater than or equal to 0 is replaced by a Z*Z unit matrix that is cyclically right shifted by p positions. The check matrix H of NR LDPC is obtained.

[0087] See also Figure 3 , Figure 3 A flow chart of a signal decoding method provided in an embodiment of the present application, the method comprising:

[0088] S101: Acquire a received signal, and modulate and demodulate the received signal to obtain soft bit information;

[0089] S102: Performing new air interface low-density parity check belief propagation iterative decoding on the soft bit information to obtain a codeword corresponding to a low-density parity check mother code;

[0090] S103: performing bit-flip hard decision decoding on the codeword corresponding to the low-density parity check mother code to obtain a finite field linear block code codeword;

[0091] S104: Perform finite field linear block code hard decision decoding on the finite field linear block code codeword to obtain decoded information bits of the received signal.

[0092] After acquiring the received signal, the received signal is modulated and demodulated to obtain soft bit information. Specifically, soft demodulation can be used, that is, digital signal demodulation based on software algorithm can be performed on the received signal, and the received signal can be sampled to convert the continuous signal into a discrete signal. The sampling frequency should satisfy the Nyquist sampling theorem to avoid signal distortion. Subsequently, the sampled signal is quantized to convert the continuous analog signal into a discrete digital signal.

[0093] Soft bit information is LLR (Log-Likelihood Ratio) information, which represents the logarithm of the probability ratio of a certain bit in the received signal being 1 or 0, and can be obtained by calculating the probability distribution of the received signal. Specifically, for the k-th bit, its LLR information can be calculated by comparing the distance between the received signal and the symbol set corresponding to the bit being 0 and 1 in the constellation diagram.

[0094] The received signal obtained in this embodiment is a signal generated by concatenating finite field linear block code encoding and low density parity check code encoding.

[0095] After that, the soft bit information is subjected to the belief propagation iterative decoding of the new air interface low-density parity check to obtain the codeword corresponding to the low-density parity check mother code. Specifically, the following steps may be included:

[0096] S1021: using a bipartite graph including variable nodes and check nodes to represent a check matrix; for each non-zero element in the check matrix, adding an edge in the bipartite graph to connect the corresponding check node and variable node;

[0097] S1022: Initialize the variable node using the soft bit information;

[0098] S1023: passing the information of the variable node to the check node, and updating the check node information of the check node;

[0099] S1024: passing the check node information of the check node to the variable node to update the information of the variable node, completing one iteration;

[0100] S1025: Verify the soft bit information in the variable node using a hard decision check equation; wherein each row of the check matrix represents a check equation; if all the check equations pass, proceed to S1026; if not all the check equations pass, proceed to S1027;

[0101] S1026: Outputting a codeword corresponding to the low-density parity check mother code;

[0102] S1027: Update the information between the variable node and the check node until the maximum number of iterations is met or all the check equations are passed, and then proceed to S1026.

[0103] The belief propagation decoding algorithm is an iterative decoding algorithm based on a graph model. Its core idea is to propagate information through message exchange between nodes, thereby gradually improving the estimation of the coded bits. The check matrix H of the NR LDPC code is represented by a bipartite graph. The bipartite graph is as follows: Figure 4 As shown, the upper part represents the check node, corresponding to the row of the check matrix, and the lower part represents the variable node, corresponding to the column of the check matrix. The corresponding position of the check matrix is ​​not 0. In the bipartite graph, there is an edge connecting the corresponding check node and the variable node. The check matrix represented by the bipartite graph can be:

[0104]

[0105] At the beginning of decoding, the LLR soft information r obtained by soft demodulation is used N Initialize the variable nodes, and then the information is iteratively updated between the variable nodes and the check nodes until the maximum number of iterations is reached or all check equations are satisfied, the iteration is terminated, and the hard decision outputs the codeword q corresponding to the low-density parity check mother code m The maximum number of iterations is not specifically limited here and can be set by those skilled in the art.

[0106] The check matrix H defines the relationship between codewords and check bits. Each row of the check matrix represents a check equation, and each column corresponds to a bit in the codeword.

[0107] Then, the code word q corresponding to the low-density parity check mother code is m Perform bit flip hard decision decoding to obtain a finite field linear block codeword. Specifically, the following steps may be included:

[0108] Step 1: Obtain a mother code matrix corresponding to a mother code from the check matrix;

[0109] Step 2: calculating a syndrome according to the codeword and the mother code matrix, and applying the syndrome to calculate the number of bits of the codeword that do not satisfy the check equation;

[0110] Step 3: If the number of bits is not less than the set value, flip the bits in the codeword that do not satisfy the check equation to obtain a new codeword, and complete an iteration; if the number of bits is less than the set value, proceed to step 6;

[0111] Step 4: Determine whether the current number of iterations meets the maximum number of iterations; if not, proceed to step 5; if yes, proceed to step 6;

[0112] Step 5: Use the new codeword to replace the codeword and execute step 2;

[0113] Step 6: Output the finite field linear block code codeword corresponding to the bit length in the codeword.

[0114] Get the matrix H corresponding to the mother code from the check matrix H m , calculate the syndrome according to the transposed matrix of the codeword and the mother code matrix, and then calculate the number of bits of the codeword that do not satisfy the check equation according to the product of the syndrome and the mother code matrix. m Calculate the syndrome s = q m *H m T , by calculating s*H m We can get the codeword q m The number of bits that do not satisfy the check equation. Calculate s*H m After that, we can get a vector whose length is the same as the codeword q m The length of is the same as that of , and the vector value of the Nth vector represents the number of bits that do not satisfy the check equation on the Nth bit position.

[0115] If the number of unsatisfied bits is not less than the set value, the bits that do not satisfy the check equation are flipped, that is, 0 is flipped to 1, and 1 is flipped to 0, to obtain a new codeword q′ m , one iteration is completed. The setting value is not specifically limited here, for example, it can be set to 3. If the setting value is too large, the error correction amount will be small, and if the setting value is too small, too many flips will result in no error correction.

[0116] Afterwards, using the new codeword q′ m Replace the original codeword q m Continue to calculate the syndrome to perform bit flip iterations until the maximum number of iterations is reached or the flip condition is not met, then the bit flip hard decision decoding process is completed. Finally, the output codeword q′ m The codeword w of the finite field linear block code with a bit length of L bits is obtained from L The maximum number of iterations in this embodiment is not limited and can be set by those skilled in the art.

[0117] Finally, the finite field linear block code word w is generated according to the generating polynomial g(x) used in the encoding process. L Perform hard decision decoding of finite field linear block code. Following the above example, the check bit length selected in the encoding process is 60 bits, so that the finite field linear block code can correct 6 bit errors. If the finite field linear block code codeword wL If the number of bit errors does not exceed 6, the decoding is successful, otherwise the decoding fails, and finally the information bits can be obtained.

[0118] See also Figure 5 , Figure 5 Schematic diagram of the performance curves of the three encoding and decoding methods provided in the embodiments of the present application, the horizontal axis is the symbol signal-to-noise ratio (Es / N0), which is used to reflect the ratio of each symbol energy to the noise power spectral density, in decibels dB, and the vertical axis is PER (Packet Error Rate, packet error rate). Figure 5 The NR LDPC curve is a performance curve that uses only the NR LDPC coding method, with an information bit length of 984 bits (including a 32-bit CRC check) and a code rate of 1 / 3. The BCH-LDPC curve is a performance curve of the cascade coding of BCH and NR LDPC, and its BCH coding parameters and NR LDPC coding parameters are consistent with the specific embodiments of the present application. The LDPC-BF-BCH curve is a performance curve corresponding to a signal decoding method provided by the present application. It can be seen that the signal decoding method proposed in the present application, based on LDPC-BF-BCH, has a better packet error rate reduction curve and can better achieve quasi-error-free performance.

[0119] In the decoding process, the embodiment of the present application performs hard decision decoding of the codeword bits corresponding to the low-density parity check mother code, and the bit flip hard decision decoding is performed before the hard decision decoding of the finite field linear block code, which can increase the success rate of the hard decision decoding of the finite field linear block code and significantly reduce the error platform in the short code scenario, so that it can achieve quasi-error-free performance, that is, 10^(-5) packet error rate. At the same time, the bit flip hard decision decoding has a faster decoding convergence speed, can achieve better decoding performance within a smaller number of iterations, effectively reduce the decoding delay, and is suitable for communication systems with higher real-time requirements. At the same time, the flip hard decision decoding process has low implementation complexity, is easy to implement in hardware, and has good application prospects.

[0120] See also Figure 6 , Figure 6 This is a schematic diagram of the structure of a signal decoding system provided in an embodiment of the present application. The present application also provides a signal decoding system, including:

[0121] A signal receiving module, used for acquiring a received signal, modulating and demodulating the received signal to obtain soft bit information; the received signal is a signal generated by finite field linear block code encoding and low density parity check code concatenation encoding;

[0122] A first decoding module is used to perform a belief propagation iterative decoding of a new air interface low-density parity check on the soft bit information to obtain a codeword corresponding to a low-density parity check mother code;

[0123] A bit flip module, used for performing bit flip hard decision decoding on the codeword corresponding to the low-density parity check mother code to obtain a finite field linear block code codeword;

[0124] The second decoding module is used to perform finite field linear block code hard decision decoding on the finite field linear block code codeword to obtain the decoded information bits of the received signal.

[0125] Based on the above embodiment, as a preferred embodiment, the first decoding module is a module for performing the following steps:

[0126] A check matrix is ​​represented by a bipartite graph including variable nodes and check nodes; for each non-zero element in the check matrix, an edge is added to the bipartite graph to connect the corresponding check node and variable node;

[0127] Initializing the variable node using the soft bit information;

[0128] Passing the information of the variable node to the check node, and updating the check node information of the check node;

[0129] The check node information of the check node is transferred to the variable node to update the information of the variable node, thereby completing one iteration;

[0130] The soft bit information in the variable node is verified by using a hard decision check equation; wherein each row of the check matrix represents one of the check equations;

[0131] If all the check equations pass, the codeword corresponding to the low-density parity check mother code is output;

[0132] If the check equations are not all passed, the information between the variable node and the check node is updated until the maximum number of iterations is met or the check equations are all passed, and the codeword corresponding to the low-density parity check mother code is output.

[0133] Based on the above embodiment, as a preferred embodiment, the bit flip module is a module for performing the following steps:

[0134] Step 1: Obtain a mother code matrix corresponding to a mother code from the check matrix;

[0135] Step 2: calculating a syndrome according to the codeword and the mother code matrix, and applying the syndrome to calculate the number of bits of the codeword that do not satisfy the check equation;

[0136] Step 3: If the number of bits is not less than the set value, flip the bits in the codeword that do not satisfy the check equation to obtain a new codeword, and complete an iteration; if the number of bits is less than the set value, proceed to step 6;

[0137] Step 4: Determine whether the current number of iterations meets the maximum number of iterations; if not, proceed to step 5; if yes, proceed to step 6;

[0138] Step 5: Use the new codeword to replace the codeword and execute step 2;

[0139] Step 6: Output the finite field linear block code codeword corresponding to the bit length in the codeword.

[0140] Based on the above embodiment, as a preferred embodiment, the bit flip module includes:

[0141] and a bit check unit, configured to calculate a syndrome according to the codeword and a transposed matrix of the mother code matrix; and calculate the number of bits of the codeword that do not satisfy the check equation according to the product of the syndrome and the mother code matrix.

[0142] Based on the above embodiment, as a preferred embodiment, the bit flip module further includes:

[0143] A parameter configuration unit is used to configure the set value according to the set error correction amount.

[0144] Based on the above embodiments, as a preferred embodiment, the second decoding module is a module for performing finite field linear block code hard decision decoding on the finite field linear block code codeword using the generating polynomial applied in the receiving signal encoding process, and when the number of bit errors in the finite field linear block code codeword is less than the set value, obtaining the information bits of the received signal after decoding.

[0145] Based on the above embodiments, as a preferred embodiment, it also includes:

[0146] A coding module, used for the coding process of the information bits;

[0147] The encoding process comprises the following steps:

[0148] Get information bits;

[0149] Determine the check bit length according to the length of the information bit and the finite field linear block code parameters; the finite field linear block code parameters include the total length of the finite field linear block code codeword, the information bit length and the maximum number of correctable error bits;

[0150] Obtaining a generating polynomial according to the check bit length;

[0151] Using the generator polynomial to perform finite field linear block code encoding on the information bits to obtain a finite field linear block code codeword;

[0152] The finite field linear block code codeword is NR low density parity check encoded to obtain a second codeword; the second codeword is used to generate the received signal.

[0153] The present application also provides a computer program product, including a computer program, which implements the steps of the signal decoding method described in the above embodiment when being executed.

[0154] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed, the steps provided in the above embodiment can be implemented. The storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0155] The present application also provides an electronic device, see Figure 7 , a structural diagram of an electronic device provided in an embodiment of the present application, such as Figure 7 As shown, a processor 1410 and a memory 1420 may be included.

[0156] Among them, the processor 1410 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1410 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 1410 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1410 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1410 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0157] The memory 1420 may include one or more computer-readable storage media, which may be non-transitory. The memory 1420 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 1420 is at least used to store the following computer program 1421, wherein, after the computer program is loaded and executed by the processor 1410, it can implement the relevant steps in the method performed by the electronic device side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 1420 may also include an operating system 1422 and data 1423, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 1422 may include Windows, Linux, Android, etc.

[0158] In some embodiments, the electronic device may further include a display screen 1430 , an input / output interface 1440 , a communication interface 1450 , a sensor 1460 , a power source 1470 , and a communication bus 1480 .

[0159] certainly, Figure 7 The structure of the electronic device shown does not constitute a limitation on the electronic device in the embodiments of the present application. In actual applications, the electronic device may include Figure 7 More or fewer components than shown, or combinations of certain components.

[0160] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the system provided in the embodiment, since it corresponds to the method provided in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0161] Specific examples are used herein to illustrate the principles and implementation methods of the present application, and the description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

[0162] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A signal decoding method, characterized in that: include: Acquire a received signal, and obtain soft bit information after modulating and demodulating the received signal; The received signal is a signal generated by finite field linear block code encoding and low density parity check code concatenation encoding; Performing a belief propagation iterative decoding of a new air interface low-density parity check on the soft bit information to obtain a codeword corresponding to a low-density parity check mother code; Performing bit-flip hard decision decoding on the codeword corresponding to the low-density parity check mother code to obtain a finite field linear block code codeword; Finite field linear block code hard decision decoding is performed on the finite field linear block code codeword to obtain decoded information bits of the received signal.

2. The signal decoding method according to claim 1, characterized in that: The soft bit information is subjected to a confidence propagation iterative decoding of a new air interface low-density parity check, and a codeword corresponding to a low-density parity check mother code is obtained, comprising: A check matrix is ​​represented by a bipartite graph including variable nodes and check nodes; for each non-zero element in the check matrix, an edge is added to the bipartite graph to connect the corresponding check node and variable node; Initializing the variable node using the soft bit information; Passing the information of the variable node to the check node, and updating the check node information of the check node; The check node information of the check node is transferred to the variable node to update the information of the variable node, thereby completing one iteration; The soft bit information in the variable node is verified by using a hard decision check equation; wherein each row of the check matrix represents one of the check equations; If all the check equations pass, the codeword corresponding to the low-density parity check mother code is output; If the check equations are not all passed, the information between the variable node and the check node is updated until the maximum number of iterations is met or the check equations are all passed, and the codeword corresponding to the low-density parity check mother code is output.

3. The signal decoding method according to claim 2, characterized in that: The codeword corresponding to the low-density parity check mother code is subjected to bit-flip hard decision decoding to obtain a finite field linear block code codeword, comprising: Step 1: Obtain a mother code matrix corresponding to a mother code from the check matrix; Step 2: calculating a syndrome according to the codeword and the mother code matrix, and applying the syndrome to calculate the number of bits of the codeword that do not satisfy the check equation; Step 3: If the number of bits is not less than the set value, flip the bits in the codeword that do not satisfy the check equation to obtain a new codeword, and complete an iteration; if the number of bits is less than the set value, proceed to step 6; Step 4: Determine whether the current number of iterations meets the maximum number of iterations; if not, proceed to step 5; if yes, proceed to step 6; Step 5: Use the new codeword to replace the codeword and execute step 2; Step 6: Output the finite field linear block code codeword corresponding to the bit length in the codeword.

4. The signal decoding method according to claim 3, characterized in that: Calculating a syndrome according to the codeword and the mother code matrix, and applying the syndrome to calculate the number of bits of the codeword that do not satisfy the check equation includes: Calculate a syndrome according to the codeword and a transposed matrix of the mother code matrix; The number of bits of the codeword that do not satisfy the check equation is calculated according to the product of the syndrome and the mother code matrix.

5. The signal decoding method according to claim 3, characterized in that: The bit positions in the codeword that do not satisfy the check equation are flipped to obtain a new codeword, and the method further includes: The set value is configured according to a set error correction amount.

6. The signal decoding method according to claim 5, characterized in that: Performing finite field linear block code hard decision decoding on the finite field linear block code codeword to obtain decoded information bits of the received signal includes: The finite field linear block code codeword is subjected to finite field linear block code hard decision decoding using the generating polynomial used in the received signal encoding process, and when the number of bit errors in the finite field linear block code codeword is less than the set value, the decoded information bits of the received signal are obtained.

7. The signal decoding method according to claim 1, characterized in that: The encoding process of the information bits includes: Get information bits; Determine the check bit length according to the length of the information bit and the finite field linear block code parameters; the finite field linear block code parameters include the total length of the finite field linear block code codeword, the information bit length and the maximum number of correctable error bits; Obtaining a generating polynomial according to the check bit length; Using the generator polynomial to perform finite field linear block code encoding on the information bits to obtain a finite field linear block code codeword; The finite field linear block code codeword is NR low density parity check encoded to obtain a second codeword; the second codeword is used to generate the received signal.

8. A signal decoding system, characterized in that: include: A signal receiving module is used to obtain a received signal, and to obtain soft bit information after modulating and demodulating the received signal; The received signal is a signal generated by finite field linear block code encoding and low density parity check code concatenation encoding; A first decoding module is used to perform a belief propagation iterative decoding of a new air interface low-density parity check on the soft bit information to obtain a codeword corresponding to a low-density parity check mother code; A bit flip module, used for performing bit flip hard decision decoding on the codeword corresponding to the low-density parity check mother code to obtain a finite field linear block code codeword; The second decoding module is used to perform finite field linear block code hard decision decoding on the finite field linear block code codeword to obtain the decoded information bits of the received signal.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the signal decoding method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the steps of the signal decoding method according to any one of claims 1 to 7 are implemented.

11. A computer program product, characterized in that The invention comprises a computer program, which implements the steps of the signal decoding method according to any one of claims 1 to 7 when being executed.

Images