Recoding Metric Determination System, Method, and Ordered Statistic Decoder

Abstract

The present application discloses a re - encoding metric determination system, method, and ordered statistic decoder, which relate to the technical field of channel coding. The system includes: a storage unit stores first data to be encoded when the signal state type of the valid signal is the first preset state type; a combination number generation unit generates a combination number vector when the signal state type is the second preset state type; a metric determination unit reads the stored data to be encoded from the storage unit when receiving the combination number vector; the storage unit re - stores the output stored data to be encoded as second data to be encoded; the metric determination unit performs re - encoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric. Since when the valid signal changes to the second preset state, the storage unit outputs and re - transmits the data simultaneously, it realizes the data circular shift in the re - encoding process, improves the re - encoding efficiency while occupying less logical resources.

Description

Technical Field

[0001] This application relates to the technical field of channel coding, and particularly to a re-encoding metric determination system, method, and ordered statistics decoder. Background Art

[0002] Ordered Statistics Decoding (OSD) is a general decoding algorithm that can decode all linear block codes. Research shows that for channel coding with medium and short code lengths, the OSD algorithm generally has a lower bit error rate than traditional decoding algorithms. Currently, most research on the OSD algorithm stays at the software simulation stage. However, in engineering implementation, to meet the real-time requirements of communication systems, it is necessary to use a Field Programmable Gate Array (FPGA) for parallel processing to improve the decoding speed.

[0003] OSD decoding is a decoding algorithm based on a generator matrix, mainly including steps such as sorting, Gaussian elimination, and re-encoding metric calculation. For an OSD decoder implemented based on an FPGA, the sorting and Gaussian elimination processes are suitable for storing and processing the generator matrix by column, while the re-encoding metric calculation process is suitable for storing and processing the generator matrix by row. There are two intuitive ways to handle this problem. One is to add logic for matrix transposition between the Gaussian elimination module and the re-encoding module. However, for matrices with a large dimension, the transposition operation will consume a large amount of logic resources. The other is to use the same matrix storage method (by row or by column) throughout the decoding process. However, this will cause some modules in sorting, Gaussian elimination, and re-encoding metric calculation to reduce their operating efficiency due to using an inappropriate matrix storage format. Summary of the Invention

[0004] The main purpose of this application is to provide a re-encoding metric determination system, method, and ordered statistics decoder, aiming to solve the technical problems that the existing ordered statistics decoder consumes a large amount of logic resources and has low operating efficiency during re-encoding metric calculation.

[0005] To achieve the above purpose, this application proposes a re-encoding metric determination system, and the re-encoding metric determination system includes: a storage unit, a combination number generation unit, and a metric calculation unit;

[0006] The storage unit is used to store first data to be encoded when the signal state type of the valid signal is a first preset state type;

[0007] The combination number generation unit is used to generate a combination number vector when the signal state type is a second preset state type;

[0008] The metric calculation unit is configured to, when receiving the combination number vector, read the stored data to be encoded from the storage unit, where the stored data to be encoded includes first data to be encoded.

[0009] The storage unit is further configured to re-store the output stored data to be encoded as second data to be encoded.

[0010] The metric calculation unit is configured to perform re-encoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

[0011] In one embodiment, the storage unit includes a plurality of storage subunits.

[0012] The number of the storage subunits is the same as the number of data types included in the data to be encoded.

[0013] The storage subunit is composed of a selector and a shift register.

[0014] Input ports of the selector are respectively connected to a valid signal input, an encoded data input, and a shift register output.

[0015] The selector is configured to, when detecting that the valid signal is of a first preset state type, obtain the data to be encoded from the data to be encoded input and store the data to be encoded into the shift register.

[0016] The selector is further configured to, when detecting that the valid signal is of a second preset state type, obtain the stored data to be encoded from the shift register output and re-store the stored data to be encoded as second data to be encoded back into the shift register.

[0017] In one embodiment, the metric calculation unit is composed of a plurality of metric calculation subunits of the same structure connected in sequence.

[0018] The number of the metric calculation subunits is the same as the code length value of the order statistic decoder applied by the re-encoding metric determination system.

[0019] Each metric calculation subunit has a common input port, and the common input port is connected to the storage unit for reading the stored data to be encoded from the storage unit.

[0020] In one embodiment, the metric calculation subunit further includes two independent input ports and corresponding independent output ports, namely a first independent input port, a first independent output port, a second independent input port, and a second independent output port.

[0021] Among them, the first independent input port of the first metric calculation subunit is connected to the combination number generation unit, and the input of the second independent input port of the first metric calculation subunit is fixed to a preset fixed input;

[0022] The first independent output port of the Nth metric calculation subunit is floating, and the independent output result of the second independent output port of the Nth metric calculation subunit is the codeword metric;

[0023] Between the second metric calculation subunit and the Nth metric calculation subunit, the first independent input port of the subsequent metric calculation subunit is connected to the first independent output port of the previous metric calculation subunit, and the second independent input port of the subsequent metric calculation subunit is connected to the second independent output port of the previous metric calculation subunit.

[0024] In one embodiment, the data types of the data to be encoded include: MRB codewords, hard decisions, soft information, and generation matrices;

[0025] Correspondingly, the storage subunit includes: an MRB codeword subunit for storing the data to be encoded with the data type of MRB codewords, a hard decision subunit for storing the data to be encoded with the data type of hard decisions, a soft information subunit for storing the data to be encoded with the data type of soft information, and a generation matrix subunit for storing the data to be encoded with the data type of generation matrices.

[0026] In one embodiment, the second independent output port includes: a bit selector, a bit exclusive-OR area, a real number selector area, and a real number addition area;

[0027] Among them, the number of the bit selectors is the same as the decoding order value of the order statistic decoder applied by the re-encoding metric determination system;

[0028] The bit selector is used to select the matrix elements in the generation matrix data as the output when the input conditions of the input generation matrix data meet the preset input conditions;

[0029] The bit exclusive-OR area is used to perform an exclusive-OR operation on the output of the bit selector and the MRB codeword data and the hard decision data to obtain a bit exclusive-OR result;

[0030] The real number selector area is used to select the soft information elements in the soft information data as the output when the bit exclusive-OR result is the first exclusive-OR result;

[0031] The real number addition area is used to perform a real number addition based on the output of the real number selector area and the input data of the second independent input port to obtain the independent output result of the second independent output port.

[0032] In one embodiment, the bit selector is further configured to select a preset element as the output when the input conditions of the input generated matrix data do not meet the preset conditions;

[0033] The real number selection area is further configured to select a preset real number as the output when the bitwise XOR result is the second XOR result.

[0034] In one embodiment, the system further includes: a control unit;

[0035] The control unit is respectively connected to the storage unit and the combination number generation unit;

[0036] The control unit is configured to monitor the valid signal;

[0037] The control unit is further configured to generate a start signal when the signal state type is the second preset state type, and send the start signal to the combination number generation unit;

[0038] The combination number generation unit is further configured to trigger the generation of a combination number vector based on the start signal.

[0039] In addition, to achieve the above object, the present application further proposes a method for determining a recoding metric. The method for determining a recoding metric is applied to the recoding metric determination system as described above. The recoding metric determination system includes: a storage unit, a combination number generation unit, and a metric calculation unit. The method includes:

[0040] The storage unit stores first data to be encoded when the signal state type of the valid signal is the first preset state type;

[0041] The combination number generation unit generates a combination number vector when the signal state type changes to the second preset state type;

[0042] When receiving the combination number vector, the metric calculation unit reads the stored data to be encoded from the storage unit. The stored data to be encoded includes the first data to be encoded;

[0043] The storage unit re-stores the output stored data to be encoded as the second data to be encoded;

[0044] The metric calculation unit performs recoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

[0045] In addition, to achieve the above object, the present application further provides an order statistic decoder, in which the above-mentioned recoding metric determination system is provided.

[0046] One or more technical solutions proposed by this application have at least the following technical effects:

[0047] The recoding metric determination system of this application includes: a storage unit, a combination number generation unit, and a metric calculation unit; when the signal state type of the valid signal is the first preset state type, the storage unit stores the first data to be encoded; when the signal state type is the second preset state type, the combination number generation unit generates a combination number vector; when receiving the combination number vector, the metric calculation unit reads the stored data to be encoded from the storage unit, and the stored data to be encoded includes the first data to be encoded; the storage unit feeds back the output stored data to be encoded as the second data to be encoded and stores it again; the metric calculation unit performs recoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric. Since it is through the monitoring of the valid signal, and when the valid signal changes to the second preset state, the storage unit outputs and feeds back the data simultaneously, realizing the data circular shift in the recoding process, enabling multiple recoding operations to be completed simultaneously as much as possible, improving the recoding efficiency while occupying fewer logic resources. Brief Description of the Drawings

[0048] The drawings here are incorporated into the description and form a part of this description, showing embodiments consistent with this application, and are used together with the description to explain the principles of this application.

[0049] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0050] Figure 1 It is a schematic structural diagram of the recoding metric determination system in the first embodiment of this application;

[0051] Figure 2 It is a schematic structural diagram of the storage unit in the second embodiment of the recoding metric determination system of this application;

[0052] Figure 3 It is a schematic structural diagram of the metric calculation unit in the third embodiment of the recoding metric determination system of this application;

[0053] Figure 4 It is a schematic structural diagram of the second independent output port of the metric calculation subunit in one implementation manner of this application;

[0054] Figure 5 It is a schematic flowchart of the recoding metric determination method in the embodiment of this application.

[0055] The realization of the purpose, functional features, and advantages of this application will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0056] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of this application and are not used to limit this application.

[0057] To better understand the technical solutions of this application, the following will be described in detail in conjunction with the accompanying drawings of the specification and specific implementation manners.

[0058] The embodiment of this application designs an FPGA structure (i.e., a recoding metric determination system) for implementing recoding metric calculation in an order statistic decoder. This structure stores the generator matrix column by column to facilitate adapting to the requirements of the sorting and Gaussian elimination modules. During the operation process, through the design of the operation steps, the module can perform recoding metric calculation in a pipelined manner, ensuring the operation efficiency. At the same time, through experiments, the structure proposed in this application occupies fewer logic resources than the structure with matrix transpose logic added.

[0059] In the first embodiment of the embodiment of this application, the recoding metric determination system of this application can be as Figure 1 shown Figure 1 which is the system structure schematic diagram of the recoding metric determination system in the first embodiment of this application.

[0060] Specifically, in the embodiment of this application, the recoding metric determination system includes: a storage unit, a combination number generation unit, and a metric calculation unit.

[0061] The storage unit is used to store the first data to be encoded when the signal state type of the valid signal is the first preset state type.

[0062] It should be noted that in an FPGA, a storage unit is a basic component that can be used to store data. In the embodiment of this application, the storage device used by the storage unit can be a random access memory, a read-only memory, a shift register, etc., and this application does not limit this.

[0063] In the recoding metric determination system of the embodiment of this application, the inputs of the system can include the data to be encoded and a valid signal. Among them, the data to be encoded can be the data involved in the system during recoding and recoding metric, and the valid signal can be a signal used by the system to identify the validity of the data to be encoded.

[0064] It can be understood that the order statistic decoding algorithm is a decoding method based on a probability decoding criterion. In the embodiment of this application, the above data to be encoded can include data to be encoded of data types such as MRB codewords, hard decisions, soft information, and generator matrices.

[0065] In some embodiments of the present application, it may be assumed that the code length of the applied order statistic decoder is N ( N The value of can be 128 or other values, and the embodiments of the present application do not limit this), and the information bit length is K ( K The value of can be 64 or other values, and the embodiments of the present application do not limit this), and the decoding order is D ( D The value of can be 3 or other values, and the embodiments of the present application do not limit this). Specifically, the MRB codeword, that is, the codeword determined based on the most reliable information set, where the MRB codeword can be N a Viterbi vector (the dimension value is the same as the code length value of the order statistic decoder), denoted as m ; the hard decision can be N a Viterbi vector, denoted as h ; the soft information can be N a real-valued vector of dimension, denoted as r ; the generator matrix can be N column K row matrix (the number of columns of the generator matrix is the same as the code length value of the order statistic decoder, and the number of rows of the generator matrix is the same as the information length value of the order statistic decoder), denoted as G . In the embodiments of the present application, the input data to be encoded can be completed within N clock cycles, where the generator matrix can be input column by column, and the MRB codeword, hard decision, and soft information are input element by element. At time t , the inputs are respectively: the th bit of the MRB codeword, the th bit of the hard decision, the th element of the soft information, and the th column of the generator matrix.

[0066] It can be understood that the process of calculating the recoding metric can be briefly described as: exclusive-ORing the specified number of rows in the generator matrix with the input original codeword (MRB codeword), and according to the result of the exclusive-OR, selecting the bit metric corresponding to bit 1 for addition to obtain the codeword metric. When the generator matrix is stored row by row, the exclusive-OR operation can be completed within one clock cycle, but when the generator matrix is stored column by column, the exclusive-OR operation is performed bit by bit, and the required number of clock cycles is equal to the code length of the order statistic decoder (i.e., the number of columns of the generator matrix).

[0067] In some embodiments of the present application, the valid signal in the embodiments of the present application may be a level signal. Specifically, the signal state types in the embodiments of the present application may include a high-level state and a low-level state. Through the signal state type of the valid signal, the validity identification of the data to be encoded input to the system can be achieved.

[0068] In some embodiments of the present application, the high-level state may be used as the first preset state type of the valid signal, and the low-level state may be used as the second preset state type of the valid signal. When the signal state of the valid signal is the first preset state type, it can be indicated that the input data to be encoded is valid, and at this time, the data to be encoded can be stored; when the signal state type of the valid signal is the second preset state type, it can be indicated that the input data to be encoded is invalid, and at this time, the data to be encoded is not stored.

[0069] It should be noted that in the implementation of the present application, the above first data to be encoded is also the data to be encoded input from the outside of the system to the storage unit.

[0070] In a specific implementation, the embodiments of the present application can identify the first data to be encoded input from outside the system to the system by monitoring the signal state type of the valid signal. When the signal state type of the valid signal is the high-level state, the first data to be encoded is stored in the storage unit; when the signal type of the valid signal is the low-level state, the first data to be encoded is not stored.

[0071] The combination number generation unit is configured to generate a combination number vector when the signal state type is the second preset state type;

[0072] The metric calculation unit is configured to, when receiving the combination number vector, read the stored data to be encoded from the storage unit, and the stored data to be encoded includes the first data to be encoded;

[0073] The metric calculation unit is configured to perform re-encoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

[0074] It should be noted that when the signal state type is the second preset state type, the combination number unit in the embodiments of the present application can generate a combination number vector (specifically a D dimensional integer vector, denoted as c ) in each clock cycle. Based on this combination number vector, the re-encoding of the data to be encoded can be achieved, and at the same time, the codeword metric can be obtained.

[0075] It should be noted that when the metric calculation unit receives the combination number vector sent by the combination number generation unit, it can read the data to be encoded from the storage unit. The data to be encoded read by the metric calculation unit can be part of the data to be encoded stored in the storage unit or all of the data to be encoded stored in the storage unit, and can be specifically selected according to the actual situation in practical applications. The embodiments of the present application do not limit this.

[0076] In the embodiments of the present application, the stored data to be encoded described above includes the first data to be encoded and may also include the second data to be encoded.

[0077] It should be noted that the above-mentioned first data to be encoded is the data to be encoded input from outside the system, and the above-mentioned second data to be encoded is the data to be encoded circulating inside the system.

[0078] It should be understood that the metric calculation unit can perform re-encoding operations based on the stored data to be encoded read from the storage unit and the combination number vector, and then achieve re-encoding and obtain a codeword metric. This codeword metric can be a parameter used to evaluate the similarity between the re-encoded codeword and the original codeword.

[0079] It can be understood that when the metric calculation unit reads the storage unit, the valid signal monitored by the storage unit is also of the second preset state type. At this time, the storage unit does not store the first data to be encoded input from outside, but instead uses the data output by the storage unit as the second data to be encoded and sends it back again to realize the internal circulation of the data to be encoded, which is convenient for the next re-encoding task. That is, the storage unit is also used to send back the output stored data to be encoded as the second data to be encoded and re-store it.

[0080] It should be noted that through the above method of the present application, the generation matrix can be stored by column. At the same time, by sending back the output data to be encoded, the storage shift of the data to be encoded in the storage unit is realized, and the order of each re-encoding operation is changed. For example, the calculation order of the first re-encoding task is bits 1 to n, and the calculation order of the second re-encoding task is bits 2 to n, and finally bit 1 is calculated. Since the second re-encoding task arrives 1 clock cycle later than the first re-encoding task, when the second re-encoding task calculates bit 2, the first re-encoding task is also calculating bit 2, which enables these two operations to be completed simultaneously. By designing the operation steps in a similar way, the solution of the present application can enable multiple re-encoding tasks to be carried out simultaneously, so as to ensure that the module can work in a pipeline manner, improve the operation efficiency, and occupy less logic resources than the structure with matrix transpose logic added.

[0081] In some embodiments of the embodiments of the present application, in order to achieve better generation of the combination number vector, the recoding metric determination system of the embodiments of the present application may further include a control unit, and the control unit is respectively connected to the storage unit and the combination number generation unit;

[0082] The control unit is configured to monitor the valid signal;

[0083] The control unit is further configured to generate a start signal when the signal state type is a second preset state type, and send the start signal to the combination number generation unit;

[0084] The combination number generation unit is further configured to trigger the generation of a combination number vector based on the start signal.

[0085] In some embodiments of the embodiments of the present application, the overall working process of the recoding metric determination system of the present application can be described as follows: when the valid signal is at a high level, the storage unit first stores the input data to be encoded; at the same time, the control unit can continuously monitor the valid signal, and when the valid signal is at a low level, generate a start signal and input it to the combination number generation unit; the combination number generation unit is triggered by the start signal, generates a combination number vector every clock cycle and inputs the combination number vector to the metric calculation unit; the metric calculation unit can perform recoding according to the data to be encoded stored in the storage unit and the generated combination number vector, and calculate the codeword metric.

[0086] The recoding metric determination system of the embodiments of the present application includes: a storage unit, a combination number generation unit, and a metric calculation unit; the storage unit stores the first data to be encoded when the signal state type of the valid signal is a first preset state type; the combination number generation unit generates a combination number vector when the signal state type is a second preset state type; the metric calculation unit reads the stored data to be encoded from the storage unit when receiving the combination number vector, and the stored data to be encoded includes the first data to be encoded; the storage unit feeds back and stores the output stored data to be encoded as the second data to be encoded; the metric calculation unit performs recoding based on the stored data to be encoded and the combination number vector to obtain the codeword metric. Since the valid signal is monitored, and when the valid signal changes to the second preset state, the storage unit outputs and feeds back the data at the same time, realizing the data circular shift in the recoding process, enabling multiple recoding operations to be completed simultaneously as much as possible, improving the recoding efficiency while occupying less logic resources.

[0087] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar content as that in the above-mentioned first embodiment can be referred to the above introduction and will not be repeated hereinafter. On this basis, please refer to Figure 2 , Figure 2This is a schematic diagram of the storage unit structure in the second embodiment of the recoding metric determination system of the present application.

[0088] In the embodiment of the present application, in the storage unit, a plurality of storage subunits may be included. Among them, the number of the storage subunits is the same as the number of data types involved in the data to be encoded.

[0089] In some embodiments of the embodiment of the present application, the data to be encoded in the embodiment of the present application may include: data to be encoded of four data types, namely, MRB codewords, hard decisions, soft information, and generator matrices.

[0090] Correspondingly, the storage subunits include: an MRB codeword subunit for storing the data to be encoded of the data type of MRB codewords, a hard decision subunit for storing the data to be encoded of the data type of hard decisions, a soft information subunit for storing the data to be encoded of the data type of soft information, and a generator matrix subunit for storing the data to be encoded of the data type of generator matrices.

[0091] It should be noted that each storage subunit may be composed of a selector and a shift register. Among them, the input ports of the selector are respectively connected to the valid signal input, the encoded data input, and the shift register output, and the output port of the selector is connected to the input of the shift register for inputting data into the shift register for storage.

[0092] The selector is configured to obtain the data to be encoded from the data to be encoded input and store the data to be encoded in the shift register when it monitors that the valid signal is of the first preset state type;

[0093] The selector is further configured to obtain the stored data to be encoded from the output of the shift register and feed back the stored data to be encoded as the second data to be encoded to the shift register for re-storage when it monitors that the valid signal is of the second preset state type.

[0094] In some embodiments of the embodiment of the present application, the above storage unit may be composed of 4 storage elements with a number of NIt is composed of shift registers (the specific number of shift registers is related to the data type of the data to be encoded). These four shift registers store the MRB codeword, hard decision, soft information, and generation matrix respectively. Among them, each shift register has a 2-input selector connected to its input terminal. This 2-input selector can monitor the valid signal. When the valid signal is in the high-level state, it selects the data to be encoded input externally as the input of the shift register. At this time, the shift register can load and store the data to be encoded input externally. When the valid signal is in the low-level state, the selector can select the output of the shift register as the input of the shift register, thereby enabling the shift register to continuously circularly shift the saved data.

[0095] It should be noted that when the input is completed, the valid signal can be converted to the low-level state. At this time, the control unit and the selector can detect the change in the level state of the valid signal. The control unit can generate a start signal and input it to the combination number generation unit. When the combination number generation unit receives the start signal, it enables the internal counter and counts from 0 to and the value of the internal counter is incremented by 1 in each clock cycle.

[0096] It should be explained that the combination number generation unit can calculate the combination number vector s according to the value of the internal counter c , and the calculation method of the i th element of the combination number vector can be as follows:

[0097] ;

[0098] where floor is the floor function and mod is the remainder function.

[0099] In the embodiment of the present application, when the selector monitors that the valid signal is in the first preset state type, it obtains the data to be encoded from the input of the data to be encoded and stores the data to be encoded in the shift register. When the selector monitors that the valid signal is in the second preset state type, it obtains the stored data to be encoded from the output of the shift register and returns the stored data to be encoded as the second data to be encoded to the shift register for re-storage. Since the circular shift of the data to be encoded in the shift register is realized through the selector, the system can perform the recoding metric calculation in a pipeline manner, ensuring the operation efficiency.

[0100] Based on the first embodiment and / or the second embodiment of the present application, in the third embodiment of the present application, the content that is the same as or similar to the above-mentioned embodiment one and / or embodiment two can be referred to the above introduction and will not be elaborated hereinafter. On this basis, please refer to Figure 3 , Figure 3This is a schematic structural diagram of the metric calculation unit in the third embodiment of the recoding metric determination system of the present application.

[0101] As Figure 3 shown, in the embodiment of the present application, the metric calculation unit is composed of several metric calculation sub-units with the same structure connected in sequence, and the serial numbers of each metric calculation sub-unit increase in sequence (specifically, it can start from 0 and increase in sequence, that is, the serial number of the first metric sub-unit is 0). Among them, the number of the metric calculation sub-units is the same as the code length value of the order statistic decoder applied by the recoding metric determination system, that is, the number of the metric calculation sub-units is N .

[0102] It should be noted that for each of the metric calculation sub-units, there is a common input port, and the common input port can be connected to the storage unit. Through this common input port, the metric calculation sub-unit can read the stored data to be encoded from the storage unit.

[0103] It should be explained that for each of the metric calculation sub-units, there may also be two independent input ports and independent output ports corresponding to the independent input ports, namely the first independent input port, the first independent output port, the second independent input port and the second independent output port.

[0104] Among them, the input of the first input port and the output of the first output port can be D dimensional integer vectors (the dimension is the same as the order of the order statistic decoder), and the input of the second input port and the output of the second output port can be real numbers.

[0105] In some embodiments of the embodiment of the present application, the first independent input port of the first metric calculation sub-unit (that is, the metric calculation sub-unit with the serial number 0) is connected to the combination number generation unit, and the input of the second independent input port of the first metric calculation sub-unit is fixed to a preset fixed input (this preset fixed input can specifically be "0"). The N metric calculation sub-unit (that is, the metric calculation sub-unit with the serial number N -1) has its first independent output port floating, and the independent output result of the second independent output port of the N metric calculation sub-unit is the codeword metric.

[0106] In some embodiments of the embodiment of the present application, the serial number is p (0 < p < N ) of the first input port of the metric calculation sub-unit is connected to the first output port of the metric calculation sub-unit with the serial number p -1, and the second input port of the metric calculation sub-unit with the serial number p is connected to the serial number ofp The second output port of the metric calculation subunit of -1. That is, between the second metric calculation subunit and the Nth metric calculation subunit, the first independent input port of the subsequent metric calculation subunit is connected to the first independent output port of the previous metric calculation subunit, and the second independent input port of the subsequent metric calculation subunit is connected to the second independent output port of the previous metric calculation subunit.

[0107] It should be understood that through the above connection method, the output of the first independent output port of the previous metric calculation subunit can be used as the input of the first independent input port of the subsequent metric calculation subunit, and the output of the second independent output port of the previous metric calculation subunit can be used as the input of the second independent input port of the subsequent metric calculation subunit. Specifically, at the moment corresponding to a certain clock cycle T , the input of the first independent input port of the metric calculation subunit with serial number 0 A (-1, T ) = c ( T ), and the input of the second independent input port B (-1, T ) = 0, where c ( T ) is T the combination number vector at the moment. After re-encoding in the metric calculation subunit with serial number 0, the output of the first independent output port A (0, T+1 ) and the output of the second independent output port B (0, T+1 ) can be obtained, and these outputs can be used as the inputs of the corresponding independent input ports of the metric calculation subunit with serial number 1 at the next moment.

[0108] It can be understood that for adjacent metric calculation subunits, for the convenience of description, the metric calculation subunit with a smaller serial number can be regarded as the previous metric calculation subunit, and the metric calculation subunit with a larger serial number can be regarded as the subsequent metric calculation subunit. Exemplarily, for the ninth metric calculation subunit with serial number 8 and the tenth metric calculation subunit with serial number 9, the ninth metric calculation subunit can be regarded as the previous metric calculation subunit, and the tenth metric calculation subunit can be regarded as the subsequent metric calculation subunit.

[0109] In some embodiments of the present application, at the moment corresponding to a certain clock cycle T , the value of the first independent input port of the metric calculation subunit with serial number p can be denoted as , and the value of the second independent input port can be denoted as . Since the storage unit can continuously circularly shift the stored data to be encoded, the input of the common input port is the MRB codeword bit at this time , hard decision bits , soft information elements , columns of the generator matrix .

[0110] It should be noted that each metric calculation subunit can calculate the output for the next moment based on the input at the current moment. That is, at moment T , the metric calculation subunit with the serial number p can calculate based on , and the value of the common input port to calculate and . Among them, the A output port is calculated according to the following formula:

[0111] .

[0112] It should be noted that since the XOR operation is performed bit by bit when the generator matrix is stored by column, the number of required clock cycles is equal to the value of the code length N , and in this application, by designing N metric calculation subunits as metric calculation units in the recoded metric determination system, each metric calculation subunit can be based on the input data bits to be encoded (such as MRB codeword bits , hard decision bits , soft information elements , generator matrix ) for calculation, and the time required for each metric calculation subunit to calculate is one clock cycle. Therefore, for the moment corresponding to one clock cycle T , the output of the previous metric calculation subunit is the input for the next clock cycle corresponding to the subsequent metric calculation subunit at the moment T +1.

[0113] It should be explained that, in order to calculate the output of the second output port, a partial structure of the metric calculation subunit in the embodiment of this application can be as Figure 4 shown Figure 4 is a schematic diagram of the second independent output port structure of the metric calculation subunit in an implementation manner of this application.

[0114] Referring to Figure 4 , the second independent output port in the metric calculation subunit in the embodiment of this application can include: a plurality of bit selectors, a bit XOR area, a real number selection area, and a real number addition area;

[0115] Among them, the number of the bit selectors is the same as the encoding order value D of the successive statistical encoder applied in the recoded metric determination system.

[0116] Specifically, the embodiments of the present application can D bit K selector to select the input generation matrix . The i th (0 ≤ i ≤ D ) K bit selector can select the generation matrix according to the i th element of the first independent input port. When is less than K , select the th element in the generation matrix as the output of the bit selector; when is not less than K , select the preset element "0" bit as the output. That is, the bit selector is used to select the matrix element in the input generation matrix data as the output when the input condition of the input generation matrix data meets the preset input condition; the bit selector is also used to select the preset element as the output when the input condition of the input generation matrix data does not meet the preset condition.

[0117] Further, the D bits K selected from the D bit selectors (that is, the outputs of each bit selector) can be XORed with the MRB codeword bits and the hard decision bits to obtain the bit XOR result. That is, the bit XOR area is used to perform an XOR operation on the output of the bit selector, the MRB codeword data, and the hard decision data to obtain the bit XOR result. The generation matrix data is the data to be encoded with the data type of the generation matrix;

[0118] Further, a real number selection can be performed based on the bit XOR result. If the bit XOR result is the first XOR result ("1" bit), the soft information element can be selected as the real number selection result and output to the real number addition area; if the bit XOR result is the second XOR result ("0" bit), the preset real number "0" can be selected as the real number selection result and output to the real number addition area. That is, the real number selection area is used to select the soft information element in the soft information data as the output when the bit XOR result is the first XOR result; the real number selection area is also used to select the preset real number as the output when the bit XOR result is the second XOR result.

[0119] Further, the output of the real number selection area can be combined with the input of the second independent input port Perform real number addition to obtain the independent output result of the second independent output port. , and this independent output result is also the input of the second independent input port of the metric calculation subunit with the serial number T +1 at the next moment ( p +1 moment). That is, the real number addition area is used to perform real number addition based on the output of the real number selection area and the input data of the second independent input port to obtain the independent output result of the second independent output port.

[0120] It should be noted that through the above system, the second independent output interface with the serial number N -1 is connected to the codeword metric output. Each metric calculation subunit introduces a clock cycle delay, N a total of N clock cycles of delay are introduced by metric calculation subunits. Therefore, for the metric output subunit, is the valid output of the codeword metric.

[0121] The second independent output port of the metric calculation subunit in the embodiment of the present application includes: a bit selector, a bit exclusive-OR area, a real number selection area, and a real number addition area; the bit selector selects a matrix element in the generated matrix data as the output when the input condition of the input generated matrix data meets the preset input condition; the bit exclusive-OR area performs an exclusive-OR operation on the output of the bit selector, the MRB codeword data, and the hard decision data to obtain a bit exclusive-OR result; the real number selection area selects a soft information element in the soft information data as the output when the bit exclusive-OR result is the first exclusive-OR result; the real number addition area performs real number addition based on the output of the real number selection area and the input data of the second independent input port to obtain the independent output result of the second independent output port. Since N metric calculation subunits are designed, the independent output result of the second independent output port can be calculated by each metric calculation subunit through one clock cycle, and recoding is realized through N metric calculation subunits, improving the recoding efficiency.

[0122] It should be noted that the above examples are only for understanding the present application and do not constitute a limitation on the recoding metric determination system of the present application. Based on this technical concept, more forms of simple transformations are within the protection scope of the present application.

[0123] The present application also provides a method for determining a recoding metric. Please refer to Figure 5 , Figure 5 is a schematic flowchart of the method for determining a recoding metric in the embodiment of the present application. The method for determining a recoding metric is applied to the recoding metric determination system as described above. The recoding metric determination system includes: a storage unit, a combination number generation unit, and a metric calculation unit. The method includes:

[0124] Step S10, when the signal state type of the valid signal is the first preset state type, the storage unit stores the first data to be encoded;

[0125] Step S20, when the signal state type changes to the second preset state type, the combination number generation unit generates a combination number vector;

[0126] Step S30, when receiving the combination number vector, the metric calculation unit reads the stored data to be encoded from the storage unit, and the stored data to be encoded includes the first data to be encoded;

[0127] Step S40, the storage unit feeds back and re-stores the output stored data to be encoded as the second data to be encoded;

[0128] Step S50, the metric calculation unit performs re-encoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

[0129] The re-encoding metric determination method provided by this application, based on the re-encoding metric determination system in the above embodiment, can solve the technical problems that the existing order statistic decoder consumes a large amount of logic resources and has a low operation efficiency when calculating the re-encoding metric. Compared with the prior art, the beneficial effects of the re-encoding metric determination method provided by this application are the same as those of the re-encoding metric determination system provided by the above embodiment, and other technical features in the re-encoding metric determination method are the same as the features disclosed in the above embodiment system, which will not be elaborated here.

[0130] This application also provides an order statistic decoder, in which at least one re-encoding metric calculation module is provided, and this re-encoding metric calculation module realizes the functions of re-encoding and codeword metric calculation based on the re-encoding metric determination system in the above embodiment.

[0131] The above are only partial embodiments of this application, and thus do not limit the patent scope of this application. Any equivalent structural transformation made under the technical concept of this application by using the content of the specification and drawings of this application, or direct / indirect application in other related technical fields, is included in the patent protection scope of this application.

Claims

1. A recoding metric determination system, characterized in that: The recoding metric determination system comprises: a storage unit, a combination number generation unit and a metric calculation unit; The storage unit is used to store the first data to be encoded when the signal state type of the valid signal is the first preset state type; The combination number generating unit is used to generate a combination number vector when the signal state type is a second preset state type; The metric calculation unit is used to read the stored data to be encoded from the storage unit when receiving the combination number vector, wherein the stored data to be encoded includes the first data to be encoded; The storage unit is further used to transmit the outputted stored data to be encoded as second data to be encoded back for re-storage; The metric calculation unit is used to re-encode based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

2. The recoding metric determination system according to claim 1, wherein: The storage unit includes a plurality of storage subunits; The number of the storage subunits is the same as the number of data types included in the data to be encoded; The storage subunit is composed of a selector and a shift register; The input ports of the selector are respectively connected to the effective signal input, the coded data input and the shift register output; The selector is used to obtain the data to be encoded from the data to be encoded input and store the data to be encoded in the shift register when detecting that the valid signal is of the first preset state type; The selector is further used to obtain the stored data to be encoded from the shift register output when it is detected that the valid signal is of the second preset state type, and return the stored data to be encoded as the second data to be encoded to the shift register for re-storage.

3. The recoding metric determination system according to claim 2, wherein: The metric calculation unit is composed of a plurality of metric calculation sub-units with the same structure connected in sequence; The number of the metric calculation subunits is the same as the code length value of the order statistics decoder applied by the re-encoding metric determination system; Each of the metric calculation subunits has a common input port, and the common input port is connected to the storage unit and is used to read the stored data to be encoded from the storage unit.

4. The recoding metric determination system according to claim 3, wherein: The metric calculation subunit further includes two independent input ports and independent output ports corresponding to the independent input ports, which are respectively a first independent input port, a first independent output port, a second independent input port and a second independent output port; Wherein, the first independent input port of the first metric calculation subunit is connected to the combination number generation unit, and the input of the second independent input port of the first metric calculation subunit is fixed to a preset fixed input; No. N The first independent output port of the metric calculation subunit is suspended, and the independent output result of the second independent output port of the Nth metric calculation subunit is the codeword metric; In the second metric calculation subunit to the N Between the metric calculation subunits, the first independent input port of the subsequent metric calculation subunit is connected to the first independent output port of the preceding metric calculation subunit, and the second independent input port of the subsequent metric calculation subunit is connected to the second independent output port of the preceding metric calculation subunit.

5. The recoding metric determination system according to claim 4, wherein: The data types of the data to be encoded include: MRB codewords, hard decisions, soft information and generator matrices; Correspondingly, the storage subunit includes: an MRB codeword subunit for storing data to be encoded whose data type is an MRB codeword, a hard decision subunit for storing data to be encoded whose data type is a hard decision, a soft information subunit for storing data to be encoded whose data type is soft information, and a generation matrix subunit for storing data to be encoded whose data type is a generation matrix.

6. The recoding metric determination system according to claim 5, wherein: The second independent output port includes: a bit selector, a bit XOR area, a real number selection area and a real number addition area; wherein the number of the bit selectors is the same as the decoding order value of the order statistics decoder applied by the recoding metric determination system; The bit selector is used to select a matrix element in the generator matrix as output when an input condition of the generator matrix meets a preset input condition; The bit XOR area is used to perform an XOR operation on the output of the bit selector, the MRB codeword, and the hard decision to obtain a bit XOR result; The real number selection area is used to select a soft information element in the soft information as output when the bit XOR result is a first XOR result; The real number addition area is used to add real numbers based on the output of the real number selection area and the input data of the second independent input port to obtain an independent output result of the second independent output port.

7. The recoding metric determination system of claim 6, wherein: The bit selector is further used to select a preset element as output when an input condition of the input generator matrix does not meet a preset condition; The real number selection area is also used to select a preset real number as output when the bit XOR result is a second XOR result.

8. The recoding metric determination system of claim 1, wherein: The system further comprises: a control unit; The control unit is connected to the storage unit and the combination number generating unit respectively; The control unit is used to monitor the effective signal; The control unit is further configured to generate a start signal when the signal state type is a second preset state type, and send the start signal to the combination number generating unit; The combination number generating unit is further configured to trigger the generation of a combination number vector based on the start signal.

9. A method for determining a recoding metric, characterized in that: The method is applied to a recoding metric determination system according to any one of claims 1 to 8, wherein the recoding metric determination system comprises: A storage unit, a combination number generating unit and a metric calculating unit, the method comprising: The storage unit stores the first data to be encoded when the signal state type of the valid signal is a first preset state type; The combination number generating unit generates a combination number vector when the signal state type is changed to a second preset state type; When receiving the combination number vector, the metric calculation unit reads the stored data to be encoded from the storage unit, where the stored data to be encoded includes the first data to be encoded; The storage unit transmits the outputted stored data to be encoded as second data to be encoded back for re-storage; The metric calculation unit performs re-encoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

10. An order statistical decoder, characterized in that: The order statistics decoder is provided with a re-encoding metric determination system as described in any one of claims 1-8.

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