Optical module, network equipment and data transmission method

Abstract

The invention provides an optical module, network equipment and a data transmission method, and belongs to the field of optical communication. A FlexE interface is arranged in the optical module, after a FlexE code block stream from a system side is converted into a plurality of paths of Ethernet code block streams by utilizing a FlexE channelization characteristic, an optical signal is generated after electro-optical conversion, and then the optical signal is sent out, so that one interface, butted with network equipment, of the optical module is mapped into a plurality of optical interfaces, the optical interface density is improved, and the optical communication efficiency is improved. And hashing of a high-density optical interface can be realized.

Description

Technical Field

[0001] The present application relates to the field of optical communications, and in particular to an optical module, a network device, and a data transmission method. Background Art

[0002] In the current hash optical module, the number of channels (transmission channels for optical signals) provided by the line side interface (optical interface) is the same as the number of channels (transmission channels for electrical signals) provided by the system side interface (electrical interface), resulting in insufficient density of the line side interface (optical interface), which limits the interface capacity of the network equipment. Summary of the invention

[0003] The embodiments of the present application provide an optical module, a network device, and a data transmission method, which can improve the density of optical interfaces.

[0004] In a first aspect, an optical module is provided, including a flexible Ethernet (FlexE) interface, a processing circuit, an optoelectronic conversion device and multiple optical interfaces; the FlexE interface is used to receive a first FlexE code block stream from a network device through a FlexE channel, and the FlexE interface is communicatively connected to the network device through the FlexE channel; the processing circuit is used to obtain multiple first Ethernet code block streams based on the first FlexE code block stream; the optoelectronic conversion device is used to perform electrical-to-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; and the multiple optical interfaces are used to send the multiple first optical signals to optical fibers.

[0005] The FlexE interface may also be referred to as a system-side interface. The optical interface may also be referred to as a line-side interface. The optical interface is, for example, an Ethernet interface.

[0006] The first aspect provides an optical module with a FlexE interface. By utilizing the FlexE channelization feature, the FlexE code block stream from the system side is converted into a multi-channel Ethernet code block stream, which is then sent out after being generated through electro-optical conversion. This enables an interface (FlexE interface) for connecting the optical module to a network device to be mapped into multiple optical interfaces, thereby improving the optical interface density and helping to achieve hashing of high-density optical interfaces.

[0007] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the FlexE shim circuit is used to obtain multiple first FlexE client code block streams based on the first FlexE code block stream, and the multiple first FlexE client code block streams include code blocks with a FlexE encoding format; the transcoding circuit is used to convert the encoding format of the code blocks in the multiple first FlexE client code block streams from the FlexE encoding format to the Ethernet encoding format to obtain the multiple first Ethernet code block streams.

[0008] Taking into account that in some scenarios, code blocks in FlexE coding format and code blocks in Ethernet coding format have different coding formats, the coding format of the code blocks is converted from FlexE coding format to Ethernet coding format by using a transcoding circuit, so that the optical interface is adapted to the standard Ethernet interface (such as an Ethernet interface that complies with the IEEE 802.3 standard), thereby reducing the complexity of decoding the code blocks by the remote device connected to the optical module through the optical fiber, and reducing the risk of decoding failure when the remote device decodes the code block stream according to the Ethernet coding format after the code block stream is transmitted to the remote device.

[0009] In some embodiments, the FlexE shim circuit is used to perform time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain multiple first FlexE client code block streams, and the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

[0010] By utilizing the flexible and configurable characteristics of FlexE shim, the conversion between FlexE code block stream and FlexE client code block stream is realized based on the time slot configuration information, so that the number of optical interfaces and the transmission rate of the optical interfaces are configurable, thereby improving flexibility.

[0011] In some embodiments, the multiple first Ethernet block streams include a first Ethernet block stream at a first transmission rate and a first Ethernet block stream at a second transmission rate, the multiple first FlexE client block streams include a first FlexE client block stream at the first transmission rate and a first FlexE client block stream at a second transmission rate, the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client block stream at the first transmission rate occupies a first number of time slots and the first FlexE client block stream at the second transmission rate occupies a second number of time slots, and the second number is different from the first number.

[0012] By utilizing the time division multiplexing (TDM) feature of FlexE, the code blocks in the FlexE code block stream are mapped to different numbers of time slots, thereby supporting the output of multiple FlexE client code block streams at different rates, thereby enabling an optical module to hash multiple rate interfaces at the same time, helping to reduce the use of different rate interface boards and reduce costs.

[0013] In some implementations, a transmission rate of each first Ethernet block stream in the multiple first Ethernet block streams is lower than a transmission rate of the first FlexE block stream.

[0014] Since a higher-rate FlexE code block stream is converted into multiple lower-rate Ethernet code block streams, a hash optical module is implemented, which helps the optical module to connect with multiple remote devices.

[0015] In some embodiments, the multiple optical interfaces are further used to receive multiple second optical signals from the optical fiber, the multiple second optical signals including multiple second Ethernet code block streams; the optoelectronic conversion device is further used to perform optoelectronic conversion on the multiple second optical signals to obtain multiple electrical signals, the multiple electrical signals including multiple second Ethernet code block streams; the processing circuit is further used to obtain a second FlexE code block stream based on the multiple second Ethernet code block streams; the FlexE interface is further used to send the second FlexE code block stream to the network device through the FlexE channel.

[0016] By utilizing the FlexE channelization feature, multiple Ethernet block streams from the line side are converted into FlexE block streams, which are then sent out after being converted into electrical signals through photoelectric conversion. This allows multiple optical interfaces connected to multiple remote devices to be mapped into one interface for the optical module to connect to the network device, thereby meeting the needs of multiple remote devices to communicate with the network device through the optical module.

[0017] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the transcoding circuit is used to convert the encoding format of the code blocks in the multiple second Ethernet code block streams from the Ethernet encoding format to the FlexE encoding format to obtain the multiple second FlexE client code block streams; the FlexE shim circuit is used to obtain the second FlexE code block stream based on the multiple second FlexE client code block streams.

[0018] Taking into account that in some scenarios, code blocks in FlexE coding format and code blocks in Ethernet coding format have different coding formats, the coding format of the code block is converted from the Ethernet coding format to the FlexE coding format by using a transcoding circuit, so that the optical interface is adapted to the standard Ethernet interface (such as an Ethernet interface that complies with the IEEE 802.3 standard), reducing the complexity of decoding the code block by the network device.

[0019] In some embodiments, the optical module includes an interface chip, and the FlexE interface and the processing circuit are both disposed on the interface chip.

[0020] By integrating the FlexE interface and processing circuit on the same interface chip, the layout of the optical module is simplified and the overall size of the optical module is saved.

[0021] In a second aspect, an optical module is provided, comprising: a shell body, provided with an electrical interface and multiple optical interfaces, the electrical interface is used to connect to a network device outside the optical module, and the multiple optical interfaces are used to connect to optical fibers outside the optical module; an interface chip, arranged in the shell body, the interface chip comprises a Flexible Ethernet FlexE interface, a processing circuit and multiple Ethernet interfaces, the FlexE interface is opposite to the electrical interface, the processing circuit is arranged between the FlexE interface and the multiple Ethernet interfaces, the processing circuit is used to convert the FlexE code block stream received by the FlexE interface into a multiple Ethernet code block stream and output the multiple Ethernet code block stream to the multiple Ethernet interfaces, the multiple Ethernet interfaces correspond one to one to the multiple optical interfaces; an optoelectronic conversion device, arranged in the shell body, one end of the optoelectronic conversion device is electrically connected to the multiple Ethernet interfaces of the interface chip, and the other end of the optoelectronic conversion device is opposite to the multiple optical interfaces.

[0022] The second aspect provides an optical module with a FlexE interface. Since one FlexE interface is mapped to multiple Ethernet interfaces and multiple Ethernet interfaces are mapped to multiple optical interfaces, the optical interface density is improved, which helps to achieve hashing of high-density optical interfaces.

[0023] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the FlexE shim circuit is used to obtain multiple first FlexE client code block streams based on the first FlexE code block stream, and the multiple first FlexE client code block streams include code blocks with a FlexE encoding format; the transcoding circuit is used to convert the encoding format of the code blocks in the multiple first FlexE client code block streams from the FlexE encoding format to the Ethernet encoding format to obtain the multiple first Ethernet code block streams.

[0024] In some embodiments, the FlexE shim circuit is used to perform time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain multiple first FlexE client code block streams, and the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

[0025] In some embodiments, the multiple first Ethernet block streams include a first Ethernet block stream at a first transmission rate and a first Ethernet block stream at a second transmission rate, the multiple first FlexE client block streams include a first FlexE client block stream at the first transmission rate and a first FlexE client block stream at a second transmission rate, the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client block stream at the first transmission rate occupies a first number of time slots and the first FlexE client block stream at the second transmission rate occupies a second number of time slots, and the second number is different from the first number.

[0026] In some implementations, a transmission rate of each first Ethernet block stream in the multiple first Ethernet block streams is lower than a transmission rate of the first FlexE block stream.

[0027] In some embodiments, the multiple optical interfaces are further used to receive multiple second optical signals from the optical fiber, the multiple second optical signals including multiple second Ethernet code block streams; the optoelectronic conversion device is further used to perform optoelectronic conversion on the multiple second optical signals to obtain multiple electrical signals, the multiple electrical signals including multiple second Ethernet code block streams; the processing circuit is further used to obtain a second FlexE code block stream based on the multiple second Ethernet code block streams; the FlexE interface is further used to send the second FlexE code block stream to the network device through the FlexE channel.

[0028] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the transcoding circuit is used to convert the encoding format of the code blocks in the multiple second Ethernet code block streams from the Ethernet encoding format to the FlexE encoding format to obtain the multiple second FlexE client code block streams; the FlexE shim circuit is used to obtain the second FlexE code block stream based on the multiple second FlexE client code block streams.

[0029] In some embodiments, the optical module includes an interface chip, and the FlexE interface and the processing circuit are both disposed on the interface chip.

[0030] In a third aspect, a network device is provided, including a processor, a first flexible Ethernet FlexE interface and an optical module, the optical module including a second FlexE interface, a processing circuit, an optoelectronic conversion device and multiple optical interfaces, the first FlexE interface is communicatively connected to the second FlexE interface through a FlexE channel; the processor is used to generate a first FlexE code block stream; the first FlexE interface is used to send the first FlexE code block stream to the second FlexE interface through the FlexE channel; the processing circuit is used to obtain multiple first Ethernet code block streams based on the first FlexE code block stream; the optoelectronic conversion device is used to perform electrical-to-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; and the multiple optical interfaces are used to send the multiple first optical signals to optical fibers.

[0031] In the network device provided by the third aspect, since an optical module with a FlexE interface is provided, the FlexE code block stream from the system side is converted into a multi-channel Ethernet code block stream by utilizing the FlexE channelization characteristics, and then the optical signal is generated after electro-optical conversion and sent out, so that an interface (FlexE interface) for connecting the optical module to the network device is mapped to multiple optical interfaces, thereby improving the optical interface density and helping to achieve hashing of high-density optical interfaces.

[0032] In addition, network devices can be connected to multiple remote devices through optical modules, which improves the interface capabilities and scalability of network devices and helps support more complex network topologies.

[0033] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the FlexE shim circuit is used to obtain multiple first FlexE client code block streams based on the first FlexE code block stream, and the multiple first FlexE client code block streams include code blocks with a FlexE encoding format; the transcoding circuit is used to convert the encoding format of the code blocks in the multiple first FlexE client code block streams from the FlexE encoding format to the Ethernet encoding format to obtain the multiple first Ethernet code block streams.

[0034] In some embodiments, the FlexE shim circuit is used to perform time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain multiple first FlexE client code block streams, and the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

[0035] In some embodiments, the multiple first Ethernet block streams include a first Ethernet block stream at a first transmission rate and a first Ethernet block stream at a second transmission rate, the multiple first FlexE client block streams include a first FlexE client block stream at the first transmission rate and a first FlexE client block stream at a second transmission rate, the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client block stream at the first transmission rate occupies a first number of time slots and the first FlexE client block stream at the second transmission rate occupies a second number of time slots, and the second number is different from the first number.

[0036] In some implementations, a transmission rate of each first Ethernet block stream in the multiple first Ethernet block streams is lower than a transmission rate of the first FlexE block stream.

[0037] In some embodiments, the multiple optical interfaces are further used to receive multiple second optical signals from the optical fiber, the multiple second optical signals including multiple second Ethernet code block streams; the optoelectronic conversion device is further used to perform optoelectronic conversion on the multiple second optical signals to obtain multiple electrical signals, the multiple electrical signals including multiple second Ethernet code block streams; the processing circuit is further used to obtain a second FlexE code block stream based on the multiple second Ethernet code block streams; the second FlexE interface is further used to send the second FlexE code block stream to the network device through the FlexE channel.

[0038] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the transcoding circuit is used to convert the encoding format of the code blocks in the multiple second Ethernet code block streams from the Ethernet encoding format to the FlexE encoding format to obtain the multiple second FlexE client code block streams; the FlexE shim circuit is used to obtain the second FlexE code block stream based on the multiple second FlexE client code block streams.

[0039] In some embodiments, the optical module includes an interface chip, and the second FlexE interface and the processing circuit are both disposed on the interface chip.

[0040] In a fourth aspect, a data transmission method is provided, which is applied to an optical module, including: receiving a first FlexE code block stream from a first network device through a flexible Ethernet FlexE channel, and the optical module is communicatively connected to the first network device through the FlexE channel; obtaining multiple first Ethernet code block streams based on the first FlexE code block stream; performing electrical-to-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; and sending the multiple first optical signals to a second network device through optical fibers.

[0041] In some embodiments, obtaining multiple first Ethernet code block streams based on the first FlexE code block stream includes: obtaining multiple first FlexE client code block streams based on the first FlexE code block stream, the multiple first FlexE client code block streams including code blocks having a FlexE coding format; converting the coding format of the code blocks in the multiple first FlexE client code block streams from the FlexE coding format to the Ethernet coding format to obtain the multiple first Ethernet code block streams.

[0042] In some embodiments, obtaining multiple first FlexE client code block streams based on the first FlexE code block stream includes: based on time slot configuration information, performing time slot mapping on the first FlexE code block stream to obtain multiple first FlexE client code block streams, the time slot configuration information indicating at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

[0043] In some embodiments, multiple first FlexE client code block streams include a first FlexE client code block stream of a first transmission rate and a first FlexE client code block stream of a second transmission rate, the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client code block stream of the first transmission rate occupies a first number of time slots and the first FlexE client code block stream of the second transmission rate occupies a second number of time slots, and the second number is different from the first number.

[0044] In some implementations, a transmission rate of each first Ethernet block stream in the multiple first Ethernet block streams is lower than a transmission rate of the first FlexE block stream.

[0045] In some embodiments, the method further includes: receiving multiple second optical signals from a second network device, the multiple second optical signals including multiple second Ethernet code block streams; performing photoelectric conversion on the multiple second optical signals to obtain multiple electrical signals, the multiple electrical signals including multiple second Ethernet code block streams; obtaining a second FlexE code block stream based on the multiple second Ethernet code block streams; and sending the second FlexE code block stream to the first network device through a FlexE channel.

[0046] In some embodiments, obtaining a second FlexE code block stream based on multiple second Ethernet code block streams includes: converting the coding format of the code blocks in the multiple second Ethernet code block streams from the Ethernet coding format to the FlexE coding format to obtain multiple second FlexE client code block streams; obtaining a second FlexE code block stream based on the multiple second FlexE client code block streams. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a panel schematic diagram of a single board using a QSFP28 10ⅹ10G hashed optical module provided in an embodiment of the present application;

[0048] Figure 2 It is a panel schematic diagram of a single board using an SFP+10ⅹ10G hashed optical module provided in an embodiment of the present application;

[0049] Figure 3 It is a schematic diagram of the architecture of a network device provided in an embodiment of the present application;

[0050] Figure 4 yes Figure 3 A schematic diagram of an internal structure of a processing circuit;

[0051] Figure 5 This is a schematic diagram of a FlexE encoding format provided in an embodiment of the present application;

[0052] Figure 6 This is a schematic diagram of an Ethernet encoding format provided in an embodiment of the present application;

[0053] Figure 7 It is a schematic diagram of the architecture of another network device provided in an embodiment of the present application;

[0054] Figure 8 yes Figure 7 Schematic diagram of the architecture of the interface chip inside the optical module;

[0055] Fig. 9 It is a schematic diagram of the architecture of another network device provided in an embodiment of the present application;

[0056] Fig.10 yes Fig. 9 A schematic diagram of the structure of the interface chip inside the optical module;

[0057] Fig.11 It is a schematic diagram of the architecture of another network device provided in an embodiment of the present application;

[0058] Fig.12 is a flow chart of a data transmission method provided in an embodiment of the present application;

[0059] Fig.13 is a flow chart of a data transmission method provided in an embodiment of the present application;

[0060] Fig.14 yes Fig.11 Schematic diagram of the structure of the interface chip inside the optical module. DETAILED DESCRIPTION

[0061] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0062] The following is an example of an application scenario of the embodiment of the present application.

[0063] The embodiments of the present application can be applied to a scenario in which a network device communicates with other network devices based on a high-density hashed optical module. The network device can be a network device such as a switch, a router, a firewall, etc. The network device can also be a part of the components on the network device, such as a single board on the network device (including a main control board, an interface board or a line card, etc.). The network device can also be a functional module on the network device, and can also be a media access control (MAC) chip, a network processor (NP) or a central processing unit (CPU) that supports flexible Ethernet (FlexE). The network device can also be a computing device such as a server or a terminal. The embodiments of the present application mainly take the scenario in which the network device is a single board, such as a single board communicating with a high-density hashed optical module set on the single board as an example.

[0064] Optical modules are electronic devices used to realize photoelectric conversion and / or electro-optical conversion functions in optical fiber communication. Optical modules mainly include electrical interfaces, photoelectric conversion devices, functional circuits and optical interfaces.

[0065] The electrical interface is connected to the network device outside the optical module. The electrical interface is used to transmit electrical signals. The electrical interface can also be called a system-side interface or an electrical signal interface. The electrical interface is, for example, a serializer / deserializer (SerDes) interface. The electrical interface includes one or more pairs of serialized channels (lanes), each pair of lanes includes a receiving channel and a transmitting channel, and each pair of lanes includes a SerDes for sending and a SerDes for receiving.

[0066] The optical interface is connected to the optical fiber. The optical interface is used to transmit optical signals. The optical interface can also be called the line side interface or optical signal interface of the optical module. The optical interface can be an Ethernet interface, and the optical signal transmitted by the optical interface is used to carry a code block stream (hereinafter referred to as Ethernet code block stream) that complies with the Ethernet protocol standard (such as the IEEE 802.3 standard).

[0067] A hashed optical module is an optical module. The main function of a hashed optical module is to hash a higher-speed electrical interface into multiple lower-speed optical interfaces. For example, a hashed optical module converts a set of higher-speed electrical signals received from an electrical interface into multiple lower-speed optical signals, and sends multiple lower-speed optical signals through an optical interface. Since the hashed optical module provides multiple optical interfaces, or supports the output of multiple optical signals, it helps to improve the interface capability to a certain extent. The optical interface of a hashed optical module is usually an optical interface provided by a multi-fiber push on (MPO) connector. The MPO connector uses a multi-core optical fiber structure. For example, an MPO connector has 12 optical fiber cores, thereby supporting the transmission and reception of 12 pairs of optical signals.

[0068] At present, the hash optical module is usually straight-through. That is, the number of channels for transmitting optical signals between the hash optical module and the optical fiber (hereinafter referred to as line-side channels) is the same as the number of channels for transmitting electrical signals between the hash optical module and the network device (hereinafter referred to as system-side channels). For example, the number of line-side channels of the hash optical module is the same as the number of SerDes lanes. In other words, the number of optical signal paths and electrical signal paths transmitted by the hash optical module is the same, and there is a one-to-one correspondence between the optical signal and the electrical signal.

[0069] However, when using a straight-through hash optical module, since the number of line-side channels is the same as the number of system-side channels, the density of the optical interface is too small, resulting in a small number of remote network devices supported by the hash optical module, which affects the interface capabilities of the network devices and leads to certain limitations in application. In addition, the transmission rate of the system-side channel of the hash optical module needs to be reduced to the transmission rate of the line-side channel, resulting in the inability to fully utilize the bandwidth resources of the system-side interface, resulting in a loss of bandwidth resources of the system-side interface.

[0070] For example, typical hashed optical modules include 40G QSFP+SR4 optical modules or 100G QSFP28 SR4 optical modules. Both 40G QSFP+SR4 optical modules and 100G QSFP28 SR4 optical modules have 4 pairs of serdes lanes, and the number of system-side channels and the number of line-side channels are both 4. The basic principle of 40G QSFP+SR4 optical modules and 100G QSFP28 SR4 optical modules is to drive the received 4 electrical signals and then convert them into 4 parallel optical signals through optoelectronic conversion devices, and the way of sending electrical signals is the same. 40G QSFP+SR4 optical modules support hashing out 4 Ethernet interfaces with a rate of 10G, that is, 40G QSFP+SR4 optical modules support the transmission of 4 optical signals, each of which carries a 10G Ethernet code block stream. The 100G QSFP28 SR4 optical module supports hashing out four 25G Ethernet interfaces. The 100G QSFP28 SR4 optical module can transmit four optical signals, each of which carries one 25G Ethernet code block stream.

[0071] In order to improve the density of the optical interface of the hashed optical module, in one implementation, a multi-link gearbox (MLG) chip is added inside the hashed optical module. The main function of the MLG chip is signal rate conversion and channel mapping. In one example, the MLG chip uses bits as units for data distribution, such as assigning a corresponding output channel to each bit in the data stream, and sending the data carried by the bit through the output channel corresponding to the bit. For example, the optical module containing the MLG chip is a 100G SR10 optical module, and the electrical interface of the 100G SR10 optical module is an interface with a rate of 100G. The electrical interface supports the transmission of 4 Ethernet code block streams with a rate of 25G, and the optical interface supports the transmission of 10 Ethernet code block streams with a rate of 10G. When the MLG chip in the 100G SR10 optical module receives a data stream with a rate of 100G from the electrical interface, it sends the first bit in the data stream to the first output channel, and the second bit in the data stream to the second output channel, and so on. This is equivalent to dividing the entire data stream with a rate of 100G into 10 parts, and cyclically distributing each bit in the data stream between the 10 output channels. For the implementation details of MLG, please refer to the description of the OIF-MLG-03.0 standard.

[0072] However, if the MLG chip is added to the hash optical module to increase the optical interface density, the chip on the board that interfaces with the optical module must support the MLG function. If the chip on the board that interfaces with the optical module does not support the MLG function, since the MLG chip does not support the MAC port, it needs to rely on an external MAC chip or the MAC circuit inside the NP to convert it into 10 MAC layer data streams with a rate of 10G, resulting in the need to add a separate MLG chip and MAC chip on the board, which results in high board cost and high PCB layout pressure.

[0073] Based on this, an embodiment of the present application provides a FlexE-based hashed optical module. The hashed optical module includes a FlexE interface. The interface chip in the hashed optical module supports FlexE. The interface chip in the hashed optical module uses the FlexE channelization feature to map the Ethernet interface to the FlexE time slot, or to map the FlexE time slot to the Ethernet interface, so that the number of line-side channels of the hashed optical module is greater than the number of system-side channels, which helps to achieve high-density fan-out of optical interfaces such as 10G, 25G or 50G, and improve the density of the optical interface of the optical module.

[0074] In one possible implementation, the interface chip distributes the received FlexE code block stream to multiple FlexE sub-channels. For example, the chip on the single board generates a FlexE code block stream, and the FlexE code block stream includes a series of 64B / 66B code blocks with a coding format of FlexE. The chip on the single board sends the FlexE code block stream to the hash optical module. After the interface chip in the hash optical module receives the FlexE code block stream, the interface chip uses 64B / 66B code blocks as units for data distribution. For example, the interface chip distributes each 64B / 66B code block in the FlexE code block stream to multiple FlexE sub-channels in sequence to generate multiple FlexE client code block streams. Each FlexE client code block stream includes part of the 64B / 66B code blocks in the FlexE code block stream. After the interface chip converts the coding format of the code blocks in the multiple FlexE client code block streams into the Ethernet coding format, multiple Ethernet code block streams are generated. After the photoelectric conversion, the multiple Ethernet code block streams generate multiple optical signals, and the multiple optical signals are sent to the optical fiber outside the optical module through the optical interface of the hash optical module.

[0075] The FlexE channel is equivalent to the system side channel of the interface chip in the optical module. The FlexE channel can be located between the optical module and the MAC chip on the single board that is connected to the optical module. One end of the FlexE channel can be the FlexE group interface of the interface chip, and the other end of the FlexE channel can be the FlexE group interface of the MAC chip on the single board that is connected to the interface chip. The FlexE channel can be used to transmit the FlexE code block stream between the interface chip and the single board. The transmission rate of the FlexE channel is greater than the transmission rate of the FlexE sub-channel. The 64B / 66B code block means that the code block includes 66 bits, the first two bits of the 66 bits are synchronization bits, and the last 64 bits are data bits.

[0076] The FlexE subchannel is equivalent to the line side channel of the interface chip. The FlexE subchannel can be implemented through the FlexE shim inside the interface chip. The FlexE subchannel can be located between the FlexE shim circuit inside the interface chip and the remote device connected to the optical interface of the optical module through the optical fiber. One end of the FlexE subchannel can be the FlexE shim circuit inside the interface chip, and one end of the FlexE subchannel can be the remote device connected to the optical interface of the optical module. The number of FlexE subchannels is greater than the number of FlexE channels. Each FlexE subchannel carries one FlexE client code block stream.

[0077] Since the interface chip distributes the code blocks in the FlexE code block stream to the corresponding FlexE sub-channel, it is possible to generate multiple lower-rate code block streams (FlexEclient code block streams) based on a higher-rate code block stream (FlexE code block stream) input by the electrical interface, and output multiple lower-rate code block streams (FlexE client code block streams) through the optical interface, so that the number of line-side channels is greater than the number of system-side channels, thereby improving the optical interface density and helping to support the hashing of high-density optical interfaces. In addition, the interface chip achieves a similar function to the MLG chip, and does not require the chip on the board that is connected to the hash optical module to support MLG, thereby reducing dependence on the MLG chip to a certain extent. Since there is no need to deploy the MLG chip on the board, the problems of complex PCB layout on the board, power consumption and cost caused by deploying the MLG chip are reduced, making the implementation solution simpler and lower in cost and power consumption.

[0078] For example, the transmission rate of the FlexE channel is 100G, and the FlexE shim circuit in the interface chip distributes the FlexE code block stream received from the FlexE channel to two FlexE sub-channels in a cyclic manner, so that the transmission rate of each FlexE sub-channel is 50G, or two FlexE client code block streams with a rate of 50G are generated. In one example, the interface chip distributes the first code block in the code block stream received from the FlexE channel to the first FlexE sub-channel, the interface chip distributes the second code block in the code block stream received from the FlexE channel to the second FlexE sub-channel, distributes the third code block in the code block stream received from the FlexE channel to the first FlexE sub-channel, distributes the fourth code block received from the FlexE channel to the second FlexE sub-channel, and so on. The interface chip converts a received FlexE code block stream with a rate of 100G into two FlexE client code block streams with a rate of 50G.

[0079] For example, the transmission rate of the FlexE channel is 100G. The FlexE shim circuit in the interface chip distributes the code block stream received from the FlexE channel to the four FlexE sub-channels in a cyclic manner, so that the transmission rate of each FlexE sub-channel is 25G, or four FlexE client code block streams with a rate of 25G are generated. In an example, the interface chip distributes the first code block in the code block stream received from the FlexE channel to the first FlexE sub-channel, the interface chip distributes the second code block received from the FlexE channel to the second FlexE sub-channel, the third code block received from the FlexE channel to the third FlexE sub-channel, the fourth code block received from the FlexE channel to the fourth FlexE sub-channel, the fifth code block in the code block stream received from the FlexE channel to the first FlexE sub-channel, the interface chip distributes the sixth code block in the code block stream received from the FlexE channel to the second FlexE sub-channel, and so on. The interface chip converts a received FlexE code block stream with a rate of 100G into four FlexE client code block streams with a rate of 25G.

[0080] For another example, the transmission rate of the FlexE channel is 100G, and the FlexE shim circuit in the interface chip will distribute the code block stream received from the FlexE channel to 10 FlexE sub-channels in a cyclic manner, so that the transmission rate of each FlexE sub-channel is 10G, or in other words, 10 FlexE client code block streams with a rate of 10G are generated. In one example, the interface chip distributes the first code block in the code block stream received from the FlexE channel to the first FlexE sub-channel, the interface chip distributes the second code block received from the FlexE channel to the second FlexE sub-channel, the third code block received from the FlexE channel to the third FlexE sub-channel, the fourth code block received from the FlexE channel to the fourth FlexE sub-channel, the fifth code block in the code block stream received from the FlexE channel to the fifth FlexE sub-channel, the interface chip distributes the sixth code block in the code block stream received from the FlexE channel to the sixth FlexE sub-channel, and the interface chip distributes the seventh code block received from the FlexE channel to the sixth FlexE sub-channel. The first code block is distributed to the seventh FlexE sub-channel, the eighth code block received from the FlexE channel is distributed to the eighth FlexE sub-channel, the ninth code block received from the FlexE channel is distributed to the ninth FlexE sub-channel, the tenth code block in the code block stream received from the FlexE channel is distributed to the tenth FlexE sub-channel, the eleventh code block in the code block stream received from the FlexE channel is distributed to the first FlexE sub-channel, the twelfth code block in the code block stream received from the FlexE channel is distributed to the second FlexE sub-channel, and so on. The FlexE code block stream with a rate of 100G received by the electrical interface of the optical module is converted into ten FlexE client code block streams with a rate of 10G.

[0081] FlexE subchannels can be obtained by further dividing FlexE channels based on the time division multiplexing (TDM) mechanism. In one example, a period of time is divided into multiple time slots, each FlexE subchannel occupies one or more time slots, and different FlexE subchannels occupy different time slots. The interface chip can send each code block received from the FlexE channel within a period of time to the optical port through the corresponding time slot. Exemplarily, the transmission rate of the FlexE channel is 100G, and a period of time is divided into 20 time slots. The bandwidth corresponding to one time slot is 5G. The FlexE shim circuit of the interface chip can allocate the bandwidth occupied by a FlexE client code block stream at a granularity of 1 or more times of 5G. The FlexE shim circuit inside the interface chip groups every 20 64B / 66B code blocks in the received FlexE code block stream into a group, maps the 20 64B / 66B code blocks to time slots 0 to 19 respectively, and distributes the 20 64B / 66B code blocks in sequence through time slots 0 to 19, and repeats this cycle to finally form a FlexE sub-channel.

[0082] In one possible implementation, the FlexE shim circuit of the interface chip performs time slot mapping on the input FlexE code block stream based on the time slot configuration information, thereby outputting a FlexE client code block stream of a specified rate. The time slot configuration information includes at least one of the number of time slots occupied by one or more FlexE client code block streams or the time slot positions occupied by one or more FlexE client code block streams. For example, the bandwidth corresponding to a time slot is 5G, and the time slot configuration information indicates that the FlexE client code block stream occupies 2 time slots. The FlexE shim circuit selects any two time slots from time slot 0 to time slot 19 as time slots occupied by a FlexE client code block stream, and maps the FlexE client code block stream to 2 time slots, so that the rate of the output FlexE client code block stream is 5G*2=10G. For another example, the time slot configuration information indicates that the FlexE client code block stream occupies 5 time slots. The FlexE shim circuit selects any five time slots from time slot 0 to time slot 19 as the time slots occupied by a FlexE client code block stream, and maps the FlexE client code block stream to 5 time slots, so that the output FlexE client code block stream rate is 5G*5=25G.

[0083] In one possible implementation, the FlexE shim circuit of the interface chip maps the code blocks in the FlexE code block stream to different numbers of time slots based on the time slot configuration information, thereby supporting the output of multiple FlexE client code block streams of different rates. Exemplarily, the time slot configuration information includes a first number of time slots occupied by the first FlexE client code block stream and a second number of time slots occupied by the second FlexE client code block stream. The FlexE shim circuit maps part of the code blocks in the FlexE code block stream to the first number of time slots based on the time slot configuration information to obtain a first FlexE client code block stream of a first transmission rate; the FlexE shim circuit maps another part of the code blocks in the FlexE code block stream to the second number of time slots based on the time slot configuration information to obtain a first FlexE client code block stream of a second transmission rate.

[0084] In an exemplary scenario, some Ethernet network devices cannot provide more Ethernet interfaces due to limited interface space on a single board. For example, when an Ethernet network device cannot provide a higher density 10G SFP+ interface, the network device can use a QSFP28 100G FlexE interface (4ⅹ25G) to connect to an optical module with a package type of QSFP28. The 100GQSFP28 optical module can use the method provided in the embodiment of the present application to hash a QSFP28 100G interface into 10 Ethernet interfaces with a rate of 10G, forming a QSFP28 10ⅹ10G hashed optical module, which greatly improves the density of the 10G Ethernet interface. After installing a QSFP28 10ⅹ10G hashed optical module on an Ethernet network device, it can be connected to 10 10G SFP+ interfaces of a remote device through the QSFP28 10ⅹ10G hashed optical module, thereby increasing the number of devices that the Ethernet network device can connect to.

[0085] For example, please refer to the attached Figure 1 , attached Figure 1 1 is a schematic diagram of a panel of a single board using a QSFP28 10ⅹ10G hashed optical module provided in an embodiment of the present application, Figure 1 The single board shown includes 4 QSFP28 100G interfaces, each of which can be connected to a QSFP28 10ⅹ10G hashing optical module provided in an embodiment of the present application. Each QSFP28 10ⅹ10G hashing optical module can hash out 10 Ethernet interfaces with a rate of 10G. The 4 QSFP28 10ⅹ10G hashing optical modules hash out a total of 40 Ethernet interfaces with a rate of 10G (represented by 40ⅹ10G in the figure), so that the single board can provide a total of 40 Ethernet interfaces with a rate of 10G. Figure 2is a schematic diagram of another panel provided in an embodiment of the present application, Figure 2 The board shown includes 10 SFP+ interfaces with a rate of 10G. Figure 2 A 10G Ethernet interface hashed from a QSFP28 100G interface can be used to communicate with the attached Figure 2 A 10G SFP+ interface is used for connection.

[0086] In another exemplary scenario, the system side interface of the optical module is an interface with a rate of 200G, and the physical interface corresponding to the system side interface includes 4 pairs of serializer / deserializer channels (serdes lanes) and the rate of each pair of serdes lanes is 53G. If a straight-through hashing optical module is used, in order to connect the hashing optical module with the Ethernet interface with a rate of 10G of the remote device, the transmission rate of each pair of serdes lanes in the hashing optical module needs to be reduced from 53 to 10, thereby providing 4 Ethernet interfaces with a rate of 10, resulting in the inability to fully utilize the system side bandwidth and too few Ethernet interfaces provided. However, by using the optical module provided in the embodiment of the present application, the optical module can hash the system side interface with a rate of 200G into 8 Ethernet interfaces with a rate of 25G, thereby not sacrificing the system side bandwidth and increasing the number of optical interfaces.

[0087] In another exemplary scenario, a system-side interface with a rate of 400G (the physical interface includes 4 pairs of serdes lanes and the rate of each pair of serdes lanes is 112G) can be hashed into 8 optical interfaces with a rate of 50G.

[0088] To summarize the various scenarios listed above, in the scenario where the transmission rate of the system-side interface of the optical module is high and the number of serdes lanes in the system-side interface is small, if an ordinary hashing optical module is used, the serdes can only be slowed down and used, and the number of optical interfaces cannot be increased. However, through the method provided in the embodiment of the present application, the number of optical interfaces can be increased as much as possible without sacrificing the system-side bandwidth; for example, when a 100G interface uses an ordinary hashing optical module, the rate of 4 pairs of 25G serdes lanes on the system side can only be reduced from 25 to 10, and 4 10G interfaces are hashed, while by using the method provided in this embodiment, 10 10G interfaces can be hashed.

[0089] Optionally, the FlexE interface of the optical module and the processing circuit of the optical module are both provided in the interface chip, by integrating the FlexE interface and the processing circuit in the same chip, or the FlexE interface and the processing circuit are separately provided in different chips.

[0090] In some embodiments, the optical module can be deployed outside the network device, for example, the optical module includes a housing; the housing is provided with an electrical interface and multiple optical interfaces, the electrical interface is used to connect to the network device outside the optical module; an interface chip is arranged in the housing, the interface chip includes a FlexE interface, a processing circuit and multiple Ethernet interfaces, the FlexE interface is opposite to the electrical interface, the processing circuit is used to convert the FlexE code block stream received by the FlexE interface into a multiple Ethernet code block stream and output the multiple Ethernet code block stream to the multiple Ethernet interfaces, the multiple Ethernet interfaces correspond to the multiple optical interfaces one by one; an optoelectronic conversion device is arranged in the housing, one end of the optoelectronic conversion device is electrically connected to the multiple Ethernet interfaces of the interface chip, and the other end of the optoelectronic conversion device is opposite to the multiple optical interfaces. In some embodiments, the optical module is deployed inside the network device.

[0091] The optical module, the network device including the optical module, and the data transmission method based on the optical module provided in the embodiments of the present application are further illustrated with reference to four examples below.

[0092] Example 1

[0093] Attached Figure 3 1 is a schematic diagram of the architecture of a network device 1 provided in an embodiment of the present application. Figure 3 The network device 1 shown includes an optical module 10 and a PCB 20 .

[0094] Attached Figure 3 The optical module 10 shown is a 10x10G hashing optical module. Figure 3 The optical module 10 shown supports hashing the 100G FlexE interface on the system side into 10 10G Ethernet interfaces on the line side. The 100G FlexE interface on the system side can be implemented using 4 serdes lanes with a transmission rate of 25G. Figure 3 The optical module 10 shown can convert four serdes lanes with a transmission rate of 25G on the system side into ten Ethernet channels with a rate of 10G on the line side.

[0095] The optical module 10 can be a Quad Small Form-factor Pluggable 28 (QSFP28) optical module. The optical module 10 includes a housing 18, an interface chip 11, an optoelectronic conversion device 12, and an optical port connector 13. The optical port connector 13 includes an optical interface 14. The interface chip 11, the optoelectronic conversion device 12, and the optical port connector 13 are arranged in the housing 18. The interface chip 11 and the optoelectronic conversion device 12 are arranged inside the housing 18 of the optical module 10. The interface chip 11, the optoelectronic conversion device 12, and the optical port connector 13 are connected in series in sequence. In a possible implementation, the interface chip 11, the optoelectronic conversion device 12, the optical port connector 13, and the optical interface 14 are interconnected through a path (such as a bus, an optical fiber, or other types of signal lines) inside the optical module 10.

[0096] The interface chip 11 includes a system side interface 111, a processing circuit 112 and a line side interface 113. The system side interface 111, the processing circuit 112 and the line side interface 113 are connected in series in sequence.

[0097] The system side interface 111 is communicatively connected with the MAC chip 21 on the PCB 20. The system side interface 111 includes one or more FlexE interfaces. The system side interface 111 may include a 100G FlexE interface, and the system side interface 111 is used to transmit a FlexE code block stream with a rate of 100G between the optical module 10 and the PCB 20. In one possible implementation, the interface chip 11 configures the working mode of the system side interface 111 to the FlexE mode, so that the system side interface 111 implements the function of the FlexE interface. The system side interface 111 is connected to the MAC chip 21 through the FlexE channel 310. The system side interface 111 can be an electrical signal interface. In other words, the system side interface 111 is used to transmit the FlexE code block stream between the processing circuit 112 and the MAC chip 21 in the form of an electrical signal. The system side interface 111 may include multiple physical interfaces. Each physical interface in the system side interface 111 can be connected to the MAC chip 21 through a signal line. Exemplarily, the system side interface 111 includes a 4-lane serdes interface, which is connected to the PCB 20 via 4 pairs of differential signal lines, and the 4 pairs of differential signal lines are used to transmit four pairs of electrical signals, each pair of differential signal lines includes two signal lines, one signal line is used to receive one electrical signal, and the other signal line is used to send one electrical signal. Figure 3, the system side interface 111 includes interface 0, interface 1, interface 2 and interface 3 in the sending direction and interface 0, interface 1, interface 2 and interface 3 in the receiving direction. Interface 0 in the sending direction and interface 0 in the receiving direction belong to the serdes interface of the first pair of lanes, and interface 1 in the sending direction and interface 1 in the receiving direction belong to the serdes interface of the second pair of lanes. The receiving interface and the sending interface in the system side interface 111 can be implemented through the same physical interface, and the receiving interface and the sending interface in the system side interface 111 can also be implemented through different physical interfaces. The system side interface 111 may include one or more FlexEgroup interfaces. For example, the interface chip 11 adds interface 0, interface 1, interface 2 and interface 3 to the same FlexE group, and based on the bundling characteristics of FlexE, enables interface 0, interface 1, interface 2 and interface 3 to collaborate to implement a FlexE group interface.

[0098] The processing circuit 112 is used to implement the conversion between the FlexE code block stream and the Ethernet code block stream. For example, the processing circuit 112 is used to implement the conversion between the FlexE code block stream with a rate of 100G and the 10-way Ethernet code block stream with a rate of 10G. In the process of PCB 20 sending a signal to the optical module 10, the processing circuit 112 is used to convert the received FlexE code block stream with a rate of 100G into a 10-way Ethernet code block stream with a rate of 10G, thereby hashing the FlexE interface with a rate of 100G into a 10-way Ethernet interface with a rate of 10G. In one possible implementation, the processing circuit 112 is used to distribute the code blocks in the FlexE code block stream with a rate of 100G to 10 time slots in sequence based on the time slot mapping mechanism of the FlexE shim, so as to generate a 10-way Ethernet code block stream with a rate of 10G. In the process of the remote device sending a signal to the optical module 10 through the optical fiber 40, the processing circuit 112 is used to convert the received 10-channel Ethernet code block stream with a rate of 10G into a FlexE code block stream with a rate of 100G. The processing circuit 112 may include an integrated circuit or a microprocessor for realizing the conversion between the FlexE code block stream and the Ethernet code block stream. For example, the processing circuit 112 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general array logic (GAL) or any combination thereof.

[0099] The line side interface 113 is communicatively connected with the photoelectric conversion device 12. The line side interface 113 includes one or more Ethernet interfaces. The line side interface 113 is used to transmit the Ethernet code block stream between the photoelectric conversion device 12 and the processing circuit 112. For example, the line side interface 113 is a 10x10G Ethernet interface. The line side interface 113 is used to transmit 10 Ethernet code block streams with a rate of 10G. For example, the line side interface 113 includes interface 0, interface 1, interface 2 to interface 9 in the sending direction and interface 0, interface 1, interface 2 to interface 9 in the receiving direction. Interface 0 is used to transmit the first Ethernet code block stream with a rate of 10G. Interface 1 is used to transmit the second Ethernet code block stream with a rate of 10G. Interface 1 is used to transmit the second Ethernet code block stream with a rate of 10G. By analogy, interface 9 is used to transmit the ninth Ethernet code block stream with a rate of 10G. The line side interface 113 can be an electrical signal interface. In other words, the line side interface 113 is used to transmit the Ethernet block stream in the form of electrical signals between the processing circuit 112 and the optoelectronic conversion device 12. The receiving interface and the transmitting interface in the line side interface 113 can be implemented through the same physical interface, or the receiving interface and the transmitting interface in the line side interface 113 can be implemented through different physical interfaces.

[0100] The photoelectric conversion device 12 includes an optical transmitter 121 and an optical receiver 122. One end of the optical transmitter 121 is connected to the line side interface 113 of the interface chip 11, and the other end of the optical transmitter 121 is connected to the optical port connector 13. The optical transmitter 121 is used to convert the electrical signal from the interface chip 11 into an optical signal and then send it to the optical port connector 13. Specifically, the optical transmitter 121 receives 10 electrical signals from the line side interface 113 of the interface chip 11, and each of the 10 electrical signals includes an Ethernet code block stream with a rate of 10G. The optical transmitter 121 converts the 10 electrical signals into 10 optical signals, and each of the 10 optical signals includes an Ethernet code block stream with a rate of 10G. The optical transmitter 121 sends the 10 optical signals to the optical port connector 13. The optical transmitter 121 may include a light source circuit. The light source circuit 1213 is a circuit element capable of generating light signals, such as a laser diode (LD) or a light emitting diode (LED). The light source circuit 1213 is used to generate 10 optical signals based on 10 electrical signals.

[0101] The optical receiver 122 is used to convert the optical signal from the optical port connector 13 into an electrical signal and then send it to the interface chip 11. For example, the optical receiver 122 receives 10 optical signals from the optical port connector 13, and each of the 10 optical signals includes an Ethernet code block stream with a rate of 10G. The optical receiver 122 converts the 10 optical signals into 10 electrical signals, and each of the 10 electrical signals includes an Ethernet code block stream with a rate of 10G. The optical receiver 122 sends the 10 electrical signals to the line side interface 113 of the interface chip 11. The optical receiver 122 may include a photodetection circuit. The photodetection circuit is, for example, a photosensitive detector (such as a photodiode or a photodiode array) and related circuits. The photodetection circuit is used to convert 10 optical signals into 10 electrical signals, such as current signals or voltage signals.

[0102] The optical port connector 13 is also called a fiber optic interface connector, that is, a fiber optic connector connected to an optical module. The optical port connector 13 is used to connect to the optical fiber 40. The optical port connector 13 is used to transmit the optical signal between the optical fiber 40 and the optoelectronic conversion device 12. One end of the optical port connector 13 is connected to the optoelectronic conversion device 12. The other end of the optical port connector 13 is connected to the optical fiber 40. The optical port connector 13 includes a plurality of optical interfaces 14. For example, the plurality of optical interfaces 14 include 10 optical interfaces, namely, optical interface 0, optical interface 1 to optical interface 9 in the sending direction, and 10 optical interfaces, namely, optical interface 0, optical interface 1 to optical interface 9 in the receiving direction. Optical interface 0 is used to transmit the first optical signal between the optical fiber 40 and the optoelectronic conversion device 12. Optical interface 1 is used to transmit the second optical signal between the optical fiber 40 and the optoelectronic conversion device 12. Similarly, optical interface 9 is used to transmit the tenth optical signal between the optical fiber 40 and the optoelectronic conversion device 12. The optical port connector 13 is, for example, an MPO connector.

[0103] PCB 20 is used to generate four electrical signals, and the four electrical signals carry 100G FlexE code block streams. PCB 20 transmits the four electrical signals to the optical module 10. PCB 20 is, for example, a main control board. PCB 20 is also an interface board. PCB 20 is also a circuit board where a processor is located. For example, PCB 20 is a circuit board where an NP or a CPU is located. PCB 20 includes a MAC chip 21.

[0104] The FlexE channel 310 is a FlexE channel in the sending direction (from the PCB 20 to the optical module 10). The FlexE channel 310 is used to transmit the FlexE code block stream transmitted from the PCB 20 to the optical fiber 40 through the optical module 10. The FlexE channel 310 includes a FlexE interface located at the optical module 10 and a FlexE interface located at the PCB 20. In one example, the FlexE channel 310 includes a FlexE interface located at the interface chip 11 and a FlexE interface located at the MAC chip 21. For example, the FlexE channel 310 includes four physical interfaces, namely, interface 0, interface 1, interface 2, and interface 3 located at the interface chip 11, and each of the four physical interfaces is used to receive a FlexE code block stream with a rate of 25G from the PCB 20. The FlexE channel 310 can be a FlexE group channel. The FlexE channel 310 includes a FlexE group interface located at the interface chip 11 and a FlexE group interface located at the MAC chip 21.

[0105] FlexE channel 320 is a FlexE channel in the receiving direction (from optical module 10 to PCB 20). FlexE channel 320 is used to transmit the FlexE code block stream transmitted from optical fiber 40 to PCB 20 through optical module 10. FlexE channel 320 includes four physical interfaces, namely interface 0, interface 1, interface 2 and interface 3, located on interface chip 11. Each of the four physical interfaces is used to send a FlexE code block stream with a rate of 25G to PCB 20. FlexE channel 320 can be a FlexE group channel. FlexE channel 320 includes a FlexE group interface located on interface chip 11 and a FlexE group interface located on MAC chip 21.

[0106] In the process of PCB 20 sending signals to the optical module 10, the MAC chip 21 generates 4 electrical signals. The 4 electrical signals are used as a whole to carry a FlexE code block stream with a rate of 100G. Each of the 4 electrical signals carries a FlexE code block stream with a rate of 25G, that is, 4×25G FlexE code block streams. The MAC chip 21 sends 4 electrical signals to the system side interface 111 of the interface chip 11 in the optical module 10. The system side interface 111 of the interface chip 11 receives the 4 electrical signals from the MAC chip 21 through the FlexE channel 310. The system side interface 111 of the interface chip 11 sends the 4 electrical signals carrying the FlexE code block stream with a rate of 100G to the processing circuit 112 inside the interface chip 11. For example, please refer to the attached Figure 3In the transmit (Transmit, TX) direction, the system side interface 111 includes four FlexE interfaces, namely, interface 0, interface 1, interface 2 and interface 3. Interface 0 in the system side interface 111 receives the first electrical signal (TX0) from PCB 20, and the first electrical signal (TX0) includes a FlexE code block stream with a rate of 25G. Interface 0 sends the first electrical signal to the processing circuit 112. Interface 1 in the system side interface 111 receives the second electrical signal (TX1) from PCB 20, and the second electrical signal (TX1) includes a FlexE code block stream with a rate of 25G. Interface 1 sends the second electrical signal to the processing circuit 112. Interface 2 in the system side interface 111 receives the third electrical signal from PCB 20, and the third electrical signal (TX3) includes a FlexE code block stream with a rate of 25G. Interface 2 sends the third electrical signal to the processing circuit 112. Interface 3 in the system-side interface 111 receives the fourth electrical signal (TX4) from PCB 20 , where the fourth electrical signal (TX4) includes a FlexE code block stream with a rate of 25G. Interface 3 sends the fourth electrical signal to the processing circuit 112 .

[0107] The processing circuit 112 obtains FlexE code block streams with a rate of 100G carried by 4 electrical signals. The processing circuit 112 performs time slot mapping based on the FlexE code block stream with a rate of 100G to obtain 10 Ethernet code block streams, and the transmission rate of each of the 10 Ethernet code block streams is 10G. The processing circuit 112 obtains 10 electrical signals based on the 10 Ethernet code block streams with a rate of 10G, and the processing circuit 112 sends 10 electrical signals to the line side interface 113 of the interface chip 11, each of which carries 1 Ethernet code block stream with a rate of 10G. The line side interface 113 of the interface chip 11 sends 10 electrical signals to the optical transmitter 121. For example, please refer to the attached Figure 3 In the TX direction, the line side interface 113 of the interface chip 11 includes 10 Ethernet interfaces, namely, interface 0, interface 1, interface 2 to interface 9. Interface 0 in the line side interface 113 sends the first electrical signal carrying the Ethernet block stream at a rate of 10G to the optical transmitter 121. Interface 1 in the line side interface 113 sends the second electrical signal carrying the Ethernet block stream at a rate of 10G to the optical transmitter 121. Similarly, interface 9 in the line side interface 113 sends the tenth electrical signal carrying the Ethernet block stream at a rate of 10G to the optical transmitter 121.

[0108] The optical transmitter 121 receives 10 electrical signals from the line side interface 113. The optical transmitter 121 performs electrical-optical conversion on the 10 electrical signals to obtain 10 optical signals, each of which carries 1 Ethernet block stream with a rate of 10G. The optical transmitter 121 sends the 10 optical signals to the optical port connector 13. The optical port connector 13 sends the 10 optical signals to the optical fiber 40 through the optical interface 14. The optical fiber 40 sends the 10 optical signals to the remote device (the remote device is not shown in the figure).

[0109] When the remote device sends a signal to the optical module 10, the optical fiber 40 sends 10 optical signals to the optical interface 14, and each of the 10 optical signals carries one Ethernet code block stream with a rate of 10G. The optical port connector 13 sends the 10 optical signals to the optical receiver 122. The optical receiver 122 receives the 10 optical signals, and performs photoelectric conversion on the 10 optical signals to obtain 10 electrical signals, and each of the 10 electrical signals carries one Ethernet code block stream with a rate of 10G. The optical receiver 122 sends the 10 electrical signals to the line side interface 113 of the interface chip 11.

[0110] The line side interface 113 of the interface chip 11 sends 10 electrical signals to the processing circuit 112. For example, the line side interface 113 includes 10 Ethernet interfaces, namely, interface 0, interface 1, interface 2 to interface 9. Interface 0 in the line side interface 113 sends the first electrical signal carrying the Ethernet block stream at a rate of 10G to the processing circuit 112. Interface 1 in the line side interface 113 sends the second electrical signal carrying the Ethernet block stream at a rate of 10G to the processing circuit 112. Similarly, interface 9 in the line side interface 113 sends the tenth electrical signal carrying the Ethernet block stream at a rate of 10G to the processing circuit 112.

[0111] The processing circuit 112 receives 10 electrical signals and obtains 10 Ethernet block streams with a rate of 10G carried by the 10 electrical signals. The processing circuit 112 performs time slot mapping on the 10 Ethernet block streams with a rate of 10G to obtain a FlexE block stream with a rate of 100G. The processing circuit 112 obtains 4 electrical signals based on the FlexE block stream with a rate of 100G. The 4 electrical signals are used as a whole to carry a FlexE block stream with a rate of 100G, and each of the 4 electrical signals carries a FlexE block stream with a rate of 25G. The processing circuit 112 sends the 4 electrical signals to the system side interface 111. The system side interface 111 sends the 4 electrical signals to the MAC chip 21 through the FlexE channel 320. For example, please refer to the attached Figure 3In the receive (Receive, RX) direction, the system side interface 111 includes interface 0, interface 1, interface 2 and interface 3. Interface 0 is used to receive the first electrical signal (RX0) from the processing circuit 112, and interface 0 sends the received first electrical signal (RX0) to the MAC chip 21. The first electrical signal (RX0) includes a FlexE code block stream with a rate of 25G. Interface 1 is used to receive the second electrical signal (RX1) from the processing circuit 112, and interface 1 sends the received second electrical signal (RX0) to the MAC chip 21. The second electrical signal (RX1) includes a FlexE code block stream with a rate of 25G. Interface 2 is used to receive the third electrical signal (RX2) from the processing circuit 112, and interface 2 sends the received third electrical signal (RX2) to the MAC chip 21. The third electrical signal (RX2) includes a FlexE code block stream (RX2) with a rate of 25G. The interface 3 is used to receive the fourth electrical signal (RX3) from the processing circuit 112, and the interface 3 sends the received fourth electrical signal (RX3) to the MAC chip 21. The fourth electrical signal (RX3) includes a FlexE code block stream with a rate of 25G.

[0112] Attached Figure 4 Yes Figure 3 Schematic diagram of the internal structure of the processing circuit 112. The processing circuit 112 includes a system-side PCS circuit 1121, a FlexE shim circuit 1122, a 64B / 66B transcoding adaptation circuit 1123, and a line-side PCS circuit 1124. The system-side PCS circuit 1121, the FlexE shim circuit 1122, the 64B / 66B transcoding adaptation circuit 1123, and the line-side PCS circuit 1124 are connected in series in sequence.

[0113] The system-side PCS circuit 1121 is used to connect to the PCS circuit (not shown in the figure) in the MAC chip 21. The system-side PCS circuit 1121 performs PCS layer processing on the received FlexE code block stream.

[0114] The FlexE shim circuit 1122 is used to perform time slot mapping to achieve conversion between a FlexE code block stream with a rate of 100G and 10 FlexE client code block streams with a rate of 10G. The FlexE shim circuit 1122 is equivalent to logically dividing the FlexE interface with a rate of 100G into 10 FlexE client interfaces, and the transmission rate of each FlexE client interface is 10G. For example, the bandwidth corresponding to a time slot is 5G, and the FlexE shim circuit 1122 configures each FlexE client code block stream to occupy 2 time slots. In this way, the FlexE shim circuit 1122 increases the number of channels on the line side while almost not losing bandwidth resources on the system side.

[0115] The 64B / 66B transcoding adaptation circuit 1123 is used to implement the conversion between the code blocks in the FlexE coding format and the code blocks in the Ethernet coding format. For example, the code blocks received by the FlexE interface follow the following Figure 5 The 64B / 66B encoding format of the 10G Ethernet interface 113 complies with the IEEE 802.3 64B / 66B blocks formats shown in the attached figure. Figure 6 The IEEE 802.3 64B / 66B blocks formats shown in FIG. 64B / 66B transcoding adaptation circuit 1123 inside the interface chip is used to implement the conversion between the two encoding formats.

[0116] The line-side PCS circuit 1124 is used to connect to the PCS circuit in the remote device. The line-side PCS circuit 1124 performs PCS layer processing on the received FlexE code block stream.

[0117] When the PCB 20 sends a signal to the optical module 10, the processing circuit 112 receives a FlexE code block stream with a rate of 100G, and the system-side PCS circuit 1121 performs PCS layer processing on the FlexE code block stream with a rate of 100G, and sends the processed FlexE code block stream with a rate of 100G to the FlexE shim circuit 1122. When the FlexE shim circuit 1122 receives the FlexE code block stream with a rate of 100G, the FlexE shim circuit 1122 performs time slot mapping on the FlexE code block stream with a rate of 100G, and generates 10 FlexE client code block streams with a rate of 10G. The FlexE shim circuit 1122 sends 10 FlexE client code block streams with a rate of 10G to the 64B / 66B transcoding adaptation circuit 1123. The 64B / 66B transcoding adaptation circuit 1123 receives the 10 FlexE client code block streams with a rate of 10G, and the 64B / 66B transcoding adaptation circuit 1123 changes the encoding format of each code block in each FlexE client code block stream with a rate of 10G in the 10 FlexE client code block streams with a rate of 10G from the following: Figure 5 The FlexE encoding format shown is converted to the attached Figure 6 The Ethernet encoding format shown in FIG. 11 is used to obtain 10 Ethernet code block streams with a rate of 10G. The 64B / 66B transcoding adaptation circuit 1123 sends the 10 Ethernet code block streams with a rate of 10G to the line side PCS circuit 1124. The line side PCS circuit 1124 performs PCS layer processing on the 10 Ethernet code block streams with a rate of 10G and sends them to the line side interface 113. Based on this, the interface chip 11 implements hashing of a FlexE interface with a rate of 100G into 10 Ethernet interfaces with a rate of 10G, thereby improving the density of the Ethernet interface on the line side.

[0118] In the process of the optical module 10 sending a signal to the PCB 20, the processing circuit 112 receives 10 Ethernet code block streams with a rate of 10G, and the line-side PCS circuit 1124 performs PCS layer processing on the 10 Ethernet code block streams with a rate of 10G and sends them to the 64B / 66B transcoding adaptation circuit 1123. The 64B / 66B transcoding adaptation circuit 1123 converts the encoding format of each code block in each Ethernet code block stream with a rate of 10G in the 10 Ethernet code block streams with a rate of 10G from the attached Figure 6 The Ethernet encoding format shown is converted to the following Figure 5The FlexE encoding format shown in the figure obtains 10 FlexE client code block streams with a rate of 10G. The 64B / 66B transcoding adaptation circuit 1123 sends the 10 FlexE client code block streams with a rate of 10G to the system side PCS circuit 1121. The system side PCS circuit 1121 performs PCS layer processing on the 10 FlexE client code block streams with a rate of 10G and sends them to the system side interface 111. Based on this, the interface chip 11 realizes mapping 10 Ethernet interfaces with a rate of 10G to FlexE interfaces with a rate of 100G.

[0119] Example 2

[0120] Attached Figure 7 1 is a schematic diagram of the architecture of another network device 1 provided in an embodiment of the present application. Figure 7 In the architecture shown, the optical module 10 is an 8x25G hashing optical module. The optical module 10 supports hashing the 200G FlexE interface on the system side into 8 25G Ethernet interfaces. The 200G FlexE interface on the system side can be implemented using 4 53G serdes lanes. Figure 3 The optical module 10 shown can convert four serdes lanes with a transmission rate of 53G on the system side into eight Ethernet channels with a rate of 25G on the line side.

[0121] The system side interface 111 of the optical module 10 is a FlexE interface with a transmission rate of 200G. The system side interface 111 is used to transmit a FlexE code block stream with a transmission rate of 200G between the optical module 10 and the MAC chip 21. The physical interface corresponding to the system side interface 111 can be a 4lane serdes interface. The line side interface 113 of the optical module 10 is an 8x25G Ethernet interface, and the line side interface 113 is used to transmit 8 Ethernet code block streams, and the transmission rate of each Ethernet code block stream is 25G.

[0122] In the process of PCB 20 sending signals to the optical module 10, the MAC chip 21 generates 4 electrical signals, and the 4 electrical signals are used as a whole to carry a FlexE code block stream with a rate of 200G. Each of the 4 electrical signals carries a FlexE code block stream with a rate of 53G, that is, 4×53G FlexE code block streams. The system side interface 111 receives 4 electrical signals; the processing circuit 112 obtains the FlexE code block stream with a rate of 200G carried by the 4 electrical signals. The processing circuit 112 performs time slot mapping on the FlexE code block stream with a rate of 200G to obtain 8 Ethernet code block streams. The rate of each of the 8 Ethernet code block streams is 25G. The processing circuit 112 sends 8 electrical signals to the line side interface 113, and each electrical signal carries 1 Ethernet code block stream with a rate of 25G. The line side interface 113 of the interface chip 11 sends 8 electrical signals to the optical transmitter 121. For example, please refer to the attached Figure 7 In the TX direction, the line side interface 113 of the interface chip 11 includes 10 Ethernet interfaces, namely interface 0, interface 1, interface 2 to interface 7. Interface 0 in the line side interface 113 sends the first electrical signal carrying an Ethernet block stream at a rate of 25G to the optical transmitter 121. Interface 1 in the line side interface 113 sends the second electrical signal carrying an Ethernet block stream at a rate of 25G to the optical transmitter 121. Similarly, interface 7 in the line side interface 113 sends the eighth electrical signal carrying an Ethernet block stream at a rate of 25G to the optical transmitter 121. The optical transmitter 121 receives 8 electrical signals from the line side interface 113. The optical transmitter 121 performs electrical-to-optical conversion on the 8 electrical signals to obtain 8 optical signals, each of which carries 1 Ethernet block stream at a rate of 25G. The optical transmitter 121 sends the 8 optical signals to the optical port connector 13. The optical port connector 13 sends the 8 optical signals to the optical fiber 40 through the optical interface 14. The optical fiber 40 sends the 8 optical signals to the remote device.

[0123] In the process of the remote device sending a signal to the optical module 10, the optical fiber 40 sends 8 optical signals to the optical interface 14, and each of the 8 optical signals carries 1 Ethernet code block stream with a rate of 25G. The optical port connector 13 sends the 8 optical signals to the optical receiver 122. The optical receiver 122 receives the 8 optical signals, and the optical receiver 122 performs photoelectric conversion on the 8 optical signals to obtain 8 electrical signals, and each of the 8 electrical signals carries 1 Ethernet code block stream with a rate of 25G. The optical receiver 122 sends the 8 electrical signals to the line side interface 113 of the interface chip 11. The line side interface 113 of the interface chip 11 sends the 8 electrical signals to the processing circuit 112. For example, the line side interface 113 includes 8 Ethernet interfaces, namely interface 0, interface 1, interface 2 to interface 7. Interface 0 in the line side interface 113 sends the first electrical signal carrying the Ethernet code block stream with a rate of 25G to the processing circuit 112. Interface 1 in the line side interface 113 sends the second electrical signal carrying the Ethernet block stream at a rate of 25G to the processing circuit 112. Similarly, interface 7 in the line side interface 113 sends the eighth electrical signal carrying the Ethernet block stream at a rate of 25G to the processing circuit 112. The processing circuit 112 receives 8 electrical signals and obtains 8 Ethernet block streams at a rate of 25G carried by the 8 electrical signals. The processing circuit 112 performs time slot mapping on the 8 Ethernet block streams at a rate of 25G to obtain a FlexE block stream at a rate of 200G. The processing circuit 112 obtains 4 electrical signals based on the FlexE block stream at a rate of 200G, and the 4 electrical signals are used as a whole to carry the FlexE block stream at a rate of 200G, and each of the 4 electrical signals carries a FlexE block stream at a rate of 53G. The processing circuit 112 sends 4 electrical signals to the system side interface 111. The system side interface 111 sends the four electrical signals to the MAC chip 21 through the FlexE channel 320. For example, please refer to the attached Figure 7In the RX direction, the system side interface 111 includes interface 0, interface 1, interface 2 and interface 3. Interface 0 is used to receive the first electrical signal (RX0) from the processing circuit 112, and interface 0 sends the received first electrical signal (RX0) to the MAC chip 21. The first electrical signal (RX0) includes a FlexE code block stream with a rate of 53G. Interface 1 is used to receive the second electrical signal (RX1) from the processing circuit 112, and interface 1 sends the received second electrical signal (RX0) to the MAC chip 21. The second electrical signal (RX1) includes a FlexE code block stream with a rate of 53G. Interface 2 is used to receive the third electrical signal (RX2) from the processing circuit 112, and interface 2 sends the received third electrical signal (RX2) to the MAC chip 21. The third electrical signal (RX2) includes a FlexE code block stream (RX2) with a rate of 53G. The interface 3 is used to receive the fourth electrical signal (RX3) from the processing circuit 112, and the interface 3 sends the received fourth electrical signal (RX3) to the MAC chip 21. The fourth electrical signal (RX3) includes a FlexE code block stream with a rate of 53G.

[0124] Please refer to the attached Figure 8 , attached Figure 8 Yes Figure 7 The structure diagram of the interface chip 11 in the optical module 10 is shown in the attached figure. Figure 8 As shown, in the process of PCB 20 sending a signal to the optical module 10, the system side interface 111 sends a FlexE code block stream with a rate of 200G to the FlexE shim circuit 1122. Based on time slot mapping, the FlexE shim circuit 1122 converts the FlexE code block stream with a rate of 200G into 8 FlexE client code block streams. The transmission rate of each FlexE client code block stream in the 8 FlexE client code block streams is 25G. The FlexE shim circuit 1122 is equivalent to logically dividing the FlexE interface with a rate of 200G into 8 FlexE client interfaces, and the transmission rate of each FlexE client interface is 25G. For example, the bandwidth corresponding to a time slot is 5G, and the FlexE shim circuit 1122 configures each FlexE client code block stream to occupy 5 time slots. In this way, the FlexEshim circuit 1122 increases the number of channels on the line side while almost not losing bandwidth resources on the system side.

[0125] The 64B / 66B transcoding adaptation circuit 1123 converts the encoding format of each code block in each FlexE client code block stream with a rate of 25G in the 8 FlexE client code block streams from the following Figure 5 The FlexE encoding format shown is converted to the attached Figure 6 The Ethernet encoding format shown in FIG. 1 obtains 8 Ethernet code block streams, each of which has a rate of 25G. Based on this, the interface chip 11 implements hashing a FlexE interface with a rate of 200G into 8 Ethernet interfaces with a rate of 25G.

[0126] When the optical module 10 sends a signal to the PCB 20, the processing circuit 112 receives 8 Ethernet code block streams, and the rate of each Ethernet code block stream in the 8 Ethernet code block streams is 25G. The line-side PCS circuit 1124 performs PCS layer processing on the 8 Ethernet code block streams with a rate of 25G and sends them to the 64B / 66B transcoding adaptation circuit 1123. The 64B / 66B transcoding adaptation circuit 1123 converts the encoding format of each code block in each Ethernet code block stream with a rate of 25G in the 8 Ethernet code block streams with a rate of 25G from the attached Figure 6 The Ethernet encoding format shown is converted to the following Figure 5 The FlexE encoding format shown in the figure obtains 8 FlexE client code block streams, each of which has a rate of 25G. The 64B / 66B transcoding adaptation circuit 1123 sends 8 FlexE client code block streams with a rate of 25G to the FlexE shim circuit 1122. Based on time slot mapping, the FlexE shim circuit 1122 converts 8 FlexE client code block streams with a rate of 25G into 1 FlexE code block stream with a rate of 200G. The system-side PCS circuit 1121 performs PCS layer processing on 1 FlexE code block stream with a rate of 200G and sends it to the system-side interface 111. Based on this, the interface chip 11 realizes mapping 8 Ethernet interfaces with a rate of 25G to 1 FlexE interface with a rate of 200G.

[0127] Example 3

[0128] Attached Fig. 9 1 is a schematic diagram of the architecture of another network device 1 provided in an embodiment of the present application. Fig. 9 The optical module 10 in the architecture shown is an 8×50G hash optical module. Fig. 9 The optical module 10 shown supports hashing the FlexE interface with a rate of 400G on the system side into eight Ethernet interfaces with a rate of 50G on the line side. The FlexE interface with a rate of 400G on the system side can be implemented using four serdes lanes with a transmission rate of 112G. Figure 3 The optical module 10 shown can convert four serdes lanes with a transmission rate of 112G on the system side into eight Ethernet channels with a rate of 50G on the line side.

[0129] The system side interface 111 of the optical module 10 is a FlexE interface with a transmission rate of 400G. The system side interface 111 is used to transmit a FlexE code block stream with a transmission rate of 400G between the optical module 10 and the MAC chip 21. The physical interface corresponding to the system side interface 111 can be a 4lane serdes interface. The line side interface 113 of the optical module 10 is an 8x50G Ethernet interface, and the line side interface 113 is used to transmit 8 Ethernet code block streams, and the transmission rate of each Ethernet code block stream is 50G. Fig. 9 The processing circuit 112 in the interface chip 11 in the optical module 10 converts the FlexE code block stream with a rate of 400G into 8 Ethernet code block streams based on time slot mapping, and the transmission rate of each Ethernet code block stream is 50G, thereby mapping one FlexE interface with a rate of 400G to 8 Ethernet interfaces with a rate of 50G.

[0130] Please refer to the attached Fig.10 , attached Fig.10 Yes Fig. 9 The structure diagram of the interface chip 11 in the optical module 10 is shown in the attached figure. Fig.10 As shown, in the process of PCB 20 sending a signal to the optical module 10, the system side interface 111 sends a FlexE code block stream with a rate of 400G to the FlexE shim circuit 1122. Based on time slot mapping, the FlexE code block stream with a rate of 400G is converted into 8 FlexE client code block streams, and the transmission rate of each FlexE client code block stream in the 8 FlexE client code block streams is 50G. Since the encoding format of the 64B / 66B code block in the Ethernet code block stream with a rate of 50G is the same as the FlexE encoding format, there is no need to deploy a 64B / 66B transcoding adapter module in the interface chip 11.

[0131] Example 4

[0132] Attached Fig.11 1 is a schematic diagram of the architecture of another network device 1 provided in an embodiment of the present application. Fig.11 The optical module 10 in the system architecture shown is a multi-rate hashing optical module. In Example 4, the optical module 10 utilizes the flexible and configurable characteristics of FlexE to enable the optical module to hash a FlexE interface into Ethernet interfaces with multiple transmission rates. Fig.11 In the embodiment, an optical module 10 hashes a FlexE interface with a rate of m times 100G into n1 Ethernet interfaces with a rate of 10G, n2 Ethernet interfaces with a rate of 25G, and n3 Ethernet interfaces with a rate of 25G as an example for explanation. In other embodiments, the optical module 10 hashes a FlexE interface into Ethernet interfaces with two rates or Ethernet interfaces with three or more rates.

[0133] For example, as attached Fig.11 As shown, the system side interface 111 in the optical module 10 is a FlexE interface with a transmission rate of m times 100G. The system side interface 111 is used to transmit the FlexE code block stream with a rate of m times 100G between the optical module 10 and the PCB 20. Fig.11 In the figure, m x 100G FlexE code block stream is used. m represents the ratio of the bandwidth occupied by the system side interface 111 to 100G, that is, how many times the 100G bandwidth is occupied by the system side interface 111. m is a positive integer. For example, the system side interface 111 is a FlexE interface with a rate of 100G, a FlexE interface with a rate of 200G, a FlexE interface with a rate of 400G, or a FlexE interface with a rate of 800G. Correspondingly, m is 1, 2, 4, or 8.

[0134] The line side interface 113 in the interface chip 11 includes (n1+n2+n3) Ethernet interfaces, each of the n1 Ethernet interfaces is used for transmitting a 10G Ethernet block stream. Each of the n2 Ethernet interfaces is used for transmitting a 25G Ethernet block stream. Each of the n3 Ethernet interfaces is used for transmitting a 50G Ethernet block stream.

[0135] n1 is the number of 10G FlexE subchannels, the number of 10G FlexE client code block flows, and the number of 10G Ethernet interfaces hashed by the optical module. n1 x 10G represents the total bandwidth occupied by 10G Ethernet code block flows. n1 is 0 or a positive integer.

[0136] n2 is the number of 25G FlexE subchannels, the number of 25G FlexE client code block flows, and the number of 25G Ethernet interfaces hashed by the optical module. n2 x 25G represents the total bandwidth occupied by 25G Ethernet code block flows. n2 is 0 or a positive integer.

[0137] n3 is the number of 50G FlexE subchannels, the number of 50G FlexE client code block flows, and the number of 50G Ethernet interfaces hashed by the optical module. n3 x 50G represents the total bandwidth occupied by 50G Ethernet code block flows. n3 is 0 or a positive integer.

[0138] The total bandwidth occupied by the line side interface 113 is less than the total bandwidth occupied by the system side interface 111. That is, n1x10G+n2x25G+n3x50G≤mx100G is satisfied. The sum of n1, n2 and n3 can be greater than m, that is, the number of line side channels is greater than the number of system side channels.

[0139] The following is attached Fig.11 The process of PCB 20 sending data to optical module 10 is illustrated by way of example. Fig.12 is a flow chart of a data transmission method provided by an embodiment of the present application, Fig.12 The method shown is applied to the Fig.11 In the optical module 10 shown, Fig.12 The method shown includes the following steps.

[0140] S510, the MAC chip 21 in the PCB 20 sends a FlexE code block stream with a rate of m times 100G to the system side interface 111 in the interface chip 11 through the FlexE channel.

[0141] S520 , the system-side interface 111 in the interface chip 11 receives a FlexE code block stream with a rate of m times 100G from the FlexE channel. The system-side interface 111 sends the m times 100G FlexE code block stream to the processing circuit 112 in the interface chip 11 .

[0142] S530, the processing circuit 112 converts the FlexE code block stream with a rate of m times 100G into n1 Ethernet code block streams with a rate of 10G, n2 Ethernet code block streams with a rate of 25G, and n3 Ethernet code block streams with a rate of 50G, thereby hashing the FlexE interface with a rate of m times 100G on the system side into n1 Ethernet interfaces with a rate of 10G, n2 Ethernet interfaces with a rate of 25G, and n3 Ethernet interfaces with a rate of 50G on the line side.

[0143] S540 , the processing circuit 112 sends the n1 Ethernet block stream with a rate of 10G, the n2 Ethernet block stream with a rate of 25G, and the n3 Ethernet block stream with a rate of 50G to the line side interface 113 in the interface chip 11 .

[0144] S550 , the line-side interface 113 sends the n1 Ethernet block stream with a rate of 10G, the n2 Ethernet block stream with a rate of 25G, and the n3 Ethernet block stream with a rate of 50G to the optical transmitter 121 .

[0145] S560, the optical transmitter 121 performs electrical-optical conversion on the n1 Ethernet block stream with a rate of 10G, the n2 Ethernet block stream with a rate of 25G, and the n3 Ethernet block stream with a rate of 50G, respectively, to obtain (n1+n2+n3) optical signals. The optical transmitter 121 sends the (n1+n2+n3) optical signals to the optical port connector 13.

[0146] In a possible implementation, S560 includes the following S5601 to S5603.

[0147] S5601, the 10G optical transmitter receives n1 Ethernet block streams with a rate of 10G, performs electrical-to-optical conversion on the n1 Ethernet block streams with a rate of 10G, and obtains n1 optical signals, each of which includes an Ethernet block stream with a rate of 10G. The 10G optical transmitter sends the n1 optical signals to the optical port connector 13.

[0148] S5602, the 25G optical transmitter is used to receive n2 Ethernet code block streams with a rate of 25G, perform electrical-to-optical conversion on the n2 Ethernet code block streams with a rate of 25G, and obtain n2 optical signals. Each of the n2 optical signals includes an Ethernet code block stream with a rate of 25G. The 25G optical transmitter sends the n2 optical signals to the optical port connector 13.

[0149] S5603, the 50G optical transmitter is used to receive n3 Ethernet code block streams with a rate of 50G, perform electrical-to-optical conversion on the n3 Ethernet code block streams with a rate of 50G, and obtain n3 optical signals. Each of the n3 optical signals includes an Ethernet code block stream with a rate of 50G. The 50G optical transmitter sends the n3 optical signals to the optical port connector 13.

[0150] S570, the optical port connector 13 receives the optical signal of the n1 path carrying the Ethernet block stream with a rate of 10G, the optical signal of the n2 path carrying the Ethernet block stream with a rate of 25G, and the optical signal of the n3 path carrying the Ethernet block stream with a rate of 50G. The optical port connector 13 sends the optical signal of the n1 path carrying the Ethernet block stream with a rate of 10G, the optical signal of the n2 path carrying the Ethernet block stream with a rate of 25G, and the optical signal of the n3 path carrying the Ethernet block stream with a rate of 50G to the optical fiber 40 through the optical interface 14.

[0151] Through the method provided in this embodiment, by utilizing the flexible and configurable characteristics of FlexE, one optical module can simultaneously hash interfaces of multiple rates.

[0152] The following is attached Fig.11 The process of the optical module 10 sending data to the PCB 20 is described by way of example. Fig.13 is a flow chart of a data transmission method provided by an embodiment of the present application, Fig.13 The method shown is applied to the Fig.11 In the optical module 10 shown, Fig.13 The method shown includes the following steps.

[0153] S610, the optical interface 14 of the optical port connector 13 receives the optical signal of the n1 path carrying the Ethernet block stream with a rate of 10G, the optical signal of the n2 path carrying the Ethernet block stream with a rate of 25G, and the optical signal of the n3 path carrying the Ethernet block stream with a rate of 50G. The optical port connector 13 sends the optical signal of the n1 path carrying the Ethernet block stream with a rate of 10G, the optical signal of the n2 path carrying the Ethernet block stream with a rate of 25G, and the optical signal of the n3 path carrying the Ethernet block stream with a rate of 50G to the optical receiver 122.

[0154] S620, the optical receiver 122 performs photoelectric conversion on the optical signal of the n1 path carrying the Ethernet code block stream with a rate of 10G, the optical signal of the n2 path carrying the Ethernet code block stream with a rate of 25G, and the optical signal of the n3 path carrying the Ethernet code block stream with a rate of 50G, to obtain (n1+n2+n3) electrical signals.

[0155] In a possible implementation, step S620 includes the following steps S6201 to S6203.

[0156] S6201, the 10G optical receiver receives n1 optical signals carrying an Ethernet code block stream with a rate of 10G, and the 10G optical receiver performs photoelectric conversion on the n1 optical signals to obtain n1 electrical signals, each of which includes an Ethernet code block stream with a rate of 10G. The 10G optical receiver sends the n1 electrical signals to the Ethernet interface with a rate of 10G in the line side interface 113 in the interface chip 11.

[0157] S6202, the 25G optical receiver receives n2 optical signals carrying an Ethernet code block stream with a rate of 25G, performs photoelectric conversion on the n2 optical signals, and obtains n2 electrical signals, each of the n2 electrical signals includes an Ethernet code block stream with a rate of 25G. The 25G optical receiver sends the n2 electrical signals to the Ethernet interface with a rate of 25G in the line side interface 113 in the interface chip 11.

[0158] S6203, the 50G optical receiver receives n3 optical signals carrying an Ethernet code block stream with a rate of 50G, performs photoelectric conversion on the n3 optical signals, and obtains n3 electrical signals, each of the n3 electrical signals includes an Ethernet code block stream with a rate of 50G. The 50G optical receiver sends the n3 electrical signals to the Ethernet interface with a rate of 50G in the line side interface 113 in the interface chip 11.

[0159] S630, the line side interface 113 sends the n1 Ethernet block stream with a rate of 10G, the n2 Ethernet block stream with a rate of 25G, and the n3 Ethernet block stream with a rate of 50G to the processing circuit 112 in the form of electrical signals.

[0160] S640, the processing circuit 112 converts the n1 Ethernet block stream with a rate of 10G, the n2 Ethernet block stream with a rate of 25G, and the n3 Ethernet block stream with a rate of 50G into a FlexE block stream with a rate of m times 100G, thereby converting the n1 Ethernet interface with a rate of 10G, the n2 Ethernet interface with a rate of 25G, and the n3 Ethernet interface with a rate of 50G on the line side into a FlexE interface with a rate of m times 100G on the system side.

[0161] S650 , the processing circuit 112 sends the FlexE code block stream with a rate of m times 100G to the system side interface 111 in the interface chip 11 .

[0162] S660, the system-side interface 111 sends a FlexE code block stream with a rate of m times 100G to the MAC chip 21 in the PCB 20 through the FlexE channel.

[0163] Please refer to the attached Fig.14 , attached Fig.14 Yes Fig.11 Schematic diagram of the structure of the interface chip 11 inside the optical module 10. The line-side PCS circuit 1124 in the interface chip 11 includes a line-side PCS circuit A, a line-side PCS circuit B, and a line-side PCS circuit C. The line-side PCS circuit A is used to perform PCS layer processing on the n1-channel Ethernet code block stream with a rate of 10G. The line-side PCS circuit B is used to perform PCS layer processing on the n2-channel Ethernet code block stream with a rate of 25G. The line-side PCS circuit C is used to perform PCS layer processing on the n3-channel Ethernet code block stream with a rate of 50G.

[0164] The 64B / 66B transcoding adaptation circuit 1123 includes a 64B / 66B transcoding adaptation circuit A and a 64B / 66B transcoding adaptation circuit B. The 64B / 66B transcoding adaptation circuit A corresponds to an Ethernet interface with a rate of 10G. The 64B / 66B transcoding adaptation circuit B corresponds to an Ethernet interface with a rate of 25G. Since the FlexE code blocks in the FlexE code block stream with a rate of 50G and the Ethernet code blocks in the Ethernet code block stream with a rate of 50G have the same encoding format, it is not necessary to deploy a 64B / 66B transcoding adaptation module for the FlexE code block stream with a rate of 50G.

[0165] The following is combined with Fig.14 The internal structure of the chip shown is similar to the Fig.12The step S530 of the method shown is further described. S530 may include the following S530a to S530c.

[0166] S530a, the FlexE shim circuit 1122 performs time slot mapping on the FlexE code block stream with a rate of m times 100G, and obtains the FlexE client code block stream with a rate of n1 at 10G, the FlexE client code block stream with a rate of n2 at 25G, and the FlexE client code block stream with a rate of n3 at 50G. The FlexE shim circuit 1122 sends the FlexE client code block stream with a rate of n1 at 10G to the 64B / 66B transcoding adaptation circuit A, sends the FlexE client code block stream with a rate of n2 at 25G to the 64B / 66B transcoding adaptation circuit B, and sends the FlexE client code block stream with a rate of n3 at 50G as an Ethernet code block stream to the line-side PCS circuit C.

[0167] S530b, the 64B / 66B transcoding adaptation circuit A changes the encoding format of each code block in each FlexE client code block stream with a rate of 10G in n1 FlexE client code block streams with a rate of 10G from the following: Figure 5 The FlexE encoding format shown is converted to the attached Figure 6 The Ethernet coding format shown in FIG. 1 is used to obtain an Ethernet code block stream with a rate of n1 at 10G. The 64B / 66B transcoding adaptation circuit A sends the Ethernet code block stream with a rate of n1 at 10G to the line-side PCS circuit A. The 64B / 66B transcoding adaptation circuit B obtains the coding format of each code block in each FlexE client code block stream with a rate of 25G in the n2 FlexE client code block streams with a rate of 25G from the following: Figure 5 The FlexE encoding format shown is converted to the attached Figure 6 The Ethernet encoding format shown in FIG. 1 obtains n2 Ethernet code block streams with a rate of 25G. The 64B / 66B transcoding adaptation circuit B sends the n2 Ethernet code block streams with a rate of 25G to the line-side PCS circuit B.

[0168] S530c, after the line-side PCS circuit A performs PCS layer processing on the n1-channel Ethernet block stream with a rate of 10G, it outputs the processed n1-channel Ethernet block stream with a rate of 10G to the line-side interface 113. After the line-side PCS circuit B performs PCS layer processing on the n2-channel Ethernet block stream with a rate of 25G, it outputs the processed n2-channel Ethernet block stream with a rate of 25G to the line-side interface 113.

[0169] The following is combined with Fig.14 The internal structure of the chip shown is similar to the Fig.13The step S640 of the method shown is further described. Step S640 may include the following S640a to S640c.

[0170] S640a, the line-side PCS circuit A receives the n1-channel Ethernet block stream with a rate of 10G from the line-side interface 113, performs PCS layer processing on the n1-channel Ethernet block stream with a rate of 10G, and outputs the processed n1-channel Ethernet block stream with a rate of 10G to the 64B / 66B transcoding adaptation circuit A. The line-side PCS circuit B receives the n2-channel Ethernet block stream with a rate of 25G from the line-side interface 113, performs PCS layer processing on the n2-channel Ethernet block stream with a rate of 25G, and outputs the processed n2-channel Ethernet block stream with a rate of 25G to the 64B / 66B transcoding adaptation circuit B. The line-side PCS circuit B receives the n3-channel Ethernet block stream with a rate of 50G from the line-side interface 113 , performs PCS layer processing on the n3-channel Ethernet block stream with a rate of 50G, and outputs the processed n3-channel Ethernet block stream with a rate of 50G to the FlexE shim circuit 1122 .

[0171] S640b, the 64B / 66B transcoding adaptation circuit A encodes each code block in each of the n1 Ethernet code block streams with a rate of 10G from the following: Figure 6 The Ethernet encoding format shown is converted to the attached Figure 5 The FlexE encoding format shown in the figure is used to obtain n1 FlexE code block streams with a rate of 10G. The 64B / 66B transcoding adaptation circuit A sends the n1 FlexE code block streams with a rate of 10G to the FlexE shim circuit 1122. The 64B / 66B transcoding adaptation circuit B obtains the encoding format of each code block in each of the n2 Ethernet code block streams with a rate of 25G from the following figure: Figure 6 The Ethernet encoding format shown is converted to the attached Figure 5 The FlexE encoding format shown in the figure obtains n2 FlexE code block streams with a rate of 25G. The 64B / 66B transcoding adaptation circuit B sends the n2 FlexE code block streams with a rate of 25G to the FlexE shim circuit 1122.

[0172] S640c, the FlexE shim circuit 1122 performs time slot mapping on the n1 FlexE client code block stream with a rate of 10G, the n2 FlexE client code block stream with a rate of 25G, and the n3 FlexE client code block stream with a rate of 50G to obtain a FlexE code block stream with a rate of m times 100G.

[0173] The method provided in this embodiment realizes one optical module hashing Ethernet interfaces of multiple rates. After the optical module is installed on a single board, the single board can send multiple Ethernet code block streams of different rates through one optical module, thereby meeting the demand for transmitting Ethernet code block streams of different rates. There is no need to deploy interface boards of corresponding rates for each transmission demand, thereby reducing the use of interface boards of different rates and saving costs.

[0174] The present application embodiment provides an optical module, which can be the attached optical module in Example 1. Figure 3 The 10ⅹ10G hashing optical module shown in the figure can also be the attached Figure 7 The 8×25G hashed optical module shown can also be the attached Fig. 9 The 8×50 scattered optical module shown can also be the attached Fig.11 The optical module includes a FlexE interface, a processing circuit, an optoelectronic conversion device, and multiple optical interfaces.

[0175] The FlexE interface is, for example, Figure 3 The system side interface 111 in the embodiment, the FlexE interface may be a 100G interface. The FlexE interface may be the 100G interface in the embodiment 2. Figure 7 The system side interface 111 in the embodiment, the FlexE interface may be a 200G interface. The FlexE interface may be the attached Fig. 9 The system side interface 111, the FlexE interface may be a 400G interface. The FlexE interface may be the 400G interface in Example 4. Fig.11 The system side interface 111, the FlexE interface may be an mx100G interface. The FlexE interface is used to receive a first FlexE code block stream from a network device through a FlexE channel, and the FlexE interface is communicatively connected with the network device through the FlexE channel.

[0176] In order to distinguish the Ethernet block stream transmitted from the network device to the optical module and the Ethernet block stream transmitted from the optical module to the network device, the Ethernet block stream transmitted from the network device to the optical module is referred to as the first Ethernet block stream, and the Ethernet block stream transmitted from the optical module to the network device is referred to as the first Ethernet block stream.

[0177] The processing circuit is, for example, the one in Example 1. Figure 3 The processing circuit 112 in Example 2 is also as shown in the attached Figure 7 The processing circuit 112 in Example 3 is also as shown in the attached Fig. 9 The processing circuit 112 in Example 4 is also provided. Fig.11The processing circuit 112 in. The processing circuit is used to obtain multiple first Ethernet code block streams based on the first FlexE code block stream; the optoelectronic conversion device is used to perform electrical-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; the multiple optical interfaces are used to send the multiple first optical signals to the optical fiber. The first Ethernet code block stream refers to the Ethernet code block stream transmitted from the network device to the optical module. In order to distinguish the FlexE client code block stream transmitted from the network device to the optical module and the FlexE client code block stream transmitted from the optical module to the network device, the FlexE client code block stream transmitted from the network device to the optical module is referred to as the first FlexE client code block stream, and the FlexE client code block stream transmitted from the optical module to the network device is referred to as the first FlexE client code block stream.

[0178] In a possible implementation, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the FlexE shim circuit is used to obtain multiple first FlexE client code block streams based on the first FlexE code block stream, and the multiple first FlexE client code block streams include code blocks with a FlexE coding format; the transcoding circuit is used to convert the coding format of the code blocks in the multiple first FlexE client code block streams from the FlexE coding format to the Ethernet coding format to obtain the multiple first Ethernet code block streams. The FlexE shim circuit can be the attached example 1. Figure 4 The FlexEshim circuit 1122 in Example 2 may also be Figure 8 The FlexE shim circuit 1122 in the embodiment may also be the attached Fig.10 The FlexE shim circuit 1122 in the embodiment may also be the attached Fig.14 The transcoding circuit may be the FlexE shim circuit 1122 in Example 1. Figure 4 The 64B / 66B transcoding adaptation circuit 1123 in Example 2 may also be the attached Figure 8 The 64B / 66B transcoding adaptation circuit 1123 in the embodiment 3 may also be the attached Fig.10 The 64B / 66B transcoding adaptation circuit 1123 in the embodiment 4 may also be the attached Fig.14 The 64B / 66B transcoding adaptation circuit 1123 in.

[0179] In one possible implementation, the FlexE shim circuit is used to perform time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain multiple first FlexE client code block streams, and the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

[0180] In one possible implementation, the multiple first FlexE client code block streams include a first FlexE client code block stream of a first transmission rate and a first FlexE client code block stream of a second transmission rate, the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client code block stream of the first transmission rate occupies a first number of time slots and the first FlexE client code block stream of the second transmission rate occupies a second number of time slots, and the second number is different from the first number.

[0181] In a possible implementation, a transmission rate of each first Ethernet code block stream in the multiple first Ethernet code block streams is lower than a transmission rate of the first FlexE code block stream.

[0182] In a possible implementation, the multiple optical interfaces are also used to receive multiple second optical signals from the optical fiber, and the multiple second optical signals include multiple second Ethernet code block streams; the optoelectronic conversion device is also used to perform optoelectronic conversion on the multiple second optical signals to obtain multiple electrical signals, and the multiple electrical signals include multiple second Ethernet code block streams; the processing circuit is also used to obtain a second FlexE code block stream based on the multiple second Ethernet code block streams; the FlexE interface is also used to send the second FlexE code block stream to the network device through the FlexE channel.

[0183] In one possible implementation, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the transcoding circuit is used to convert the encoding format of the code blocks in the multiple second Ethernet code block streams from the Ethernet encoding format to the FlexE encoding format to obtain multiple second FlexE client code block streams; the FlexE shim circuit is used to obtain the second FlexE code block stream based on the multiple second FlexE client code block streams.

[0184] In a possible implementation, the optical module includes an interface chip, and the FlexE interface and the processing circuit are both provided on the interface chip.

[0185] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0186] A refers to B, which means that A is the same as B or A is a simple variant of B.

[0187] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe the specific order of the objects, and cannot be understood as indicating or implying relative importance. For example, the first FlexE code block stream and the second FlexE code block stream are used to distinguish different FlexE code block streams, rather than to describe the specific order of the FlexE code block streams, and cannot be understood as the first FlexE code block stream being more important than the second FlexE code block stream.

[0188] In the embodiments of the present application, unless otherwise specified, "at least one" means one or more, and "multiple" means two or more. For example, multiple first Ethernet block streams means two or more first Ethernet block streams.

[0189] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in accordance with the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk SolidState Disk (SSD)), etc.

[0190] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An optical module, characterized in that: Includes Flexible Ethernet FlexE interface, processing circuit, optoelectronic conversion device and multiple optical interfaces; The FlexE interface is used to receive a first FlexE code block stream from a network device through a FlexE channel, and the FlexE interface is communicatively connected with the network device through the FlexE channel; The processing circuit is used to obtain multiple first Ethernet code block streams based on the first FlexE code block stream; The photoelectric conversion device is used to perform electrical-to-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; The multiple optical interfaces are used to send the multiple first optical signals to the optical fiber.

2. The optical module according to claim 1, characterized in that: The processing circuit includes a FlexE shim circuit and a transcoding circuit; The FlexE shim circuit is used to obtain a plurality of first FlexE client code block streams based on the first FlexE code block stream, wherein the plurality of first FlexE client code block streams include code blocks having a FlexE coding format; The transcoding circuit is used for converting the coding format of the code blocks in the multiple first FlexE client code block streams from the FlexE coding format to the Ethernet coding format to obtain the multiple first Ethernet code block streams.

3. The optical module according to claim 2, characterized in that: The FlexE shim circuit is used to perform time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain multiple first FlexE client code block streams, wherein the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

4. The optical module according to claim 3, characterized in that: The multiple first Ethernet block streams include a first Ethernet block stream at a first transmission rate and a first Ethernet block stream at a second transmission rate, the multiple first FlexE client block streams include a first FlexE client block stream at a first transmission rate and a first FlexEclient block stream at a second transmission rate, the second transmission rate is different from the first transmission rate, the time slot configuration information indicates that the first FlexE client block stream at the first transmission rate occupies a first number of time slots and the first FlexE client block stream at the second transmission rate occupies a second number of time slots, and the second number is different from the first number.

5. The optical module according to any one of claims 1 to 4, characterized in that: The transmission rate of each first Ethernet code block stream in the multiple first Ethernet code block streams is lower than the transmission rate of the first FlexE code block stream.

6. The optical module according to any one of claims 1 to 5, characterized in that: The plurality of optical interfaces are further used to receive multiple second optical signals from the optical fiber, wherein the multiple second optical signals include multiple second Ethernet code block streams; The photoelectric conversion device is further used to perform photoelectric conversion on the multiple second optical signals to obtain multiple electrical signals, wherein the multiple electrical signals include multiple second Ethernet code block streams; The processing circuit is further configured to obtain a second FlexE code block stream based on the multiple second Ethernet code block streams; The FlexE interface is further used to send the second FlexE code block stream to the network device through the FlexE channel.

7. The optical module according to claim 6, characterized in that: The processing circuit includes a FlexE shim circuit and a transcoding circuit; The transcoding circuit is used to convert the coding format of the code blocks in the multiple second Ethernet code block streams from the Ethernet coding format to the FlexE coding format to obtain multiple second FlexE client code block streams; The FlexE shim circuit is used to obtain the second FlexE code block stream based on multiple second FlexE client code block streams.

8. The optical module according to claim 1, characterized in that: The optical module includes an interface chip, and the FlexE interface and the processing circuit are both arranged on the interface chip.

9. An optical module, characterized in that: include: A housing, provided with an electrical interface and a plurality of optical interfaces, wherein the electrical interface is used to connect to a network device outside the optical module, and the plurality of optical interfaces are used to connect to optical fibers outside the optical module; an interface chip, disposed in the housing, the interface chip comprising a flexible Ethernet FlexE interface, a processing circuit and a plurality of Ethernet interfaces, the FlexE interface being opposite to the electrical interface, the processing circuit being disposed between the FlexE interface and the plurality of Ethernet interfaces, the processing circuit being used for converting a FlexE code block stream received by the FlexE interface into a multi-channel Ethernet code block stream and outputting the multi-channel Ethernet code block stream to the plurality of Ethernet interfaces, the plurality of Ethernet interfaces corresponding one to one with the plurality of optical interfaces; The photoelectric conversion device is arranged in the housing, one end of the photoelectric conversion device is electrically connected to the multiple Ethernet interfaces of the interface chip, and the other end of the photoelectric conversion device is opposite to the multiple optical interfaces.

10. A network device, characterized in that: It includes a processor, a first flexible Ethernet FlexE interface and an optical module, wherein the optical module includes a second FlexE interface, a processing circuit, an optoelectronic conversion device and a plurality of optical interfaces, and the first FlexE interface is communicatively connected with the second FlexE interface through a FlexE channel; The processor is configured to generate a first FlexE code block stream; The first FlexE interface is used to send the first FlexE code block stream to the second FlexE interface through the FlexE channel; The processing circuit is used to obtain multiple first Ethernet code block streams based on the first FlexE code block stream; The photoelectric conversion device is used to perform electrical-to-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; The multiple optical interfaces are used to send the multiple first optical signals to the optical fiber.

11. A data transmission method, characterized in that: Applied to optical modules, including: Receiving a first FlexE code block stream from a first network device through a flexible Ethernet FlexE channel, wherein the optical module is communicatively connected with the first network device through the FlexE channel; Obtaining multiple first Ethernet block streams based on the first FlexE block stream; Performing electrical-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; The multiple paths of first optical signals are sent to the second network device through optical fibers.

12. The method according to claim 11, characterized in that The obtaining multiple first Ethernet code block streams based on the first FlexE code block stream includes: Obtaining a plurality of first FlexE client code block streams based on the first FlexE code block stream, wherein the plurality of first FlexE client code block streams include code blocks in a FlexE coding format; The coding format of the code blocks in the multiple first FlexE client code block streams is converted from the FlexE coding format to the Ethernet coding format to obtain the multiple first Ethernet code block streams.

13. The method according to claim 12, characterized in that The obtaining a plurality of first FlexE client code block streams based on the first FlexE code block stream includes: Based on the time slot configuration information, the first FlexE code block stream is time slot mapped to obtain multiple first FlexE client code block streams, and the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

14. The method according to claim 13, characterized in that The multiple first FlexE client code block streams include a first FlexE client code block stream at a first transmission rate and a first FlexE client code block stream at a second transmission rate, wherein the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client code block stream at the first transmission rate occupies a first number of time slots and the first FlexE client code block stream at the second transmission rate occupies a second number of time slots, and the second number is different from the first number.

15. The method according to any one of claims 11 to 14, characterized in that The transmission rate of each first Ethernet code block stream in the multiple first Ethernet code block streams is lower than the transmission rate of the first FlexE code block stream.

16. The method according to any one of claims 11 to 15, characterized in that The method further comprises: receiving a plurality of second optical signals from the second network device, wherein the plurality of second optical signals include a plurality of second Ethernet code block streams; Performing photoelectric conversion on the multiple second optical signals to obtain multiple electrical signals, wherein the multiple electrical signals include multiple second Ethernet code block streams; Obtaining a second FlexE code block stream based on the multiple second Ethernet code block streams; The second FlexE code block stream is sent to the first network device through the FlexE channel.

17. The method according to claim 16, characterized in that The obtaining a second FlexE code block stream based on the multiple second Ethernet code block streams includes: Converting the encoding format of the code blocks in the multiple second Ethernet code block streams from the Ethernet encoding format to the FlexE encoding format to obtain multiple second FlexE client code block streams; The second FlexE code block stream is obtained based on multiple second FlexE client code block streams.

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