Data Eye Width Extended Decision Feedback Equalizer and Data Eye Width Extension Method

Abstract

The present invention discloses a data eye width extended decision feedback equalizer and a data eye width extension method, which relate to the technical field of digital signal processing. The decision feedback equalizer includes: a first numerically controlled delay unit, a second numerically controlled delay unit, an OR gate logic circuit, a NOR gate logic circuit, a data sampler, and a decision feedback circuit; the first numerically controlled delay unit is used for delaying the positive-phase signal and outputting and sending it to the OR gate logic circuit; the second numerically controlled delay unit is used for delaying the negative-phase signal and outputting and sending it to the NOR gate logic circuit; the data sampler is used for outputting 4 sampled data; the decision feedback circuit is used for taking the odd-bit signal as the first output signal and taking the even-bit signal as the second output signal. The present invention realizes the extension of the data eye width, thereby effectively improving the jitter tolerance of the deserializer and reducing the bit error rate of the deserializer.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and particularly relates to a data eye width extension decision feedback equalizer and a data eye width extension method. Background Art

[0002] With the increasing size of in-vehicle video data and the continuous improvement of the serial-deserializer (SerDes) interface rate, more solutions are needed to improve the signal quality of high-speed interfaces. The decision feedback equalizer (DFE) is one of the widely used and effective solutions to improve the received signal quality. It can effectively improve the receiving performance of the RX, especially in high-speed data transmission systems. However, when the data rate of the serdes (deserializer) interface continues to increase, the channel insertion loss and return loss become more and more serious, resulting in an increase in the signal data clock jitter at the receiving end and a decrease in the data eye diagram width. Existing traditional DFE mainly solves the adjacent data amplitude distortion caused by inter-symbol interference, that is, equivalently improves the data eye height. However, when the data eye width becomes narrow due to factors such as noise introduced by the signal channel, radiation interference to the system, and large power supply fluctuations in the receiver system, the traditional DFE cannot solve such problems. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, the present invention provides a data eye width extension decision feedback equalizer and a data eye width extension method. By extending the data width and combining the decision feedback circuit structure, the data eye width is extended, thereby effectively improving the jitter tolerance of the deserializer and reducing the bit error rate of the deserializer.

[0004] In one aspect of the present invention, a data eye width extension decision feedback equalizer is provided, including:

[0005] A first numerically controlled delay unit, a second numerically controlled delay unit, an OR gate logic circuit, a NOR gate logic circuit, a data sampler, and a decision feedback circuit;

[0006] The first numerically controlled delay unit is used to delay the positive-phase signal of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before delay into the OR gate logic circuit together. The OR gate logic circuit outputs a first data signal, and the first data signal is a logic 1 width extension signal;

[0007] The second numerically controlled delay unit is used to delay the negative-phase signal of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before delay into the NOR gate logic circuit together. The NOR gate logic circuit outputs a second data signal, and the second data signal is a logic 0 width extension signal;

[0008] A data sampler, configured to sample the odd bits of the first data signal and the second data signal according to a first clock signal to obtain the odd-bit signal of the first data signal and the odd-bit signal of the second data signal; sample the even bits of the first data signal and the second data signal according to a second clock signal to obtain the even-bit signal of the first data signal and the even-bit signal of the second data signal, wherein the phase difference between the first clock signal and the second clock signal is 180 degrees;

[0009] A decision feedback circuit, configured to use the odd-bit signal in the first data signal or the second data signal as a first output signal, and use the even-bit signal in the first data signal or the second data signal as a second output signal; wherein, the first output signal decides to select and output a logic 0 width extension signal or a logic 1 width extension signal according to the situation of the second output signal; the second output signal decides to select and output a logic 0 width extension signal or a logic 1 width extension signal according to the situation of the first output signal.

[0010] Further, the decision feedback circuit includes a first selector, a first D flip-flop, a second selector, and a second D flip-flop. Among them, two input terminals of the first selector are connected to the odd-bit signal of the first data signal and the odd-bit signal of the second data signal, and the enable control terminal of the first selector is connected to the output terminal of the second D flip-flop; two input terminals of the second selector are connected to the even-bit signal of the first data signal and the even-bit signal of the second data signal, and the enable control terminal of the second selector is connected to the output terminal of the first D flip-flop; the data input terminal of the first D flip-flop is connected to the output terminal of the first selector, the clock input terminal of the first D flip-flop is connected to the first clock signal, and the output terminal of the first D flip-flop outputs the first output signal; the data input terminal of the second D flip-flop is connected to the output terminal of the second selector, the clock input terminal of the second D flip-flop is connected to the second clock signal, and the output terminal of the second D flip-flop outputs the second output signal.

[0011] Further, the first numerically controlled delay unit includes a first inverter, a second inverter, and a first delay capacitor; the input end of the first inverter receives the positive-phase signal of the input high-speed serial data differential signal, the output end of the first inverter is connected to the input end of the second inverter and the first end of the first delay capacitor, the second end of the first delay capacitor is grounded through a first switch, and the output end of the second inverter outputs the delayed positive-phase signal; the second numerically controlled delay unit includes a third inverter, a fourth inverter, and a second delay capacitor; the input end of the third inverter receives the negative-phase signal of the input high-speed serial data differential signal, the output end of the third inverter is connected to the input end of the fourth inverter and the first end of the second delay capacitor, the second end of the second delay capacitor is grounded through a second switch, and the output end of the fourth inverter outputs the delayed negative-phase signal.

[0012] Further, both the first delay capacitor and the second delay capacitor are 8-bit capacitor arrays, both the first switch and the second switch are 8-bit switches, and the 8-bit capacitor array and the 8-bit switch control the delay between the input and the output by controlling the size of the first delay capacitor or the second delay capacitor.

[0013] Further, the size of the first delay capacitor or the second delay capacitor is controlled by an 8-bit digital control word.

[0014] Further, the data sampler includes a sense amplifier and a set-reset latch; the sense amplifier is used to amplify the input first data signal and the second data signal, and sample and hold the amplified first data signal and second data signal through the first clock signal and the second clock signal to output a set signal and a reset signal to the set-reset latch; the set-reset latch is used to receive the set signal and the reset signal output by the sense amplifier, and output logic 1 or logic 0 according to the states of the set signal and the reset signal.

[0015] Further, the sense amplifier is an 8-channel sense amplifier, and the set-reset latch is an 8-channel set-reset latch.

[0016] On the other hand, the present invention also provides a data eye width expansion method based on the above data eye width expansion decision feedback equalizer, including:

[0017] The positive-phase signal of the input high-speed serial data differential signal is delayed by the first numerically controlled delay unit, and the delayed output signal and the input signal before delay are input into an OR gate logic circuit together, and the OR gate logic circuit outputs a first data signal, and the first data signal is a logic 1 width expansion signal;

[0018] The negative-phase signal of the input high-speed serial data differential signal is delayed by a second numerically controlled delay unit, and the delayed output signal and the input signal before delay are input into a NOR logic circuit together. The NOR logic circuit outputs a second data signal, and the second data signal is a logic 0 width extension signal;

[0019] Based on the first clock signal, the odd bits of the first data signal and the second data signal are sampled by a data sampler to obtain the odd-bit signals of the first data signal and the second data signal; based on the second clock signal, the even bits of the first data signal and the second data signal are sampled by a data sampler to obtain the even-bit signals of the first data signal and the second data signal; the phase difference between the first clock signal and the second clock signal is 180 degrees;

[0020] The odd-bit signal in the first data signal or the second data signal is used as the first output signal through a decision feedback circuit, and the even-bit signal in the first data signal or the second data signal is used as the second output signal; the first output signal decides to select and output a logic 0 width extension signal or a logic 1 width extension signal according to the situation of the second output signal; the second output signal decides to select and output a logic 0 width extension signal or a logic 1 width extension signal according to the situation of the first output signal.

[0021] Further, the step of using the odd-bit signal in the first data signal or the second data signal as the first output signal and the even-bit signal in the first data signal or the second data signal as the second output signal through the decision feedback circuit includes: inputting the odd-bit signal of the first data signal and the odd-bit signal of the second data signal into a first selector, inputting the output signal of the first selector into the data input terminal of a first D flip-flop, inputting the first clock signal into the clock input terminal of the first D flip-flop, inputting the output signal of the second D flip-flop into the enable control terminal of the first selector, and using the output signal of the first D flip-flop as the first output signal; inputting the even-bit signal of the first data signal and the even-bit signal of the second data signal into a second selector, inputting the output signal of the second selector into the data input terminal of a second D flip-flop, inputting the second clock signal into the clock input terminal of the second D flip-flop, inputting the output signal of the first D flip-flop into the enable control terminal of the second selector, and using the output signal of the second D flip-flop as the second output signal.

[0022] Further, the step of delaying the positive-phase signal of the input high-speed serial data differential signal by the first numerically controlled delay unit includes: inputting the positive-phase signal of the high-speed serial data differential signal to the input terminal of the first inverter, inputting the output signal of the first inverter to the input terminal of the second inverter and the first end of the first delay capacitor, grounding the second end of the first delay capacitor through a switch, and using the output signal of the second inverter as the delayed positive-phase signal; the step of delaying the negative-phase signal of the input high-speed serial data differential signal by the second numerically controlled delay unit includes: inputting the negative-phase signal of the high-speed serial data differential signal to the input terminal of the third inverter, inputting the output signal of the third inverter to the input terminal of the fourth inverter and the first end of the second delay capacitor, grounding the second end of the delay capacitor through a switch, and using the output signal of the fourth inverter as the delayed negative-phase signal.

[0023] The data eye width extension decision feedback equalizer and the data eye width extension method provided by the present invention realize the equivalent extension of the data eye width by expanding the data width and combining the decision feedback circuit structure, thereby effectively improving the jitter tolerance of the deserialization device and reducing the bit error rate of the deserialization device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects, and advantages of the present application will become more apparent:

[0025] Figure 1 is a timing diagram of data eye width extension provided by an embodiment of the present application;

[0026] Figure 2 is a schematic circuit diagram of a data eye width extension decision feedback equalizer provided by an embodiment of the present application;

[0027] Figure 3 is a circuit structure diagram of a numerically controlled delay unit provided by an embodiment of the present application;

[0028] Figure 4 is a circuit structure diagram of a data sampler provided by an embodiment of the present application;

[0029] Figure 5 is a schematic flow diagram of a data eye width extension method provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] The terms used in the embodiments of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The singular forms "a", "the", and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise.

[0032] It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present invention to describe the acquisition modules, these acquisition modules should not be limited to these terms. These terms are only used to distinguish the acquisition modules from each other.

[0033] Depending on the context, the word "if" as used herein can be interpreted as "when" or "while" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detected (stated condition or event)" can be interpreted as "when determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)".

[0034] It should be noted that the orientation terms such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described from the angles shown in the drawings and should not be construed as limiting the embodiments of the present invention. In addition, in the context, it should also be understood that when it is mentioned that one element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also be indirectly formed "on" or "under" another element through an intermediate element.

[0035] The differential signal in the prior art is also called a differential-mode signal. When using differential signal transmission, 2 signal lines are required. The amplitudes of these 2 signal lines are equal and the phases are opposite. The voltage difference between the 2 signal lines is used to represent logic 0 and logic 1. See Figure 1, the logic 0 and logic 1 of the normally input differential signal (hereinafter referred to as data 0 and data 1) have the same width. In order to expand the data width, the present invention processes data 1 and data 0 separately to form two output channels. Channel 1 expands the width of data 1 and compresses the width of data 0, and channel 2 expands the width of data 0 and compresses the width of data 1. By means of a decision feedback structure, the data with the expanded width is alternately selected, thereby equivalently expanding the eye width of the input signal.

[0036] See Figure 2 , an embodiment of the present invention discloses a data eye width expansion decision feedback equalizer 100, including:

[0037] A first numerically controlled delay unit 101, a second numerically controlled delay unit 102, an OR gate logic circuit 103, a NOR gate logic circuit 104, a data sampler 105, and a decision feedback circuit 106.

[0038] Specifically, the first numerically controlled delay unit 101 is used to delay the positive phase signal (the signal input at the INP terminal) of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before delay into the OR gate logic circuit 103 together. Since the output of the OR gate logic circuit 103 is also logic 1 when any of its inputs is logic 1, the OR gate logic circuit 103 will perform output gating on the logic 1 signal in the input delayed signal, thus forming a path for expanding the width of logic 1 (i.e., data 1). Similarly, the execution logic of the NOR gate logic circuit is opposite to that of the OR gate logic circuit, and it will perform output gating on the logic 0 signal in the input delayed signal, thus forming a path for expanding the width of logic 0 (i.e., data 0).

[0039] Specifically, the second numerically controlled delay unit 102 is used to delay the negative phase signal (the signal input at the INN terminal) of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before delay into the OR gate logic circuit 103 together. Since the output of the OR gate logic circuit 103 is also logic 1 when any of its inputs is logic 1, the OR gate logic circuit 103 will perform output gating on the logic 1 signal in the input delayed signal, thus forming a path for expanding the width of logic 1 (i.e., data 1). Similarly, the execution logic of the NOR gate logic circuit is opposite to that of the OR gate logic circuit, and it will perform output gating on the logic 0 signal in the input delayed signal, thus forming a path for expanding the width of logic 0 (i.e., data 0).

[0040] See Figure 3, preferably, the first numerically controlled delay unit 101 includes a first inverter 1011, a second inverter 1012, and a first delay capacitor 1013; the input terminal of the first inverter 1011 receives the positive-phase signal INP of the input high-speed serial data differential signal, the output terminal of the first inverter 1011 is connected to the input terminal of the second inverter 1012 and the first end of the first delay capacitor 1012, the second end of the first delay capacitor 1013 is grounded through a first switch 1014, and the output terminal of the second inverter 1012 outputs the delayed positive-phase signal. See Figure 3 , the second numerically controlled delay unit 102 includes a third inverter 1021, a fourth inverter 1022, and a second delay capacitor 1023; the input terminal of the third inverter 1021 receives the negative-phase signal INN of the input high-speed serial data differential signal, the output terminal of the third inverter 1021 is connected to the input terminal of the fourth inverter 1022 and the first end of the second delay capacitor 1023, the second end of the second delay capacitor 1023 is grounded through a second switch 1024, and the output terminal of the fourth inverter 1022 outputs the delayed negative-phase signal.

[0041] More preferably, both the first delay capacitor 1013 and the second delay capacitor 1023 are 8-bit capacitor arrays, and both the first switch 1014 and the second switch 1024 are 8-bit switches. The 8-bit capacitor array and the 8-bit switch control the delay between the input and the output by controlling the size of the first delay capacitor 1013 or the second delay capacitor 1023. Further, the size of the first delay capacitor 1013 or the second delay capacitor 1023 can be controlled by an 8-bit digital control word.

[0042] Further, the data 1 width expansion channel and the data 0 width expansion channel simultaneously transmit data to the data sampler 105. The data sampler 105 samples the data of the two channels using ck0 and ck2 with a 180° phase interval. The sampling clock ck0 samples the data at the odd positions of the two input data paths, and the sampling clock ck2 samples the data at the even positions of the two input data paths, thereby generating four data channels: the odd-position data 1 expansion path inp1_ck0, the odd-position data 0 expansion path inn1_ck0, the even-position data 1 expansion path inp1_ck2, and the even-position data 0 expansion path inn1_ck2. More preferably, the data sampler 105 samples the two input signals using four orthogonal signals ck0, ck1, ck2, and ck3 with a 90° interval, and uses the clock signal ck0 to sample the data of the data 1 expansion path and the data 0 expansion path respectively to generate the output signals inp1_ck0 and inn1_ck0. Among them, inp1_ck0 is the data sampling output of ck0 for the data 1 expansion path, and inn1_ck0 is the data sampling output of ck0 for the data 0 expansion path. The clock signal ck2 is also used to sample the data of the data 1 expansion path and the data 0 expansion path respectively to generate the output signals inp1_ck2 and inn1_ck2. Among them, inp1_ck2 is the data sampling output of ck2 for the data 1 expansion, and inn1_ck2 is the data sampling output of ck2 for the data 0 expansion path. Ck0 and ck2 are clock signals with a 180° phase difference. Ck1 and Ck3 also sample the data of the input data 1 expansion path and the data 0 expansion path respectively to generate the serial data transition band data edge_data, and combine the output data odd and data even to provide phase lead and lag information to the phase detector in the CDR loop.

[0043] See Figure 4 , the data sampler 105 includes a sense amplifier 1051 and a set-reset latch 1052. The sense amplifier 1051 amplifies the input inp1 and inn1, and samples and holds the amplified inp1 and inn1 through ck0 and ck2 to output a set signal S and a reset signal R to the set-reset latch 1052. The set-reset latch 1052 is used to receive the set signal S and the reset signal R output by the sense amplifier 1051, and outputs a logic 1 or a logic 0 according to the states of the set signal S and the reset signal R. More preferably, the sense amplifier 1051 is an 8-channel sense amplifier, and the set-reset latch 1052 is an 8-channel set-reset latch.

[0044] Further, the decision feedback circuit 106 is configured to use the odd-bit signals in the above inp1_ck0 and inn1_ck0 as the first output signal, and use the even-bit signals in inp1_ck2 and inn1_ck2 as the second output signal. Refer to Figure 2 , the four output data inp1_ck0, inn1_ck0, inp1_ck2, and inn1_ck2 of the data sampler 105 are sent to the decision feedback circuit 106 composed of the first selector 1061, the first D flip-flop 1062, the second selector 1063, and the second D flip-flop 1064. The decision feedback circuit 106 controls the first selector 1061 and the second selector 1063 to select data with a width extension of data 1 or 0 according to the current data situation, so as to achieve the effect of eye width extension of the input high-speed serial signal. More specifically, the two input terminals of the first selector 1061 are connected to the inp1_ck0 and inn1_ck0, and the enable control terminal of the first selector 1061 is connected to the output terminal of the second D flip-flop 1064; the two input terminals of the second selector 1063 are connected to the inp1_ck2 and inp1_ck2, and the enable control terminal of the second selector 1063 is connected to the output terminal of the first D flip-flop 1062; the data input terminal of the first D flip-flop 1062 is connected to the output terminal of the first selector 1061, the clock input terminal of the first D flip-flop 1062 is connected to the first clock signal ck0, and the output terminal of the first D flip-flop 1062 outputs the first output signal. The data input terminal of the second D flip-flop 1064 is connected to the output terminal of the second selector 1063, the clock input terminal of the second D flip-flop 1064 is connected to the second clock signal ck2, and the output terminal of the second D flip-flop 1064 outputs the second output signal. Among them, the first output signal and the second output signal are the signals after the equivalent extension of the data eye width.

[0045] The data eye width extension decision feedback equalizer 100 provided by the present invention realizes the equivalent extension of the data eye width by extending the data width and combining the decision feedback circuit structure, thereby effectively improving the jitter tolerance of the deserialization device and reducing the bit error rate of the deserialization device.

[0046] Refer to Figure 5 , another embodiment of the present invention further provides a data eye width extension method, which is implemented based on the above data eye width extension decision feedback equalizer 100, and specifically includes:

[0047] Step S101, delay the positive phase signal of the input high-speed serial data differential signal through the first numerically controlled delay unit, and input the delayed output signal and the input signal before delay into the OR logic circuit together, and the OR logic circuit outputs the first data signal, and the first data signal is a logic 1 width extension signal;

[0048] In step S102, the negative-phase signal of the input high-speed serial data differential signal is delayed by a second digital control delay unit, and the delayed output signal and the input signal before delay are input into a NOR logic circuit together. The NOR logic circuit outputs a second data signal, and the second data signal is a logic 0 width extended signal;

[0049] In step S103, based on the first clock signal, the odd bits of the first data signal and the second data signal are sampled by a data sampler to obtain the odd-bit signals of the first data signal and the second data signal; based on the second clock signal, the even bits of the first data signal and the second data signal are sampled by a data sampler to obtain the even-bit signals of the first data signal and the second data signal; the phase difference between the first clock signal and the second clock signal is 180 degrees;

[0050] In step S104, the odd-bit signals in the first data signal or the second data signal are used as the first output signal through a decision feedback circuit, and the even-bit signals in the first data signal or the second data signal are used as the second output signal; the first output signal decides to select and output a logic 0 width extended signal or a logic 1 width extended signal according to the situation of the second output signal; the second output signal decides to select and output a logic 0 width extended signal or a logic 1 width extended signal according to the situation of the first output signal.

[0051] Further, step S104 further includes:

[0052] In step S1041, the odd-bit signals of the first data signal and the odd-bit signals of the second data signal are input into a first selector, the output signal of the first selector is input into the data input terminal of a first D flip-flop, the first clock signal is input into the clock input terminal of the first D flip-flop, the output signal of the second D flip-flop is input into the enable control terminal of the first selector, and the output signal of the first D flip-flop is used as the first output signal;

[0053] In step S1042, the even-bit signals of the first data signal and the even-bit signals of the second data signal are input into a second selector, the output signal of the second selector is input into the data input terminal of a second D flip-flop, the second clock signal is input into the clock input terminal of the second D flip-flop, the output signal of the first D flip-flop is input into the enable control terminal of the second selector, and the output signal of the second D flip-flop is used as the second output signal.

[0054] Further, step S101 further includes: inputting the positive-phase signal of the high-speed serial data differential signal to the input terminal of the first inverter, inputting the output signal of the first inverter to the input terminal of the second inverter and the first end of the first delay capacitor, grounding the second end of the first delay capacitor through a switch, and using the output signal of the second inverter as the delayed positive-phase signal;

[0055] Further, step S102 further includes: inputting the negative-phase signal of the high-speed serial data differential signal to the input terminal of the third inverter, inputting the output signal of the third inverter to the input terminal of the fourth inverter and the first end of the second delay capacitor, grounding the second end of the delay capacitor through a switch, and using the output signal of the fourth inverter as the delayed negative-phase signal.

[0056] The above description is only the preferred embodiment of the present invention. Those skilled in the art should understand that the disclosed scope of the present invention is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present invention.

Claims

1. A data eye width extended decision feedback equalizer, characterized in that, Comprising: A first numerically controlled delay unit, a second numerically controlled delay unit, an OR gate logic circuit, a NOR gate logic circuit, a data sampler, and a decision feedback circuit; The first numerically controlled delay unit is used to delay the positive-phase signal of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before delay into the OR gate logic circuit together. The OR gate logic circuit outputs a first data signal, and the first data signal is a logic 1 width extended signal; The second numerically controlled delay unit is used to delay the negative-phase signal of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before delay into the NOR gate logic circuit together. The NOR gate logic circuit outputs a second data signal, and the second data signal is a logic 0 width extended signal; A data sampler, which is used to sample the odd bits of the first data signal and the second data signal according to a first clock signal to obtain the odd-bit signal of the first data signal and the odd-bit signal of the second data signal; sample the even bits of the first data signal and the second data signal according to a second clock signal to obtain the even-bit signal of the first data signal and the even-bit signal of the second data signal. The phase difference between the first clock signal and the second clock signal is 180 degrees; A decision feedback circuit, which is used to use the odd-bit signal in the first data signal or the second data signal as the first output signal, and use the even-bit signal in the first data signal or the second data signal as the second output signal; wherein, the first output signal decides to select and output a logic 0 width extended signal or a logic 1 width extended signal according to the situation of the second output signal; the second output signal decides to select and output a logic 0 width extended signal or a logic 1 width extended signal according to the situation of the first output signal.

2. The data eye width extended decision feedback equalizer according to claim 1, wherein The decision feedback circuit includes a first selector, a first D flip-flop, a second selector, and a second D flip-flop, wherein, Two input ends of the first selector are connected to the odd-bit signal of the first data signal and the odd-bit signal of the second data signal, and the enable control end of the first selector is connected to the output end of the second D flip-flop; Two input ends of the second selector are connected to the even-bit signal of the first data signal and the even-bit signal of the second data signal, and the enable control end of the second selector is connected to the output end of the first D flip-flop; The data input end of the first D flip-flop is connected to the output end of the first selector, the clock input end of the first D flip-flop is connected to the first clock signal, and the output end of the first D flip-flop outputs the first output signal; The data input end of the second D flip-flop is connected to the output end of the second selector, the clock input end of the second D flip-flop is connected to the second clock signal, and the output end of the second D flip-flop outputs the second output signal.

3. The data eye width extended decision feedback equalizer according to claim 1, wherein: The first numerically controlled delay unit includes a first inverter, a second inverter, and a first delay capacitor; the input terminal of the first inverter receives the positive-phase signal of the input high-speed serial data differential signal, the output terminal of the first inverter is connected to the input terminal of the second inverter and the first end of the first delay capacitor, the second end of the first delay capacitor is grounded through a first switch, and the output terminal of the second inverter outputs the delayed positive-phase signal; The second numerically controlled delay unit includes a third inverter, a fourth inverter, and a second delay capacitor; the input terminal of the third inverter receives the negative-phase signal of the input high-speed serial data differential signal, the output terminal of the third inverter is connected to the input terminal of the fourth inverter and the first end of the second delay capacitor, the second end of the second delay capacitor is grounded through a second switch, and the output terminal of the fourth inverter outputs the delayed negative-phase signal.

4. The data eye width extended decision feedback equalizer according to claim 3, characterized in that Both the first delay capacitor and the second delay capacitor are 8-bit capacitor arrays, both the first switch and the second switch are 8-bit switches, and the 8-bit capacitor array and the 8-bit switch control the delay between the input and the output by controlling the size of the first delay capacitor or the second delay capacitor.

5. The data eye width extended decision feedback equalizer according to claim 4, characterized in that, The size of the first delay capacitor or the second delay capacitor is controlled by an 8-bit digital control word.

6. The data eye width extended decision feedback equalizer according to claim 1, characterized in that, The data sampler includes a sense amplifier and a set-reset latch; The sense amplifier is used to amplify the input first data signal and the second data signal, and sample and hold the amplified first data signal and second data signal through the first clock signal and the second clock signal, so as to output a set signal and a reset signal to the set-reset latch; The set-reset latch is used to receive the set signal and the reset signal output by the sense amplifier, and output logic 1 or logic 0 according to the states of the set signal and the reset signal.

7. A data eye width extended decision feedback equalizer according to claim 6, characterized in that The sense amplifier is an 8-channel sense amplifier, and the set-reset latch is an 8-channel set-reset latch.

8. A data eye width extension method for a data eye width extended decision feedback equalizer according to any one of claims 1-7, characterized in that Including: The positive-phase signal of the input high-speed serial data differential signal is delayed by the first numerically controlled delay unit, and the delayed output signal and the input signal before delay are input into an OR logic circuit together, and the OR logic circuit outputs a first data signal, and the first data signal is a logic 1 width expansion signal; The negative-phase signal of the input high-speed serial data differential signal is delayed by the second numerically controlled delay unit, and the delayed output signal and the input signal before delay are input into a NOR logic circuit together, and the NOR logic circuit outputs a second data signal, and the second data signal is a logic 0 width expansion signal; Based on the first clock signal, the odd bits of the first data signal and the second data signal are sampled by a data sampler to obtain the odd-bit signals of the first data signal and the odd-bit signals of the second data signal; based on the second clock signal, the even bits of the first data signal and the second data signal are sampled by a data sampler to obtain the even-bit signals of the first data signal and the even-bit signals of the second data signal; the phase difference between the first clock signal and the second clock signal is 180 degrees; The odd-bit signals in the first data signal or the second data signal are used as the first output signal through a decision feedback circuit, and the even-bit signals in the first data signal or the second data signal are used as the second output signal; the first output signal decides to select and output a logic 0 width extension signal or a logic 1 width extension signal according to the situation of the second output signal; the second output signal decides to select and output a logic 0 width extension signal or a logic 1 width extension signal according to the situation of the first output signal.

9. The data eye width extension method according to claim 8, wherein The step of using the odd-bit signals in the first data signal or the second data signal as the first output signal and the even-bit signals in the first data signal or the second data signal as the second output signal through a decision feedback circuit includes: Input the odd-bit signals of the first data signal and the odd-bit signals of the second data signal into a first selector, input the output signal of the first selector into the data input terminal of a first D flip-flop, input the first clock signal into the clock input terminal of the first D flip-flop, input the output signal of the second D flip-flop into the enable control terminal of the first selector, and use the output signal of the first D flip-flop as the first output signal; Input the even-bit signals of the first data signal and the even-bit signals of the second data signal into a second selector, input the output signal of the second selector into the data input terminal of a second D flip-flop, input the second clock signal into the clock input terminal of the second D flip-flop, input the output signal of the first D flip-flop into the enable control terminal of the second selector, and use the output signal of the second D flip-flop as the second output signal.

10. The data eye width extension method according to claim 8, wherein: The step of delaying the positive-phase signal of the input high-speed serial data differential signal by the first numerically controlled delay unit includes: inputting the positive-phase signal of the high-speed serial data differential signal into the input terminal of a first inverter, inputting the output signal of the first inverter into the input terminal of a second inverter and the first end of a first delay capacitor, grounding the second end of the first delay capacitor through a switch, and using the output signal of the second inverter as the delayed positive-phase signal; The step of delaying the negative-phase signal of the input high-speed serial data differential signal through the second digital control delay unit includes: inputting the negative-phase signal of the high-speed serial data differential signal to the input terminal of a third inverter, inputting the output signal of the third inverter to the input terminal of a fourth inverter and the first terminal of a second delay capacitor, grounding the second terminal of the delay capacitor through a switch, and using the output signal of the fourth inverter as the delayed negative-phase signal.

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