Substrate, electronic device, and electronic apparatus

Abstract

The embodiment of the invention discloses a substrate, an electronic device and electronic equipment, relates to the field of electronic devices, and solves the problem of poor mechanical performance of an interconnection structure. According to the specific scheme, the substrate comprises an interconnection assembly, a plurality of wiring layers and a plurality of dielectric layers. And one dielectric layer is arranged between two adjacent wiring layers. The interconnection assembly comprises an accommodating hole and a plurality of conductive parts, the plurality of conductive parts are arranged at intervals, and the accommodating hole penetrates through the plurality of wiring layers and the plurality of dielectric layers; the plurality of conductive parts are positioned in the accommodating hole and are connected with the inner wall of the accommodating hole; and one conductive piece is electrically connected with the two wiring layers, so that the multiple wiring layers are interconnected. Under the condition that the circuit design complexity on the substrate is the same, the number of the containing holes formed in the substrate is reduced. At least two conductive pieces are arranged in one containing hole. The number of the accommodating holes is further reduced. Complex circuit design can be realized in a small area on the substrate, and layout difficulty is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic devices, and in particular to a substrate, an electronic device, and an electronic device. Background Art

[0002] In the field of integrated circuits, devices achieve signal conduction through interconnects. For example, multiple bare chips are interconnected through interconnects. For example, multiple chip packaging structures on printed circuit boards (PCBs) are connected through interconnects. As the integration of integrated circuits increases, the density of interconnects increases, and the difficulty of interconnect layout increases. Summary of the invention

[0003] The embodiments of the present application provide a substrate, an electronic device, and an electronic device, which can reduce the difficulty of layout of interconnection lines.

[0004] In the first aspect, an embodiment of the present application provides a substrate. The substrate includes an interconnection component, a multi-layer wiring layer and a multi-layer dielectric layer. The multi-layer wiring layers are stacked, and a dielectric layer is provided between each two adjacent layers of the wiring layers. The interconnection component includes a receiving hole and a plurality of conductive members, and the receiving hole runs through the multi-layer wiring layers and the multi-layer dielectric layers; the opposite ends of any one of the multiple conductive members are electrically connected to the two layers of the wiring layers, respectively, and the two layers of the wiring layers connected by at least two of the multiple conductive members are not completely the same. There are at least two conductive members in one of the receiving holes. Because the receiving hole runs through the multi-layer wiring layers and the multi-layer dielectric layers. Then the number of holes that need to be opened for the multiple conductive members is small. A substrate of the same area size can be provided with more receiving holes and more conductive members, which can be applied to more complex circuits and reduce the difficulty of layout of interconnection lines in the substrate. Alternatively, the area of ​​the substrate where no holes are provided is larger. The area where no holes are provided can be connected to other components, making the substrate more compact and increasing the selectivity of the layout of the substrate and other components.

[0005] In combination with the first aspect, in some achievable ways, the plurality of the conductive members include a first conductive member, the two wiring layers connected to the two ends of the first conductive member are respectively a first wiring layer and a second wiring layer, the first wiring layer includes a plurality of first metal wires arranged at intervals along the circumference of the receiving hole; the second wiring layer includes a plurality of second metal wires arranged at intervals along the circumference of the receiving hole; the first conductive member includes a plurality of conductive portions arranged at intervals along the circumference of the receiving hole; the plurality of the first metal wires and the plurality of the second metal wires are electrically connected one by one through the plurality of conductive portions. Since the conductive member is located in the receiving hole, the plurality of conductive portions are also located in the receiving hole. The conductive portions connecting the plurality of first metal wires and the plurality of second metal wires are all located in the receiving hole. Compared with each conductive portion being located in one hole. The number of receiving holes opened on the first wiring layer is reduced. The area of ​​the region where the receiving holes are not provided on the first wiring layer is increased. The region where the receiving holes are not provided on the first wiring layer can be connected to the component that needs to avoid the holes. The integration of the first wiring layer is increased. Under the condition that the complexity of the circuit design on the substrate is the same, the number of receiving holes provided on the substrate is reduced. The layout difficulty is reduced. In addition, the number of receiving holes opened on the first wiring layer is reduced, the support strength of the first wiring layer is increased, and the mechanical performance is improved. Similarly, the integration of the second wiring layer is increased, and the mechanical performance of the second wiring layer is improved.

[0006] In combination with the first aspect, in some achievable manners, the projections of the receiving holes on each dielectric layer and wiring layer overlap, so that the area occupied by the receiving holes on the substrate is small, which is beneficial to improving the integration of the substrate.

[0007] In conjunction with the first aspect, in some achievable manners, the difference between the thickness of the first metal line and the thickness of the conductive portion is less than or equal to 10 μm. In this way, the difference between the thickness of the first metal line and the thickness of the conductive portion is small, and when electrons flow through the connection position between the conductive portion and the first metal line, the electron flow rate changes little, and the signal loss is small.

[0008] In combination with the first aspect, in some achievable manners, the first metal line extends in a direction away from the receiving hole, and the difference between the size of the conductive portion along the circumference of the receiving hole and the line width of the first metal line is less than or equal to 50 μm. In this way, when electrons flow through the connection position between the conductive portion and the first metal line, the electron flow rate changes less and the signal loss is small.

[0009] In combination with the first aspect, in some achievable manners, the first metal wire extends in a direction away from the receiving hole, and the size of the conductive portion along the circumference of the receiving hole is equal to the line width of the first metal wire; and / or the size of the conductive portion along the radial direction of the receiving hole is equal to the thickness of the first metal wire. When electrons flow through the connection position between the conductive portion and the first metal wire, the electron flow rate changes less and the signal loss is small.

[0010] The interconnection assembly also includes a first insulating member, which is disposed in the receiving hole; along the circumference of the receiving hole, the first insulating member is disposed between any two adjacent conductive parts. The first insulating member can prevent any two adjacent conductive parts from being directly electrically connected, thereby preventing a short circuit on the substrate.

[0011] In combination with the first aspect, in some achievable ways, the interconnection assembly further comprises a second insulating member, the second insulating member being disposed between any two adjacent conductive members. The second insulating member can prevent a conductive member from being directly electrically connected to another conductive member, and prevent the two conductive members from being directly electrically connected and causing a short circuit on the substrate.

[0012] In combination with the first aspect, in some achievable manners, a plurality of conductive members are arranged at intervals along the extension direction of the receiving hole, and a conductive member interconnects two adjacent wiring layers, thereby electrically connecting multiple wiring layers.

[0013] In combination with the first aspect, in some achievable ways, the conductive member covers the inner wall of the receiving hole along the circumferential direction. Thus, the size of the conductive member along the circumferential direction of the receiving hole is equal to the size of the circumferential direction of the receiving hole. In the process of forming the conductive member, the conductive member can indiscriminately cover the inner wall of the receiving hole along the circumferential direction, and the process cost of the conductive member is low.

[0014] In combination with the first aspect, in some achievable ways, the projections of at least two of the conductive parts on the reference plane overlap, the reference plane is parallel to the extension direction of the receiving hole, and the plurality of conductive parts are arranged at intervals along the circumference of the receiving hole. Thus, the receiving hole can accommodate a larger number of conductive parts, providing a guarantee for the complex circuit design of the interconnection component. In combination with the first aspect, in some achievable ways, the substrate further includes: a connecting portion, the connecting portion being electrically connected to the outermost wiring layer of the multiple wiring layers. Thus, the signal in the multiple wiring layers can be output through the connecting portion, or the signal can be transmitted to the multiple wiring layers through the connecting portion.

[0015] In a second aspect, an embodiment of the present application provides an electronic device. The electronic device includes a component and any one of the substrates provided in the first aspect, and the component is electrically connected to one end of the substrate. Since the substrate has the advantages of high integration and excellent mechanical properties. Obviously, the electronic device including the substrate also has the characteristics of high integration and excellent mechanical properties.

[0016] In conjunction with the second aspect, in some achievable manners, the substrate is a packaging substrate, and the component includes at least one bare chip. Therefore, when the wiring complexity is equal, the number of accommodating holes opened on the packaging substrate is small. When the area of ​​the packaging substrate is equal, more accommodating holes can be opened to layout more complex circuits, thereby reducing the difficulty of layout of complex circuits.

[0017] In conjunction with the second aspect, in some achievable manners, the substrate is a printed circuit board, and the component is a chip packaging structure formed by packaging the packaging substrate and at least one bare chip. Since a plurality of conductive members can be accommodated in one receiving hole, more receiving holes can be opened when the area of ​​the printed circuit board is equal to each other, so as to layout a more complex circuit and reduce the difficulty of layout of the complex circuit.

[0018] In a third aspect, an electronic device is provided, the electronic device comprising a housing and any electronic device provided in the second aspect, the electronic device being located in the housing. Since the aforementioned electronic device can lay out a relatively complex circuit, the difficulty of laying out a complex circuit is reduced. Obviously, the electronic device can realize the functions of a relatively complex circuit.

[0019] In a fourth aspect, a method for preparing a substrate is provided, comprising:

[0020] A plurality of wiring layers and a plurality of dielectric layers are formed, wherein the plurality of wiring layers are stacked and a dielectric layer is arranged between each two adjacent wiring layers; a receiving hole is formed that penetrates the plurality of wiring layers and the plurality of dielectric layers; a conductive layer is formed in the receiving hole; the conductive layer is etched to form a plurality of conductive parts; the opposite ends of one conductive part are electrically connected to the two wiring layers respectively, and the two wiring layers connected to at least two conductive parts are not completely the same.

[0021] In combination with the fourth aspect, in some feasible embodiments, the multiple conductive members include a first conductive member, and the two wiring layers connected to the two ends of the first conductive member are respectively a first wiring layer and a second wiring layer; etching the conductive layer to form multiple conductive members includes: etching the conductive layer to form multiple conductive parts arranged at circumferential intervals along the accommodating hole to obtain the first conductive member; wherein the first wiring layer includes a plurality of first metal wires arranged at circumferential intervals along the accommodating hole, and the second wiring layer includes a plurality of second metal wires arranged at circumferential intervals along the accommodating hole; the plurality of first metal wires and the plurality of second metal wires are electrically connected one-to-one through the plurality of conductive parts.

[0022] In a fifth aspect, a substrate is provided, which is prepared by any one of the substrate preparation methods provided in the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1a The figure is a schematic diagram of the structure of an electronic device.

[0024] Figure 1b The figure is a schematic diagram of the structure of an electronic device and a housing.

[0025] Figure 1c A schematic diagram of the structure of another electronic device.

[0026] Figure 1dA schematic diagram of the structure of another electronic device.

[0027] Figure 1e A schematic diagram of the structure of yet another electronic device.

[0028] Figure 2 It is a schematic diagram of the structure of the chip interconnection structure in the related technology.

[0029] Figure 3 A schematic structural diagram of a substrate provided in an embodiment of the present application.

[0030] Figure 4 A schematic structural diagram of another substrate provided in an embodiment of the present application.

[0031] Figure 5a A schematic diagram of the decomposed structure of the first wiring layer and the second wiring layer provided in an embodiment of the present application.

[0032] Figure 5b A schematic structural diagram of another first wiring layer and a first conductive member provided in an embodiment of the present application.

[0033] Figure 5c A schematic diagram of the structure of the first wiring layer and the first dielectric layer provided in an embodiment of the present application.

[0034] Figure 6 A schematic structural diagram of another substrate provided in an embodiment of the present application.

[0035] Figure 7 A schematic diagram of the structure of another substrate provided in an embodiment of the present application.

[0036] Figure 8a A process flow chart of a substrate provided in an embodiment of the present application.

[0037] Figure 8b To complete Figure 8a Schematic diagram of the structure after S1.

[0038] Figure 8c To complete Figure 8a Schematic diagram of the structure after S2.

[0039] Figure 8d To complete Figure 8a Schematic diagram of the structure after S3.

[0040] Figure 8e To complete Figure 8a Schematic diagram of the structure after S4.

[0041] Figure 8f To complete Figure 8a Schematic diagram of the structure after S5.

[0042] In the figure: 001-chip interconnection structure; 002-first chip; 003-second chip; 004-dielectric layer; 005-copper wiring; 006-metal via; 10-electronic device; 11-electronic device; 12-housing; 13-components; 14-chip packaging assembly; 15-connecting part; 16-first bare chip; 17-second bare chip; 18-chip; 19-packaging shell; 20-substrate; 110-interconnection assembly; 111-accommodating hole; 112-conductive member; 113-first conductive member; 121 -first metal wire; 122-second metal wire; 123-conductive part; 114-insulating layer; 101-first wiring layer; 102-second wiring layer; 103-third wiring layer; 104-fourth wiring layer; 105-fifth wiring layer; 106-sixth wiring layer; 201-first dielectric layer; 202-second dielectric layer; 203-third dielectric layer; 204-fourth dielectric layer; 205-fifth dielectric layer; 108-conductive layer; 124-first insulating member; 125-gap; 126-second insulating member. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0044] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0045] In addition, in the present application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the changes in the orientation of the components in the drawings.

[0046] Figure 1a FIG. 1 is a schematic diagram of the structure of an electronic device 10. Figure 1a The electronic device 10 includes an electronic device 11 and a housing 12. The electronic device 11 is located in the housing 12, and the electronic device 11 and the housing 12 are connected.

[0047] The embodiment of the present application does not limit the type of the electronic device 10. For example, the electronic device may be a mobile phone, a tablet computer (pad), a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk machine, a sweeping robot), a drone, a radar, an aerospace equipment, a vehicle-mounted device, and other different types of user devices or terminal devices. The embodiment of the present application does not specifically limit the specific form of the electronic device.

[0048] The embodiment of the present application does not limit the connection method between the housing 12 and the electronic device 11 . For example, the electronic device 11 is located inside the housing 12 . Figure 1b It is a schematic diagram of the structure of an electronic device 11 and a housing 12. Figure 1b In the embodiment, the electronic device 11 includes a component 13, a substrate 20 and a connecting portion 15. The component 13 and the connecting portion 15 are electrically connected through the substrate 20. The substrate 20 realizes signal transmission of the component 13 and circuit wiring of the component 13. The signal of the substrate 20 can be output to other components through the connecting portion 15. Alternatively, the signal of other components can be transmitted to the component 13 through the connecting portion 15 and the substrate 20.

[0049] The embodiment of the present application does not limit the structure of the connection part 15. For example, the connection part 15 can be a solder ball. The embodiment of the present application does not limit the number of the connection parts 15, which can be set according to the power of the electronic device 11.

[0050] The embodiment of the present application does not limit the structure of the component 13 , and it can be configured according to the type of the electronic device 11 . Figure 1c FIG. 1 is a schematic diagram of the structure of another electronic device 11 . Figure 1c In the example of FIG. 1 , the component 13 includes a first bare chip 16 and a second bare chip 17, and the first bare chip 16 and the second bare chip 17 are electrically connected through a substrate 20. The substrate 20 realizes signal interconnection between the first bare chip 16 and the second bare chip 17. The embodiment of the present application does not limit the number of the first bare chips 16 and the number of the second bare chips 17. For example, the number of the first bare chips 16 can be one, two or more. The number of the second bare chips 17 can be one, two or more. Figure 1c In the example of FIG. 1 , the first bare chip 16 and the second bare chip 17 are respectively located on opposite sides of the substrate 20 . In other examples, the first bare chip 16 and the second bare chip 17 may both be located on the same side of the substrate 20 .

[0051] Figure 1d FIG. 1 is a schematic diagram of the structure of another electronic device 11 . Figure 1d In the embodiment, the component 13 includes a chip package assembly 14. The chip package assembly 14 is electrically connected to a substrate 20. The substrate 20 is used to output the signal in the chip package assembly 14, for example, to the connection portion 15. Figure 1c In the example of FIG. 1 , the substrate 20 may be a printed circuit board (PCB). Figure 1d In the embodiment, the number of chip packaging components 14 is not limited, for example, it can be one, two or more.

[0052] Figure 1e FIG. 1 is a schematic diagram of the structure of yet another electronic device 11 . Figure 1e In the embodiment, the electronic device 11 is a chip packaging structure. The component 13 includes a plurality of chips 18 and a packaging shell 19. The plurality of chips 18 are located in the packaging shell 19. The plurality of chips 18 are electrically connected to a substrate 20. The packaging shell 19 is connected to the substrate 20. Figure 1d In the embodiment, the substrate 20 is a package substrate. The package substrate and the package shell 19 are connected to package the chip 18. Exemplarily, the chip 18 may include one bare chip. Alternatively, the chip 18 may include a plurality of bare chips.

[0053] It is understood that the substrate 20 is not limited to the above Figure 1c , Figure 1d and Figure 1e The application scenario shown can also be used in other circuit designs and will not be described in detail here.

[0054] Figure 2 It is a structural schematic diagram of a chip interconnection structure 001 in the related art. Figure 2 In the embodiment, the chip interconnection structure 001 includes a first chip 002, a second chip 003, a multi-layer dielectric layer 004 and a multi-layer copper wiring 005. There is a dielectric layer 004 between two adjacent layers of copper wiring 005. The first chip 002 and the second chip 003 are electrically connected to the two outermost layers of copper wiring 005 in the multi-layer copper wiring 005, respectively. Figure 2 In the example, a metal via 006 is provided in the dielectric layer 004, and the metal via 006 electrically connects two adjacent layers of copper wiring 005. The two adjacent layers of copper wiring 005 are electrically connected. In this example, if the complexity of the circuit between the first chip 002 and the second chip 003 increases, the number of metal vias 006 increases, the processing is limited, and the processing difficulty increases.

[0055] Figure 3 This is a schematic diagram of the structure of a substrate 20 provided in an embodiment of the present application. Figure 3The substrate 20 includes an interconnection component 110, a multi-layer wiring layer and a multi-layer dielectric layer. A dielectric layer is arranged between each two adjacent wiring layers. The multi-layer wiring layer includes a first wiring layer 101, a second wiring layer 102 and a third wiring layer 103. The multi-layer dielectric layer includes a first dielectric layer 201 and a second dielectric layer 202. The first wiring layer 101, the first dielectric layer 201, the second wiring layer 102, the second dielectric layer 202 and the third wiring layer 103 are stacked in sequence. The multi-layer wiring layers are electrically connected through the interconnection component 110. For example, the first wiring layer 101, the second wiring layer 102 and the third wiring layer 103 are electrically connected through the interconnection component 110.

[0056] The substrate 20 provided in the embodiment of the present application is intended to reduce the difficulty of layout of complex circuits and reduce the difficulty of routing design.

[0057] The embodiment of the present application does not limit the number of dielectric layers in the substrate 20. For example, the number of dielectric layers can be two, three, four or more layers. The embodiment of the present application does not limit the number of wiring layers in the substrate 20. For example, the number of wiring layers can be three, four, five or more layers.

[0058] Figure 3 In the embodiment, there are three wiring layers, namely, a first wiring layer 101, a second wiring layer 102, and a third wiring layer 103, which are stacked in sequence. There are two dielectric layers, namely, a first dielectric layer 201 and a second dielectric layer 202. The interconnection component 110 includes a receiving hole 111 and a plurality of conductive members 112, and the plurality of conductive members 112 are located in the receiving hole 111. The first wiring layer 101, the second wiring layer 102, and the third wiring layer 103 are electrically connected through the interconnection component 110. The receiving hole 111 penetrates the first wiring layer 101, the second wiring layer 102, the third wiring layer 103, the first dielectric layer 201, and the second dielectric layer 202.

[0059] Multiple conductive members 112 are all located in the receiving hole 111, and multiple conductive members 112 are all connected to the inner wall of the receiving hole 111. Multiple conductive members 112 are arranged at intervals. In this way, two adjacent conductive members 112 are not directly electrically connected, so as to avoid short circuit between the two conductive members 112. One conductive member 112 is electrically connected to any two wiring layers. The two wiring layers connected to at least two conductive members 112 among the multiple conductive members 112 are not completely the same. The aforementioned at least two conductive members 112 are located in one receiving hole 111. For example, one of the conductive members 112 connects the first wiring layer 101 and the second wiring layer 102, and the other conductive member 112 connects the first wiring layer 101 and the third wiring layer 103.

[0060] Since the two wiring layers connected by at least two conductive members 112 are not completely the same, under the same wiring conditions, the number of receiving holes 111 opened on the substrate 20 is reduced. The substrate 20 with the same area can have more receiving holes 111, further accommodating more conductive members 112. The wiring design difficulty of the substrate 20 with the same area is reduced, and the density of the receiving holes 111 is reduced. The layout difficulty of complex circuits is reduced.

[0061] In addition, the receiving holes 111 that penetrate the multi-layer wiring layer and the multi-layer dielectric layer can be formed by a one-time process. Compared with forming metal vias on different dielectric layers, the process flow of forming the receiving holes 111 of the embodiment of the present application is simpler and the process cost is lower. The area where the receiving holes 111 are distributed on the substrate 20 is reduced. The presence of the holes will reduce the mechanical strength of the substrate 20. The reduction in the number of receiving holes 111 can improve the support strength of the substrate 20 and improve its mechanical properties.

[0062] The receiving holes 111 penetrate through the multiple wiring layers and the multiple dielectric layers, and the projections of the receiving holes 111 on each wiring layer and dielectric layer overlap, so that the density of the holes on the substrate 20 is reduced.

[0063] Exemplarily, the two wiring layers connected by at least two conductive members 112 are not completely the same, including: in an embodiment where the number of conductive members 112 is two, one of the two conductive members 112 is connected to two of the wiring layers, and the other conductive member 112 is connected to the other two wiring layers. One of the two wiring layers and the other two wiring layers is the same wiring layer, or the two wiring layers and the other two wiring layers are different from each other. In an embodiment where the number of conductive members 112 is greater than two, two of the conductive members 112 meet the above conditions, and the rest are not limited.

[0064] The present application embodiment does not limit the material of the first wiring layer 101. For example, the material of the first wiring layer 101 includes metal materials such as copper, tungsten or aluminum. Similarly, the materials of the second wiring layer 102 and the third wiring layer 103 may also include metal materials such as copper, tungsten or aluminum.

[0065] The embodiment of the present application does not limit the material of the first dielectric layer 201, and it can be set according to the use scenario of the substrate 20. For example, in the embodiment where the substrate 20 and the chip 18 are connected, the first dielectric layer 201 can be a packaging substrate. The material of the first dielectric layer 201 can be silicon. The receiving hole 111 that penetrates the silicon wafer can be formed by a through silicon via (TSV) process. Alternatively, the material of the first dielectric layer 201 can be a material such as resin or silicon dioxide. Correspondingly, the material of the second dielectric layer 202 is the same, and it will not be repeated here.

[0066] As mentioned above, a conductive member 112 is electrically connected to any two wiring layers. The embodiment of the present application does not limit the positional relationship of the two wiring layers connected to the same conductive member 112, and can be set according to the circuit of the substrate 20. For example, the two ends of the conductive member 112 are electrically connected to the first wiring layer 101 and the second wiring layer 102 respectively. Alternatively, the two ends of the conductive member 112 are electrically connected to the second wiring layer 102 and the third wiring layer 103 respectively. Alternatively, the two ends of the conductive member 112 are electrically connected to the second wiring layer 102 and the fourth wiring layer 104 (such as Figure 6 As shown) electrical connections, etc.

[0067] The embodiment of the present application does not limit the number of conductive members 112 in an interconnection component 110. For example, the number of conductive members 112 can be two, three, four or more, which is set according to the circuit design of the substrate 20 and the number of wiring layers. The embodiment of the present application does not limit the number of receiving holes 111 in an interconnection component 110. The number of receiving holes 111 can be two, three, four or more, which can also be set according to wiring requirements.

[0068] In addition, since the plurality of conductive members 112 are arranged at intervals, there is no direct contact between two adjacent conductive members 112, thereby preventing the two conductive members 112 from short-circuiting. The embodiment of the present application does not limit the extension direction of the conductive member 112. For example, the extension direction of the conductive member 112 is parallel to the extension direction of the receiving hole 111. Alternatively, the angle between the extension direction of the conductive member 112 and the extension direction of the receiving hole 111 is 5° to 80°, etc. In other words, when the plurality of conductive members 112 are arranged at intervals and connected to the wiring layer, the conductive member 112 can extend in any direction.

[0069] In addition, the extension directions of two adjacent conductive members 112 may be parallel to each other or may not be parallel to each other. The embodiment of the present application does not limit the angle between the extension directions of two adjacent conductive members 112 .

[0070] The present embodiment of the present application does not limit the preparation method of the conductive member 112. For example, a coating layer may be formed on the hole wall of the receiving hole 111 by electroplating or chemical plating, and a portion of the area may be etched away to form the conductive member 112. In this way, multiple conductive members 112 may be formed simultaneously. Figure 2 Compared with the one-time process required for one metal via 006 in the embodiment of the present application, the multiple conductive members 112 in the embodiment of the present application can be formed by the same process, thus saving process time and process cost.

[0071] The embodiment of the present application does not limit the shape of the receiving hole 111. For example, the receiving hole 111 may be a circular hole, a square hole, or an irregularly shaped hole. As mentioned above, the receiving hole 111 penetrates multiple wiring layers and multiple dielectric layers. On this basis, according to the requirements of the substrate 20, an insulating layer may be further provided at one end of the receiving hole 111.

[0072] Figure 4 This is a schematic structural diagram of another substrate 20 provided in an embodiment of the present application. Figure 4 and Figure 3 The difference is that Figure 4 In the embodiment, the substrate 20 further includes an insulating layer 114. The insulating layer 114 is connected to the side of the third wiring layer 103 away from the second dielectric layer 202. The insulating layer 114 closes one end of the receiving hole 111. Thus, the receiving hole 111 is a blind hole. The insulating layer 114 can prevent the third wiring layer 103 from being connected to other components (such as Figure 1a The chip package assembly 14 contacts other conductive parts) to avoid short circuit.

[0073] Similarly, in some other embodiments of the present application, the substrate 20 may include two insulating layers 114. One insulating layer 114 is connected to the side of the third wiring layer 103 away from the second dielectric layer 202, and the other insulating layer 114 is connected to the side of the first wiring layer 101 away from the first dielectric layer 201. In this way, the receiving hole 111 is a buried hole. The insulating layer 114 can prevent the first wiring layer 101 from being connected to other components (such as Figure 1a The chip package assembly 14 contacts other conductive parts) to avoid short circuit.

[0074] The structures of the insulating layer 114 and the second dielectric layer 202 may be the same or different, and this embodiment of the present application does not limit this.

[0075] As mentioned above, a conductive member is electrically connected to any two wiring layers. Figure 5a The conductive member 112 connecting the first wiring layer 101 and the second wiring layer 102 is described exemplarily. For the convenience of description, the conductive member connecting the first wiring layer 101 and the second wiring layer 102 is named as the first conductive member 113. It can be understood that the connection between the other two wiring layers is similar and will not be described here.

[0076] Figure 5a This is a schematic diagram of the decomposed structure of the first wiring layer 101 and the second wiring layer 102 provided in the embodiment of the present application. Figure 5aThe first wiring layer 101 includes a plurality of first metal wires 121, which are arranged at intervals, so that the plurality of first metal wires 121 are not directly electrically connected. The second wiring layer 102 includes a plurality of second metal wires 122, which are arranged at intervals, so that the plurality of second metal wires 122 are not directly electrically connected.

[0077] The first conductive member 113 includes a plurality of conductive parts 123, and the plurality of conductive parts 123 are arranged at intervals, and the plurality of conductive parts 123 are not directly electrically connected. The opposite ends of a conductive part 123 are electrically connected to a first metal wire 121 and a second metal wire 122, respectively. As mentioned above, all the conductive members 112 are located in the receiving hole 111, and obviously, the first conductive member 113 is also located in the receiving hole 111. Then the plurality of conductive parts 123 are located in the same receiving hole 111, and the conductive parts 123 electrically connect the first metal wire 121 and the second metal wire 122. In this way, the plurality of first metal wires 121 and the plurality of second metal wires 122 are connected one by one through the plurality of conductive parts 123 located in the same receiving hole 111. One receiving hole 111 realizes the interconnection of the plurality of first metal wires 121 and the plurality of second metal wires 122. Compared with the example in which a first metal wire 121 and a second metal wire 122 are connected through a via, the number of openings on the first wiring layer 101 is reduced. Under the same wiring conditions, the number of receiving holes 111 opened on the first wiring layer 101 is reduced, the difficulty of wiring design is reduced, and the density of receiving holes 111 is reduced, which reduces the difficulty of layout of complex circuits.

[0078] The density of the accommodating holes 111 is reduced, which can avoid the reduction of the structural strength of the first wiring layer 101 due to the large number of openings. In addition, the number of accommodating holes 111 is small, the area of ​​the area on the first wiring layer 101 that needs to be opened is small, and the area of ​​the remaining area on the first wiring layer 101 that does not need to be opened is large, so there can be a larger area to set the components that need to avoid the opening area, reducing the area of ​​the first wiring layer 101, thereby reducing the volume of the substrate 20. Similarly, the number of openings on the second wiring layer 102 and the first dielectric layer 201 is small, which is conducive to reducing the difficulty of layout of complex circuits. The structural strength of the second wiring layer 102 and the first dielectric layer 201 can also be improved, and there are larger areas on the second wiring layer 102 and the first dielectric layer 201 to set the components that need to avoid the opening area. The area of ​​the second wiring layer 102 and the first dielectric layer 201 can be reduced, thereby reducing the volume of the substrate 20.

[0079] The embodiment of the present application does not limit the extension direction of the first metal line 121, and can be set according to the circuit design in the first wiring layer 101. The extension direction of the first metal line 121 has little effect on the conductive portion 123, so the routing of the first metal line 121 is more flexible.

[0080] Likewise, in the embodiment of the present application, the extension direction of the second metal wire 122 has little influence on the conductive portion 123 , and therefore, the routing of the second metal wire 122 is more flexible.

[0081] In the embodiment of the present application, the relationship between the extension direction of the first metal wire 121 and the extension direction of the second metal wire 122 connected to the opposite ends of the same conductive portion 123 is not limited. For example, the extension direction of the first metal wire 121 and the extension direction of the second metal wire 122 connected to the opposite ends of the same conductive portion 123 are parallel. Alternatively, the extension direction of the first metal wire 121 and the extension direction of the second metal wire 122 connected to the opposite ends of the same conductive portion 123 are perpendicular to each other. In this way, the wiring of the first wiring layer 101 and the second wiring layer 102 is more flexible and is not limited by the conductive portion 123.

[0082] The embodiment of the present application does not limit the number of the first metal wires 121, the conductive parts 123, and the second metal wires 122, which can be set according to the circuit design. The first metal wires 121, the conductive parts 123, and the second metal wires 122 are connected one by one. For example, the number of the first metal wires 121 can be two, three, four, or more.

[0083] In some embodiments, the thickness of the first metal line 121 is equal to the thickness of the conductive portion 123. In this way, when the electrical signal flows through the connection position of the first metal line 121 and the conductive portion 123, the current flow fluctuation is small and the signal loss is small. Exemplarily, the difference between the thickness of the first metal line 121 and the thickness of the conductive portion 123 is less than or equal to 10 μm, for example, the thickness difference can be 0, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, etc.

[0084] In some embodiments, the first metal wire 121 extends in a direction away from the receiving hole 111, the line width of the first metal wire 121 is n, and the dimension m of the conductive portion 123 along the circumference of the receiving hole 111 is equal to the line width n of the first metal wire 121. Accordingly, when the electrical signal flows through the connection position between the first metal wire 121 and the conductive portion 123, the current flow fluctuation is small and the signal loss is small. Exemplarily, the difference between the dimension m of the conductive portion 123 and the dimension n of the first metal wire 121 is less than or equal to 50μm. For example, the difference between the dimension m and the dimension n can be 0, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm or 50μm, etc.

[0085] Accordingly, in some embodiments, the thickness of the second metal line 122 is equal to the thickness of the conductive portion 123. The dimension m of the conductive portion 123 along the circumference of the receiving hole 111 is equal to the line width k of the second metal line 122. When the electrical signal flows through the connection position of the second metal line 122 and the conductive portion 123, the signal loss is small.

[0086] It is understood that in the embodiment where there are multiple first metal lines 121, the sizes of the multiple first metal lines 121 may be equal or may not be completely equal. Similarly, in the embodiment where there are multiple second metal lines 122, the sizes of the multiple second metal lines 122 may be equal or may not be completely the same.

[0087] As described above, the first conductive member 113 includes a plurality of conductive portions 123 disposed at intervals. The embodiment of the present application does not limit the structure between two adjacent conductive portions 123. Figure 5a In the example, there is a gap 125 between two adjacent conductive parts 123, and the gap 125 is filled with gas, for example, the gap 125 is filled with air, nitrogen or argon. In this way, the gas in the gap 125 can also prevent the flow of current and prevent the two adjacent conductive parts 123 from being electrically connected.

[0088] Alternatively, in some embodiments, an insulating member may be disposed between two adjacent conductive portions 123 to avoid electrical connection between the two adjacent conductive portions 123 .

[0089] Figure 5b A schematic diagram of the structure of another first wiring layer 101 and a first conductive member 113 provided in an embodiment of the present application. Figure 5b and Figure 5a The difference is that a first insulating member 124 is provided between two adjacent conductive parts 123. One end of the first insulating member 124 is connected to one conductive part 123, and the other end of the first insulating member 124 is connected to the other conductive part 123. This prevents the two conductive parts 123 from short-circuiting.

[0090] The embodiment of the present application does not limit the material of the first insulating member 124. For example, the first insulating member 124 may be an insulating material such as a non-conductive medium. For example, the non-conductive medium is a resin.

[0091] Figure 5b In the embodiment, the first insulating member 124 extends between two adjacent first metal wires 121. In the area close to the receiving hole 111, the distance between two adjacent first metal wires 121 is small. The first insulating member 124 between the first metal wires 121 can prevent current from passing through, avoid direct electrical conduction between the two adjacent first metal wires 121, and avoid signal crosstalk between the two adjacent first metal wires 121.

[0092] Figure 5a and Figure 5b The example shows a connection mode in which the first wiring layer 101 and the second wiring layer 102 are electrically connected through the conductive member 112. It is understandable that the connection mode of the electrical connection between any other two wiring layers can be obtained in the same way. For example, the connection mode in which the second wiring layer 102 and the third wiring layer 103 are electrically connected. And the connection mode in which the first wiring layer 101 and the third wiring layer 103 are electrically connected can be obtained in the same way. It will not be repeated here.

[0093] As described above, in some embodiments, the connection portion 15 is connected to the first wiring layer 101 . Figure 5c A schematic structural diagram of a first wiring layer 101 and a first dielectric layer 201 provided in an embodiment of the present application. Figure 5c In the embodiment, the connection portion 15 is connected to the first metal wire 121 . Figure 5c In the embodiment, the first wiring layer 101 includes three first metal wires 121, and the three connection parts 15 are connected to the three first metal wires 121 in a one-to-one correspondence. The current in the substrate 20 can be output through the connection parts 15.

[0094] As mentioned above, the type of the first dielectric layer 201 can be set according to the type of the substrate 20. For example, the first dielectric layer 201 can be a PCB board, a packaging substrate, a silicon wafer, and the like.

[0095] The embodiment of the present application does not limit the connection method between the connection portion 15 and the first metal wire 121. For example, the connection portion 15 and one end of the first metal wire 121 are welded.

[0096] The embodiment of the present application does not limit the number of wiring layers. Figure 6 This is a schematic structural diagram of another substrate 20 provided in an embodiment of the present application. Figure 6 In the embodiment, there are six wiring layers, namely, a first wiring layer 101, a second wiring layer 102, a third wiring layer 103, a fourth wiring layer 104, a fifth wiring layer 105 and a sixth wiring layer 106, which are stacked in sequence. There are five dielectric layers, namely, a first dielectric layer 201, a second dielectric layer 202, a third dielectric layer 203, a fourth dielectric layer 204 and a fifth dielectric layer 205.

[0097] Figure 6 In the embodiment, the receiving hole 111 of the interconnection component 110 penetrates through the multiple wiring layers and the multiple dielectric layers. Exemplarily, the receiving hole 111 penetrates the first wiring layer 101, the second wiring layer 102, the third wiring layer 103, the fourth wiring layer 104, the fifth wiring layer 105 and the sixth wiring layer 106. And the receiving hole 111 penetrates the first dielectric layer 201, the second dielectric layer 202, the third dielectric layer 203, the fourth dielectric layer 204 and the fifth dielectric layer 205.

[0098] exist Figure 6In the example, the positional relationship of a conductive member 112 relative to the two wiring layers connected at both ends is not limited. For example, it can be two adjacent wiring layers, or it can be two non-adjacent wiring layers. For example, Figure 6 In the embodiment, there are a plurality of conductive members 112, and the first wiring layer 101 and the second wiring layer 102 are electrically connected through the conductive member 112. The second wiring layer 102 and the third wiring layer 103 are electrically connected through the conductive member 112. The third wiring layer 103 and the fourth wiring layer 104 are electrically connected through the conductive member 112. The third wiring layer 103 and the fifth wiring layer 105 are electrically connected through the conductive member 112. The fifth wiring layer 105 and the sixth wiring layer 106 are electrically connected through the conductive member 112.

[0099] It is understood that in other embodiments of the present application, the number of wiring layers is not limited to Figure 3 The three layers and Figure 6 The six layers can be designed according to the circuit requirements of the substrate 20.

[0100] Figure 3 and Figure 6 In the example, the conductive member 112 only covers a portion of the inner wall of the receiving hole 111 in the circumferential direction. In other embodiments, the conductive member 112 and the receiving hole 111 may be in other positional relationships.

[0101] Figure 6 In the example, multiple conductive members 112 are arranged at intervals along the circumference of the receiving hole 111. The projections of at least two conductive members 112 on the reference plane overlap. The reference plane is parallel to the extension direction of the receiving hole 111, and multiple conductive members 112 are arranged at intervals along the circumference of the receiving hole 111. The sum of the lengths of the two conductive members 112 along the extension direction of the receiving hole 111 is greater than the length of the receiving hole 111. Multiple conductive members 112 are arranged at intervals along the circumference of the receiving hole 111, which can prevent the conductive members 112 from directly contacting the adjacent conductive members 112 on both sides of the circumference of the receiving hole 111 and causing a short circuit.

[0102] Figure 7 This is a schematic diagram of the structure of another substrate 20 provided in an embodiment of the present application. Figure 7 , the conductive member 112 covers the entire circumference of the receiving hole 111. Multiple conductive members 112 are arranged at intervals along the radial direction of the receiving hole 111. A second insulating member 126 is arranged between two adjacent conductive members 112, and the second insulating member 126 is located between two adjacent conductive members 112. The two adjacent conductive members 112 are not directly electrically connected, thereby avoiding a short circuit caused by the direct electrical connection of the two conductive members 112.

[0103] exist Figure 7In the example, the difference between the thickness of the conductive member 112 and each wiring layer is less than or equal to 10μm. For example, the thickness difference can be 0, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm or 10μm, etc.

[0104] Alternatively, in other embodiments, there is a gap between two adjacent conductive members 112, which prevents the two adjacent conductive members 112 from being directly electrically connected, thereby avoiding a short circuit caused by direct electrical connection between the two conductive members 112. For example, the gap between two adjacent conductive members 112 is located on the surface of the dielectric layer.

[0105] exist Figure 7 In the example, since the conductive member 112 covers the entire circumference of the receiving hole 111, one conductive member 112 connects two adjacent wiring layers. For example, the first wiring layer 101 and the second wiring layer 102 are electrically connected through one conductive member 112. The third wiring layer 103 and the fourth wiring layer 104 are electrically connected through one conductive member 112.

[0106] The embodiment of the present application does not limit the number of interconnection components 110 in the substrate 20. For example, the number of interconnection components 110 is one, two, three or more. In the embodiment where the number of interconnection components 110 is two or more, the structures of the interconnection components 110 may be the same or different.

[0107] The embodiment of the present application does not limit the method for preparing the substrate 20 , and is configured according to the structure of the substrate 20 .

[0108] Exemplarily, the method for preparing the substrate 20 includes:

[0109] First, multiple wiring layers and multiple dielectric layers are formed. The multiple wiring layers are stacked and arranged, and a dielectric layer is arranged between each two adjacent wiring layers. Then, a receiving hole is formed that penetrates the multiple wiring layers and the multiple dielectric layers. Subsequently, a conductive layer is formed in the receiving hole; secondly, the conductive layer is etched to form multiple conductive parts; the opposite ends of one conductive part are electrically connected to the two wiring layers respectively, and the two wiring layers connected by at least two conductive parts are not completely the same. Because the conductive parts connecting the multiple wiring layers are located in the same receiving hole, multiple conductive parts can be formed in the same process flow, saving the process flow.

[0110] Obviously, the number of wiring layers and dielectric layers and the number of conductive elements can be set according to the structure of the substrate 20. Figure 8a right Figure 4 The method for preparing the substrate 20 shown in FIG. 1 is exemplarily described. Figure 8a A process flow chart of a substrate 20 provided in an embodiment of the present application. Figure 8a , the preparation method of the substrate 20 includes:

[0111] S1. Formed on the insulating layer 114 Figure 8b The third wiring layer 103 is shown.

[0112] Figure 8b To complete Figure 8a Schematic diagram of the structure after S1. Figure 8b In the embodiment of the present application, the third wiring layer 103 and the insulating layer 114 are stacked. The present application embodiment does not limit the method for forming the third wiring layer 103. Exemplarily, a conductive layer is first formed on the insulating layer 114, and the redundant part of the conductive layer is etched to form the third wiring layer 103. The present application embodiment does not limit the material of the insulating layer 114, for example, it can be silicon or resin.

[0113] S2. Forming on the third wiring layer 103 Figure 8c The second dielectric layer 202 is shown.

[0114] Figure 8c To complete Figure 8a Schematic diagram of the structure after S2. Figure 8c In the embodiment, the second dielectric layer 202 is connected to the side of the third wiring layer 103 away from the insulating layer 114. The present application embodiment does not limit the preparation method of the second dielectric layer 202. For example, the second dielectric layer 202 is formed by coating.

[0115] S3 . Repeat step S1 and step S2 to form a second wiring layer 102 on the second dielectric layer 202 , form a first dielectric layer 201 on the second wiring layer 102 , and form a first wiring layer 101 on the first dielectric layer 201 .

[0116] Figure 8d To complete Figure 8a Schematic diagram of the structure after S3. Figure 8d In the embodiment, the first wiring layer 101, the first dielectric layer 201, the second wiring layer 102, the second dielectric layer 202, the third wiring layer 103 and the insulating layer 114 are stacked.

[0117] S4. Formation Figure 8e The receiving hole 111 is shown.

[0118] Figure 8e To complete Figure 8a Schematic diagram of the structure after S4. Figure 8e In the embodiment, the receiving hole 111 penetrates the first wiring layer 101 , the first dielectric layer 201 , the second wiring layer 102 , the second dielectric layer 202 , and the third wiring layer 103 .

[0119] S5. Plating the inner wall of the receiving hole 111 Figure 8fConductive layer 108 is shown.

[0120] Figure 8f To complete Figure 8a Schematic diagram of the structure after S5. Figure 8f In the embodiment, the conductive layer 108 covers the entire inner wall of the receiving hole 111 .

[0121] S6. Remove part of the conductive layer 108 to form Figure 3 The conductive member 112 is shown.

[0122] like Figure 3 As shown, the portion of the conductive layer 108 that is removed is set according to the shape and size of the conductive member 112. For example, the conductive member 112 can be formed by removing a portion of the conductive layer 108 by etching.

[0123] Figure 8a In the manufacturing method shown, the receiving hole 111 penetrating the first wiring layer 101, the second wiring layer 102 and the third wiring layer 103 is formed by a one-time molding process, which reduces the process flow and reduces the cost compared with multiple molding processes.

[0124] Understandably, Figure 6 and Figure 7 The substrate 20 shown may also be Figure 8a The relevant preparation method is prepared and will not be described in detail here.

[0125] Connect the substrate 20 Figure 1c In the embodiment of the first bare chip 16 and the second bare chip 17 shown, the area where the receiving holes are distributed on the substrate 20 is small, which is conducive to improving the strength of the substrate 20. Even if the circuit design between the first bare chip 16 and the second bare chip 17 is more complicated, the supporting performance of the substrate 20 for the first bare chip 16 and the second bare chip 17 can be well guaranteed.

[0126] Accordingly, the substrate 20 is connected Figure 1e In the embodiment of the middle chip 18 , the provision of the substrate 20 can reduce the volume of the packaging shell 19 . Even if the circuit design between the multiple chips 18 is more complicated, the substrate 20 can also provide guarantee for the supporting performance of the chip 18 .

[0127] Connect the substrate 20 Figure 1d In the embodiment of the chip package assembly 14 , even if the circuit design between the chip package assemblies 14 is relatively complex, the substrate 20 can still provide guarantee for the supporting performance of the chip package assembly 14 .

[0128] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application shall be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A substrate, characterized in that: The substrate comprises: A multi-layer wiring layer, wherein the plurality of wiring layers are stacked; A multi-layer dielectric layer, wherein one dielectric layer is disposed between each two adjacent wiring layers; and An interconnection component, the interconnection component includes a receiving hole and a plurality of conductive members located in the receiving hole; the receiving hole penetrates multiple layers of the wiring layers and multiple layers of the dielectric layers, the opposite ends of one conductive member are electrically connected to two layers of the wiring layers respectively, and the two wiring layers connected to at least two of the multiple conductive members are not completely the same.

2. The substrate according to claim 1, characterized in that The multiple conductive members include a first conductive member, and the two wiring layers connected to the two ends of the first conductive member are respectively a first wiring layer and a second wiring layer, the first wiring layer includes a plurality of first metal wires arranged at circumferential intervals along the accommodating hole, and the second wiring layer includes a plurality of second metal wires arranged at circumferential intervals along the accommodating hole; the first conductive member includes a plurality of conductive parts arranged at circumferential intervals along the accommodating hole; the plurality of first metal wires and the plurality of second metal wires are electrically connected one-to-one through the plurality of conductive parts.

3. The substrate according to claim 2, characterized in that A difference between a thickness of the first metal wire and a thickness of the conductive portion is less than or equal to 10 μm.

4. The substrate according to claim 2 or 3, characterized in that The first metal wire extends in a direction away from the receiving hole, and a difference between a size of the conductive portion along a circumferential direction of the receiving hole and a line width of the first metal wire is less than or equal to 50 μm.

5. The substrate according to any one of claims 2 to 4, characterized in that: The first metal wire extends in a direction away from the receiving hole, and a size of the conductive portion along the circumference of the receiving hole is equal to a line width of the first metal wire; And / or, a dimension of the conductive portion along a radial direction of the accommodating hole is equal to a thickness of the first metal wire.

6. The substrate according to any one of claims 2 to 5, characterized in that: The interconnection assembly further includes a first insulating member, which is disposed in the receiving hole; along the circumference of the receiving hole, the first insulating member is disposed between any two adjacent conductive parts.

7. The substrate according to any one of claims 1 to 6, characterized in that: The interconnection assembly further includes a second insulating member, which is disposed between any two adjacent conductive members.

8. The substrate according to any one of claims 1 to 7, characterized in that: The plurality of conductive members are arranged at intervals along the extending direction of the accommodating hole.

9. The substrate according to claim 8, characterized in that The conductive member covers the inner wall of the accommodating hole along the circumferential direction.

10. The substrate according to any one of claims 1 to 7, characterized in that: The projections of at least two of the conductive members overlap on the reference plane, the reference plane is parallel to the extension direction of the accommodating hole, and the plurality of conductive members are arranged at intervals along the circumference of the accommodating hole.

11. The substrate according to any one of claims 1 to 10, characterized in that: The substrate further includes a connection portion electrically connected to the outermost wiring layer among the plurality of wiring layers.

12. The substrate according to any one of claims 1 to 11, characterized in that: An insulating layer covers a side of the outermost wiring layer among the multiple wiring layers away from the dielectric layer.

13. An electronic device, characterized in that: The electronic device comprises: Components; and The substrate according to any one of claims 1 to 12, wherein the component is electrically connected to the substrate.

14. The electronic device according to claim 13, characterized in that: The substrate is a packaging substrate, and the components include at least one bare chip.

15. The electronic device according to claim 13, characterized in that: The substrate is a printed circuit board, and the components are a chip packaging structure formed by packaging a packaging substrate and at least one bare chip.

16. An electronic device, characterized in that: The electronic device comprises: Housing; and The electronic device according to any one of claims 13 to 15, wherein the electronic device is located in the housing.

17. A method for preparing a substrate, characterized in that: include: Forming multiple wiring layers and multiple dielectric layers, wherein the multiple wiring layers are stacked and a dielectric layer is disposed between every two adjacent wiring layers; Forming a receiving hole penetrating through the multiple wiring layers and the multiple dielectric layers; forming a conductive layer in the receiving hole; The conductive layer is etched to form a plurality of conductive members; two opposite ends of one of the conductive members are electrically connected to two wiring layers respectively, and the two wiring layers connected to at least two of the plurality of conductive members are not completely the same.

18. The method for preparing a substrate according to claim 17, characterized in that: The plurality of conductive members include a first conductive member, and the two wiring layers connected to the two ends of the first conductive member are respectively a first wiring layer and a second wiring layer; The etching of the conductive layer to form a plurality of conductive members comprises: etching the conductive layer to form a plurality of conductive portions spaced apart along the circumference of the receiving hole to obtain the first conductive member; Among them, the first wiring layer includes a plurality of first metal wires arranged at intervals along the circumference of the accommodating hole, and the second wiring layer includes a plurality of second metal wires arranged at intervals along the circumference of the accommodating hole; the plurality of first metal wires and the plurality of second metal wires are electrically connected one-to-one through the plurality of conductive parts.

19. A substrate, characterized in that: The substrate is prepared by the method for preparing a substrate according to claim 17 or 18.

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