A MTP device and preparation method thereof

Abstract

The present invention provides an MTP device and a preparation method thereof. The present invention replaces a MOS capacitor composed of a substrate, a gate oxide layer and a floating gate in a traditional MTP device with a capacitor composed of a floating gate, an insulating layer and a conductive plug, so as to control the potential of the floating gate through capacitive coupling between the floating gate and the conductive plug, thereby completing programming and erasing operations in a floating gate transistor region. In the MTP device of the present invention, the capacitor is completely isolated from the substrate, and will not be affected by the substrate potential during programming and erasing operations, thereby effectively expanding the operating range of the MTP device, that is, improving the programming efficiency and erasing efficiency of the MTP device, and at the same time achieving higher capacitive coupling efficiency in a smaller area, which is beneficial to reducing the chip area.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to an MTP device and a preparation method thereof. Background Art

[0002] Generally, a memory that does not lose data after power failure and can be programmed multiple times is called a multi-time programmable memory (MTP). MTP devices are widely used in personal computers, electronic devices, mobile storage and other fields. Conventional MTP devices that are compatible with CMOS processes usually use a single-layer floating gate structure, such as Figure 1-Figure 2 As shown, the MTP device is composed of a floating gate transistor 1, a selection transistor 2 and a MOS capacitor 3. The MOS capacitor 3 is composed of a substrate at the P well PW, an insulating layer and a floating gate FG, wherein the substrate at the P well PW serves as the CG electrode terminal 31 (i.e., the lower electrode) of the MOS capacitor 3, and the floating gate FG serves as the FG electrode terminal (i.e., the upper electrode) of the MOS capacitor 3. The operating principle of the MTP device is: by applying pressure to the CG electrode terminal 31 of the MOS capacitor, the potential of the FG electrode terminal is controlled by the capacitive coupling effect; the floating gate transistor 1 is programmed by using the HCI (hot electron injection effect, HotCarrier Injection) effect, and erased by using FN tunneling; the storage state is determined by the selection transistor.

[0003] In order to increase the programming efficiency and the erasing efficiency, it is usually necessary to increase the voltage of the CG electrode terminal 31 of the MOS capacitor or to increase the area of ​​the MOS capacitor. Among them, in the scheme of increasing the voltage of the CG electrode terminal 31 of the MOS capacitor, the voltage of the CG electrode terminal 31 is affected by the reverse-biased breakdown voltage BVdss of the junction formed by the deep N-well DNW in the MOS capacitor 3 and the P-type substrate Sub and the P-well PW, so that the voltage applied to the CG electrode terminal 31 needs to be less than the breakdown voltage BVdss, thereby limiting the operable range of the voltage of the CG electrode terminal 31. In the scheme of increasing the area of ​​the MOS capacitor, although the increase in the area of ​​the MOS capacitor can enhance the coupling efficiency of the MOS capacitor, it seriously increases the overall area of ​​the chip.

[0004] Therefore, how to effectively improve the programming efficiency and erasing efficiency of MTP devices remains an urgent issue to be solved. Summary of the invention

[0005] The object of the present invention is to provide an MTP device and a preparation method thereof, which can improve the programming efficiency and erasing efficiency of the MTP device.

[0006] In order to solve the above technical problems, the present invention provides an MTP device, including a floating gate transistor, a selection transistor and a capacitor formed on a substrate, wherein a groove is provided in the substrate, and the floating gate of the floating gate transistor serves as a lower electrode of the capacitor. The capacitor also includes an insulating layer and a conductive plug, wherein a portion of the floating gate covers an inner wall of the groove, the insulating layer covers the floating gate in the groove, and the conductive plug fills the groove from the inner side of the insulating layer.

[0007] Optionally, the substrate includes a base, the base has an active region, a first well region and a second well region are arranged in the base of the active region, the first well region is located below the second well region, and the first well region and the second well region are arranged in contact, and the first well region is arranged in the base;

[0008] A first shallow trench isolation structure and a second shallow trench isolation structure are arranged in the second well region, the first shallow trench isolation structure is arranged around the second well region, the second shallow trench isolation structure is arranged at intervals on the inner side of the first shallow trench isolation structure, and the first shallow trench isolation structure and the second shallow trench isolation structure separate the substrate of the active region into a first area and a second area.

[0009] Furthermore, the groove is arranged in the first shallow trench isolation structure, and the groove is spaced apart from the first region.

[0010] Furthermore, the depth of the groove is more than half of the height of the first shallow trench isolation structure.

[0011] Furthermore, the depth of the groove is 2 / 3 to 3 / 4 times the height of the first shallow trench isolation structure.

[0012] On the other hand, the present invention also provides a method for preparing an MTP device, comprising the following steps:

[0013] Providing a substrate, wherein a groove is provided in the substrate;

[0014] A floating gate transistor, a selection transistor and a capacitor are formed on the substrate, wherein the floating gate of the floating gate transistor serves as a lower electrode of the capacitor, and the capacitor further includes an insulating layer and a conductive plug, a portion of the floating gate covers an inner wall of the groove, the insulating layer covers the floating gate in the groove, and the conductive plug fills the groove from the inner side of the insulating layer.

[0015] Optionally, the specific method of forming the groove is:

[0016] Providing a substrate, the substrate comprising a base, the base having an active region, a first well region and a second well region being arranged in the base of the active region, the first well region being located below the second well region, the first well region and the second well region being arranged in contact, and the first well region being arranged in the base;

[0017] A first shallow trench isolation structure and a second shallow trench isolation structure are provided in the second well region, the first shallow trench isolation structure is arranged around the second well region, the second shallow trench isolation structure is arranged at intervals inside the first shallow trench isolation structure, and the first shallow trench isolation structure and the second shallow trench isolation structure separate the substrate of the active region into a first region and a second region;

[0018] forming a sacrificial layer on the second well region and the first shallow trench isolation structure, and then depositing a first hard mask layer on the sacrificial layer by a PECVD process;

[0019] Sequentially etching the first hard mask layer and the sacrificial layer to expose the first shallow trench isolation structure;

[0020] The first shallow trench isolation structure is etched using the first hard mask layer and the sacrificial layer as masks to form the groove, and the first hard mask layer is removed.

[0021] Furthermore, the depth of the groove is more than half of the height of the first shallow trench isolation structure.

[0022] Furthermore, the depth of the groove is 2 / 3 to 3 / 4 times the height of the first shallow trench isolation structure.

[0023] Furthermore, the specific method of forming the capacitor is:

[0024] The sacrificial layer is removed, and a gate oxide film layer and a polysilicon film layer are sequentially formed, wherein the gate oxide film layer covers the surface of the substrate and the inner wall of the groove, and the polysilicon film layer is located on the gate oxide film layer;

[0025] forming a filling material layer in the groove;

[0026] Etching the polysilicon film layer to form a floating gate and a polysilicon gate, and forming a first gate oxide layer and a second gate oxide layer, wherein the first gate oxide layer is located below the floating gate, and the second gate oxide layer is located below the polysilicon gate;

[0027] A first sidewall is formed outside the floating gate, and a second sidewall is formed outside the polysilicon gate, wherein the first sidewall is arranged on the sidewall of the floating gate and the sidewall of the first gate oxide layer, and the second sidewall is arranged on the sidewall of the polysilicon gate and the sidewall of the second gate oxide layer, thereby forming a first gate structure and a second gate structure, wherein the first gate structure includes a first gate oxide layer, a floating gate and a first sidewall, and the second gate structure includes a second gate oxide layer, a polysilicon gate and a second sidewall;

[0028] Forming a P-type doping region in a first region on both sides of the first gate structure and the second gate structure, and forming an N-type doping region in the second region to form a floating gate transistor and a selection transistor;

[0029] removing the filling material layer;

[0030] forming a SAB layer on the floating gate, wherein the SAB layer at least covers the floating gate at the groove;

[0031] Sequentially forming a dielectric layer on the substrate, wherein the dielectric layer covers the first gate structure and the second gate structure;

[0032] sequentially forming a dielectric layer on the substrate by a deposition process, wherein the dielectric layer covers the first gate structure and the second gate structure;

[0033] Etching the dielectric layer and a partial thickness of the SAB layer to form an opening, wherein the opening is located above the groove;

[0034] A conductive plug is formed, the conductive plug filling the opening.

[0035] Compared with the prior art, the present invention has the following unexpected technical effects:

[0036] The present invention provides an MTP device and a preparation method thereof. The MTP device comprises a floating gate transistor, a selection transistor and a capacitor formed on a substrate. A groove is provided in the substrate. The floating gate of the floating gate transistor serves as a lower electrode of the capacitor. The capacitor further comprises an insulating layer and a conductive plug. A part of the floating gate covers the inner wall of the groove, the insulating layer covers the floating gate in the groove, and the conductive plug fills the groove from the inner side of the insulating layer. The present invention replaces the MOS capacitor composed of a substrate, a gate oxide layer and a floating gate in a traditional MTP device with a capacitor located on the substrate composed of a floating gate, an insulating layer and a conductive plug, so as to control the potential of the floating gate through capacitive coupling between the floating gate and the conductive plug, thereby completing programming and erasing operations in the floating gate transistor region. In the MTP device of the present invention, the capacitor is completely isolated from the substrate and will not be affected by the substrate potential during programming and erasing operations, thereby effectively extending the operating range of the MTP device (adjusting the lower electrode voltage of the capacitor from not exceeding the breakdown voltage BVdss of the deep N-well DNW and the P-type substrate Sub and the P-well PW respectively to not exceeding the breakdown voltage of the first gate oxide layer), that is, improving the programming efficiency and erasing efficiency of the MTP device, while achieving higher capacitive coupling efficiency in a smaller area, which is conducive to reducing the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic top view of an MTP device.

[0038] Figure 2 for Figure 1 Cross-sectional view along MM'.

[0039] Figure 3 A schematic top view of an MTP device provided by an embodiment of the present invention.

[0040] Figure 4 for Figure 3 Cross-sectional view along AA'.

[0041] Figure 5 for Figure 3 Cross-sectional view along BB'.

[0042] Figure 6 for Figure 3 Cross-sectional view along CC'.

[0043] Figure 7 A cross-sectional view of a substrate along line BB' provided by an embodiment of the present invention.

[0044] Figure 8 The cross-sectional view is a diagram showing a first patterned photoresist layer after being formed according to an embodiment of the present invention.

[0045] Fig. 9 It is a cross-sectional view after forming a groove according to an embodiment of the present invention.

[0046] Fig.10 It is a cross-sectional view after forming a filling material layer according to an embodiment of the present invention.

[0047] Fig.11 The cross-sectional view is a diagram showing a second patterned photoresist layer after being formed according to an embodiment of the present invention.

[0048] Fig.12 FIG. 1 is a cross-sectional view of a floating gate after forming the floating gate according to an embodiment of the present invention.

[0049] Fig.13 It is a cross-sectional view after forming a first gate structure and a second gate structure according to an embodiment of the present invention.

[0050] Fig.14 FIG. 4 is a cross-sectional view of a SAB layer after forming the SAB layer according to an embodiment of the present invention.

[0051] Fig.15 It is a cross-sectional view after forming a patterned third photoresist layer according to one embodiment of the present invention.

[0052] Fig.16 It is a cross-sectional view after forming a hole in one embodiment of the present invention.

[0053] Description of reference numerals:

[0054] Figure 1-Figure 2 Middle: 1- floating gate transistor; 2- selection transistor; 3- MOS capacitor; 31- CG electrode terminal;

[0055] Figure 3-Figure 16 middle:

[0056] 100-substrate; 101-base; 102-first well region; 103-second well region; 1041-first shallow trench isolation structure; 1042-second shallow trench isolation structure; 105-P-type doping region; 106-N-type doping region; 107-groove; 111-sacrificial layer; 112'-gate oxide film layer; 112-first gate oxide layer; 113-second gate oxide layer; 120-first hard mask layer; 131-first photoresist layer; 132-second photoresist layer; 133-third photoresist layer; 140-polysilicon film layer; 141-floating gate; 142-polysilicon gate; 150-filling material layer; 161-first sidewall; 162-second sidewall; 171-silicon nitride layer; 172-silicon oxide layer; 181-dielectric layer; 182-masking layer; 190-conductive plug; 200-floating gate transistor; 300-select transistor; 400-capacitor. DETAILED DESCRIPTION

[0057] A MTP device and a method for preparing the same of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art may modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.

[0058] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.

[0059] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0060] like Figure 3-Figure 6 As shown, this embodiment provides an MTP device, including a floating gate transistor 200, a selection transistor 300 and a capacitor 400 formed on a substrate, wherein a groove is provided in the substrate, and a floating gate 141 of the floating gate transistor 200 serves as a lower electrode of the capacitor 400, and the capacitor 400 further includes an insulating layer and a conductive plug 190, wherein a portion of the floating gate 141 covers an inner wall of the groove 107, the insulating layer covers the floating gate 141 in the groove 107, and the conductive plug 190 fills the groove 107 from the inner side of the insulating layer.

[0061] In this embodiment, the MOS capacitor 400 formed by the substrate 100, the gate oxide layer and the floating gate 141 is replaced by a capacitor 400 located on the substrate 100 formed by the floating gate 141, the insulating layer and the conductive plug 190, so as to control the potential of the floating gate 141 through the coupling of the capacitor 400 between the floating gate 141 and the conductive plug 190, thereby completing the programming and erasing operations in the floating gate transistor 200 region. In the MTP device of this embodiment, the capacitor 400 is completely isolated from the substrate 100, and will not be affected by the potential of the substrate 100 during programming and erasing operations, thereby effectively expanding the operating range of the MTP device (adjusting the lower electrode voltage of the capacitor 400 from not exceeding the breakdown voltage BVdss of the deep N-well DNW and the P-type substrate 100Sub and the P-well PW respectively to not exceeding the breakdown voltage of the first gate oxide layer 112), that is, improving the programming efficiency and erasing efficiency of the MTP device, and at the same time achieving a higher coupling efficiency of the capacitor 400 in a smaller area, which is conducive to reducing the chip area.

[0062] In detail, the MTP device includes a substrate 100, and the substrate 100 includes a base 101, and the base 101 is, for example, a P-type silicon base 101. The base 101 has an active region, and a first well region 102 and a second well region 103 are arranged in the base 101 of the active region, the first well region 102 is located below the second well region 103, and the first well region 102 and the second well region 103 are arranged in contact, the first well region 102 is arranged in the base 101, and the second well region 103 extends from the surface of the substrate 100 into the substrate 100. The doping type of the first well region 102 and the second well region 103 is the same, and both are N-type doping, and the ion doping concentration of the first well region 102 is less than the ion doping concentration of the second well region 103.

[0063] A shallow trench isolation structure is provided in the second well region 103, and the depth of the shallow trench isolation structure is less than the depth of the second well region 103. The shallow trench isolation structure defines the active region. In the present embodiment, the shallow trench isolation structure includes a first shallow trench isolation structure 1041 and a second shallow trench isolation structure 1042, the first shallow trench isolation structure 1041 is arranged around the second well region 103, the second shallow trench isolation structure 1042 is arranged in the second well region 103, and is arranged at intervals on the inner side of the first shallow trench isolation structure 1041, the first isolation structure and the second isolation structure separate the substrate 101 of the active region into a first region and a second region, and further, the first region and the second region are arranged at intervals along the first direction through the second shallow trench isolation structure 1042. Wherein, the first region and the second region are both rectangular. The materials of the first shallow trench isolation structure 1041 and the second shallow trench isolation structure 1042 are both silicon oxide.

[0064] A groove 107 is also provided in the first trench isolation structure, and the groove 107 is extended along the second direction, and the groove 107 is spaced apart from the first region, wherein the first direction and the second direction are perpendicular to each other. A first gate structure and a second gate structure are spaced apart on the substrate 100, and the first gate structure and the second gate structure are parallelly provided along the second direction, and both the first gate structure and the second gate structure cover a part of the first region, and both the first gate structure and the second gate structure are arranged across the first region (i.e., in the second direction, both the first gate structure and the second gate structure extend into the first shallow trench isolation structure 1041 at both ends of the first region).

[0065] Wherein, in the first direction, the width of the first gate structure above the first region is less than or equal to the width of the first gate structure at the groove 107. The depth of the groove 107 is more than half of the height of the first shallow trench isolation structure 1041. Preferably, the depth of the groove 107 is 2 / 3 times to 3 / 4 times the height of the first shallow trench isolation structure 1041, for example, the depth of the groove 107 is 2 / 3 times, 3 / 4 times, etc., of the height of the first shallow trench isolation structure 1041.

[0066] The first gate structure includes a first gate oxide layer 112, a floating gate 141, and a first sidewall 161 arranged on the sidewalls of the first gate oxide layer 112 and the sidewalls of the floating gate 141. In the groove 107, the first gate oxide layer 112 covers the bottom wall and the sidewalls of the groove 107, and also covers the surface of the first shallow trench isolation structure 1041 near the groove 107. The floating gate 141 is stacked on the first gate oxide layer 112, and the first gate oxide layer 112 and the floating gate 141 have the same shape and size. Therefore, in the first direction and at the groove 107, the width of the floating gate 141 is greater than the width of the groove 107. The material of the floating gate 141 is polysilicon material.

[0067] The second gate structure includes a second gate oxide layer 113, a polysilicon gate 142, and a second sidewall 162 arranged on the sidewalls of the second gate oxide layer 113 and the sidewalls of the polysilicon gate 142. A P-type doping region 105 is arranged in the first region on both sides of the first gate structure and the second gate structure, and the first gate structure and the second gate structure share the same P-type doping region 105, and an N-type doping region 106 is arranged in the second region. The N-type doping region 106, the first gate structure, and the P-type doping regions 105 on both sides of the first gate structure together constitute a floating gate transistor 200. The P-type doping regions 105 on both sides of the second gate structure and the second gate structure together constitute a selection transistor 300.

[0068] An insulating layer is further disposed on the floating gate 141 , and the insulating layer covers the floating gate 141 at the groove 107 , so that the insulating layer covers the floating gate 141 in the groove 107 and the floating gate 141 above the substrate 100 at the groove 107 .

[0069] A dielectric layer 181 is formed on the substrate 100, and the dielectric layer 181 covers the first gate structure and the second gate structure, and an opening is provided in the dielectric layer, the opening is located above the groove 107, and the opening exposes the insulating layer, the groove width of the opening is less than or equal to the groove width of the groove 107, and the central axis of the opening overlaps with the central axis of the groove 107, so that the width of the opening in the first direction is less than the width of the floating gate 141 in the first direction. The material of the insulating layer can be conventional insulating materials such as silicon nitride or silicon oxide. In this embodiment, the material of the insulating layer is silicon nitride.

[0070] The opening is provided with a conductive plug 190, which fills the opening and covers the surface of the insulating layer. The conductive plug 190 includes a first metal film layer, a metal compound layer, and a second metal filling layer from bottom to top, wherein the material of the first metal film layer is titanium, the material of the metal compound layer is titanium nitride, and the material of the second metal filling layer is tungsten. The conductive plug 190, the insulating layer, and the floating gate 141 constitute the capacitor 400 of the MTP device.

[0071] This embodiment also provides a method for preparing an MTP device, comprising the following steps:

[0072] Step S1: providing a substrate, wherein a groove is provided in the substrate;

[0073] Step S2: forming a floating gate transistor, a selection transistor and a capacitor on the substrate, wherein the floating gate of the floating gate transistor serves as the lower electrode of the capacitor, the capacitor further includes an insulating layer and a conductive plug, a portion of the floating gate covers the inner wall of the groove, the insulating layer covers the floating gate in the groove, and the conductive plug fills the groove from the inner side of the insulating layer.

[0074] The following combination Figure 3-Figure 16 A method for preparing an MTP device provided in this embodiment is described in detail.

[0075] See also Figure 7-Figure 9 First, step S1 is performed to provide a substrate 100 , in which a groove 107 is provided.

[0076] This step specifically includes:

[0077] like Figure 7 As shown, a substrate 100 is first provided, and the substrate 100 includes a base 101, and the base 101 is, for example, a P-type silicon base 101. The base 101 has an active region, and a first well region 102 and a second well region 103 are arranged in the base 101 of the active region, the first well region 102 is located below the second well region 103, and the first well region 102 and the second well region 103 are arranged in contact, the first well region 102 is arranged in the base 101, and the second well region 103 extends from the surface of the substrate 100 into the substrate 100. The doping type of the first well region 102 and the second well region 103 is the same, and both are N-type doping, and the ion doping concentration of the first well region 102 is less than the ion doping concentration of the second well region 103.

[0078] A shallow trench isolation structure is provided in the second well region 103, and the depth of the shallow trench isolation structure is less than the depth of the second well region 103. The shallow trench isolation structure defines the active region. In the present embodiment, the shallow trench isolation structure includes a first shallow trench isolation structure 1041 and a second shallow trench isolation structure 1042, the first shallow trench isolation structure 1041 is arranged around the second well region 103, the second shallow trench isolation structure 1042 is arranged in the second well region 103, and is arranged at intervals on the inner side of the first shallow trench isolation structure 1041, the first isolation structure and the second isolation structure separate the substrate 101 of the active region into a first region and a second region, and further, the first region and the second region are arranged at intervals along the first direction through the second shallow trench isolation structure 1042. Wherein, the first region and the second region are both rectangular. The materials of the first shallow trench isolation structure 1041 and the second shallow trench isolation structure 1042 are both silicon oxide.

[0079] like Figure 8 As shown, a sacrificial layer 111 is formed on the second well region 103 and the shallow trench isolation structure by a thermal oxidation growth process, and then a first hard mask layer 120 is deposited on the sacrificial layer 111 by a PECVD process. The material of the first hard mask layer 120 is silicon nitride, and when forming the first hard mask layer 120, the ratio of silane, ammonia and carrier gas (such as nitrogen) is adjusted to form Si nitride. 3 N 4 , so as to reduce the stress of the silicon nitride film and minimize the influence of the silicon nitride stress on the substrate 100. The thickness of the first hard mask layer 120 is about 330Å; the material of the sacrificial layer 111 is silicon oxide, and the thickness of the sacrificial layer 111 is about 150Å.

[0080] Next, a patterned first photoresist layer 131 is formed on the first hard mask layer 120 by a photolithography process, wherein the patterned first photoresist layer 131 defines the shape of the groove 107 .

[0081] like Fig. 9 See also Figure 3 Then, using the patterned first photoresist layer 131 as a mask, the first hard mask layer 120 and the sacrificial layer 111 are sequentially etched through a dry etching process to expose the first shallow trench isolation structure 1041 and remove the first photoresist layer 131.

[0082] Next, the first shallow trench isolation structure 1041 is etched by a dry etching process using the first hard mask layer 120 and the sacrificial layer 111 as masks to form the groove 107. The groove 107 is extended along the second direction, and the groove 107 is spaced from the first region, wherein the first direction and the second direction are perpendicular to each other. The depth of the groove 107 is more than half of the height of the first shallow trench isolation structure 1041. Preferably, the depth of the groove 107 is 2 / 3 times to 3 / 4 times the height of the first shallow trench isolation structure 1041, for example, the depth of the groove 107 is 2 / 3 times, 3 / 4 times, etc., of the height of the first shallow trench isolation structure 1041.

[0083] Next, the first hard mask layer 120 is removed by a wet process to expose the sacrificial layer 111 outside the groove 107. The wet process uses an etching solution of phosphoric acid solution at a temperature of about 145 degrees, and the etching time is about 20 minutes.

[0084] like Figure 10-Figure 16 As shown, step S2 is then performed to form a floating gate transistor 200, a selection transistor 300 and a capacitor 400 on the substrate 100, wherein the floating gate 141 of the floating gate 141 transistor serves as a lower electrode of the capacitor 400, and the capacitor 400 also includes an insulating layer and a conductive plug 190, a portion of the floating gate 141 covers the inner wall of the groove 107, the insulating layer covers the floating gate 141 in the groove 107, and the conductive plug 190 fills the groove 107 from the inner side of the insulating layer.

[0085] This step specifically includes:

[0086] like Fig.10As shown, first, the surface of the substrate 100 is cleaned to remove the sacrificial layer 111. Then, a gate oxide film layer 112' with a dense structure and few interface defects is generated by an in-situ water vapor method, wherein the gate oxide film layer 112' covers the surface of the substrate 100 (i.e., the surface of the shallow trench isolation structure and the surface of the substrate 100 of the second well region 103), and covers the inner wall (bottom wall and side wall) of the groove 107. The thickness of the gate oxide film layer 112' is, for example, greater than 100 Å, for example, about 130 Å.

[0087] Next, a polysilicon film layer 140 is formed by a PECVD process, and the polysilicon film layer 140 is located on the gate oxide film layer 112'. The thickness of the polysilicon film layer 140 is greater than 2000 Å, for example, about 2600 Å.

[0088] Next, a filling material layer 150 is formed in the groove 107 by a HDP-CVD process, and the filling material layer 150 also covers the polysilicon film layer 140 outside the groove 107. The material of the filling material layer 150 is silicon oxide.

[0089] Next, the filling material layer 150 is planarized by a CMP process to expose the polysilicon film layer 140 outside the groove 107 .

[0090] like Fig.11 As shown, a patterned second photoresist layer 132 is formed on the polysilicon film layer 140 , and the patterned second photoresist layer 132 also covers the filling material layer 150 . The patterned second photoresist layer 132 defines the shapes of the floating gate 141 and the polysilicon gate 142 .

[0091] like Fig.12 See also Figure 4Then, the polysilicon film layer 140 is etched by dry etching process using the patterned second photoresist layer 132 as a mask to form a floating gate 141 and a polysilicon gate 142, and a first gate oxide layer 112 and a second gate oxide layer 113 are formed at the same time, wherein the first gate oxide layer 112 is located below the floating gate 141, and the second gate oxide layer 113 is located below the polysilicon gate 142. The floating gate 141 is stacked on the first gate oxide layer 112, and has the same structure and size. The first gate oxide layer 112 covers part of the first region, and also covers the inner wall of the groove 107 and the first shallow trench isolation structure 1041 near the outer side of the groove 107. At the same time, the first gate oxide layer 112 also extends in the second direction to the first shallow trench isolation structure 1041 at both ends of the first region. The polysilicon gate 142 is stacked on the second gate oxide layer 113, and has the same structure and size. The second gate oxide layer 113 covers a portion of the first region, the first gate oxide layer 112 and the second gate oxide layer 113 are arranged parallel and spaced apart along the second direction, and the second gate oxide layer 113 extends in the second direction to the first shallow trench isolation structure 1041 at both ends of the first region. The width of the floating gate 141 on the first region in the second direction is greater than the width of the floating gate 141 at the groove 107 in the second direction.

[0092] like Fig.13 As shown, a first sidewall 161 is formed outside the floating gate 141, and a second sidewall 162 is formed outside the polysilicon gate 142. The first sidewall 161 is arranged on the sidewall of the floating gate 141 and the sidewall of the first gate oxide layer 112, and the second sidewall 162 is arranged on the sidewall of the polysilicon gate 142 and the sidewall of the second gate oxide layer 113, thereby forming a first gate structure and a second gate structure. Wherein, the first sidewall 161 and the second sidewall 162 are both ONO structures. At this time, the filling material layer 150 can effectively prevent the sidewall material from remaining in the groove 107.

[0093] Next, a P-type doping region is formed in the first region on both sides of the first gate structure and the second gate structure, and an N-type doping region 106 is formed in the second region to form a floating gate transistor 200 and a selection transistor 300 .

[0094] Next, the filling material layer 150 is removed.

[0095] like Fig.14As shown, then, a SAB layer is formed on the floating gate 141, and a SAB layer is formed on the floating gate 141 and the polysilicon gate 142 where metal silicide is not required to be formed, and the SAB layer at least covers the floating gate 141 at the groove 107. The SAB layer includes a silicon nitride layer 171 and a silicon oxide layer 172 from bottom to top.

[0096] like Fig.15 As shown, next, a dielectric layer 181 is formed on the substrate 100 by a deposition process, and the dielectric layer 181 covers the first gate structure and the second gate structure, wherein the material of the dielectric layer 181 is BPTEOS or TEOS.

[0097] Next, a masking layer 182 is formed on the dielectric layer 181. The masking layer 182 may be a second hard mask layer or a second hard mask layer and a BARC layer from bottom to top. Next, a patterned third photoresist layer 133 is formed on the masking layer 182. The patterned third photoresist layer 133 defines the shape of the opening.

[0098] Next, the masking layer 182 is etched using the patterned third photoresist layer 133 as a mask to expose the dielectric layer 181 , and the remaining third photoresist layer 133 and the BARC layer are removed.

[0099] like Fig.16 As shown, then, using the second hard mask layer as a mask, the dielectric layer 181 and the silicon oxide layer 172 are etched to form an opening, wherein the opening is located above the groove 107, and the opening exposes the silicon nitride layer 171, and the groove width of the opening is less than or equal to the groove width of the groove 107, and the central axis of the opening overlaps with the central axis of the groove 107, so that the width of the opening in the second direction is less than the width of the floating gate 141 in the second direction.

[0100] like Figure 3-Figure 6 As shown, then, a first metal film layer, a metal compound layer and a second metal filling layer are sequentially formed on the inner wall of the opening by a PECVD deposition process to form a conductive plug 190, and the conductive plug 190 fills the opening and covers the silicon nitride layer 171. The material of the first metal film layer is titanium, the material of the metal compound layer is titanium nitride, and the material of the second metal filling layer is tungsten. The conductive plug 190, the insulating layer and the floating gate 141 constitute the capacitor 400 of the MTP device.

[0101] In summary, the present invention provides an MTP device and a preparation method thereof. The MTP device includes a floating gate transistor, a selection transistor and a capacitor formed on a substrate. A groove is provided in the substrate. The floating gate of the floating gate transistor serves as a lower electrode of the capacitor. The capacitor also includes an insulating layer and a conductive plug. A portion of the floating gate covers the inner wall of the groove, the insulating layer covers the floating gate in the groove, and the conductive plug fills the groove from the inside of the insulating layer. The present invention replaces the MOS capacitor composed of a substrate, a gate oxide layer and a floating gate in a traditional MTP device with a capacitor located on the substrate composed of a floating gate, an insulating layer and a conductive plug, so as to control the potential of the floating gate through capacitive coupling between the floating gate and the conductive plug, thereby completing programming and erasing operations in the floating gate transistor region. In the MTP device of the present invention, the capacitor is completely isolated from the substrate and will not be affected by the substrate potential during programming and erasing operations, thereby effectively extending the operating range of the MTP device (adjusting the lower electrode voltage of the capacitor from not exceeding the breakdown voltage BVdss of the deep N-well DNW and the P-type substrate Sub and the P-well PW respectively to not exceeding the breakdown voltage of the first gate oxide layer), that is, improving the programming efficiency and erasing efficiency of the MTP device, while achieving higher capacitive coupling efficiency in a smaller area, which is conducive to reducing the chip area.

[0102] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0103] It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. An MTP device, characterized in that: The invention comprises a floating gate transistor, a selection transistor and a capacitor formed on a substrate, wherein a groove is provided in the substrate, a floating gate of the floating gate transistor serves as a lower electrode of the capacitor, and the capacitor further comprises an insulating layer and a conductive plug, a part of the floating gate covers an inner wall of the groove, the insulating layer covers the floating gate in the groove, and the conductive plug fills the groove from the inner side of the insulating layer; The substrate comprises a base having an active region, a first well region and a second well region are arranged in the base of the active region, the first well region is located below the second well region, and the first well region and the second well region are arranged in contact, and the first well region is arranged in the base; A first shallow trench isolation structure and a second shallow trench isolation structure are arranged in the second well region, the first shallow trench isolation structure is arranged around the second well region, the second shallow trench isolation structure is arranged at intervals on the inner side of the first shallow trench isolation structure, and the first shallow trench isolation structure and the second shallow trench isolation structure separate the substrate of the active region into a first area and a second area.

2. The MTP device according to claim 1, characterized in that The groove is disposed in the first shallow trench isolation structure, and the groove is spaced apart from the first region.

3. The MTP device according to claim 1, characterized in that The depth of the groove is more than half of the height of the first shallow trench isolation structure.

4. The MTP device according to claim 3, characterized in that The depth of the groove is 2 / 3 to 3 / 4 times the height of the first shallow trench isolation structure.

5. A method for preparing an MTP device, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a base, the base having an active region, a first well region and a second well region being arranged in the base of the active region, the first well region being located below the second well region, the first well region and the second well region being arranged in contact, and the first well region being arranged in the base; A first shallow trench isolation structure and a second shallow trench isolation structure are provided in the second well region, the first shallow trench isolation structure is arranged around the second well region, the second shallow trench isolation structure is arranged at intervals inside the first shallow trench isolation structure, and the first shallow trench isolation structure and the second shallow trench isolation structure separate the substrate of the active region into a first region and a second region; forming a sacrificial layer on the second well region and the first shallow trench isolation structure, and then depositing a first hard mask layer on the sacrificial layer by a PECVD process; Sequentially etching the first hard mask layer and the sacrificial layer to expose the first shallow trench isolation structure; Using the first hard mask layer and the sacrificial layer as masks, etching the first shallow trench isolation structure to form a groove, and removing the first hard mask layer; A floating gate transistor, a selection transistor and a capacitor are formed on the substrate, wherein the floating gate of the floating gate transistor serves as a lower electrode of the capacitor, and the capacitor further includes an insulating layer and a conductive plug, a portion of the floating gate covers an inner wall of the groove, the insulating layer covers the floating gate in the groove, and the conductive plug fills the groove from the inner side of the insulating layer.

6. The preparation method according to claim 5, characterized in that: The depth of the groove is more than half of the height of the first shallow trench isolation structure.

7. The preparation method according to claim 6, characterized in that: The depth of the groove is 2 / 3 to 3 / 4 times the height of the first shallow trench isolation structure.

8. The preparation method according to claim 5, characterized in that: The specific method of forming a capacitor is: The sacrificial layer is removed, and a gate oxide film layer and a polysilicon film layer are sequentially formed, wherein the gate oxide film layer covers the surface of the substrate and the inner wall of the groove, and the polysilicon film layer is located on the gate oxide film layer; forming a filling material layer in the groove; Etching the polysilicon film layer to form a floating gate and a polysilicon gate, and forming a first gate oxide layer and a second gate oxide layer at the same time, wherein the first gate oxide layer is located under the floating gate, and the second gate oxide layer is located under the polysilicon gate; A first sidewall is formed outside the floating gate, and a second sidewall is formed outside the polysilicon gate, wherein the first sidewall is arranged on the sidewall of the floating gate and the sidewall of the first gate oxide layer, and the second sidewall is arranged on the sidewall of the polysilicon gate and the sidewall of the second gate oxide layer, thereby forming a first gate structure and a second gate structure, wherein the first gate structure includes a first gate oxide layer, a floating gate and a first sidewall, and the second gate structure includes a second gate oxide layer, a polysilicon gate and a second sidewall; Forming a P-type doping region in a first region on both sides of the first gate structure and the second gate structure, and forming an N-type doping region in the second region to form a floating gate transistor and a selection transistor; removing the filling material layer; forming a SAB layer on the floating gate, wherein the SAB layer at least covers the floating gate at the groove; Sequentially forming a dielectric layer on the substrate, wherein the dielectric layer covers the first gate structure and the second gate structure; sequentially forming a dielectric layer on the substrate by a deposition process, wherein the dielectric layer covers the first gate structure and the second gate structure; Etching the dielectric layer and a partial thickness of the SAB layer to form an opening, wherein the opening is located above the groove; A conductive plug is formed, the conductive plug filling the opening.

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