Edge Ai chip multi-layer storage unit vertical interconnection packaging method and device

Abstract

The present invention relates to a vertical interconnection packaging method and device for multi-layer storage units of edge AI chips. The method comprises the following steps: first, obtaining the initial packaging parameters of the multi-layer storage units of the edge AI chip, and ensuring that the packaging parameters contain physical properties related to vertical interconnection. Subsequently, by constructing a vertical interconnection model of the multi-layer storage unit, combined with the packaging parameters of each storage unit, a connection structure between the layers is generated. Next, based on the generated connection structure, the conductive structure between the storage units is partitioned to obtain a plurality of independent transmission channels. Then, an automatic wiring algorithm is used to optimize the signal layout of these transmission channels to determine the layout mode of the signal in each route, and the packaging parameters are adjusted according to the layout mode, and finally the vertical interconnection packaging of the multi-layer storage unit of the edge AI chip is completed. This invention not only improves the packaging accuracy, but also effectively enhances the stability and anti-interference performance of signal transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a method and device for vertically interconnecting multi-layer storage units of an edge Ai chip. Background Art

[0002] Edge computing, as a way to achieve data processing and intelligent decision-making on the terminal side, has received widespread attention in recent years. In particular, with the rapid increase in the number of IoT devices and smart terminals, more and more data is generated and processed at the edge, and the traditional centralized data processing method has been difficult to meet the needs of real-time and efficiency. Therefore, edge AI chips have become the key to solving this problem. By processing data locally and reducing dependence on the cloud, it not only significantly reduces the delay of data transmission, but also improves the level of privacy protection. However, with the increasing complexity of data, the interconnect packaging technology of existing edge AI chip storage units faces challenges in terms of precision and accuracy. This limitation directly affects the efficiency and effectiveness of data processing.

[0003] Most current edge AI chips use a multi-layer storage unit design. Although this design improves the parallelism of data processing to a certain extent, due to the complexity of the interconnection between the multi-layer structures, data transmission between storage units is often affected by significant latency and signal integrity loss. In high-frequency data interaction scenarios, especially when multi-layer structures frequently exchange data, signal attenuation and interference problems in transmission become particularly prominent, resulting in an increase in bit error rate and a significant decrease in data processing accuracy.

[0004] Specifically, in the vertical interconnection process of multi-layer storage units in existing edge AI chips, due to the complex packaging structure between layers, there is a large delay when the signal is transmitted between different layers, and the signal integrity is often damaged. At present, there is no effective solution to this problem. Summary of the invention

[0005] The main purpose of the present invention is to provide a vertical interconnect packaging method and device for edge Ai chip multi-layer storage units to solve the signal attenuation and interference problems during the transmission of high-frequency data interaction.

[0006] To achieve the above-mentioned purpose, the present invention provides a vertical interconnection packaging method for multi-layer storage units of an edge AI chip, comprising the following steps: obtaining initial packaging parameters of each storage unit in the multi-layer storage structure of the edge AI chip, wherein the packaging parameters at least include: physical property parameters related to vertical interconnection; adopting the vertical interconnection model of the multi-layer storage units of the edge AI chip, and combining the packaging parameters of each storage unit to generate each layer connection structure in the multi-layer storage structure of the edge AI chip; based on the each layer connection structure in the multi-layer storage structure of the edge AI chip, partitioning the conduction structure between the multi-layer storage units to obtain multiple independent transmission channels; using an automatic wiring algorithm to perform layout optimization processing on multiple transmission channels of the multi-layer storage structure to determine the layout mode of the signal in the route; based on the layout mode of the signal in the route, adjusting the initial packaging parameters to obtain the final packaging parameters, and then using the final packaging parameters to perform vertical interconnection packaging on the multi-layer storage units of the edge AI chip.

[0007] The present invention also provides a vertical interconnection packaging device for multi-layer storage units of an edge AI chip, comprising: an acquisition unit, used to acquire initial packaging parameters of each storage unit in the multi-layer storage structure of the edge AI chip, wherein the packaging parameters include at least: physical property parameters related to vertical interconnection; a generation unit, used to adopt the vertical interconnection of the multi-layer storage units of the edge AI chip to construct a model, and generate each layer of connection structure in the multi-layer storage structure of the edge AI chip in combination with the packaging parameters of each storage unit; a division unit, used to partition and divide the conduction structure between the multi-layer storage units based on the connection structure of each layer in the multi-layer storage structure of the edge AI chip to obtain multiple independent transmission channels; a determination unit, used to use an automatic wiring algorithm to perform layout optimization processing on multiple transmission channels of the multi-layer storage structure, and determine the layout method of the signal in the route; a packaging unit, used to adjust the initial packaging parameters based on the layout method of the signal in the route to obtain the final packaging parameters, and then use the final packaging parameters to perform vertical interconnection packaging on the multi-layer storage units of the edge AI chip.

[0008] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0009] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0010] The present invention provides a method and device for vertically interconnecting packaging of multi-layer storage units of edge Ai chips, which realizes high efficiency and stability of signal transmission through the design of independent transmission channels, especially significantly reduces the signal attenuation and interference problems during transmission in high-frequency data interaction. Specifically, the method extracts the initial packaging parameters of each storage unit to obtain the physical property parameters related to the vertical interconnection of each layer of storage units, and then uses the constructed multi-layer storage unit vertical interconnection model to generate the connection structure between each layer. On this basis, the system adopts partitioning technology to divide the conductive structure in the multi-layer storage structure into multiple independent transmission channels, so that each channel can undertake the data transmission task separately, thereby effectively avoiding signal interference between different channels.

[0011] Specifically, the design of independent transmission channels effectively isolates the signal flow between different channels, and reduces the interaction complexity of vertical and horizontal channels in the multi-layer structure by dividing the transmission sub-areas and rationally configuring and optimizing the paths. This design not only improves the data transmission rate between multi-layer storage units, but also ensures the integrity of the signal and the accuracy of transmission in complex data interaction scenarios, thereby improving the overall performance and reliability of edge AI chips in real-time data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the steps of a vertical interconnect packaging method of a multi-layer storage unit of an edge Ai chip in one embodiment of the present invention;

[0013] Figure 2 It is a structural block diagram of a vertical interconnect packaging device of a multi-layer storage unit of an edge Ai chip in one embodiment of the present invention;

[0014] Figure 3 It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0015] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0017] Reference Figure 1 , an embodiment of the present invention provides a vertical interconnect packaging method of a multi-layer storage unit of an edge Ai chip, comprising:

[0018] S1, obtaining initial packaging parameters of each storage unit in the multi-layer storage structure of the edge AI chip, wherein the packaging parameters at least include: physical property parameters related to vertical interconnection;

[0019] S2, using the vertical interconnection model of the multi-layer storage unit of the edge AI chip, and combining the packaging parameters of each storage unit to generate the connection structure of each layer in the multi-layer storage structure of the edge AI chip;

[0020] S3, based on the connection structure of each layer in the multi-layer storage structure of the edge AI chip, partition the conduction structure between the multi-layer storage units to obtain multiple independent transmission channels;

[0021] S4, using an automatic routing algorithm to perform layout optimization processing on multiple transmission channels of the multi-layer storage structure to determine the layout mode of the signal in the route;

[0022] S5, based on the layout of the signal in the route, adjusting the initial packaging parameters to obtain final packaging parameters, and then using the final packaging parameters to vertically interconnect and package the multi-layer storage units of the edge AI chip.

[0023] To realize the vertical interconnect packaging method of the edge AI chip multi-layer storage unit of the present invention, it is necessary to fully understand and execute each step in sequence, and combine the relevant initial packaging parameters and automatic optimization algorithms to finally achieve an efficient and stable vertical interconnect packaging structure. The core of this packaging method is to analyze the independent parameters of each layer of storage unit in the multi-layer storage structure, reasonably divide the conduction structure, and use automatic wiring optimization in the precise transmission channel design to minimize the interference of transmission signals between different channels, thereby significantly improving the transmission quality of the signal and the reliability of the package.

[0024] In the first step of the method, S1, the system needs to first obtain the initial packaging parameters of each layer of memory cells. These packaging parameters are the basic data for the entire packaging process because they contain the physical properties required for vertical interconnection, such as on-resistance, dielectric constant, interlayer distance and other key properties. For example, assuming that a certain memory cell has a higher resistance characteristic, it should be appropriately adjusted in the subsequent wiring optimization to ensure that signal transmission is not obstructed. By accurately obtaining these initial parameters, the system can lay the foundation for subsequent model building and layout optimization.

[0025] In the next step S2, the system uses these initial packaging parameters to build a vertical interconnection model of multi-layer storage units of an edge AI chip. In this process, the packaging parameters of each layer of storage units will be integrated into the model to generate the connection structure of each layer. For example, suppose a chip contains a three-layer storage structure, and the storage units of each layer have different physical parameters. The system will map these packaging parameters to a three-dimensional coordinate system to establish a spatial relationship and connection model of the multi-layer structure. The construction of the model must not only consider the direct connection between layers, but also ensure the accuracy of the transmission nodes and cross-layer nodes of each layer in the physical space. This design is particularly conducive to the subsequent optimization of data transmission paths, because the model already includes the spatial relationship and node distribution between different levels.

[0026] After entering step S3, the system further partitions the conductive structure based on the multi-layer connection structure model constructed in S2 to obtain multiple independent transmission channels. This step is particularly critical because the divided independent transmission channels will serve as the main carrier of signal transmission and can effectively avoid signal interference between different layers. For example, using the hierarchical coordinate matching algorithm, vertical channels and horizontal channels can be identified and isolated, thereby dividing different conductive areas in the physical structure. Assuming that there are two vertical channels and one horizontal channel in a certain storage layer, the system will independently mark the coordinate points of these channels to ensure that each transmission channel remains independent in space. In addition, in order to further refine the division of the conductive area, the system will analyze the boundary features of the channel, determine the coordinate information and shape complexity of its boundary, and finally generate multiple non-overlapping transmission sub-areas as independent transmission channels. Such a channel division process can not only achieve spatial isolation of the channel, but also reduce the attenuation of the signal during high-frequency transmission.

[0027] After completing the division of the transmission channels, the system enters step S4, where it will perform layout optimization on these independent transmission channels and use an automatic routing algorithm to determine how the signal is laid out in each channel. At this point, the system will analyze the signal requirement parameters of each transmission channel, such as signal strength, signal frequency, required bandwidth, etc., to form a signal transmission requirement data set. On this basis, the path impedance value of each transmission channel is calculated. Assuming that the impedance value of a channel is too high, the layout will be redesigned through the automatic routing algorithm to optimize the signal transmission quality on the path. For example, the Dijkstra algorithm is used to select a shorter path with lower impedance to ensure maximum transmission efficiency. In addition, the automatic routing algorithm will also identify electromagnetic interference areas during layout optimization, and make detour adjustments to the signal path when necessary to reduce the impact of interference. For example, if an interference overlap area is found between two channels, the system will automatically adjust the path so that the signal bypasses the high interference area as much as possible to improve the integrity and stability of the signal.

[0028] Finally, in step S5, based on the signal path and layout method after layout optimization, the system will adjust the initial packaging parameters to obtain the final packaging parameters. These parameters include the optimized transmission channel configuration, such as the transmission path, impedance value, congestion parameters, etc. of each channel. For example, assuming that the impedance value of a transmission channel has reached the ideal state after adjustment, the system will apply this parameter to the final packaging. Finally, these adjusted packaging parameters are used for the vertical interconnection packaging of multi-layer storage units to ensure that the transmission nodes and paths of each layer of the structure meet the transmission requirements in actual applications.

[0029] Through the above steps, the present invention can efficiently realize the vertical interconnection packaging of multi-layer storage units of edge AI chips, which not only improves the accuracy and stability of signal transmission, but also solves the delay and interference problems of high-frequency data transmission in the prior art through reasonable transmission channel design and optimization, thereby improving the overall performance of the chip and the reliability of data processing.

[0030] In one example, a model is constructed by vertically interconnecting multiple layers of storage units of an edge AI chip, and the connection structures of each layer in the multi-layer storage structure of the edge AI chip are generated in combination with the packaging parameters of each storage unit, including: performing hierarchical extraction processing on the packaging parameters of each layer of storage units to obtain a hierarchical packaging parameter list; using a multi-layer structure calculation algorithm, in combination with the hierarchical packaging parameter list, mapping the packaging parameters of each layer of storage units to a three-dimensional space coordinate system to obtain a preliminary model framework of vertical interconnection, wherein the preliminary model framework of vertical interconnection is used to express the preliminary connection relationship between each layer; in the preliminary model framework, in combination with the packaging parameters of each layer, the transmission nodes that need to be vertically interconnected in each layer are determined, and all cross-layer transmission nodes are processed as a set to obtain a cross-layer transmission node set, and each node in the cross-layer transmission node set is annotated with hierarchical information and coordinate values; based on the cross-layer transmission node set, the preliminary connection path between the transmission nodes is determined, and based on the preliminary connection path between the transmission nodes, the connection structures of each layer in the multi-layer storage structure of the edge AI chip are constructed on the basis of the preliminary model framework.

[0031] In this example, the construction of a vertically interconnected packaging model for multi-layer storage units of edge AI chips involves several important steps, mainly focusing on the extraction of layered packaging parameters and the generation of a three-dimensional spatial model. First, the system extracts the packaging parameters of the multi-layer storage units in layers to form a complete list of layered packaging parameters. This list lists the independent packaging properties of each layer of storage units, including electrical performance parameters, physical dimensions, thermal resistance parameters, etc. These parameters directly affect the interconnection requirements and transmission characteristics between each layer of storage units and other layers. Through this layered processing, it is ensured that the packaging parameters of each layer can be independently extracted and analyzed, providing data support for the subsequent construction of the spatial model.

[0032] Next, the system uses a multi-layer structure calculation algorithm to integrate these layered packaging parameters into a three-dimensional spatial coordinate system to obtain a preliminary model framework of the multi-layer storage structure. This three-dimensional coordinate system can not only represent the spatial position of each layer of storage units, but also reflect their physical connection relationship. For example, in the three-dimensional model, the position of each layer of storage units will be accurately mapped to a specific coordinate point, so that the system can clearly see the vertical connection requirements between each layer. This preliminary model framework effectively describes the connection relationship between each layer, helping the system understand the spatial layout of each layer and the location of the connection points of adjacent layers.

[0033] In the preliminary model framework, the system further combines the encapsulation parameters of each layer to determine the vertically interconnected transmission nodes. Transmission nodes are the key points for data to flow between different layers. The system will extract the specific nodes that need to be vertically interconnected from the encapsulation parameters of each layer and mark these nodes as "transmission nodes". Subsequently, these transmission nodes in each layer are processed as a set to generate a cross-layer transmission node set. This set marks the hierarchical information and spatial coordinates of the transmission nodes to ensure that each node can be uniquely identified. For example, if there is a vertical transmission requirement between the first and third layers, the transmission node is marked with its hierarchical relationship and spatial coordinates in the set so that it can be clearly displayed in the model.

[0034] Based on the set of cross-layer transmission nodes, the system begins to build preliminary connection paths between nodes. This path is the basic channel connecting each layer of transmission nodes. The system will create a reasonable connection path based on the coordinates and hierarchical information of these transmission nodes. These paths ensure the smooth flow of data in the vertical direction. Finally, based on the preliminary model framework, the system builds the connection structure between layers based on these connection paths. This final multi-layer connection structure model can not only represent the transmission path of data between different layers, but also provide an accurate and clear three-dimensional spatial diagram for subsequent packaging steps, which is convenient for reference and adjustment in the actual packaging process.

[0035] Through the above steps, the system can achieve efficient vertical interconnect packaging between multi-layer storage units, so that data can be quickly transmitted in the multi-layer structure, reduce transmission delays, and effectively reduce the risk of signal interference.

[0036] In one example, based on the connection structures of each layer in the multi-layer storage structure of the edge AI chip, the conductive structure between the multi-layer storage units is partitioned to obtain multiple independent transmission channels, including: using a preset hierarchical coordinate matching algorithm to determine the vertical channels and horizontal channels of the connection structures of each layer, and based on the vertical channels and the horizontal channels, determining the conductive area range of each layer; performing boundary analysis on the conductive area range of each layer to determine the coordinate points and boundary features of each conductive area to obtain a conductive area boundary data set, wherein the boundary features characterize the complexity of the boundary shape; based on the conductive area boundary data set, performing channel area division on each of the conductive areas, and determining multiple non-overlapping transmission sub-areas as independent transmission channels.

[0037] In this example, the conductive structure is partitioned based on the connection structure of the multi-layer storage structure to create multiple independent transmission channels. The core of this process is to identify vertical and horizontal channels and to refine the conductive area of ​​each layer so that data can be transmitted efficiently and stably between layers.

[0038] First, through the preset hierarchical coordinate matching algorithm, the system analyzes the connection structure of each layer in the multi-layer storage structure and identifies the vertical channel and horizontal channel. The vertical channel usually refers to the connection path across multiple storage layers, which is used to transmit signals from one layer to another; while the horizontal channel is responsible for signal transmission in the same layer. By identifying these two channels, the system can clearly determine the position and direction of each conductive area in each layer.

[0039] After identifying the vertical and horizontal channels, the system determines the scope of the conductive area of ​​each layer based on the information of these channels. Specifically, the scope of the conductive area of ​​each layer is affected by the channel layout, thus forming a specific boundary. For example, the conductive area of ​​a certain layer may be formed by the intersection of multiple vertical channels and horizontal channels, and the system determines the boundary of the conductive area through the coordinate information of these channels.

[0040] Next, the boundary analysis is performed on the conductive area range of each layer to identify the coordinate points and boundary features of each conductive area. The boundary features here are used to characterize the shape complexity of the conductive area, such as whether it is a regular rectangle or contains complex polygonal boundaries. Through this boundary analysis, the system can generate a boundary data set for the conductive area, and the boundary information of each conductive area is clearly recorded to provide a reference for subsequent area division. For example, if a conductive area has a complex boundary (such as an asymmetric shape), the system will record its boundaries in detail to more accurately determine the transmission channel during the division process.

[0041] After obtaining the conductive area boundary data set, the system will divide the channel area of ​​each conductive area based on the data set, decomposing it into multiple non-overlapping transmission sub-areas. Each transmission sub-area is an independent transmission channel to ensure that the signals between different channels do not interfere with each other. Specifically, the system will refine the conductive area into several sub-areas based on boundary features to avoid channel overlap. For example, if the signal flow in a conductive area is large or the risk of signal interference is high, the system can divide the area into multiple smaller transmission sub-areas to form independent transmission paths to ensure signal integrity and transmission accuracy.

[0042] This partitioning process ultimately enables the design of multiple independent transmission channels, each of which has clear boundaries and coordinate information and can independently handle data transmission tasks. This multi-channel structure not only improves the efficiency of data transmission, but also reduces the risk of signal interference in high-frequency data interaction, ensuring the stable performance of edge AI chips under complex tasks.

[0043] In one example, a preset hierarchical coordinate matching algorithm is used to determine the vertical channels and horizontal channels of the connection structures of each layer, and based on the vertical channels and the horizontal channels, the conduction area range of each layer is determined, including: extracting the coordinate information of each channel from the connection structure data of each layer, wherein the coordinate information includes: the starting point and end point position coordinates of the horizontal channel and the vertical channel; converting the coordinate information of each channel into a multi-layer coordinate matrix, wherein the multi-layer coordinate matrix takes each layer as a unit, and the coordinate information of all connection channels is arranged in rows; based on the preset hierarchical coordinate matching algorithm, comparing the channel coordinates of different layers in the multi-layer matrix, determining a set of coordinate points with high overlap in the vertical direction, and obtaining a set of vertical channel positions; at the vertical channel positions, Based on the set of locations, an adjacency analysis is performed on the horizontal channels of each layer to determine the horizontal channels that have similar intersections or overlaps with the vertical channels in space, wherein the distance between two associated intersections in the similar intersections is less than a first threshold; the vertical channels and horizontal channels that have similar intersections or overlaps are determined to have an adjacent relationship, and a horizontal channel adjacent relationship graph is generated based on the adjacent relationship; based on the horizontal channel adjacent relationship graph, the coordinates of the horizontal and vertical channels that have an adjacent relationship in each layer are merged, and the boundary buffer zone of a preset distance is extended to obtain a preliminary conductive area; based on the preliminary conductive area, the conductive range between the layers is corrected to keep the conductive area of ​​each layer aligned in the vertical direction, and the aligned conductive area range is obtained.

[0044] In this example, by using a preset hierarchical coordinate matching algorithm, the system is able to accurately identify and delineate the vertical and horizontal channels in the multi-layer storage structure, thereby further determining the scope of the conductive area of ​​each layer. This process first extracts the coordinate information of each channel from the connection structure data of each layer. Specifically, the system collects the starting and ending coordinate positions of each horizontal and vertical channel to ensure that the distribution of each channel in space can be clearly understood. These starting and ending coordinate information are very important because they provide the exact path and spatial positioning of each channel, which facilitates subsequent matrix conversion and comparison.

[0045] Next, the system converts the extracted channel coordinate information into a multi-layer coordinate matrix. This matrix arranges the coordinate information of all connected channels in rows, with each layer as the unit. Through this structured coordinate matrix, the system can view and compare the channel coordinate data of each layer at multiple levels at the same time, thereby achieving more efficient analysis and processing. By integrating this data in the matrix, the system can compare layers to ensure that the channel positions of different layers are aligned, which facilitates the subsequent vertical channel identification.

[0046] Based on the multi-layer coordinate matrix, the system compares the channel coordinates of different layers through a hierarchical coordinate matching algorithm to identify a set of coordinate points with high overlap in the vertical direction. These overlapping point sets will form a set of vertical channel positions. "Overlap" here means that the channel coordinates of multiple layers coincide or are close in the vertical direction. The identification of these position sets is key because they determine where data can be transmitted between different layers.

[0047] Based on the vertical channel position set, the system performs adjacency analysis on the horizontal channels in each layer to further determine which horizontal channels have similar intersections or overlaps with the vertical channels in space. The core of adjacency analysis is to find those horizontal channels that are close to the vertical channels, that is, the distance between adjacent intersections is less than the preset threshold. This distance restriction helps to screen out channels that are truly physically adjacent to ensure the spatial correlation between channels and the reliability of signal transmission.

[0048] After determining the vertical and horizontal channels with similar intersections or overlaps, the system marks these channels as having an adjacent relationship and generates a horizontal channel adjacent relationship graph based on this. This adjacent relationship graph records the spatial association relationship between horizontal and vertical channels in each layer, providing a channel distribution map to facilitate further optimization of the layout and interconnection structure between channels.

[0049] Based on the adjacent relationship graph, the system merges the coordinate information of the horizontal and vertical channels with adjacent relationships in each layer, and expands a certain distance of the boundary buffer on this basis to obtain a preliminary conduction area. The expansion of the boundary buffer is intended to ensure that there is enough space in the conduction area to accommodate all adjacent channels and avoid signal interference. The result of this step is a preliminary conduction area, which lays the foundation for further determination of the conduction range.

[0050] Based on the preliminary conduction area, the system corrects the conduction range of each layer to keep the conduction area of ​​each layer aligned in the vertical direction. This ensures the precise alignment of the conduction area of ​​each layer, thereby optimizing the signal transmission path in the multi-layer structure. This alignment operation eliminates the spatial misalignment problem between layers, and ultimately forms a continuous, aligned conduction area range, ensuring that the signal can be transmitted smoothly between different layers. This design greatly improves the signal transmission efficiency and data integrity of the multi-layer storage structure, and effectively reduces the risk of transmission delay and interference.

[0051] In one example, based on the conductive area boundary data set, each conductive area is divided into channel areas, and multiple non-overlapping transmission sub-areas are determined as independent transmission channels, including: extracting the boundary coordinates and boundary features of each conductive area from the conductive area boundary data set, and expanding the boundary coordinates of each conductive area according to the boundary features to determine the boundary of the extended area; calculating the curvature change information of each extended area boundary, and identifying the high-change area in the extended area boundary according to the curvature change information, focusing on the high-change area, combining the marked data with the curvature change information, and generating A boundary curvature data set; using the boundary curvature data set and the boundary features, assigning weights to the boundary coordinates of each conductive area to obtain a weighted boundary data set; wherein, the higher the boundary curvature, the higher the weight value of the corresponding conductive area, and the more complex the boundary shape, the higher the weight value of the corresponding conductive area; using a clustering algorithm to cluster areas with similar weights and close positions into independent partitions, and assigning transmission paths of different partitions, and identifying whether there is overlap between the boundaries of the partitions. If there is overlap, the boundaries of the overlapping areas are re-divided until independent partitions with clear boundaries are obtained, and the independent partitions are used as transmission channels.

[0052] In this example, multiple non-overlapping transmission sub-areas are determined by dividing the conductive area into channel areas, making them independent transmission channels. This process first extracts the boundary coordinates and boundary features of each conductive area from the conductive area boundary data set. The boundary coordinates record the specific boundary point locations of the conductive area, while the boundary features describe the shape, complexity and other information of the boundary. This information is very important for further area division because it determines the direction and method of area expansion.

[0053] Based on the extracted boundary features, the system will expand the boundary coordinates of each conductive area to determine the boundary of the extended area. Extending the boundary means expanding the conductive area outward by a certain distance to ensure that interference can be effectively reduced and signal integrity can be maintained during high-frequency signal transmission. This expansion process provides more operating space for subsequent division and marking of boundary change areas.

[0054] Next, the system calculates the curvature change information of each extended area boundary. The curvature change reflects the rate of change of the shape of the boundary, that is, the degree of curvature of the boundary line. By identifying these curvature changes, the system can detect the parts of the extended area boundary with large curvature changes and focus on marking these high-change areas. These marked data will be combined with the curvature change information to form a boundary curvature data set for subsequent area division. These high curvature areas are usually the most significant parts of the boundary changes, indicating that the shape of the area is more complex and may cause greater interference when transmitting signals, so special attention should be paid.

[0055] After obtaining the boundary curvature data set, the system assigns weights to the boundary coordinates of the conductive area based on these curvature data and boundary features. The weight is determined by the curvature and complexity of the boundary. The higher the boundary curvature and the more complex the shape of the conductive area, the higher the weight value. In this way, the weighted boundary data set clearly shows the importance of each area. The assignment of weights helps the system identify and prioritize complex areas in subsequent steps and make more detailed divisions.

[0056] Next, the system uses a clustering algorithm to group areas with similar weights and close locations into independent partitions. These partitions form independent transmission channels, each of which is independent of each other and does not cause signal interference. This process effectively groups conductive areas with similar characteristics into the same partition, helping the system to more reasonably allocate transmission paths. For example, areas with close locations and similar weights may be clustered into one partition, which can reduce signal interference when transmitting high-frequency signals.

[0057] After the initial partitioning, the system will further check whether there is any overlap between the boundaries of different partitions. If there is overlap, the system will re-divide the boundaries of the overlapping areas to ensure that the boundaries of each partition are clear and non-overlapping. This step is to further optimize the independence of the transmission channels, ensure that there are clear boundaries between each channel, and avoid signal interference.

[0058] Finally, the system completes the division of independent partitions with clear boundaries and uses these partitions as transmission channels. These independent transmission channels ensure that signals do not interfere with each other when transmitted between different areas, enhance the transmission quality and stability of signals, and reduce the bit error rate and interference risk during data transmission. Through this detailed regional division and weight clustering, the present invention realizes efficient signal partition transmission, providing a reliable foundation for the stable operation of edge AI chips in complex environments.

[0059] In one example, an automatic wiring algorithm is used to perform layout optimization processing on multiple transmission channels of the multi-layer storage structure to determine the layout mode of the signal in the route, including: analyzing the signal requirement parameters of the multiple transmission channels to obtain a signal transmission requirement data set, wherein the signal transmission requirement data set includes: the signal transmission requirement parameters corresponding to each transmission channel, and the requirement parameters include at least: signal strength, signal frequency and required bandwidth; based on the signal transmission requirement data set, calculating the path impedance value of each transmission channel, and splitting each of the transmission channels to calculate each transmission channel sub-area after the split based on the path impedance value of each transmission channel. domain; on the basis of the transmission channel, in combination with the path impedance value and the path congestion parameter, the signal transmission route in each transmission channel is optimized to obtain a preliminary optimized layout mode; on the basis of the preliminary optimized layout mode, an electromagnetic interference analysis is performed to identify the electromagnetic field overlapping areas between the transmission channels and the electromagnetic interference data of each electromagnetic field overlapping area; based on the electromagnetic field overlapping areas and the electromagnetic interference data of each electromagnetic field overlapping area, a high interference area in each transmission channel is determined, and a Dijkstra algorithm is used to perform a path detour calculation on the signal transmission path in the high interference area to obtain a final optimized layout mode.

[0060] In this example, an automatic routing algorithm is used to optimize the layout of multiple transmission channels in a multi-layer storage structure to improve the efficiency and stability of signal transmission. First, the system analyzes the signal requirement parameters of each transmission channel and establishes a signal transmission requirement data set. These requirement parameters include the key signal transmission requirements of each channel, such as signal strength, signal frequency, and required bandwidth. These parameters are critical to wiring layout because they determine the stability and capacity requirements of each channel when transmitting signals. For example, a channel may require higher signal strength and wider bandwidth, so it is necessary to ensure that its channel path has low resistance and sufficient space during layout.

[0061] After obtaining the signal transmission demand data set, the system further calculates the path impedance value of each transmission channel. The path impedance value indicates the degree of resistance and obstruction encountered by the channel during signal transmission. After calculating the impedance value of each channel, the system splits the transmission channel and calculates the path congestion parameter of each split transmission channel sub-area based on the path impedance value. The congestion parameter reflects the congestion of signal transmission in a specific area. For example, an area with a large signal flow will have a higher congestion value. By splitting and calculating the congestion parameters, the system can more accurately identify the transmission load of each sub-area, thereby providing a reference for layout optimization.

[0062] Based on the path impedance value and path congestion parameters, the system begins to optimize the signal transmission route in each transmission channel and obtains a preliminary optimized layout. This optimization step mainly guides the signal to the path with low impedance and small congestion parameters to ensure that the resistance of the signal is minimized and the path is unobstructed during transmission. For example, some high-impedance areas may be bypassed, and the signal will be guided to the channel with lower impedance. In this way, the system can effectively improve the transmission efficiency of the signal and reduce the attenuation and interference of the signal in the channel.

[0063] After obtaining the preliminary optimized layout, the system will further perform electromagnetic interference analysis to identify the electromagnetic field overlap areas between each transmission channel. Electromagnetic interference is one of the main challenges for signal transmission in multi-layer structures, especially at high frequencies, which may cause data transmission errors and signal instability. In this step, the system will analyze the electromagnetic interference data of each channel, find the electromagnetic field overlap areas between different channels, and determine the high interference areas in each transmission channel based on the data of these areas. For example, if the electromagnetic fields of two channels frequently overlap and interfere in a certain area, then this area will be marked as a high interference area.

[0064] After identifying high-interference areas, the system uses the Dijkstra algorithm to perform path detour calculations on the signal transmission paths in these areas. The Dijkstra algorithm is an algorithm used to find the shortest path, which can help the system find alternative paths in high-interference areas to bypass the interference source. Through path detour calculations, the system can avoid high-interference areas on the signal transmission path, thereby obtaining the final optimized layout. This path adjustment ensures that the signal is not interfered with during transmission, thereby improving the integrity of the signal and the accuracy of data transmission.

[0065] Through this series of steps, the system achieves layout optimization of the multi-layer storage structure, which not only meets the signal transmission requirements, but also effectively reduces the impact of electromagnetic interference and ensures stable signal transmission in each channel. This layout optimization greatly improves the performance of the transmission channel, allowing the edge AI chip to complete signal processing and data transmission tasks more efficiently in the multi-layer structure.

[0066] In one example, based on the transmission channel and in combination with the path impedance value, the signal transmission route in each transmission channel is optimized to obtain a preliminary optimized layout method, including: based on the path impedance value of each transmission channel, a hotspot identification algorithm is used to identify the high impedance area to obtain an impedance hotspot distribution map; based on the impedance hotspot distribution map, the signal path of each transmission channel is segmented to divide the high impedance area and the low impedance area into independent transmission sections; the path congestion parameter corresponding to each transmission section is determined, and a bypass channel is proportionally set for the corresponding transmission section based on the path congestion parameter to obtain a path relief layout; based on the path relief layout, the path impedance value of each path is identified, and based on the path impedance value of each path, an equalization algorithm is used to extend the path length of the high impedance area to obtain a preliminary optimized layout method for impedance equalization of each path segment.

[0067] In this example, by analyzing the path impedance value of the transmission channel, the system performs a series of optimizations on the signal transmission route to ensure that the signal can be transmitted stably and efficiently. First, the system uses the path impedance value and hotspot identification algorithm to find the high impedance area in each transmission channel. The impedance value reflects the resistance in signal transmission, and the high impedance area is those areas where the signal transmission will encounter greater resistance. Through the hotspot identification algorithm, the system can visualize these high impedance areas as an impedance hotspot distribution map. This distribution map reveals the part with the greatest resistance in each transmission channel, which is convenient for subsequent segmentation and adjustment.

[0068] After obtaining the impedance hotspot distribution map, the system further segments each transmission channel and divides the high impedance area and the low impedance area into independent transmission sections. The advantage of this is that targeted optimization processing can be performed for different impedance areas. For example, a transmission channel may have high impedance in one section and low impedance in another section. Through segmentation processing, the system can clearly identify and process these areas separately to improve the transmission efficiency of the entire channel.

[0069] Based on the segment processing, the system determines the path congestion parameters for each transmission segment. The congestion parameter is an indicator to measure the signal flow and congestion in the transmission path. A high congestion value indicates that the signal load on the path segment is heavy. Based on these congestion parameters, the system sets bypass channels in the same proportion for each transmission segment to form a path relief layout. These bypass channels provide an alternative path, allowing the signal to choose a smoother path to transmit when in a high congestion area, reducing the pressure on the signal in the high congestion path segment. For example, if a high impedance, high congestion transmission segment is congested, the system will automatically guide part of the signal through the bypass channel to avoid blockage and transmission delay in that area.

[0070] Based on the path relief layout, the system will identify the path impedance value of each path and balance the impedance value of each path segment. The equalization algorithm used here achieves the purpose of balancing the impedance value of each transmission segment by extending the path length in the high impedance area. Extending the path length means adjusting the direction of the path or increasing the length of the transmission segment in the high impedance area to reduce the impedance value per unit length, thereby balancing the path impedance. For example, in a high impedance area, by extending the path in the area, the impedance distribution is made more uniform, so that the resistance during signal transmission does not suddenly increase in a certain section.

[0071] Ultimately, these optimization measures work together, and the system forms a preliminary optimized layout method for impedance balance in each transmission channel. Through this balanced layout, the transmission resistance of each channel tends to be balanced, and the signal can be transmitted smoothly in each section. This not only improves the transmission efficiency of the channel, but also effectively reduces the delay and interference problems that occur during signal transmission. The final optimized layout method ensures the stable signal transmission of each channel in the multi-layer structure of the edge AI chip, greatly improving the performance and stability of the chip's data processing in the multi-layer transmission channel.

[0072] like Figure 2 As shown, the present invention also provides a vertical interconnect packaging device of edge Ai chip multi-layer storage unit, including:

[0073] An acquisition unit 1 is used to acquire initial packaging parameters of each storage unit in the multi-layer storage structure of the edge AI chip, wherein the packaging parameters at least include: physical property parameters related to vertical interconnection;

[0074] A generation unit 2 is used to construct a model by vertically interconnecting multiple layers of storage units of an edge AI chip, and to generate a connection structure of each layer in the multi-layer storage structure of the edge AI chip in combination with packaging parameters of each storage unit;

[0075] A division unit 3 is used to partition the conduction structure between the multi-layer storage units based on the connection structure of each layer in the multi-layer storage structure of the edge AI chip to obtain multiple independent transmission channels;

[0076] A determination unit 4 is used to perform layout optimization processing on multiple transmission channels of the multi-layer storage structure using an automatic routing algorithm to determine the layout mode of the signal in the route;

[0077] The packaging unit 5 is used to adjust the initial packaging parameters to obtain final packaging parameters based on the layout of the signal in the route, and then use the final packaging parameters to vertically interconnect the multi-layer storage units of the edge AI chip.

[0078] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to the above method embodiment, which will not be repeated here.

[0079] Reference Figure 3 In an embodiment of the present invention, a computer device is also provided. The computer device may be a server, and its internal structure may be as follows: Figure 3 As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0080] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0081] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0082] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0083] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0084] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A vertical interconnect packaging method for multi-layer storage units of edge Ai chips, characterized in that: The following steps are involved: Obtaining initial packaging parameters of each storage unit in the multi-layer storage structure of the edge AI chip, wherein the packaging parameters at least include: physical property parameters related to vertical interconnection; A model is constructed by vertically interconnecting multiple layers of storage units of an edge AI chip, and a connection structure of each layer in the multi-layer storage structure of the edge AI chip is generated in combination with packaging parameters of each storage unit; Based on the connection structure of each layer in the multi-layer storage structure of the edge AI chip, the conduction structure between the multi-layer storage units is partitioned to obtain multiple independent transmission channels; Using an automatic routing algorithm to perform layout optimization processing on multiple transmission channels of the multi-layer storage structure to determine the layout mode of the signal in the route; Based on the layout of the signal in the route, the initial packaging parameters are adjusted to obtain final packaging parameters, and then the final packaging parameters are used to vertically interconnect and package the multi-layer storage units of the edge AI chip.

2. The vertical interconnect packaging method according to claim 1, characterized in that: The model is constructed by vertically interconnecting the multi-layer storage units of the edge AI chip, and the connection structure of each layer in the multi-layer storage structure of the edge AI chip is generated in combination with the packaging parameters of each storage unit, including: Performing hierarchical extraction processing on the encapsulation parameters of the storage units in each layer to obtain a hierarchical encapsulation parameter list; Using a multi-layer structure calculation algorithm and combining the layered encapsulation parameter list, the encapsulation parameters of each layer of storage units are mapped into a three-dimensional space coordinate system to obtain a preliminary model framework of vertical interconnection, wherein the preliminary model framework of vertical interconnection is used to express the preliminary connection relationship between each layer; In the preliminary model framework, the transmission nodes that need to be vertically interconnected in each layer are determined in combination with the encapsulation parameters of each layer, and all cross-layer transmission nodes are processed as a set to obtain a cross-layer transmission node set, and each node in the cross-layer transmission node set is marked with layer information and coordinate values; Based on the cross-layer transmission node set, the preliminary connection path between the transmission nodes is determined, and based on the preliminary connection path between the transmission nodes and on the basis of the preliminary model framework, the connection structure of each layer in the multi-layer storage structure of the edge AI chip is constructed.

3. The vertical interconnect packaging method according to claim 1, characterized in that: Based on the connection structure of each layer in the multi-layer storage structure of the edge AI chip, the conduction structure between the multi-layer storage units is partitioned to obtain multiple independent transmission channels, including: Using a preset hierarchical coordinate matching algorithm, the vertical channels and horizontal channels of the connection structures of each layer are determined, and based on the vertical channels and the horizontal channels, the conduction area range of each layer is determined; Perform boundary analysis on the conduction area range of each layer, determine the coordinate points and boundary features of each conduction area, and obtain a conduction area boundary data set, where the boundary features represent the complexity of the boundary shape; Based on the conductive area boundary data set, channel area division is performed on each conductive area, and a plurality of non-overlapping transmission sub-areas are determined as independent transmission channels.

4. The vertical interconnect packaging method according to claim 3, characterized in that: Using a preset hierarchical coordinate matching algorithm, the vertical channels and horizontal channels of the connection structures of each layer are determined, and based on the vertical channels and the horizontal channels, the conduction area range of each layer is determined, including: Extracting coordinate information of each channel from the connection structure data of each layer, wherein the coordinate information includes: the starting point and end point position coordinates of the horizontal channel and the vertical channel; Convert the coordinate information of each channel into a multi-layer coordinate matrix, wherein the multi-layer coordinate matrix takes each layer as a unit, and the coordinate information of all connected channels is arranged in rows; Based on the preset hierarchical coordinate matching algorithm, the channel coordinates of different layers in the multi-layer matrix are compared, a set of coordinate points with high overlap in the vertical direction is determined, and a set of vertical channel positions is obtained; Based on the vertical channel position set, the adjacency analysis is performed on the horizontal channels of each layer to determine the horizontal channels that have close intersections or overlaps with the vertical channels in space, wherein the distance between two associated intersections among the close intersections is less than a first threshold; Determine the vertical channels and horizontal channels having similar intersection points or overlapping points as having an adjacent relationship, and generate an adjacent relationship graph of the horizontal channels based on the adjacent relationship; Based on the horizontal channel adjacent relationship graph, the coordinates of the horizontal and vertical channels with adjacent relationships in each layer are merged, and the boundary buffer zone of the preset distance is expanded to obtain a preliminary conductive area; On the basis of the preliminary conductive area, the conductive ranges between the layers are corrected so that the conductive areas of each layer are aligned in the vertical direction, thereby obtaining an aligned conductive area range.

5. The vertical interconnect packaging method according to claim 3, characterized in that: Based on the conductive area boundary data set, each conductive area is divided into a channel area, and a plurality of non-overlapping transmission sub-areas are determined as independent transmission channels, including: Extracting boundary coordinates and boundary features of each conductive area from the conductive area boundary data set, and extending the boundary coordinates of each conductive area according to the boundary features to determine an extended area boundary; Calculating the curvature change information of each extended area boundary, and identifying the high-change area in the extended area boundary according to the curvature change information, focusing on marking the high-change area, combining the marked data with the curvature change information, and generating a boundary curvature data set; Using the boundary curvature data set and the boundary feature, weights are assigned to the boundary coordinates of each conductive area to obtain a weighted boundary data set; wherein, a higher boundary curvature corresponds to a higher weight value of the conductive area, and a more complex boundary shape corresponds to a higher weight value of the conductive area; A clustering algorithm is used to cluster areas with similar weights and close locations into independent partitions, and the transmission paths of different partitions are allocated and processed, and it is identified whether there is overlap between the boundaries of the partitions. If there is overlap, the boundaries of the overlapping areas are subdivided until independent partitions with clear boundaries are obtained, and the independent partitions are used as transmission channels.

6. The vertical interconnect packaging method according to claim 1, characterized in that: An automatic routing algorithm is used to perform layout optimization processing on multiple transmission channels of the multi-layer storage structure to determine the layout mode of the signal in the route, including: Analyze the signal requirement parameters of the multiple transmission channels to obtain a signal transmission requirement data set, wherein the signal transmission requirement data set includes: signal transmission requirement parameters corresponding to each transmission channel, and the requirement parameters include at least: signal strength, signal frequency and required bandwidth; Based on the signal transmission demand data set, the path impedance value of each transmission channel is calculated, and each transmission channel is split, so as to calculate the path congestion parameter corresponding to each transmission channel sub-area after the splitting based on the path impedance value of each transmission channel; Based on the transmission channel, the signal transmission route in each transmission channel is optimized in combination with the path impedance value and the path congestion parameter to obtain a preliminary optimized layout mode; Performing electromagnetic interference analysis based on the preliminary optimized layout method to identify electromagnetic field overlap areas between transmission channels and electromagnetic interference data of each electromagnetic field overlap area; Based on the electromagnetic field overlapping area and the electromagnetic interference data of each electromagnetic field overlapping area, the high interference area in each transmission channel is determined, and the Dijkstra algorithm is used to perform path detour calculation on the signal transmission path of the high interference area to obtain the final optimized layout method.

7. The vertical interconnect packaging method according to claim 6, characterized in that: Based on the transmission channel and in combination with the path impedance value, the signal transmission route in each transmission channel is optimized to obtain a preliminary optimized layout, including: Based on the path impedance value of each transmission channel, a hot spot identification algorithm is used to identify high impedance areas to obtain an impedance hot spot distribution map; Based on the impedance hotspot distribution map, the signal path of each transmission channel is segmented, and the high impedance area and the low impedance area are divided into independent transmission sections; Determine the path congestion parameter corresponding to each transmission section, and set a bypass channel for the corresponding transmission section in the same proportion based on the path congestion parameter to obtain a path relief layout; On the basis of the path relief layout, the path impedance value of each path is identified, and based on the path impedance value of each path, a balancing algorithm is used to extend the path length of the high impedance area to obtain a preliminary optimized layout method for impedance balancing of each path segment.

8. A vertical interconnect packaging device for multi-layer storage units of edge Ai chips, characterized in that: include: An acquisition unit, used to acquire initial packaging parameters of each storage unit in the multi-layer storage structure of the edge AI chip, wherein the packaging parameters at least include: physical property parameters related to vertical interconnection; A generation unit, configured to construct a model by vertically interconnecting multiple layers of storage units of an edge AI chip, and to generate a connection structure of each layer in the multi-layer storage structure of the edge AI chip in combination with packaging parameters of each storage unit; A partitioning unit, configured to partition the conduction structure between the multi-layer storage units based on the connection structure of each layer in the multi-layer storage structure of the edge AI chip to obtain a plurality of independent transmission channels; A determination unit, configured to perform layout optimization processing on multiple transmission channels of the multi-layer storage structure using an automatic routing algorithm to determine a layout mode of signals in a route; The packaging unit is used to adjust the initial packaging parameters to obtain final packaging parameters based on the layout of the signal in the route, and then use the final packaging parameters to vertically interconnect the multi-layer storage units of the edge AI chip.

9. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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