High-resistance semiconductor device and manufacturing method thereof
By forming a gate structure on the high K dielectric layer and forming a high resistance layer on the interlayer dielectric layer, the high resistance semiconductor devices have high resistance characteristics, which solves the problem that high K metal gate process cannot prepare high resistance semiconductor devices, and realizes the preparation of semiconductor devices with high resistance characteristics.
Patent Information
- Application Number
- CN202411927890.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-03-14
AI Technical Summary
The high-K metal gate process process cannot prepare high-resistance semiconductor devices, which limits their application.
By forming a gate structure on the high K dielectric layer and forming a high resistance layer on the interlayer dielectric layer, the vertical projection of the high resistance layer falls on the gate structure, a high resistance semiconductor device is prepared using a high K metal gate process process.
The high-resistance semiconductor devices with high resistance characteristics are prepared through the high-K metal gate process process, and the problem that high-resistance semiconductor devices cannot be prepared by the high-K metal gate process process is solved.
Smart Images
Figure CN119630016A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a high-resistance semiconductor device and a manufacturing method thereof. Background Art
[0002] In circuit design, resistors often play the role of current limiting and voltage dividing, and are one of the essential components in the circuit. Among them, high-resistance devices are widely used in analog circuits.
[0003] At present, high-resistance semiconductor devices are usually manufactured using the Poly-SiON (polysilicon as the gate and nitrogen-doped silicon oxide as the gate oxide) process, in which the P-type doped polysilicon gate has high resistance characteristics. For the High-K Metal Gate (HKMG) process, the gate material is metal and cannot be used as a resistance material, so the High-K Metal Gate process cannot be used to prepare high-resistance semiconductor devices, limiting the application of the High-K Metal Gate process. Summary of the invention
[0004] The object of the present invention is to provide a high resistance semiconductor device and a manufacturing method thereof, so as to solve the problem of how to prepare the high resistance semiconductor device by using a high-K metal gate process.
[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a high resistance semiconductor device, comprising: Providing a substrate, wherein the substrate is formed with a shallow trench isolation region and an active region; forming a high-K dielectric layer on the shallow trench isolation region; forming a gate structure on the high-K dielectric layer; forming an interlayer dielectric layer on the gate structure; A high resistance layer is formed on the interlayer dielectric layer, and a vertical projection of the high resistance layer falls on the gate structure.
[0006] Optionally, in the method for manufacturing the high resistance semiconductor device, the method for forming the high K dielectric layer on the shallow trench isolation region includes: depositing a high-K dielectric layer on the substrate; The high-K dielectric layer on the upper portion of the active region is removed, and the high-K dielectric layer on the upper portion of the shallow trench isolation region is retained.
[0007] Optionally, in the method for manufacturing the high-resistance semiconductor device, the method for forming a gate structure on the high-K dielectric layer includes: forming a gate metal layer on the high-K dielectric layer; Part of the gate metal layer and the high-K dielectric layer is etched until the surface of the shallow trench isolation region is exposed to form a discrete gate structure.
[0008] Optionally, in the method for manufacturing the high-resistance semiconductor device, the gate structure is a virtual gate.
[0009] Optionally, in the method for manufacturing the high resistance semiconductor device, the method for forming the interlayer dielectric layer on the gate structure includes: forming an interlayer dielectric layer by a deposition process, wherein the interlayer dielectric layer covers the gate structure and the substrate surface; The interlayer dielectric layer is planarized using a chemical mechanical polishing process.
[0010] Optionally, in the method for manufacturing the high resistance semiconductor device, after forming the high resistance layer on the interlayer dielectric layer, the method for manufacturing the high resistance semiconductor device further comprises: Forming a metal connector.
[0011] Optionally, in the method for manufacturing the high resistance semiconductor device, the method for forming the metal connector includes: depositing a dielectric layer, wherein the dielectric layer covers the high resistance layer; forming a through hole in the dielectric layer until the high resistance layer is exposed; Fill the through-holes with metal to form metal connectors.
[0012] In order to solve the above technical problems, the present invention also provides a high-resistance semiconductor device, which is manufactured using the manufacturing method of a high-resistance semiconductor device as described in any of the above items, and the high-resistance semiconductor device includes a substrate, a high-K dielectric layer, a gate structure, an interlayer dielectric layer and a high-resistance layer formed in sequence from bottom to top; the vertical projection of the high-resistance layer falls on the gate structure.
[0013] Optionally, in the high-resistance semiconductor device, the gate structure includes a plurality of discrete virtual gates, and each of the virtual gates is isolated from each other by an interlayer dielectric layer.
[0014] Optionally, in the high resistance semiconductor device, the high resistance semiconductor device further comprises a dielectric layer located on the high resistance layer, a metal connector is formed in the dielectric layer, and a bottom of the metal connector is in contact with the high resistance layer.
[0015] The high-resistance semiconductor device and its manufacturing method provided by the present invention include: providing a substrate, wherein the substrate is formed with a shallow trench isolation region and an active region; forming a high-K dielectric layer on the shallow trench isolation region; forming a gate structure on the high-K dielectric layer; forming an interlayer dielectric layer on the gate structure; forming a high-resistance layer on the interlayer dielectric layer, wherein the vertical projection of the high-resistance layer falls on the gate structure. The gate structure is prepared by a high-K metal gate process, and a high-resistance layer is formed on the gate structure, so that the prepared semiconductor device has a high-resistance characteristic through the high-resistance layer, thereby solving the problem of how to prepare a high-resistance semiconductor device by using a high-K metal gate process. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A flow chart of a method for manufacturing a high resistance semiconductor device provided in this embodiment; 2(A) to 2(G) are schematic structural diagrams of a high-resistance semiconductor device corresponding to each step in the method for manufacturing a high-resistance semiconductor device provided in this embodiment; The descriptions of the reference numerals are as follows: 100 - substrate; 101 - shallow trench isolation region; 102 - active region; 110 - high-K dielectric layer; 120 - gate metal layer; 121 - gate structure; 130 - interlayer dielectric layer; 140 - high resistance layer; 150 - dielectric layer; 160 - metal connector. DETAILED DESCRIPTION
[0017] The high resistance semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below in combination with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis of each accompanying drawing is different, and sometimes different proportions are used.
[0018] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0019] This embodiment provides a method for manufacturing a high resistance semiconductor device. Figure 1 As shown, including: S1, providing a substrate, wherein the substrate is formed with a shallow trench isolation region and an active region; S2, forming a high-K dielectric layer on the shallow trench isolation region; S3, forming a gate structure on the high-K dielectric layer; S4, forming an interlayer dielectric layer on the gate structure; S5, forming a high resistance layer on the interlayer dielectric layer, wherein a vertical projection of the high resistance layer falls on the gate structure.
[0020] The manufacturing method of the high-resistance semiconductor device provided in this embodiment prepares a gate structure through a high-K metal gate process and forms a high-resistance layer on the gate structure, so that the manufactured semiconductor device has a high-resistance characteristic through the high-resistance layer, thereby solving the problem of how to use the high-K metal gate process to prepare a high-resistance semiconductor device.
[0021] Specifically, in this embodiment, step S1, a substrate is provided, wherein the substrate is formed with a shallow trench isolation region and an active region, wherein, as shown in FIG2 (A), the substrate 100 includes a shallow trench isolation region (STI) 101 and an active region (AA) 102 located on both sides of the shallow trench isolation region 101, the shallow trench isolation region 101 is used to form a gate of a semiconductor device (transistor), and the active region 102 is used to form a source and a drain of the semiconductor device (transistor). The specific preparation method of the substrate 100 is well known to those skilled in the art, and will not be described in detail in this application.
[0022] Furthermore, in this embodiment, in step S2, a high-K dielectric layer is formed on the shallow trench isolation region.
[0023] Specifically, in this embodiment, a high-K dielectric layer 110 may be first deposited on the substrate 100; then, the high-K dielectric layer 110 on the active region 102 is removed, and the high-K dielectric layer 110 on the shallow trench isolation region 101 is retained. In this way, the high-K dielectric layer 110 in the gate region is retained. At this time, the structure of the high-resistance semiconductor device is shown in FIG. 2 (B).
[0024] High-K dielectrics refer to materials with a dielectric constant greater than that of silicon dioxide (SiO2) and a dielectric constant greater than 3.9, and are generally used to reduce gate leakage current and improve transistor efficiency. The material of the high-K dielectric layer may be, for example, hafnium oxide.
[0025] Furthermore, in this embodiment, in step S3, a gate structure is formed on the high-K dielectric layer.
[0026] Specifically, as shown in FIG. 2(C) , a gate metal layer 120 may be formed on the high-K dielectric layer 110 to obtain a gate structure.
[0027] At this point, the aforementioned steps S1 to S3 can all adopt the existing conventional high-K metal gate process technology, and the specific implementation method thereof is well known to those skilled in the art and will not be described in detail in this application.
[0028] Preferably, considering that in the high-K metal gate process, the gate needs to be polished to a certain height by chemical mechanical polishing (CMP) to ensure that the characteristics of the transistor meet the requirements, and the characteristics of the chemical mechanical polishing process make the entire larger-sized gate metal layer be polished faster than the dielectric layer, resulting in its surface height being lower than the surrounding dielectric layer, that is, through chemical mechanical polishing, a depression will be formed at the gate, and when the high-resistance layer is located on the top of the gate metal layer 120, the depression of the gate will affect the stability of the upper high-resistance layer. Therefore, in this embodiment, as shown in Figure 2 (D), part of the gate metal layer 120 and the high-K dielectric layer 110 are etched until the surface of the shallow trench isolation region 101 is exposed to form a discrete gate structure 121.
[0029] In this way, even if chemical mechanical polishing causes the surface of the gate structure 121 to be lower than the surrounding dielectric layer, since the gate structures 121 are independent of each other and are filled with dielectric layers, the high resistance layer above them relies on the dielectric layer to achieve stable support, thereby maintaining the gate function while ensuring the stability of the high resistance layer.
[0030] In practical applications, multiple etching lines can be marked on the surface of the gate metal layer 120 along the arrangement direction of the metal connectors according to the layout design; then, the gate metal layer 120 and the high-K dielectric layer 110 are etched according to the etching lines to form multiple discrete gate structures 121.
[0031] Of course, in other embodiments, there may be other etching methods, such as etching according to a grid, etc., which are not limited in this application. Also, the size of the gate structure 121 after etching, the interval between the gate structures 121, etc. can be set according to actual needs to ensure that the upper high resistance layer has reliable stability after chemical mechanical polishing.
[0032] More preferably, in order to reduce over-polishing of the gate during the chemical mechanical polishing process, in this embodiment, the gate structure is a dummy gate 121 .
[0033] Furthermore, in this embodiment, in step S4, an interlayer dielectric layer is formed on the gate structure.
[0034] Specifically, as shown in FIG2(E), an interlayer dielectric layer 130 is formed by a deposition process, and the interlayer dielectric layer 130 covers the surface of the gate structure 121 and the substrate 100. In practical applications, the interlayer dielectric layer 130 can be formed by a chemical vapor deposition process, and its specific implementation method is well known to those skilled in the art and will not be described in detail in this application.
[0035] Preferably, in order to ensure the surface flatness and structural stability of the subsequent high resistance layer, in this embodiment, the interlayer dielectric layer 130 may be planarized. Specifically, the interlayer dielectric layer 130 may be planarized by using a chemical mechanical polishing (CMP) process.
[0036] Furthermore, in this embodiment, in step S5, a high resistance layer is formed on the interlayer dielectric layer, and a vertical projection of the high resistance layer falls on the gate structure.
[0037] Specifically, a photolithography process may be used to define a region on the interlayer dielectric layer 130 where the high resistance layer 140 is to be formed, and then the high resistance layer 140 is formed in the defined high resistance layer region, so that the vertical projection of the high resistance layer 140 falls on the gate structure 121. At this point, the structure of the high resistance semiconductor device is shown in FIG2 (F).
[0038] In practical applications, the material of the high resistance layer 140 may be titanium nitride, and the high resistance layer 140 may be formed by using a photomask.
[0039] In this embodiment, after forming the high resistance layer on the interlayer dielectric layer, the method for manufacturing the high resistance semiconductor device further includes: S6, forming a metal connecting piece.
[0040] Specifically, first, a dielectric layer 150 is deposited, and the dielectric layer 150 covers the high resistance layer 140 ; then, a through hole is formed on the dielectric layer 150 until the high resistance layer 140 is exposed; finally, metal is filled in the through hole to form a metal connector 160 .
[0041] In practical applications, the dielectric layer 150 can cover the entire device surface, and the material of the dielectric layer 150 can be specifically silicon oxide, or a stacked structure of silicon oxide and nitrogen oxide, wherein the material of the dielectric layer 150 and the interlayer dielectric layer 130 can be the same. The area to be through-hole is planned on the surface of the dielectric layer 150 by photoresist, and then a through hole is formed on the area to be through-hole by etching process. And, the through hole is filled with metal by electroplating process, wherein the material of the metal can be specifically copper (Cu), and the metal surface formed in the through hole is polished to be flush with the dielectric layer 150 by chemical mechanical polishing (CMP) process, so as to form a metal connector 160 in the dielectric layer 150.
[0042] At this time, the structure of the high resistance semiconductor device finally obtained is shown in FIG. 2(G).
[0043] Based on the manufacturing method of the high-resistance semiconductor device provided in this embodiment, this embodiment also provides a high-resistance semiconductor device, as shown in Figure 2 (G), the high-resistance semiconductor device includes a substrate 100, a high-K dielectric layer 110, a gate structure 121, an interlayer dielectric layer 130 and a high-resistance layer 140 formed in sequence from bottom to top; the vertical projection of the high-resistance layer 140 falls on the gate structure 121.
[0044] The high-resistance semiconductor device provided in this embodiment has a high-resistance layer formed on the gate structure, and utilizes the high-resistance layer to have high-resistance characteristics. The entire process is prepared based on a high-K metal gate process, which solves the problem of how to use a high-K metal gate process to prepare a high-resistance semiconductor device.
[0045] Furthermore, in this embodiment, the gate structure includes a plurality of discrete virtual gates 121, and each of the virtual gates 121 is isolated from each other by an interlayer dielectric layer 130. In this way, there is not only a gate structure but also an interlayer dielectric under the high resistance layer 140, so that when the surface height of the gate structure 121 is lower than the surface of the interlayer dielectric layer 130 due to chemical mechanical polishing, the high resistance layer 140 can be stably supported by the interlayer dielectric layer 130 between the gate structures 121, thereby ensuring the stability of the high resistance layer 140.
[0046] Furthermore, in order to realize electrical extraction of the high resistance layer 140 , in the present embodiment, the high resistance semiconductor device further includes a dielectric layer 150 located on the upper portion of the high resistance layer 140 , a metal connector 160 being formed in the dielectric layer 150 , and the bottom of the metal connector 160 is in contact with the high resistance layer 140 .
[0047] The high-resistance semiconductor device and its manufacturing method provided by this embodiment are implemented based on the high-K metal gate process technology throughout the entire process, which solves the problem of how to use the high-K metal gate process technology to prepare a high-resistance semiconductor device. The high-resistance semiconductor device and its manufacturing method provided by this embodiment, after forming the gate metal layer, divides the gate metal layer into a plurality of discrete gate structures by etching, thereby ensuring the structural stability of the high-resistance layer formed thereon later, thereby ensuring the stability of the device structure and function. The high-resistance semiconductor device and its manufacturing method provided by this embodiment, using a virtual gate instead of a metal gate, can further improve the stability of the device structure.
[0048] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.
[0049] The high resistance semiconductor device and the manufacturing method thereof provided in the present embodiment include: providing a substrate, wherein the substrate is formed with a shallow trench isolation region and an active region; forming a high-K dielectric layer on the shallow trench isolation region; forming a gate structure on the high-K dielectric layer; forming an interlayer dielectric layer on the gate structure; forming a high resistance layer on the interlayer dielectric layer, wherein the vertical projection of the high resistance layer falls on the gate structure. The gate structure is prepared by a high-K metal gate process, and a high resistance layer is formed on the gate structure, so that the prepared semiconductor device has a high resistance characteristic through the high resistance layer, thereby solving the problem of how to prepare a high resistance semiconductor device by using a high-K metal gate process.
[0050] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a high resistance semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate is formed with a shallow trench isolation region and an active region; forming a high-K dielectric layer on the shallow trench isolation region; forming a gate structure on the high-K dielectric layer; forming an interlayer dielectric layer on the gate structure; A high resistance layer is formed on the interlayer dielectric layer, and a vertical projection of the high resistance layer falls on the gate structure.
2. The method for manufacturing a high resistance semiconductor device according to claim 1, wherein: The method for forming a high-K dielectric layer on the shallow trench isolation region comprises: depositing a high-K dielectric layer on the substrate; The high-K dielectric layer on the upper portion of the active region is removed, and the high-K dielectric layer on the upper portion of the shallow trench isolation region is retained.
3. The method for manufacturing a high resistance semiconductor device according to claim 1, wherein: The method for forming a gate structure on a high-K dielectric layer comprises: forming a gate metal layer on the high-K dielectric layer; Part of the gate metal layer and the high-K dielectric layer is etched until the surface of the shallow trench isolation region is exposed to form a discrete gate structure.
4. The method for manufacturing a high resistance semiconductor device according to claim 1, wherein: The gate structure is a virtual gate.
5. The method for manufacturing a high resistance semiconductor device according to claim 1, wherein: The method for forming an interlayer dielectric layer on a gate structure comprises: forming an interlayer dielectric layer by a deposition process, wherein the interlayer dielectric layer covers the gate structure and the substrate surface; The interlayer dielectric layer is planarized using a chemical mechanical polishing process.
6. The method for manufacturing a high resistance semiconductor device according to claim 1, wherein: After forming the high resistance layer on the interlayer dielectric layer, the method for manufacturing the high resistance semiconductor device further comprises: Forming a metal connector.
7. The method for manufacturing a high resistance semiconductor device according to claim 6, wherein: The method for forming a metal connector comprises: depositing a dielectric layer, wherein the dielectric layer covers the high resistance layer; forming a through hole in the dielectric layer until the high resistance layer is exposed; Fill the through-holes with metal to form metal connectors.
8. A high resistance semiconductor device manufactured by the method for manufacturing a high resistance semiconductor device according to any one of claims 1 to 7, characterized in that: The high resistance semiconductor device comprises a substrate, a high-K dielectric layer, a gate structure, an interlayer dielectric layer and a high resistance layer which are sequentially formed from bottom to top; the vertical projection of the high resistance layer falls on the gate structure.
9. The high resistance semiconductor device according to claim 8, characterized in that: The gate structure includes a plurality of discrete virtual gates, and each of the virtual gates is isolated from each other by an interlayer dielectric layer.
10. The high resistance semiconductor device according to claim 8, characterized in that The high resistance semiconductor device further comprises a dielectric layer located on the upper part of the high resistance layer, a metal connector is formed in the dielectric layer, and the bottom of the metal connector is in contact with the high resistance layer.