Preparation method of semiconductor device and semiconductor device

Abstract

The invention relates to a preparation method of a semiconductor device and the semiconductor device. The preparation method comprises the steps of providing a substrate; forming a first type well region in the substrate, wherein the well region comprises a source region and a drain region which are distributed at an interval; forming a groove in the well region based on the target photomask, wherein the groove is located between the source region and the drain region; injecting second-type ions into the target side wall and part of the bottom of the groove to form a second-type target doped region with an L-shaped longitudinal section; the target side wall is adjacent to the drain region; forming a second type drift region in the well region after forming a dielectric layer in the trench; a gate structure is formed on the substrate between the target doped region and the source region, a source doped region is formed in the source region, and a drain doped region is formed in the drain region. At least the HCI reliability problem of the high-voltage device and the SOA performance of the high-voltage device can be improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the application of high-voltage devices is increasing, such as RF power amplifiers in wireless communication systems, power management and industrial microwave applications, etc. High-voltage devices such as LDMOS (Laterally Diffused Metal-Oxide Semiconductor), IGBT (Insulated Gate Bipolar Transistor), high-voltage thyristor (SCR), etc., are widely used in wireless communication base stations, industrial heating or radar fields due to their high power handling capability, high frequency performance, low conduction loss, good linearity and other characteristics.

[0003] In the related art, since the hot carrier effect of high-voltage devices is closely related to the doping concentration of the drift region, when the doping concentration increases, the impact ionization under the gate is enhanced; and when the doping concentration is low, the impact ionization near the edge of the trench under the drain is enhanced.

[0004] However, in current high-voltage devices, when the drift region doping concentration is high, hot carrier injection (HCI) reliability issues will arise; and when the drift region doping concentration is low, insufficient safe operating area (SOA) issues will arise, making it difficult to take into account both HCI and SOA of high-voltage devices. Summary of the invention

[0005] Based on this, it is necessary to provide a method for preparing a semiconductor device and a semiconductor device to address the above technical problems, which can at least improve both the HCI reliability of the high-voltage device and the SOA performance of the high-voltage device.

[0006] In order to achieve the above-mentioned purpose and other purposes, in a first aspect, the present disclosure provides a method for preparing a semiconductor device, comprising: providing a substrate; forming a first type of well region in the substrate, the well region including a source region and a drain region distributed at intervals; forming a groove in the well region based on a target mask, the groove being located between the source region and the drain region; injecting a second type of ions into a target sidewall and a portion of the bottom of the groove to form a second type of target doping region with an "L"-shaped longitudinal cross-section; the target sidewall is adjacent to the drain region; after forming a dielectric layer in the groove, a second type of drift region is formed in the well region; forming a gate structure on the substrate between the target doping region and the source region, forming a source doping region in the source region, and forming a drain doping region in the drain region.

[0007] In the method for preparing the semiconductor device in the above-mentioned embodiment, a second-type target doping region with an ion concentration different from that of the drift region and an "L"-shaped longitudinal cross-section is formed in the second-type drift region. The doping concentration of the drift region below the gate structure is relatively low, thereby reducing the hot carrier collision ionization rate below the gate structure. The doping concentration of the target doping region near the sidewall and bottom of the trench below the drain doping region is relatively high, thereby reducing the hot carrier collision ionization rate of the drain doping region in the target doping region. Therefore, the embodiments disclosed herein can at least take into account both improving the HCI reliability of the high-voltage device and the SOA performance of the high-voltage device.

[0008] In one embodiment, the doping concentration of the target doping region is: to .

[0009] In one embodiment, the doping concentration of the drift region is: to .

[0010] In the method for preparing the semiconductor device in the above embodiment, by limiting the doping concentration of the target doping region and the doping concentration of the drift region, the hot carrier injection (HCI) reliability of the high voltage device and the SOA performance of the high voltage device are further improved.

[0011] In one embodiment, the top surface of the target doping region is not lower than the bottom surface of the drain doping region; and the bottom surface of the target doping region is higher than the bottom surface of the drift region.

[0012] In the method for preparing the semiconductor device in the above embodiment, the target doping region is formed below the drain doping region by limiting the positions of the target doping region and the drain doping region, thereby ensuring that the ion concentration below the drain doping region is higher than the ion concentration in the drift region, and reducing the hot carrier collision ionization rate of the drain doping region in the target doping region, thereby improving the SOA performance.

[0013] In one embodiment, a portion of a dielectric layer is included between the gate structure and the drain doped region.

[0014] In the method for preparing the semiconductor device in the above embodiment, a partial dielectric layer is formed between the gate structure and the drain doping region, so that the channel layer below the gate structure is connected to the drain doping region via the drift region and the target doping region below the dielectric layer, thereby improving the SOA performance while avoiding the generation of a current leakage channel.

[0015] In one embodiment, the doping concentration of the well region is: to .

[0016] In one embodiment, the doping concentration of the drain doping region is: to .

[0017] In the method for preparing the semiconductor device in the above embodiment, by limiting the well region concentration and the doping concentration of the drain doping region, the hot carrier injection (HCI) reliability of the high voltage device and the improvement of the safe operating area (SOA) performance are further guaranteed.

[0018] In one of the embodiments, the longitudinal cross-section of the groove is an "inverted trapezoid", which can reduce the difficulty and process cost of groove etching.

[0019] In one embodiment, the inner angle of the "L"-shaped target doping region is an obtuse angle, which is conducive to forming a rounded target doping region and avoiding the target doping region from forming a sharp angle at the corner, thereby causing tip discharge or leakage current.

[0020] In one embodiment, after forming the gate structure, a source doping region is formed in the source region, and a drain doping region is formed in the drain region.

[0021] In the method for preparing the semiconductor device in the above embodiment, a drain doping region and a source doping region are formed in the drain region and the source region, thereby forming a basic structure of a high-voltage device, and a drain doping region in contact with a target doping region is formed in the drain region, thereby improving the safe operating area (SOA) performance.

[0022] In one of the embodiments, the dielectric layer fills the groove and covers the top surface of the substrate; forming the drift region includes: forming a patterned photoresist layer on the top surface of the dielectric layer based on the target mask; performing a second type ion implantation into the well region based on the patterned photoresist layer to form the drift region; removing the patterned photoresist layer and the dielectric layer on the top surface of the substrate so that the top surface of the dielectric layer retained in the groove is flush with the top surface of the substrate.

[0023] In the method for manufacturing a semiconductor device in the above embodiment, the same target mask is used when forming the target doping region and the drift region, thereby reducing the cost of manufacturing the high-voltage semiconductor device.

[0024] In one embodiment, before forming the drain doping region, the top surface of the target doping region is located inside the top surface of the substrate.

[0025] In the method for preparing the semiconductor device in the above embodiment, by limiting the top surface of the target doping region to be located within the top surface of the substrate before forming the drain doping region, the contact between the drain doping region and the target doping region is ensured, thereby ensuring the improvement of the safe operating area (SOA) performance.

[0026] In a second aspect, an embodiment of the present disclosure further provides a semiconductor device, comprising: a semiconductor device manufactured using any of the above-mentioned methods for manufacturing a semiconductor device.

[0027] The unexpected technical effects that can be produced by the embodiments of the present disclosure include: by forming a second-type target doping region in the second-type drift region, which has an ion concentration different from that of the drift region and has an "L"-shaped longitudinal cross-section, the doping concentration of the drift region below the gate structure is relatively low, thereby reducing the hot carrier impact ionization rate below the gate structure; the doping concentration of the target doping region near the sidewall and bottom of the trench below the drain doping region is relatively high, thereby reducing the hot carrier impact ionization rate of the drain doping region in the target doping region. Therefore, the embodiments of the present disclosure can at least improve the hot carrier injection (HCI) reliability of the high-voltage device and the safe operating area performance of the high-voltage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic diagram of a process for preparing a semiconductor device provided in an embodiment;

[0030] Figure 2 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S2000 in a method for preparing a semiconductor device provided in an embodiment Figure 1 ;

[0031] Figure 3 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S2000 in a method for preparing a semiconductor device provided in an embodiment Figure 2 ;

[0032] Figure 4 It is a schematic diagram of the longitudinal cross-section structure of the structure obtained in step S3000 in the method for preparing a semiconductor device provided in one embodiment;

[0033] Figure 5 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S4000 in a method for preparing a semiconductor device provided in an embodiment Figure 1 ;

[0034] Figure 6 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S4000 in a method for preparing a semiconductor device provided in an embodiment Figure 2;

[0035] Figure 7 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S5000 in a method for preparing a semiconductor device provided in an embodiment Figure 1 ;

[0036] Figure 8 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S5000 in a method for preparing a semiconductor device provided in an embodiment Figure 2 ;

[0037] Fig. 9 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S5000 in a method for preparing a semiconductor device provided in an embodiment Figure 3 ;

[0038] Fig.10 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S6000 in a method for preparing a semiconductor device provided in an embodiment Figure 1 ;

[0039] Fig.11 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S6000 in a method for preparing a semiconductor device provided in an embodiment Figure 2 .

[0040] Description of reference numerals:

[0041] 201, substrate; 202, well region; 401, sacrificial layer; 403, groove; 501, target doping region; 601, patterned photoresist layer; 602, high-voltage device region; 603, other regions; 701, dielectric layer; 801, drift region; 1001, gate sidewall; 1002, gate oxide layer; 1003, gate; 1101, source doping region; 1102, drain doping region. DETAILED DESCRIPTION

[0042] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0044] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0045] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0046] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0048] Please refer to Figure 1-Figure 11 The present disclosure provides a method for preparing a semiconductor device, comprising the following steps:

[0049] Step S1000: providing a substrate 201 .

[0050] Wherein, the substrate 201 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 201 can be a single-layer structure or a multi-layer structure. For example, the substrate 201 can be a silicon substrate 201, a silicon germanium substrate 201, a silicon germanium carbon substrate 201, a silicon carbide substrate 201, a gallium arsenide substrate 201, an indium arsenide substrate 201, an indium phosphide substrate 201 or other III / V semiconductor substrates 201 or II / VI semiconductor substrates 201. Alternatively, for example, the substrate 201 can be a layered substrate 201 including silicon / silicon carbide, silicon on insulator or silicon germanium on insulator. Therefore, the type of substrate 201 should not limit the scope of protection of the present disclosure.

[0051] Step S2000 : forming a first-type well region 202 in the substrate 201 .

[0052] The well region 202 includes a source region and a drain region that are distributed at intervals. The source region is used to form a source doping region, and the drain region is used to form a drain doping region.

[0053] Step S3000 : forming a trench 403 in the well region 202 based on a target mask (not shown).

[0054] The trench 403 is located between the source region and the drain region. The longitudinal section of the trench 403 may be an inverted trapezoid. The bottom surface of the trench 403 is higher than the bottom surface of the well region 202 .

[0055] Step S4000: implanting second type ions into the target sidewalls and a portion of the bottom of the trench 403 to form a second type target doped region 501 having an “L”-shaped longitudinal cross section.

[0056] The target sidewall is adjacent to the drain region.

[0057] Step S5000 : After forming a dielectric layer 701 in the trench 403 , a second type drift region 801 is formed in the well region 202 .

[0058] Step S6000: forming a gate 1003 structure on the substrate 201 between the target doping region 501 and the source region, forming a source doping region 1101 in the source region, and forming a drain doping region 1102 in the drain region.

[0059] In the above embodiment, a second-type target doping region 501 having an ion concentration different from that of the drift region 801 and having an "L"-shaped longitudinal cross-section is formed in the second-type drift region 801, and the doping concentration of the drift region 801 below the gate 1003 structure is relatively low, thereby reducing the hot carrier impact ionization rate below the gate 1003 structure, and the doping concentration of the target doping region 501 near the sidewall and bottom of the trench 403 below the drain doping region 1102 is relatively high, thereby reducing the hot carrier impact ionization rate of the drain doping region 1102 in the target doping region 501. Therefore, the embodiment of the present disclosure can at least improve the hot carrier injection (HCI) reliability of the high-voltage device and the safe operating area performance of the high-voltage device.

[0060] Here, it should be noted that HCI (Hot Carrier Injection) refers to the phenomenon in which carriers (electrons or holes) are accelerated and injected into the oxide layer of the transistor gate 1003 due to excessive electric field strength in semiconductor devices. This will cause physical or chemical changes in the gate oxide layer, thereby affecting the device performance. Hot carrier injection will cause the electrical characteristics of the device to degrade, manifested as threshold voltage drift, increased gate 1003 leakage current, reduced drive current, etc. This phenomenon is exacerbated as the device size decreases and the voltage increases, and is one of the important factors affecting the reliability of high-voltage devices. Safe Operating Area (SOA) refers to the range in which a semiconductor device can operate safely without damage under specific voltage, current and power conditions. It defines the maximum voltage, current or power consumption that a device can withstand under different operating conditions. Exceeding the SOA may cause thermal runaway, breakdown or permanent damage to the device. Therefore, the improvement of hot carrier injection (HCI) reliability and the SOA of high-voltage devices is particularly important for high-voltage devices.

[0061] In step S2000, please refer to Figure 2-Figure 3 ,in, Figure 2 A well region 202 is formed in a substrate 201 .

[0062] Specifically, the first type well region 202 may be formed in the substrate 201 by the following steps: injecting the first type of ions into the substrate 201 ; and pushing the first type of ions into the well to a position close to the bottom of the substrate 201 based on a thermal annealing process.

[0063] Here, the thermal annealing process can rearrange the doped ions in the lattice by heating and enter the active sites, thereby effectively "activating" the doped ions. The thermal annealing process restores the bond between the implanted ions and the crystalline silicon to a normal structure by heating, and can also reduce the lattice damage caused by the implantation process.

[0064] Specifically, the annealing temperature and time can be controlled to push the first type of ions into the trap close to the bottom of the substrate 201. Higher temperatures can speed up atomic migration, accelerate lattice repair and activation of dopants; and time control determines the diffusion depth and degree of stress release of the annealing process.

[0065] Wherein, the doping concentration of the well region 202 is: to .

[0066] As an example, the doping concentration of the well region 202 may be , , , etc.

[0067] As an example, taking an N-type LDMOS high voltage device as an example, after the first type of ions are implanted into the substrate 201, a semiconductor structure is formed. Figure 2 As shown in Figure 2 The semiconductor structure includes a substrate 201 and a well region 202 that has not been subjected to a thermal annealing process. After the first type of ions are pushed into the well to a position close to the bottom of the substrate 201 based on the thermal annealing process, the semiconductor structure formed is as follows: Figure 3 As shown in Figure 3 In the semiconductor structure, the first type of ions are pushed into a well to a position close to the bottom of the substrate 201 based on a thermal annealing process, thereby forming a first type of well region 202.

[0068] Taking an N-type LDMOS high voltage device as an example, the first type of ions in the well region 202 may be P-type ions.

[0069] In step S3000, please refer to Figure 4 , a trench 403 is formed in the well region 202 based on a target mask, wherein the trench 403 is located between the source region and the drain region.

[0070] As an example, please refer to Figure 4A sacrificial layer 401 may be formed between the target mask and the well region 202 to prevent the well region 202 from being damaged when etching the trench 403 device.

[0071] In step S4000, please refer to Figure 5 , Figure 6 , second type ions are implanted into the target sidewall and part of the bottom of the trench 403 to form a second type target doped region 501 with an "L" shape in the longitudinal cross section; the target sidewall is adjacent to the drain region.

[0072] Wherein, the doping concentration of the target doping region 501 is: to .

[0073] As an example, the doping concentration of the target doping region 501 may be: , , etc.

[0074] Here, by limiting the concentration of the target doping region 501, the safe operating area performance of the high voltage device is further improved.

[0075] For example, the longitudinal section of the trench 403 is an “inverted trapezoid”, which can reduce the difficulty and process cost of trench etching.

[0076] For example, the inner angle of the “L”-shaped target doping region 501 is an obtuse angle, which is conducive to forming a rounded target doping region 501 and avoiding the target doping region 501 from forming a sharp angle at the corner to cause tip discharge or leakage current.

[0077] By forming the target doping region 501 on the sidewall and bottom surface of the trench 403 close to the drain doping region 1102, a high ion concentration below the drain doping region 1102 is ensured, and the hot carrier collision ionization rate between the drain doping region 1102 and the target doping region 501 is reduced, thereby improving the safe operating area (SOA) performance.

[0078] Specifically, in step S4000, a patterned mask layer (not shown) is first formed based on the target mask, and based on the patterned mask layer, second type ions are injected into the target sidewalls and part of the bottom of the trench 403 to form a second type target doping region 501 with an "L"-shaped longitudinal cross section.

[0079] As an example, see Figure 5 , Figure 5 An “L”-shaped second-type target doping region 501 is shown formed on the target sidewall and a portion of the bottom of the trench 403 .

[0080] As an example, taking an N-type LDMOS high voltage device as an example, the second type of ions implanted into the target sidewall and a portion of the bottom of the trench 403 are N-type ions.

[0081] As an example, see Figure 6 , Figure 6 A patterned photoresist layer 601 formed on a target mask is shown, and the patterned photoresist layer 601 covers areas where ion implantation is not required, and the areas where ion implantation is not required include some high-voltage device areas 602 and other areas 603 in the semiconductor device. Based on the protection of the patterned photoresist layer 601, the ions injected during the ion implantation process are prevented from diffusing into some high-voltage device areas 602 and other areas 603 in the semiconductor device where ion implantation is not required.

[0082] In one embodiment, during the process of performing the second type ion implantation to form the target doping region 501, the "L"-shaped second type target doping region 501 can be formed on the target sidewall and part of the bottom of the trench 403 by blocking the patterned mask layer and controlling the ion implantation angle. Figure 6 , Figure 6 The arrows in illustrative examples show the ion implantation angle during the process of forming the target doping region 501 .

[0083] Here, the present disclosure does not limit the angle of ion implantation. During the actual operation, the staff can control the ion implantation angle according to the actual situation and the opening position and opening shape of the patterned photoresist layer 601 to form an "L"-shaped second-type target doping region 501 on the target side wall and part of the bottom of the groove 403.

[0084] Among them, the dielectric layer 701 fills the groove 403 and covers the top surface of the substrate 201; based on the target mask, a patterned photoresist layer 601 is formed on the top surface of the dielectric layer 701; based on the patterned photoresist layer 601, a second type of ion implantation is performed into the well region 202 to form a drift region 801; the patterned photoresist layer 601 and the dielectric layer 701 on the top surface of the substrate 201 are removed, so that the top surface of the dielectric layer 701 retained in the groove 403 is flush with the top surface of the substrate 201.

[0085] In this way, when forming the target doping region 501 and the drift region 801 , the same target mask is used, thereby reducing the complexity and cost of manufacturing the high-voltage semiconductor device.

[0086] The top surface of the target doping region 501 is not lower than the bottom surface of the drain doping region 1102; the bottom surface of the target doping region 501 is higher than the bottom surface of the drift region 801. By limiting the positions of the target doping region 501 and the drain doping region 1102, the target doping region 501 is formed below the drain doping region 1102, the top surface of the target doping region 501 is flush with the bottom surface of the drain doping region 1102, and the bottom surface of the drain doping region 1102 partially covers the top surface of the target doping region 501, ensuring that the ion concentration below the drain doping region 1102 is higher than the ion concentration of the drift region 801, thereby ensuring the improvement of the safe operating area (SOA) performance of the high-voltage device.

[0087] In step S5000, please refer to Figure 7-Figure 9 , Figure 7 The structure of the semiconductor device after the dielectric layer 701 is formed in the groove 403 is shown. Specifically, the step of forming the dielectric layer 701 in the groove 403 includes: forming the dielectric layer 701 in the groove 403, and planarizing the dielectric layer 701. The dielectric layer 701 can be formed in the groove 403 by chemical vapor deposition (CVD), thermal oxidation (Thermal Oxidation), high density plasma (HDP) deposition, etc. After the groove 403 is filled, a planarization process such as chemical mechanical polishing (CMP) can be used to polish away excess dielectric layer 701 materials to form a flat surface, and ensure that the filling in the groove 403 is uniform and defect-free.

[0088] Wherein, the doping concentration of the drift region 801 is: to .

[0089] As an example, the doping concentration of the drift region 801 may be: , , , etc.

[0090] Here, by limiting the concentration of the drift region 801 , the hot carrier injection (HCI) reliability of the high voltage device is further improved.

[0091] Please continue to refer to Figure 8 , Fig. 9 , Figure 8The semiconductor structure after forming the second type drift region 801 in the well region 202 is shown. Specifically, the step of forming the second type drift region 801 in the well region 202 includes: performing second type ion implantation into the well region 202 based on the patterned photoresist layer 601, and pushing the second type ions into the well region 202 to the region near the bottom of the well region 202 based on the annealing process to form the second type drift region 801. Please continue to refer to Figure 8 After the second-type drift region 801 is formed, two regions with different doping concentrations are formed in the drift region 801. By forming a second-type target doping region 501 with an "L"-shaped longitudinal cross-section having an ion concentration different from that of the drift region 801 in the second-type drift region 801, the doping concentration of the drift region 801 below the gate 1003 structure is low, thereby reducing the hot carrier impact ionization rate below the gate 1003 structure. The doping concentration of the target doping region 501 near the sidewall and bottom of the trench 403 below the drain doping region 1102 is high, thereby reducing the hot carrier impact ionization rate of the drain doping region 1102 in the target doping region 501.

[0092] For details, please continue to refer to Fig. 9 , Fig. 9 shows the overall structure of the semiconductor device, such as Fig. 9 As shown in FIG. 1 , the present disclosure uses the same patterned photoresist layer 601 as a mask for performing the second type ion implantation twice. When performing the ion implantation in the drift region 801, the direction of the ion implantation can be Fig. 9 The middle arrow indicates a direction perpendicular to the bottom surface of the substrate 201. Thus, the same patterned photoresist layer 601 is used as a mask in both second-type ion implantations, thereby forming the drift region 801 and the target doping region 501 and reducing the cost of preparing high-voltage semiconductor devices.

[0093] In step S6000, please refer to Figure 10-11 A gate 1003 structure is formed on the substrate 201 between the target doping region 501 and the source region, a source doping region 1101 is formed in the source region, and a drain doping region 1102 is formed in the drain region.

[0094] Among them, a partial dielectric layer 701 is included between the gate 1003 structure and the drain doping region 1102. By forming a partial dielectric layer 701 between the gate 1003 structure and the drain doping region 1102, the channel layer below the gate 1003 structure is connected to the drain doping region 1102 via the drift region 801 and the target doping region 501 below the dielectric layer 701, thereby improving the SOA performance while avoiding the generation of a current leakage channel.

[0095] Specifically, the step of forming the source doping region 1101 in the source region is to implant source ions in the source region; and the step of forming the drain doping region 1102 in the drain region is to implant drain ions in the drain region.

[0096] Specifically, after the gate 1003 structure is formed, a source doping region 1101 is formed in the source region, and a drain doping region 1102 is formed in the drain region. By forming the drain doping region 1102 and the source doping region 1101 in the drain region and the source region, the basic structure of the high-voltage device is formed, and by forming the drain doping region 1102 in contact with the target doping region 501 in the drain region, the safe operating area (SOA) performance is improved.

[0097] Please continue to refer to Fig.10 , Fig.10 FIG. 4 shows a semiconductor structure after a gate 1003 structure is formed on a substrate 201 between a target doping region 501 and a source region. Fig.10 As shown in FIG. 1 , the gate 1003 structure includes a gate 1003 , a gate spacer 1001 and a gate oxide layer 1002 .

[0098] Among them, the gate sidewall 1001 can be made of silicon dioxide or other dielectric materials, which can optimize the electric field distribution, improve the voltage resistance performance, reduce the leakage current and enhance the device reliability, ensuring that the high-voltage device can operate stably for a long time in a high voltage and high power environment.

[0099] The gate oxide layer 1002 may be made of silicon dioxide ( ) or other high dielectric constant (high-k) materials. In high-voltage devices, the gate oxide layer 1002 can form electrical isolation and affect the conduction performance, withstand voltage capability, leakage current control, etc. of the high-voltage device.

[0100] The gate 1003 may be made of polysilicon, titanium (Ti), tantalum (Ta), tungsten (W), or a transition metal with high conductivity and high stability, or titanium nitride ( )、Tantalum Nitride( ) and other nitride materials are often used to enhance heat resistance and chemical stability. Aluminum (Al) can also be used as the gate 1003 material in some low-cost or low-power devices due to its low cost and high conductivity.

[0101] Please continue to refer to Fig.11 , Fig.11The semiconductor structure after forming a source doping region 1101 in the source region and a drain doping region 1102 in the drain region is shown, wherein the source doping region 1101 is formed in the well region 202, and the drain doping region 1102 is formed in the drift region 801, and is in contact with the target doping region 501. The doping concentration of the target doping region 501 near the sidewall and bottom surface of the trench 403 below the drain doping region 1102 is relatively high, which reduces the hot carrier impact ionization rate of the drain doping region 1102 in the target doping region 501. Therefore, the embodiment of the present disclosure can at least improve the hot carrier injection (HCI) reliability of the high-voltage device and the SOA performance of the high-voltage device.

[0102] The doping concentration of the drain doping region 1102 is: to .

[0103] Wherein, the doping concentration of the source doping region 1101 is: to .

[0104] As an example, the doping concentration of the drain doping region 1102 may be: , , , etc.

[0105] As an example, the doping concentration of the source doping region 1101 may be: , , , Etc. It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0106] In some embodiments, the present disclosure provides a semiconductor device, including: a semiconductor device prepared by any of the above-mentioned semiconductor device preparation methods.

[0107] Please refer to Fig.11The unexpected technical effects that can be produced by the embodiments of the present disclosure include: by forming a second-type target doping region 501 with an ion concentration different from that of the drift region 801 and an "L"-shaped longitudinal cross-section in the second-type drift region 801, the drift region 801 below the gate 1003 structure has a lower doping concentration, which reduces the hot carrier impact ionization rate below the gate 1003 structure, and the target doping region 501 near the sidewall and bottom of the trench 403 below the drain doping region 1102 has a higher doping concentration, which reduces the hot carrier impact ionization rate of the drain doping region 1102 in the target doping region 501. Therefore, the embodiments of the present disclosure can at least improve the hot carrier injection (HCI) reliability of the high-voltage device and the SOA performance of the high-voltage device.

[0108] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; Forming a first type of well region in the substrate, wherein the well region includes a source region and a drain region that are spaced apart; Forming a trench in the well region based on a target mask, wherein the trench is located between the source region and the drain region; Implanting second type ions into the target sidewall and part of the bottom of the trench to form a second type target doping region with an "L" shape in longitudinal section; the target sidewall is adjacent to the drain region; After forming a dielectric layer in the trench, a second type drift region is formed in the well region; A gate structure is formed on the substrate between the target doping region and the source region, a source doping region is formed in the source region, and a drain doping region is formed in the drain region.

2. The preparation method according to claim 1, characterized in that: The doping concentration of the target doping region is: to ; and / or; The doping concentration of the drift region is: to .

3. The preparation method according to claim 1, characterized in that: The top surface of the target doping region is not lower than the bottom surface of the drain doping region; A bottom surface of the target doping region is higher than a bottom surface of the drift region.

4. The preparation method according to claim 1, characterized in that: A portion of the dielectric layer is included between the gate structure and the drain doped region.

5. The preparation method according to any one of claims 1 to 4, characterized in that: The doping concentration of the well region is: to ; and / or; The doping concentration of the drain doping region is: to .

6. The preparation method according to any one of claims 1 to 4, characterized in that: The longitudinal section of the groove is an "inverted trapezoid"; and / or The inner angle of the "L"-shaped target doping region is an obtuse angle.

7. The preparation method according to any one of claims 1 to 4, characterized in that: After forming the gate structure, the source doping region is formed in the source region, and the drain doping region is formed in the drain region.

8. The preparation method according to any one of claims 1 to 4, characterized in that: The dielectric layer fills the trench and covers the top surface of the substrate; forming the drift region comprises: forming a patterned photoresist layer on the top surface of the dielectric layer based on the target mask; Performing second-type ion implantation into the well region based on the patterned photoresist layer to form the drift region; The patterned photoresist layer and the dielectric layer on the top surface of the substrate are removed, so that the top surface of the dielectric layer remaining in the groove is flush with the top surface of the substrate.

9. The preparation method according to any one of claims 1 to 4, characterized in that: Before forming the drain doping region, the top surface of the target doping region is located within the top surface of the substrate.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

Images