Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for simplifying the manufacturing process of a three-dimensional laminated complementary transistor device and reducing the manufacturing difficulty of the three-dimensional laminated complementary transistor device. The semiconductor device comprises a substrate, a first transistor, a medium bonding layer and a second transistor. The first transistor is disposed on the substrate. The grid side wall of the first transistor is arranged on the side, close to the substrate, of the first transistor in the height direction of the first transistor. The dielectric bonding layer covers the side, away from the substrate, of the first transistor. The second transistor is arranged on the side, away from the first transistor, of the dielectric bonding layer. The second transistor is opposite to the first transistor below the second transistor in conductivity type. And the grid side wall of the second transistor is arranged on one side, deviating from the dielectric bonding layer, of the second transistor along the height direction of the second transistor. And the dielectric bonding layer is used for at least bonding the channel region included in the second transistor above the channel region included in the first transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The three-dimensional stacked complementary transistor includes vertically stacked N-type transistors and P-type transistors, eliminating the lateral spacing between the N-type transistors and the P-type transistors, which allows the effective channel width to be further increased, thereby facilitating the improvement of the operating performance and integration of the semiconductor device.

[0003] However, the manufacturing process of the existing three-dimensional stacked complementary transistor device is relatively complicated and has high requirements on the manufacturing process, which makes the integration of the three-dimensional stacked complementary transistor device relatively difficult. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to simplify the manufacturing process of a three-dimensional stacked complementary transistor device and reduce the manufacturing difficulty of the three-dimensional stacked complementary transistor device.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a semiconductor device, which includes: a substrate, a first transistor, a dielectric bonding layer and a second transistor. The first transistor is arranged on the substrate. The gate sidewall included in the first transistor is arranged on a side of the first transistor close to the substrate along its own height direction. The dielectric bonding layer covers the side of the first transistor away from the substrate. The second transistor is arranged on a side of the dielectric bonding layer away from the first transistor. The conductivity type of the second transistor is opposite to that of the first transistor located below it. The gate sidewall included in the second transistor is arranged on a side of the second transistor away from the dielectric bonding layer along its own height direction. The dielectric bonding layer is used to bond at least the channel region included in the second transistor above the channel region included in the first transistor, and to isolate the source / drain region and the gate stack structure included in the first transistor from the source / drain region and the gate stack structure included in the second transistor, respectively.

[0006] In the case of adopting the above technical solution, in the semiconductor device provided by the present invention, the first transistor and the second transistor are spaced apart and distributed along the thickness direction of the substrate, and the conductivity type of the second transistor is opposite to that of the first transistor located below itself. At this time, the first transistor and the second transistor can constitute a three-dimensional stacked complementary transistor device to improve the integration of the semiconductor device and facilitate the miniaturization of the semiconductor device. In addition, the semiconductor device provided by the present invention also includes a dielectric bonding layer covering the side of the first transistor away from the substrate, and the dielectric spacing layer is used to bond at least the channel region included in the second transistor to the top of the channel region included in the first transistor. At this time, in the actual manufacturing process, the second semiconductor layer and the first semiconductor layer for manufacturing the channel region included in the first transistor and the second transistor can be formed on the first semiconductor substrate and the second semiconductor substrate respectively through processes such as epitaxy, and then the integration of the two is realized through a bonding process. Since the first semiconductor layer and the second semiconductor layer are formed separately on the first semiconductor substrate and the second semiconductor substrate, the restrictions on the materials of the first semiconductor layer and the second semiconductor layer during epitaxy are relatively low, which is conducive to realizing that the channel regions included in the first transistor and the second transistor have different crystal orientations and / or materials, so that the first transistor and the second transistor both have driving performance that meets the corresponding working requirements; of course, the channel regions included in the first transistor and the second transistor can also have the same crystal orientation and / or material, thereby improving the applicability of semiconductor devices in different application scenarios. Secondly, a dielectric bonding layer is implemented to bond the channel regions included in the first transistor and the second transistor, which covers the side of the first transistor away from the substrate, and can isolate the source / drain region and gate stack structure included in the first transistor from the source / drain region and gate stack structure included in the second transistor, respectively. In other words, the above-mentioned dielectric bonding layer can not only realize the bonding between the channel regions included in the first transistor and the second transistor, but also isolate the first transistor from the second transistor to prevent leakage and interference. There is no need to additionally produce the corresponding insulating layer between the source / drain regions, the middle dielectric isolation layer between the upper and lower gate stack structures, and the shallow trench isolation structure that isolates different active areas as in the existing monolithic integration process, which is conducive to simplifying the manufacturing process of the three-dimensional stacked complementary transistor device.

[0007] In addition, the first transistor and the second transistor are described with the side with the gate sidewall as the top and the other side as the bottom: in the first transistor and the second transistor respectively arranged on both sides of the dielectric bonding layer along the thickness direction thereof, the gate sidewall included in the first transistor is arranged on the side of the first transistor close to the substrate along the height direction thereof, and the gate sidewall included in the second transistor is arranged on the side of the second transistor away from the dielectric bonding layer along the height direction thereof. At this time, the bottoms of the first transistor and the second transistor are both closer to the dielectric bonding layer. Based on this, in the actual manufacturing process, after the second semiconductor layer and the first semiconductor layer used to manufacture the channel region included in the first transistor and the second transistor are bonded through the dielectric bonding layer, the first transistor and the second transistor are respectively manufactured in the direction away from the dielectric bonding layer, which can solve the problem of a higher aspect ratio vertical structure and a more complex vertical integration caused by the simultaneous manufacture of N-type transistors and P-type transistors in the existing monolithic integration method, and is conducive to reducing the manufacturing difficulty of three-dimensional stacked complementary transistor devices.

[0008] In one example, the semiconductor device further includes a first interconnect layer disposed between the first transistor and the substrate, and the first interconnect layer is used to lead out the source / drain regions and the gate stack structure included in the first transistor.

[0009] In one example, the semiconductor device further includes a second interconnect layer disposed on a side of the second transistor away from the dielectric bonding layer, and the second interconnect layer is used to lead out the source / drain regions and the gate stack structure included in the second transistor.

[0010] In one example, the first transistor and the second transistor are both fin field effect transistors or gate-all-around transistors.

[0011] In an example, one of the first transistor and the second transistor is a fin field effect transistor, and the other is a gate-all-around transistor.

[0012] In one example, among all first transistors located in the same layer, at least one first transistor is a fin field effect transistor, and the remaining first transistors are gate-all-around transistors.

[0013] In one example, among all the second transistors located in the same layer, at least one second transistor is a fin field effect transistor, and the remaining second transistors are gate-all-around transistors.

[0014] In one example, among all first transistors located in the same layer, the conductivity type of at least one first transistor is different from the conductivity type of the other first transistors, and among all second transistors located in the same layer, the conductivity type of at least one second transistor is different from the conductivity type of the other second transistors.

[0015] In one example, a material of the channel region included in the first transistor or the channel region included in the second transistor includes silicon germanium or germanium.

[0016] In one example, a material of a channel region included in the first transistor is different from a material of a channel region included in the second transistor.

[0017] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising: first, forming a semiconductor structure. Along the height direction of the semiconductor structure, the semiconductor structure comprises a first semiconductor substrate, a first semiconductor layer, a dielectric bonding layer, and a second semiconductor layer which are stacked in sequence. The first semiconductor layer and the second semiconductor layer are bonded together by the dielectric bonding layer. Next, a first transistor is formed based on the second semiconductor layer; and a substrate is formed on the side of the first transistor away from the dielectric bonding layer. The gate sidewall included in the first transistor is arranged on the side of the first transistor close to the substrate along the height direction of itself. Next, the first semiconductor substrate is removed. Next, a second transistor is formed based on the first semiconductor layer. The conductivity type of the second transistor is opposite to that of the first transistor located below itself. The gate sidewall included in the second transistor is arranged on the side of the second transistor away from the dielectric bonding layer along the height direction of itself. The dielectric bonding layer is used to bond at least the channel region included in the second transistor above the channel region included in the first transistor, and to isolate the source / drain region and the gate stack structure included in the first transistor from the source / drain region and the gate stack structure included in the second transistor, respectively.

[0018] In one example, forming a semiconductor structure includes: forming a first semiconductor layer and a first bonding sublayer on the first semiconductor substrate in sequence along the thickness direction of the first semiconductor substrate. Next, providing a second semiconductor substrate, and forming a second semiconductor layer and a second bonding sublayer on the second semiconductor substrate in sequence along the thickness direction of the second semiconductor substrate. Next, bonding the first semiconductor layer and the second semiconductor layer together through the first bonding sublayer and the second bonding sublayer. The dielectric bonding layer includes the first bonding sublayer and the second bonding sublayer. Next, removing the second semiconductor substrate.

[0019] In one example, after forming a first transistor based on the second semiconductor layer, before forming a substrate on a side of the first transistor facing away from the dielectric bonding layer, the method for manufacturing a semiconductor device further includes: forming a first interconnection layer arranged between the first transistor and the substrate, the first interconnection layer being used to lead out the source / drain regions and gate stack structure included in the first transistor.

[0020] In one example, after forming a second transistor based on the first semiconductor layer, the method for manufacturing a semiconductor device also includes: forming a second interconnect layer arranged on the side of the second transistor away from the dielectric bonding layer, the second interconnect layer being used to lead out the source / drain regions and gate stack structure included in the second transistor.

[0021] In one example, when the first transistor is a gate-all-around transistor, the second semiconductor layer includes alternately stacked first sacrificial layers and first channel layers. The film layer close to the dielectric bonding layer in the alternately stacked first sacrificial layers and first channel layers is the first sacrificial layer.

[0022] In one example, when the second transistor is a gate-all-around transistor, the first semiconductor layer includes alternately stacked second sacrificial layers and second channel layers. The film layer close to the dielectric bonding layer in the alternately stacked second sacrificial layers and second channel layers is the second sacrificial layer.

[0023] In one example, the first transistor and / or the second transistor is formed by using a low temperature manufacturing process, wherein the manufacturing temperature of the low temperature manufacturing process is less than 800°C.

[0024] In one example, a bonding process is used to form a substrate on a side of the first transistor away from the dielectric bonding layer.

[0025] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0027] Figure 1 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 1 and hint Figure 2 ;

[0028] Figure 2 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 3 and hint Figure 4 ;

[0029] Figure 3 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 5 ;

[0030] Figure 4 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 6 ;

[0031] Figure 5 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 7;

[0032] Figure 6 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 8 ;

[0033] Figure 7 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 9 ;

[0034] Figure 8 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 ;

[0035] Fig. 9 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 one;

[0036] Fig.10 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 two;

[0037] Fig.11 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Sanhe hint Figure 10 Four;

[0038] Fig.12 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Five and the hint Figure 10 six;

[0039] Fig.13 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Seven and hint Figure 10 eight;

[0040] Fig.14 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Nine hints Figure 2 ten;

[0041] Fig.15 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 2 Eleven and hint Figure 2 twelve;

[0042] Fig.16Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 2 Thirteen and hint Figure 2 fourteen;

[0043] Fig.17 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 2 Fifteen and hint Figure 2 sixteen;

[0044] Fig.18 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 2 Seventeen and hint Figure 2 eighteen;

[0045] Fig.19 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 2 Nineteen and hint Figure 3 ten;

[0046] Fig. 20 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 3 Eleven and hint Figure 3 twelve;

[0047] Fig.21 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 3 Thirteen and hint Figure 3 fourteen;

[0048] Fig. 22 Parts (1) and (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 3 Fifteen and hint Figure 3 sixteen;

[0049] Fig.23 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 XVII;

[0050] Fig.24 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 eighteen;

[0051] Fig.25 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 nineteen;

[0052] Fig.26 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 4 ten.

[0053] Figure numerals: 11 is a substrate, 12 is a first transistor, 13 is a dielectric bonding layer, 14 is a second transistor, 15 is a gate sidewall, 16 is a channel region, 17 is a source / drain region, 18 is a gate stack structure, 19 is a first interconnection layer, 20 is a second interconnection layer, 21 is an interlayer dielectric layer, 22 is a first semiconductor substrate, 23 is a first semiconductor layer, 24 is a second semiconductor layer, 25 is a first bonding sublayer, 26 is a second semiconductor substrate, 27 is a second bonding sublayer, 28 is a first sacrificial layer, 29 is a first channel layer, 30 is a second sacrificial layer, 31 is a second channel layer, and 32 is a sacrificial gate. DETAILED DESCRIPTION

[0054] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0055] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0056] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0057] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0058] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0059] The three-dimensional stacked complementary transistor includes vertically stacked N-type transistors and P-type transistors, eliminating the lateral spacing between the N-type transistors and the P-type transistors, which allows the effective channel width to be further increased, thereby facilitating the improvement of the operating performance and integration of the semiconductor device.

[0060] However, the manufacturing process of existing CFET devices is relatively complicated and has high requirements for manufacturing technology, which makes it difficult to integrate N-type transistors and P-type transistors in CFET devices. Specifically, the existing manufacturing methods of three-dimensional stacked complementary transistors mainly have the following two integration schemes:

[0061] The first method: using a monolithic method to manufacture a three-dimensional stacked complementary transistor. Specifically, taking the N-type transistor and the P-type transistor as ring-gate transistors, and the P-type transistor is located above the N-type transistor as an example, the process of manufacturing a three-dimensional stacked complementary transistor using the existing manufacturing method is described: First, a fin structure is formed on a semiconductor substrate. The fin structure includes at least two stacked layers. Each stacked layer includes a sacrificial layer, and a channel layer located on the sacrificial layer, and the materials of the sacrificial layer and the channel layer are both semiconductor materials. Next, a sacrificial gate and sidewalls are formed across part of the fin structure. And using the sacrificial gate and sidewalls as masks, the fin structure is selectively etched to remove the portion of the fin structure exposed outside the sacrificial gate and sidewalls. Then, a first semiconductor material for manufacturing the source region and drain region included in the N-type transistor is formed on the semiconductor substrate. At this time, since the remaining parts of the sacrificial layer and the channel layer corresponding to the N-type transistor and the P-type transistor are exposed after being etched, the remaining parts of these sacrificial layers and the channel layer can be used as seed layers for the epitaxial growth of the first semiconductor material. Therefore, the first semiconductor material is formed not only on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the N-type transistor after being etched, but also on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the P-type transistor after being etched. Next, it is necessary to remove the first semiconductor material located on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the P-type transistor after being etched, and the remaining parts of the first semiconductor material form the source region and the drain region included in the N-type transistor. Then, an epitaxial isolation layer is formed covering the surface of the source region and the drain region of the N-type transistor away from the substrate; and the source region and the drain region of the P-type transistor are formed on the epitaxial isolation layer by an epitaxial growth process. Finally, the sacrificial gate and the part of the sacrificial layer located in the gate formation area are removed; and a gate stack structure surrounding the periphery of the channel area is formed to obtain a three-dimensional stacked complementary transistor.

[0062] The second method is to use a sequential method to manufacture a three-dimensional stacked complementary transistor. This method is to form the bottom transistor according to the manufacturing process of conventional semiconductor devices, and after forming the corresponding contact electrodes of the bottom transistor, use wafer-to-wafer bonding technology to cover a semiconductor layer on the top of the bottom transistor by wafer transfer. Then, the top transistor is integrated based on the semiconductor layer, and the top gate and bottom gate are connected to obtain a three-dimensional stacked complementary transistor.

[0063] From the manufacturing process of the first method mentioned above, it can be seen that in order to isolate the source region, drain region and channel region of the bottom and top transistors, the vertical distance between the two transistors is large, so this method has a relatively high aspect ratio vertical structure, resulting in subsequent patterned fin structures, sacrificial gates, gate sidewalls, and source and drain electrodes. It brings great technical challenges, and the manufacturing process of the three-dimensional stacked complementary transistor corresponding to this method is relatively complicated. The manufacturing process of the second method for manufacturing CFET devices is also relatively complicated. Secondly, the vertical interconnection spacing of the upper layer devices is large, and the process requirements are also high, which makes the manufacturing of CFET devices more difficult.

[0064] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. Among them, in the semiconductor device provided by the embodiment of the present invention, the dielectric bonding layer can not only realize the bonding between the channel regions included in the first transistor and the second transistor, but also can isolate the first transistor from the second transistor, prevent leakage and interference, and also help simplify the manufacturing process of the three-dimensional stacked complementary transistor device. The gate sidewall included in the first transistor is arranged on the side of the first transistor close to the substrate along its own height direction, and the gate sidewall included in the second transistor is arranged on the side of the second transistor away from the dielectric bonding layer along its own height direction, so as to solve the problem of a higher aspect ratio vertical structure and a more complex vertical integration caused by the simultaneous manufacture of N-type transistors and P-type transistors in the existing monolithic integration method, which is conducive to reducing the manufacturing difficulty of the three-dimensional stacked complementary transistor device.

[0065] Specifically, the first aspect is Figure 23 to Figure 26 As shown, the semiconductor device provided by the embodiment of the present invention includes: a substrate 11, a first transistor 12, a dielectric bonding layer 13 and a second transistor 14. The first transistor 12 is arranged on the substrate 11. The gate sidewall 15 included in the first transistor 12 is arranged on the side of the first transistor 12 close to the substrate 11 along the height direction of the first transistor 12. The dielectric bonding layer 13 covers the side of the first transistor 12 away from the substrate 11. The second transistor 14 is arranged on the side of the dielectric bonding layer 13 away from the first transistor 12. The conductivity type of the second transistor 14 is opposite to that of the first transistor 12 located below it. The gate sidewall 15 included in the second transistor 14 is arranged on the side of the second transistor 14 away from the dielectric bonding layer 13 along the height direction of the second transistor 14. The dielectric bonding layer 13 is used to at least bond the channel region 16 included in the second transistor 14 above the channel region 16 included in the first transistor 12, and to isolate the source / drain region 17 and the gate stack structure 18 included in the first transistor 12 from the source / drain region 17 and the gate stack structure 18 included in the second transistor 14 respectively.

[0066] When the above technical solution is adopted, Figures 1 to 26As shown, in the semiconductor device provided by the embodiment of the present invention, the first transistor 12 and the second transistor 14 are spaced apart and distributed along the thickness direction of the substrate 11, and the conductivity type of the second transistor 14 is opposite to that of the first transistor 12 located below it. At this time, the first transistor 12 and the second transistor 14 can constitute a three-dimensional stacked complementary transistor device to improve the integration of the semiconductor device and facilitate the miniaturization of the semiconductor device. In addition, the semiconductor device provided by the embodiment of the present invention also includes a dielectric bonding layer 13 covering the side of the first transistor 12 away from the substrate 11, and the dielectric bonding layer 13 is used to bond at least the channel region 16 included in the second transistor 14 to the top of the channel region 16 included in the first transistor 12. At this time, in the actual manufacturing process, the second semiconductor layer 24 and the first semiconductor layer 23 for manufacturing the channel region 16 included in the first transistor 12 and the second transistor 14 can be formed on the first semiconductor substrate 22 and the second semiconductor substrate 26 respectively by epitaxy and other processes, and then the two are integrated by a bonding process. Since the first semiconductor layer 23 and the second semiconductor layer 24 are formed separately on the first semiconductor substrate 22 and the second semiconductor substrate 26, the restriction requirements on the materials of the first semiconductor layer 23 and the second semiconductor layer 24 are relatively low during epitaxy, which is conducive to realizing that the channel region 16 included in the first transistor 12 and the second transistor 14 has different crystal orientations and / or materials, so that the first transistor 12 and the second transistor 14 both have driving performance that meets the corresponding working requirements; of course, the channel region 16 included in the first transistor 12 and the second transistor 14 can also have the same crystal orientation and / or material, thereby improving the applicability of semiconductor devices in different application scenarios. Secondly, the dielectric bonding layer 13 for bonding the channel region 16 included in the first transistor 12 and the second transistor 14 is covered on the side of the first transistor 12 away from the substrate 11, and can isolate the source / drain region 17 and the gate stack structure 18 included in the first transistor 12 from the source / drain region 17 and the gate stack structure 18 included in the second transistor 14, respectively. In other words, the above-mentioned dielectric bonding layer 13 can not only realize the bonding between the channel region 16 included in the first transistor 12 and the second transistor 14, but also can isolate the first transistor 12 from the second transistor 14 to prevent leakage and interference. At the same time, there is no need to separately produce the corresponding insulating layer between the source / drain regions, the middle dielectric isolation layer between the upper and lower gate stack structures, and the shallow trench isolation structure that isolates different active areas as in the existing monolithic integration process, which is conducive to simplifying the manufacturing process of the three-dimensional stacked complementary transistor device.In addition, the description is made by taking the side of the first transistor 12 and the second transistor 14 where the gate spacer 15 is provided as the top and the other side as the bottom: in the first transistor 12 and the second transistor 14 respectively provided on both sides of the dielectric bonding layer 13 along its own thickness direction, the gate spacer 15 included in the first transistor 12 is provided on the side of the first transistor 12 along its own height direction close to the substrate 11, and the gate spacer 15 included in the second transistor 14 is provided on the side of the second transistor 14 along its own height direction away from the dielectric bonding layer 13. At this time, the bottoms of the first transistor 12 and the second transistor 14 are closer to the dielectric bonding layer 13. Based on this, in the actual manufacturing process, after the second semiconductor layer 24 and the first semiconductor layer 23 for manufacturing the channel region 16 included in the first transistor 12 and the second transistor 14 are bonded through the dielectric bonding layer 13, the first transistor 12 and the second transistor 14 are manufactured respectively in a direction away from the dielectric bonding layer 13, which can solve the problem of a higher aspect ratio vertical structure and more complex vertical integration caused by the simultaneous manufacture of N-type transistors and P-type transistors in the existing monolithic integration method, and is conducive to reducing the difficulty of manufacturing three-dimensional stacked complementary transistor devices.

[0067] In the actual manufacturing process, the embodiment of the present invention does not specifically limit the structure and material of the substrate, as long as it can be applied to the semiconductor device provided by the embodiment of the present invention. Exemplarily, the substrate can be a substrate made of any semiconductor material including silicon, silicon germanium or germanium, or a substrate made of any insulating material including silicon oxide, silicon nitride or silicon oxynitride.

[0068] For the above-mentioned first transistor and second transistor, from the aspect of conductivity type, the embodiment of the present invention does not specifically limit the conductivity type of the first transistor and the second transistor. The conductivity type of the second transistor can be N-type, and the conductivity type of the first transistor located below the second transistor is P-type. Alternatively, the conductivity type of the second transistor can also be P-type, and the conductivity type of the first transistor located below the second transistor is N-type.

[0069] Specifically, among all first transistors located in the same layer, the conductivity types of different first transistors may be the same, and in this case, among all second transistors located in the same layer, the conductivity types of different second transistors are also the same. For example: among all first transistors located in the same layer, the conductivity types of different first transistors are all P-type, and in this case, among all second transistors located in the same layer, the conductivity types of different second transistors are all N-type.

[0070] Alternatively, the conductivity type of at least one first transistor is different from the conductivity type of the remaining first transistors, and among all the second transistors located on the same layer, the conductivity type of at least one second transistor is different from the conductivity type of the remaining second transistors. For example: the conductivity type of at least one first transistor is N-type, the conductivity type of the remaining first transistors is P-type, and among all the second transistors located on the same layer, the conductivity type of the second transistor located above the P-type first transistor is N-type, and the conductivity type of the second transistor located above the N-type first transistor is P-type. In this case, the conductivity type of the first transistor and the second transistor of the corresponding position and / or corresponding function can be set according to different actual working requirements, while improving the integration of the semiconductor device, further improving the applicability of the semiconductor device in different application scenarios.

[0071] In terms of device types, the device types of the first transistor and the second transistor can be set according to actual needs and are not specifically limited here. Fig.23 and Fig.24 As shown, the first transistor 12 may be a fin field effect transistor or a ring-gate transistor. Among all the first transistors located in the same layer, the device types of different first transistors may be the same; for example, different first transistors may all be fin field effect transistors or ring-gate transistors. Alternatively, among all the first transistors located in the same layer, at least one first transistor is a fin field effect transistor, and the rest of the first transistors are ring-gate transistors.

[0072] As for the device type of the second transistor, such as Fig.23 and Fig.24 As shown, the second transistor 14 may be a fin field effect transistor or a ring-gate transistor. Among all the second transistors located in the same layer, the device types of different second transistors may be the same; for example, different second transistors may all be fin field effect transistors or ring-gate transistors. Alternatively, among all the second transistors located in the same layer, at least one second transistor is a fin field effect transistor, and the rest of the second transistors are ring-gate transistors.

[0073] In addition, if Figure 23 to Figure 26As shown, the device types of the first transistor 12 and the second transistor 14 may be the same or different. When the device types of the first transistor 12 and the second transistor 14 are different (such as one of the first transistor 12 and the second transistor 14 is a fin field effect transistor and the other is a ring-gate transistor), the device types of all the first transistors 12 in the same layer may be different from the device type of the second transistor 14, or only the device types of some of the first transistors 12 in the same layer may be different from the device type of the second transistor 14, and the first transistors 12 with different device types may be located directly below the second transistor 14 along the thickness direction of the substrate, or may be located obliquely below the second transistor 14.

[0074] From a structural point of view, the first transistor and the second transistor may both include a channel region, a source / drain region, a gate stack structure and a gate sidewall. Among them, in the same first transistor or the same second transistor, the source / drain region is located on both sides of the channel region along its own length direction, and is in contact with the channel region respectively. The gate stack structure is formed on the periphery of the channel region, and the gate stack structure may include a gate dielectric layer formed on the periphery of the channel region, and a gate formed on the gate dielectric layer. The above-mentioned gate sidewall is formed at least on both sides of the gate stack structure along its own length direction.

[0075] The structure of the channel region is different according to the device type of the first transistor and the second transistor. For example, when the first transistor and / or the second transistor is a fin field effect transistor, the channel region is a fin structure. For another example, when the first transistor and / or the second transistor is a ring-gate transistor, the channel region includes at least one layer of nanostructure, and each layer of nanostructure is spaced apart from the dielectric bonding layer.

[0076] In terms of materials, the materials of the channel region and the source / drain region may include any semiconductor material such as silicon, silicon germanium or germanium. When the material of the channel region included in the first transistor or the channel region included in the second transistor includes silicon germanium or germanium, the carrier mobility of the channel region may be improved, thereby improving the driving performance of the first transistor or the second transistor. Figures 1 to 26 As shown, in the actual manufacturing process, after the second semiconductor layer 24 and the first semiconductor layer 23 used to manufacture the channel region 16 included in the first transistor 12 and the second transistor 14 are bonded by the dielectric bonding layer 13, when the first transistor 12 is manufactured based on the second semiconductor layer 24, the second semiconductor layer 24 has been formed; and when the second transistor 14 is manufactured based on the first semiconductor layer 23, the first transistor 12 has been formed, so it is necessary to manufacture the first transistor 12 and the second transistor 14 at a relatively low temperature. At this time, the semiconductor device provided by the embodiment of the present invention is more compatible with low-temperature channel materials such as germanium silicon or germanium, and while improving the working performance of the semiconductor device, the yield of the semiconductor device can be improved.

[0077] Secondly, the material of the channel region included in the first transistor may be the same as or different from the material of the channel region included in the second transistor. The crystal orientation of the channel region included in the first transistor may be the same as or different from the crystal orientation of the channel region included in the second transistor.

[0078] As for the material of the gate stack structure, the material of the gate dielectric layer included in the gate stack structure may include any insulating material such as HfO2, ZrO2, TiO2 or Al2O3. The material of the gate may include any conductive material such as TiN, TaN or TiSiN. The material of the gate stack structure included in the first transistor may be the same as or different from the material of the gate stack structure included in the second transistor.

[0079] The material of the gate spacer may include any insulating material such as silicon oxide, silicon nitride or silicon oxynitride, as long as it can be applied to the semiconductor device provided in the embodiment of the present invention.

[0080] In addition, if Figure 23 to Figure 26 As shown, the semiconductor device may further include an interlayer dielectric layer 21. The interlayer dielectric layer 21 may be disposed on a side of the first transistor 12 away from the dielectric bonding layer 13, and / or disposed on a side of the second transistor 14 away from the dielectric bonding layer, so as to protect the source / drain region 17 from being affected by subsequent manufacturing processes and improve the yield of the semiconductor device.

[0081] For the dielectric bonding layer, the dielectric bonding layer may be a single-layer structure made of a single insulating material. For example, the material of the bonding isolation layer may be SiO2, SiCO, SiCON, Y2O3 or HfO2.

[0082] Or, if Figure 23 to Figure 26 As shown, the dielectric bonding layer 13 may also include at least two bonding sublayers stacked along the thickness direction of the substrate 11, and the material of at least one bonding sublayer is different from the materials of the remaining bonding sublayers. Specifically, the number of bonding sublayers included in the dielectric bonding layer 13, the material types of different bonding sublayers in the dielectric bonding layer 13, and the distribution of bonding sublayers of different materials can be set according to actual needs and are not specifically limited here.

[0083] In one example, if Figure 23 to Figure 26As shown, the semiconductor device may further include a first interconnect layer 19 disposed between the first transistor 12 and the substrate 11, and the first interconnect layer 19 is used to lead out the source / drain region 17 and the gate stack structure 18 included in the first transistor 12. In this case, the gate sidewall 15 of the first transistor 12 is disposed on the side of itself away from the dielectric bonding layer 13 (i.e., the side of the first transistor 12 close to the substrate 11). Based on this, when the first interconnect layer 19 is disposed between the first transistor 12 and the substrate 11, it is beneficial to shorten the vertical transmission path of the first interconnect layer 19 and reduce the transmission loss.

[0084] In one example, if Figure 23 to Figure 26 As shown, the semiconductor device may further include a second interconnect layer 20 disposed on the side of the second transistor 14 away from the dielectric bonding layer 13, and the second interconnect layer 20 is used to lead out the source / drain region 17 and the gate stack structure 18 included in the second transistor 14. In this case, the gate sidewall 15 of the second transistor 14 is disposed on the side away from the dielectric bonding layer 13. Based on this, when the second interconnect layer 20 is also disposed on the side of the second transistor 14 away from the dielectric bonding layer 13, it is beneficial to shorten the vertical transmission path of the second interconnect layer 20 and reduce the transmission loss.

[0085] As for the materials of the first interconnect layer and the second interconnect layer, they may include any conductive material such as silver, copper, aluminum or nickel, as long as they can be applied to the semiconductor device provided in the embodiment of the present invention.

[0086] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 1 to 26 The manufacturing process is described by a cross-sectional view or a stereoscopic view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0087] First, if Figures 1 to 10 As shown, a semiconductor structure is formed. Along the height direction of the semiconductor structure, the semiconductor structure includes a first semiconductor substrate 22, a first semiconductor layer 23, a dielectric bonding layer 13 and a second semiconductor layer 24 stacked in sequence. The first semiconductor layer 23 and the second semiconductor layer 24 are bonded together through the dielectric bonding layer 13.

[0088] Specifically, the second semiconductor layer is at least used to manufacture the channel region included in the first transistor. Therefore, the structure, material and thickness of the second semiconductor layer can be determined according to the device type of the first transistor, as well as the structure, material and size of the channel region, and are not specifically limited here.

[0089] For example, Figure 1As shown in part (2) of FIG. 1 , when the first transistor is a fin field effect transistor, the second semiconductor layer 24 may be a single-layer structure or a stacked structure in which different semiconductor materials are stacked along the thickness direction of the substrate 11 .

[0090] For example, Figure 1 As shown in part (1), when the first transistor is a ring-gate transistor, the second semiconductor layer 24 includes an alternately stacked first sacrificial layer 28 and a first channel layer 29. The film layer close to the dielectric bonding layer 13 in the alternately stacked first sacrificial layer 28 and the first channel layer 29 is the first sacrificial layer 28. Among them, the number of layers of the first channel layer 29 included in the second semiconductor layer 24 is equal to the number of layers of the nanostructure included in the channel region of the first transistor. In addition, in the alternately stacked first sacrificial layer 28 and the first channel layer 29, the film layer with the largest distance from the dielectric bonding layer 13 can be the first sacrificial layer 28, or it can be the first channel layer 29. Secondly, the material of the above-mentioned first sacrificial layer 28 can be any semiconductor material different from the first channel layer 29, as long as it can be applied to the manufacturing method provided in the embodiment of the present invention.

[0091] Similarly, the above-mentioned first semiconductor layer is at least used to manufacture the channel region included in the second transistor. Therefore, the structure, material and thickness of the first semiconductor layer can be determined according to the device type of the second transistor, as well as the structure, material and size of the channel region, and no specific limitation is made here.

[0092] For example, Figure 2 As shown in part (2) of FIG. 1 , when the second transistor is a fin field effect transistor, the first semiconductor layer 23 may be a single-layer structure or a stacked structure in which different semiconductor materials are stacked along the thickness direction of the substrate 11 .

[0093] For example, Figure 2 As shown in part (1), when the second transistor is a ring-gate transistor, the first semiconductor layer 23 includes an alternately stacked second sacrificial layer 30 and a second channel layer 31. The film layer close to the dielectric bonding layer 13 in the alternately stacked second sacrificial layer 30 and the second channel layer 31 is the second sacrificial layer 30. Among them, the number of layers of the second channel layer 31 included in the first semiconductor layer 23 is equal to the number of layers of the nanostructure included in the channel region of the second transistor. In addition, in the alternately stacked second sacrificial layer 30 and the second channel layer 31, the film layer with the largest distance from the dielectric bonding layer 13 can be the second sacrificial layer 30, or it can be the second channel layer 31. Secondly, the material of the above-mentioned second sacrificial layer 30 can be any semiconductor material different from the second channel layer 31, as long as it can be applied to the manufacturing method provided in the embodiment of the present invention.

[0094] As for the first semiconductor substrate, its material may include any semiconductor material such as silicon, silicon germanium or germanium. The material and structure of the dielectric bonding layer may refer to the above, and will not be described here.

[0095] In the actual manufacturing process, the above-mentioned formation of the semiconductor structure may include the following steps: Figure 1 As shown, epitaxy or deposition processes can be used to sequentially form a first semiconductor layer 23 and a first bonding sublayer 25 on the first semiconductor substrate 22 along the thickness direction of the first semiconductor substrate 22. Next, a second semiconductor substrate is provided, and Figure 2 As shown, epitaxy or deposition processes may be used to sequentially form a second semiconductor layer 24 and a second bonding sublayer 27 on the second semiconductor substrate 26 along the thickness direction of the second semiconductor substrate 26. Next, as shown in FIG. Figures 3 to 6 As shown, the first semiconductor layer 23 and the second semiconductor layer 24 are bonded together by a bonding process through a first bonding sublayer 25 and a second bonding sublayer 27; the dielectric bonding layer 13 includes the first bonding sublayer 25 and the second bonding sublayer 27. Next, as Figures 7 to 10 As shown, the second semiconductor substrate can be removed by at least one of dry etching, wet etching, and chemical mechanical polishing.

[0096] Specifically, the materials of the above-mentioned first bonding sublayer and the second bonding sublayer can be determined with reference to the materials and structures of the dielectric bonding layer described above. For example: when the dielectric bonding layer is a single-layer structure formed by a single material, the materials of the first bonding sublayer and the second bonding sublayer are the same. For another example: when the dielectric bonding layer is a stacked structure formed by at least two materials, at least part of the materials of the first bonding sublayer and the second bonding sublayer are different. In addition, by using epitaxy or deposition processes, before forming the first semiconductor layer and the first bonding sublayer on the first semiconductor substrate, a first etch stop layer can be formed on the first semiconductor substrate by using epitaxy or deposition processes. The material of the first etch stop layer is different from the material of the first semiconductor substrate and the first semiconductor layer, so that after the first semiconductor substrate is removed, it can stop at the first etch stop layer, reduce the impact on the first semiconductor layer, and improve the yield of the second transistor. Of course, the above-mentioned first etch stop layer may not be formed.

[0097] The process of forming the second semiconductor layer and the second bonding sublayer on the second semiconductor substrate can refer to the above description, and the process of forming the first semiconductor layer and the first bonding sublayer on the first semiconductor substrate will not be repeated here. Secondly, before forming the second semiconductor layer and the second bonding sublayer on the second semiconductor substrate, a second etch stop layer can be formed on the second semiconductor substrate, so that after removing the second semiconductor substrate, it can stop at the second etch stop layer, reduce the impact on the second semiconductor layer, and improve the yield of the first transistor. Of course, the above-mentioned second etch stop layer may not be formed.

[0098] In addition, a low-temperature bonding process can be used, and the first semiconductor layer and the second semiconductor layer can be bonded together through the first bonding sublayer and the second bonding sublayer to reduce the impact on the first semiconductor layer and the second semiconductor layer. Specifically, the bonding temperature of the above-mentioned low-temperature bonding process can be less than or equal to 800°C. Next, at least one of the processes such as dry etching, wet etching and chemical mechanical polishing can be used to remove the second semiconductor substrate. If the above-mentioned second etch stop layer is formed, it is also necessary to remove the second etch stop layer after removing the second semiconductor substrate to expose the second semiconductor layer.

[0099] Next, if Figures 11 to 18 As shown, a first transistor 12 is formed based on the second semiconductor layer 24, and a substrate 11 is formed on the side of the first transistor 12 away from the dielectric bonding layer 13. The gate spacer 15 included in the first transistor 12 is arranged on the side of the first transistor 12 close to the substrate 11 along its own height direction.

[0100] In an actual manufacturing process, the specific manufacturing process of the first transistor may be determined according to the device type of the first transistor, which is not specifically limited here.

[0101] For example, when the first transistor is a fin field effect transistor, Fig.11 As shown in part (2), the second semiconductor layer 24 can be etched by photolithography and etching to form a fin structure on the dielectric bonding layer 13. Fig.12 As shown in part (2), deposition and etching processes can be used to form a sacrificial gate 32 and a gate sidewall 15 across the fin structure. The material of the sacrificial gate 32 may include an easily removable material such as polysilicon. The gate sidewall 15 is formed on at least two sides of the sacrificial gate 32 along the length direction. Next, diffusion processes can be used to dope the portion of the fin structure exposed outside the sacrificial gate and the gate sidewall to form a source / drain region. Alternatively, as Fig.13 (2) Part and Fig.14As shown in part (2), dry etching or wet etching can also be used to remove the portion of the fin structure exposed outside the sacrificial gate 32 and the gate sidewall 15. In this case, the remaining fin structure is the channel region 16. Fig.15 As shown in part (2), epitaxial growth or other processes are used to form source / drain regions 17 on both sides of the channel region 16. Next, as Fig.16 As shown in part (2), deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 21 covering the dielectric bonding layer 13, and the top of the interlayer dielectric layer 21 is flush with the top of the sacrificial gate 32. Fig.17 As shown in part (2), the sacrificial gate can be removed by wet etching or dry etching. Fig.18 As shown in part (2), a gate stack structure 18 is formed by using processes such as atomic layer deposition to obtain the first transistor 12.

[0102] Exemplarily, when the first transistor is a gate-all-around transistor, Fig.11 As shown in part (1), the second semiconductor layer 24 can be etched by photolithography and etching to form a fin structure on the dielectric bonding layer 13. Fig.12 As shown in part (1), deposition and etching processes can be used to form a sacrificial gate 32 and a gate sidewall 15 across the fin structure. The material of the sacrificial gate 32 can include easily removable materials such as polysilicon. The gate sidewall 15 is formed on at least two sides of the sacrificial gate 32 along the length direction. Next, diffusion processes can be used to dope the portion of the fin structure exposed outside the sacrificial gate and the gate sidewall to form a source / drain region. Alternatively, as shown in FIG. Fig.13 (1) Part and Fig.14 As shown in part (1), dry etching or wet etching can also be used to remove the portion of the fin structure exposed outside the sacrificial gate 32 and the gate sidewall 15. Fig.15 As shown in part (1), epitaxy or other processes are used to form source / drain regions 17 on both sides of the remaining fin structure. Fig.16 As shown in part (1), deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 21 covering the dielectric bonding layer 13, and the top of the interlayer dielectric layer 21 is flush with the top of the sacrificial gate 32. Fig.17 As shown in part (1), a wet etching or dry etching process can be used to remove the sacrificial gate 32 and each remaining second sacrificial layer. At this time, the remaining second channel layer 31 is the channel region 16. Then, as shown in FIG. Fig.18 As shown in part (1), a gate stack structure 18 is formed by using processes such as atomic layer deposition to obtain a first transistor 12.

[0103] Specifically, in the actual manufacturing process, a low-temperature manufacturing process may be used to form the first transistor to improve the yield of the first transistor. The manufacturing temperature of the low-temperature manufacturing process may be less than 800°C.

[0104] In addition, after forming the first transistor, Fig. 20 As shown, a bonding process may be used to form a substrate 11 on a side of the first transistor 12 away from the dielectric bonding layer 13. The structure and material of the substrate 11 may be referred to above and will not be described again.

[0105] Exemplarily, in the case where the manufactured semiconductor device further includes a first interconnect layer, after forming the first transistor based on the second semiconductor layer and before forming the substrate on the side of the first transistor away from the dielectric bonding layer, the manufacturing method of the semiconductor device further includes the steps of: Fig.19 As shown, a first interconnection layer 19 is formed between the first transistor 12 and the substrate, and the first interconnection layer 19 is used to lead out the source / drain region 17 and the gate stack structure 18 included in the first transistor 12. Specifically, the first interconnection layer 19 can be formed by etching and physical vapor deposition processes, and the material of the first interconnection layer 19 can be referred to above and will not be repeated here.

[0106] Next, if Fig.21 As shown, the first semiconductor substrate can be removed by using a wet etching process or a dry etching process.

[0107] It should be noted that, when the first etch stop layer is formed, it is also necessary to use a wet etching or dry etching process to remove the first etch stop layer to expose the first semiconductor layer.

[0108] Next, if Figure 22 to Figure 26 As shown, a second transistor 14 is formed based on the first semiconductor layer 23. The conductivity type of the second transistor 14 is opposite to that of the first transistor 12 located below it. The gate sidewall 15 included in the second transistor 14 is arranged on the side of the second transistor 14 away from the dielectric bonding layer 13 along the height direction of the second transistor 14. The dielectric bonding layer 13 is used to bond at least the channel region 16 included in the second transistor 14 above the channel region 16 included in the first transistor 12, and to isolate the source / drain region 17 and the gate stack structure 18 included in the first transistor 12 from the source / drain region 17 and the gate stack structure 18 included in the second transistor 14, respectively.

[0109] Specifically, the formation process of forming the second transistor based on the first semiconductor layer can refer to the manufacturing process of forming the first transistor by the second semiconductor layer described above, which will not be repeated here. Secondly, a low-temperature manufacturing process can be used to form the second transistor to improve the formation quality and yield of the second transistor. The manufacturing temperature of the above-mentioned low-temperature manufacturing process can be less than 800°C.

[0110] It should be noted that the above-mentioned operations of manufacturing the first transistor based on the second semiconductor layer and manufacturing the second transistor based on the first semiconductor layer are not the main features of the embodiments of the present invention, so in this specification, only a brief introduction is given to them so that ordinary technicians in the field can easily implement the embodiments provided by the present invention. Ordinary technicians in the field can completely imagine other ways to manufacture the first transistor based on the second semiconductor layer and manufacture the second transistor based on the first semiconductor layer.

[0111] Exemplarily, in the case where the manufactured semiconductor device further includes a first interconnect layer, after forming the second transistor based on the first semiconductor layer, the manufacturing method of the semiconductor device further includes the steps of: Figure 22 to Figure 26 As shown, a second interconnection layer 20 is formed on the side of the second transistor 14 away from the dielectric bonding layer 13, and the second interconnection layer 20 is used to lead out the source / drain region 17 and the gate stack structure 18 included in the second transistor 14. Specifically, the second interconnection layer 20 can be formed by etching and physical vapor deposition processes, and the material of the second interconnection layer 20 can be referred to above and will not be repeated here.

[0112] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0113] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0114] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; A first transistor is arranged on the substrate; the gate sidewall included in the first transistor is arranged on a side of the first transistor close to the substrate along its own height direction; a dielectric bonding layer, covering a side of the first transistor facing away from the substrate; A second transistor is arranged on a side of the dielectric bonding layer away from the first transistor; the conductivity type of the second transistor is opposite to that of the first transistor located below the second transistor; the gate sidewall included in the second transistor is arranged on a side of the second transistor along its own height direction away from the dielectric bonding layer; the dielectric bonding layer is used to at least bond the channel region included in the second transistor above the channel region included in the first transistor, and to isolate the source / drain region and gate stack structure included in the first transistor from the source / drain region and gate stack structure included in the second transistor respectively.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a first interconnect layer disposed between the first transistor and the substrate, the first interconnect layer being used to lead out the source / drain region and the gate stack structure included in the first transistor; And / or, the semiconductor device further comprises a second interconnect layer disposed on a side of the second transistor away from the dielectric bonding layer, the second interconnect layer being used for leading out source / drain regions and a gate stack structure included in the second transistor.

3. The semiconductor device according to claim 1, wherein: The first transistor and the second transistor are both fin field effect transistors or gate-all-around transistors; And / or, one of the first transistor and the second transistor is a fin field effect transistor, and the other is a gate-all-around transistor.

4. The semiconductor device according to claim 1, wherein: Among all the first transistors located in the same layer, at least one of the first transistors is a fin field effect transistor, and the rest of the first transistors are gate-all-around transistors; And / or, among all the second transistors located in the same layer, at least one of the second transistors is a fin field effect transistor, and the rest of the second transistors are gate-all-around transistors.

5. The semiconductor device according to claim 1, wherein: Among all the first transistors located in the same layer, the conductivity type of at least one first transistor is different from the conductivity type of the other first transistors; and among all the second transistors located in the same layer, the conductivity type of at least one second transistor is different from the conductivity type of the other second transistors.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The material of the channel region included in the first transistor or the channel region included in the second transistor includes silicon germanium or germanium; And / or, a material of a channel region included in the first transistor is different from a material of a channel region included in the second transistor.

7. A method for manufacturing a semiconductor device, characterized in that: include: forming a semiconductor structure; Along the height direction of the semiconductor structure, the semiconductor structure comprises a first semiconductor substrate, a first semiconductor layer, a dielectric bonding layer and a second semiconductor layer which are stacked in sequence; the first semiconductor layer and the second semiconductor layer are bonded together through the dielectric bonding layer; A first transistor is formed based on the second semiconductor layer; and a substrate is formed on a side of the first transistor away from the dielectric bonding layer; a gate sidewall included in the first transistor is arranged on a side of the first transistor close to the substrate along its own height direction; removing the first semiconductor substrate; A second transistor is formed based on the first semiconductor layer; the conductivity type of the second transistor is opposite to that of the first transistor located below the second transistor; the gate sidewall included in the second transistor is arranged on the side of the second transistor along the height direction of the second transistor away from the dielectric bonding layer; the dielectric bonding layer is used to at least bond the channel region included in the second transistor above the channel region included in the first transistor, and to isolate the source / drain region and gate stack structure included in the first transistor from the source / drain region and gate stack structure included in the second transistor respectively.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The forming of the semiconductor structure comprises: sequentially forming the first semiconductor layer and the first bonding sublayer on the first semiconductor substrate along the thickness direction of the first semiconductor substrate; Providing a second semiconductor substrate, and sequentially forming the second semiconductor layer and the second bonding sublayer on the second semiconductor substrate along the thickness direction of the second semiconductor substrate; The first semiconductor layer and the second semiconductor layer are bonded together through the first bonding sublayer and the second bonding sublayer; the dielectric bonding layer includes the first bonding sublayer and the second bonding sublayer; The second semiconductor substrate is removed.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: After forming the first transistor based on the second semiconductor layer and before forming the substrate on the side of the first transistor away from the dielectric bonding layer, the method for manufacturing a semiconductor device further comprises: forming a first interconnection layer disposed between the first transistor and the substrate, the first interconnection layer being used to lead out the source / drain region and the gate stack structure included in the first transistor; And / or, after the second transistor is formed based on the first semiconductor layer, the method for manufacturing the semiconductor device also includes: forming a second interconnect layer arranged on the side of the second transistor away from the dielectric bonding layer, the second interconnect layer being used to lead out the source / drain regions and gate stack structure included in the second transistor.

10. The method for manufacturing a semiconductor device according to claim 7, wherein: In the case where the first transistor is a gate-all-around transistor, the second semiconductor layer includes alternately stacked first sacrificial layers and first channel layers; a film layer close to the dielectric bonding layer in the alternately stacked first sacrificial layers and first channel layers is the first sacrificial layer; And / or, in the case where the second transistor is a ring-gate transistor, the first semiconductor layer includes alternately stacked second sacrificial layers and second channel layers; the film layer close to the dielectric bonding layer in the alternately stacked second sacrificial layers and second channel layers is the second sacrificial layer.

11. The method for manufacturing a semiconductor device according to any one of claims 7 to 10, characterized in that: The first transistor and / or the second transistor are formed by adopting a low temperature manufacturing process; the manufacturing temperature of the low temperature manufacturing process is less than 800°C.

12. The method for manufacturing a semiconductor device according to any one of claims 7 to 10, characterized in that: The substrate is formed on a side of the first transistor away from the dielectric bonding layer by using a bonding process.

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