Semiconductor structure and forming method thereof

Abstract

The present disclosure is directed to a semiconductor structure having a source / drain epitaxial stack having a low melting point top layer and a high melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin that is not covered by the gate structure. Further, the semiconductor structure includes a source / drain epitaxial stack disposed in the recess, where the source / drain epitaxial stack has a bottom layer and a top layer, the top layer having a higher active dopant concentration than the bottom layer. The embodiment of the invention also provides a method for forming the semiconductor structure.

Description

[0001] This application is a divisional application of the invention patent application entitled “Semiconductor structure and method for forming the same” with application number 202010644475.X filed on July 7, 2020. Technical Field

[0002] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0003] Dopants in semiconductor materials can only act as donors or acceptors if they are part of the semiconductor lattice structure. For this reason, dopants in semiconductor materials (e.g., silicon) need to be activated. An activated dopant can act as a donor or acceptor of electrons, e.g., equivalent to an n-type or p-type dopant with respect to the semiconductor material. If a dopant occupies interstitial spaces in a semiconductor material, it is considered not activated and is ineffective as a dopant (e.g., it cannot act as a donor or acceptor). Thermal energy can be supplied to the doped semiconductor material to move the dopant from the interstitial spaces to the crystalline position, a process known as "activation" or "crystal activation." Summary of the invention

[0004] Some embodiments of the present invention provide a semiconductor structure, comprising: a fin, disposed on a substrate, wherein the fin and the substrate comprise semiconductor material; a gate structure, disposed on the fin, wherein the gate structure wraps a portion of a sidewall surface of the fin; a groove, formed in a portion of the fin adjacent to the gate structure; a source / drain epitaxial stack, disposed in the groove and comprising: a bottom layer; and a top layer having an activated dopant concentration higher than that of the bottom layer; and a contact structure, disposed on the top layer of the source / drain epitaxial stack, wherein the contact is adjacent to the gate structure.

[0005] Some other embodiments of the present invention provide a method for forming a semiconductor structure, comprising: forming a fin on a substrate; forming a sacrificial gate structure on the fin, wherein the sacrificial gate structure wraps a portion of the top surface of the fin and a portion of the sidewall surface of the fin; recessing a portion of the fin not covered by the sacrificial gate structure; forming a source / drain epitaxial stack in the recessed portion of the fin, wherein forming the source / drain epitaxial stack comprises: growing a bottom layer having a crystalline microstructure; and growing a top layer having an amorphous microstructure on the bottom layer, wherein the top layer has a melting point different from that of the bottom layer; and annealing the source / drain epitaxial stack with a laser to form a melting front in the top layer.

[0006] Still other embodiments of the present invention provide a method for forming a semiconductor structure, comprising: forming a fin on a substrate; forming a gate structure on the fin; recessing a portion of the fin not covered by the gate structure; and forming a source / drain epitaxial stack on the recessed portion of the fin, wherein forming the source / drain epitaxial stack comprises: depositing a first layer comprising a first dopant; and depositing a second layer comprising a second dopant, wherein the second layer is disposed on the first layer and has a lower melting point than the first layer; and exposing the source / drain epitaxial stack to an annealing source to activate the first dopant in the first layer and the second dopant in the second layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 is a partial cross-sectional view of an exemplary array of transistor structures formed on fins during a laser annealing process and having single crystalline source / drain stacks in accordance with some embodiments.

[0009] Figure 2 is a partial cross-sectional view of a transistor structure having a source / drain epitaxial stack with an amorphous low-melting-point top layer and a single-crystalline high-melting-point bottom layer during a laser annealing process according to some embodiments.

[0010] Figure 3 is a schematic diagram of a secondary ion mass spectroscopy (SIMS) curve and a spread resistivity curve (SRP) overlay for a source / drain epitaxial stack having a top low melting point top layer and a bottom high melting point top layer after a laser annealing process according to some embodiments.

[0011] Figure 4 is a cross-sectional view of a transistor structure having a source / drain epitaxial stack with a laser annealed single crystalline top layer and a single crystalline bottom layer, according to some embodiments.

[0012] Figure 5 is a flow chart of a method for forming a source / drain epitaxial stack having a low melting point top layer and a high melting point bottom layer according to some embodiments.

[0013] Figure 6 is a partial cross-sectional view of a transistor structure along the x and y directions according to some embodiments.

[0014] Figure 7is a partial cross-sectional view of a recessed fin portion of a transistor structure along x and y directions according to some embodiments.

[0015] Figure 8 is a partial cross-sectional view of a transistor structure after forming a source / drain epitaxial stack having a low melting point top layer and a high melting point bottom layer on a recessed portion of a fin along x and y directions according to some embodiments.

[0016] Fig. 9 is a partial cross-sectional view of a transistor structure after forming contacts on a source / drain epitaxial stack having a low melting point top layer and a high melting point bottom layer along x and y directions according to some embodiments.

[0017] Fig.10 is a partial cross-sectional view of a transistor structure along the x and y directions according to some embodiments.

[0018] Fig.11 is a partial cross-sectional view of a recessed fin portion of a transistor structure along x and y directions according to some embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0020] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0021] As used herein, the term "nominal" refers to the expected or target value for a characteristic or parameter of a component or process operation, as set during the design phase of a product or process, and a range of values ​​above and / or below the expected value. The range of values ​​is typically due to slight variations in manufacturing processes or tolerances.

[0022] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). In some embodiments, the terms "about" and "substantially" indicate other values ​​based on, for example, the capabilities provided by a manufacturing process, manufacturing operation, or manufacturing tool.

[0023] As used herein, the term "vertical" refers to being nominally perpendicular to the surface of a substrate.

[0024] Diffusion is a basic property that describes the movement of one material (e.g., a dopant) through another material (e.g., a semiconductor matrix). Diffusion occurs from areas of relatively high dopant concentration to areas of lower dopant concentration. Different dopant species within a semiconductor matrix material may have different diffusivities, such as silicon (Si), silicon germanium (SiGe), silicon carbon (SiC), or silicon phosphorus (SP); and the higher the diffusivity, the faster the dopant migrates into the semiconductor matrix material. Since the diffusion rate of dopants in semiconductor matrix materials increases with temperature, thermal diffusion is the primary mechanism used in semiconductor manufacturing to move dopants through the semiconductor lattice. There are two basic methods of providing heat energy for dopant diffusion: furnace annealing and rapid thermal annealing (RTA).

[0025] Furnace annealing is a method of annealing a semiconductor matrix material (e.g., a semiconductor wafer) in a hot furnace, for example, between about 800° C. and about 910° C. for a time of about 30 minutes. However, an annealing cycle with such a duration and temperature may result in a large amount of (e.g., not strictly controlled) dopant diffusion, which is undesirable for some integrated circuit manufacturing processes (e.g., source / drain activation). In addition, furnace annealing does not apply local heating, but rather global heating. That is, each layer and / or structure present on the semiconductor material during furnace annealing is subjected to high temperature for the duration of the annealing process. This may limit the manufacture of integrated circuits (ICs).

[0026] The RTA process anneals semiconductor materials by using a fast ramp (e.g., in the millisecond (ms) or nanosecond (ns) range) and a short dwell time (e.g., in the second or sub-second range) at a target temperature (e.g., about 910°C or higher). In addition, RTA can be selective and heat can be provided locally or globally. Types of RTA include thermal annealing using lamps (e.g., tungsten halogen lamps) or lasers (e.g., laser annealing). RTA using lamps can be a global anneal because the semiconductor surface (e.g., the top, bottom, or both) is exposed to the lamp at once. Laser annealing, on the other hand, is a global anneal because of its beam size (e.g., at about 25 mm 2 and about 100mm 2Due to this feature, laser annealing is the preferred method for source / drain dopant activation in IC manufacturing.

[0027] By way of example and not limitation, during the laser annealing process, a pulsed laser beam is scanned over a semiconductor surface (e.g., the surface of a semiconductor wafer) at a speed of about 100 mm / s. Due to the size of the laser beam (e.g., at about 25 mm / s), the 2 To about 100mm 2 The depth of annealing can be controlled by process conditions such as laser energy or wavelength, the number of pulses at each location, and the dwell time of the laser beam (e.g., the time the laser is applied at each location).

[0028] However, even with a laser annealing process, dopant activation for the source / drain epitaxial layers can be challenging. This is because the source / drain regions of the transistor are smaller compared to the size of the laser beam. This problem is exacerbated by the size of the transistor and its source / drain regions, which shrink with each technology generation (e.g., with each technology node). For example, as the source / drain regions shrink, heat from the laser beam can propagate to regions outside the source / drain regions, such as the fin region located between the source and drain regions of the transistor. This can be achieved by Figure 1 To describe, Figure 1 1 is a partial cross-sectional view along the x-axis of an exemplary array of transistor structures 100 formed on a fin structure 110 and having a single crystal source / drain stack 120 and a channel region 130. The fin 110 is disposed on a substrate 140. When the laser beam 150 begins to scan the surface of the substrate 140, the heat generated by the laser beam 150 forms a melting front 160 that extends to the outside of the single crystal source / drain stack 120 (e.g., to the fin 110 and the channel region 130). As a result, the fin 110 may be deformed, which impairs the electrical characteristics of the transistor. In order to reduce fin deformation, it is necessary to modify the laser annealing conditions so as to reduce the heat generated by the laser beam and better control the melting front 160. However, reducing the heat generated by the laser beam may affect the dopant activation process within the single crystal source / drain stack 120. For example, less dopants will be activated due to this change.

[0029] To address these challenges, the embodiments described herein are directed to the formation of a source / drain epitaxial stack having a low melting point "top" layer and a high melting point "bottom" layer. In some embodiments, the low melting point top layer is deposited polycrystalline or amorphous, while the high melting point bottom layer is deposited single crystalline. In other embodiments, the low melting point top layer and the high melting point bottom layer are both deposited single crystalline or polycrystalline, but have different stoichiometries. In some embodiments, the deposited amorphous low melting point top layer is recrystallized due to the laser annealing process and has a higher defect density than the high melting point bottom layer. In addition, due to the laser annealing process, the low melting point top layer exhibits a higher activated dopant concentration compared to the high melting point bottom layer. In some embodiments, only the dopants in the low melting point top layer are activated during the laser annealing process. According to some embodiments, a laser beam with reduced power can be used for the source / drain epitaxial stack disclosed herein. Therefore, fin deformation during the laser annealing process can be avoided.

[0030] Figure 2 is a cross-sectional view of an exemplary transistor structure 200 formed on a semiconductor fin 210 across the x-axis. It should be noted that the length of the fin is parallel to Figure 2 The x-axis is shown. The semiconductor fin 210 is disposed on the semiconductor substrate 220 and is recessed to facilitate the formation of the source / drain epitaxial stack 230. The semiconductor fin 210 is laterally isolated from other transistor structures via an isolation layer 240. In some embodiments, each source / drain epitaxial stack 230 includes a deposited amorphous low-melting point top layer 230A and a deposited single crystal high-melting point bottom layer 230B. As used herein, a "top" layer refers to a layer placed (or disposed) away from the semiconductor substrate 220 along the z-axis, while a "bottom" layer refers to a layer placed (or disposed) closer to the semiconductor substrate 220 along the z-axis. In addition, as used herein, the term "amorphous" also encompasses polycrystalline microstructures (e.g., microstructures having a short-range lattice periodicity).

[0031] According to some embodiments, the dopant and semiconductor matrix material included in the source / drain epitaxial stack 230 may be selected based on the type of transistor structure 200 (e.g., whether transistor structure 200 is an n-type field effect transistor (nFET) or a p-type field effect transistor (pFET)). In some embodiments, the source / drain epitaxial stack of the nFET (e.g., the n-type source / drain epitaxial stack) includes a strained silicon carbon (SiC) layer or a strained silicon phosphorus (SiP) layer doped with phosphorus (P), while the source / drain epitaxial stack of the p-type field effect transistor (pFET) (e.g., the p-type source / drain epitaxial stack) includes a strained silicon germanium (SiGe) layer doped with boron (B). According to some embodiments, the amount of P incorporated into the n-type source / drain epitaxial stack may be as high as 1×10 21 Atom / cm -3, and the amount of B incorporated into the p-type source / drain epitaxial stack can be as high as about 1×10 21 Atom / cm -3 As an example and not limitation, P and B dopants may be incorporated into the layers of the source / drain epitaxial stack 230 during growth with suitable precursors. In addition, both the amorphous low melting point top layer 230A and the single crystal high melting point bottom layer 230B may be grown to have substantially equal P or B concentrations.

[0032] In some embodiments, the melting point of the deposited amorphous low melting point top layer 230A is about 1420K (e.g., about 1147°C), while the melting point of the single crystal high melting point bottom layer 230B is greater than about 1687K (e.g., 1414°C); however, both layers contain the same materials and are substantially equal in stoichiometry—e.g., substantially equal Si / Ge ratios for SiGe source / drain epitaxial stacks; and substantially equal Si / C ratios for SiC source / drain epitaxial stacks, or substantially equal Si / P ratios for SiP source / drain epitaxial stacks. According to some embodiments, the difference in melting points between the top and bottom layers in the source / drain epitaxial stack 230 is attributed to their microstructures (e.g., amorphous rather than single crystal). In this example, the single crystal high melting point bottom layer 230B has a higher melting point (e.g., a difference of about 267K or about 267°C) than the amorphous low melting point top layer 230A. However, this is not limiting, and a lower melting point difference can be used between the low melting point layer and the high melting point layer—for example, greater than about 200K. A threshold value of a melting point difference greater than about 200K (e.g., 267K) can ensure that the melting front is "selectively" formed by the laser beam during the laser annealing process and contained within the amorphous low melting point top layer 230A, while the single crystal high melting point bottom layer 230B remains solid. If the melting point difference between the above layers is equal to or less than about 200K, the melting front formed by the laser beam may extend beyond the boundary of the amorphous low melting point top layer 230A—for example, to the high melting point bottom layer 230B and the fin region. As previously described, this is undesirable. Therefore, as long as the heat generated by the laser beam during the laser annealing process raises the temperature of the source / drain epitaxial stack 230 to above the melting point of the amorphous low melting point top layer 230A and below the melting point of the single crystal high melting point bottom layer 230B, the above selectivity can be achieved. In some embodiments, during the laser annealing process, the temperature of the source / drain epitaxial stack 230 is equal to or greater than the melting point of the amorphous low-melting-point top layer 230A, and is equal to or less than the melting point of the single-crystalline high-melting-point bottom layer 230B (e.g., the melting point temperature of the amorphous low-melting-point top layer ≤ the temperature of the laser annealing process ≤ the melting point temperature of the single-crystalline high-melting-point bottom layer). In this operation window, a layer such as Figure 1The melting region of the melting region 160 is shown. In some embodiments, the melting point of the amorphous low-melting-point top layer 230A is also lower than the melting point of the surrounding materials such as the semiconductor fin 210, which is about 1687K in the case of crystalline silicon (e.g., closer to the melting point of the single-crystalline high-melting-point bottom layer 230B). Therefore, during the laser annealing process, deformation of the semiconductor fin 210 can be minimized or avoided.

[0033] Since less heat is required to form a melting front in the amorphous low melting point top layer 230A (e.g., due to the melting point of the amorphous layer), the power of the laser beam can be reduced. For example, if the source / drain epitaxial stack includes only a single crystalline layer (such as a single crystalline high melting point bottom layer 230B), the laser beam will need to operate at, for example, about 910 Joules to form a melting front and activate the dopant (e.g., B or P). At this power level, the laser beam will also generate enough heat to deform the semiconductor fin 210, which has a melting point substantially comparable to the single crystalline layer of the source / drain epitaxial stack. On the other hand, according to some embodiments, for a source / drain epitaxial stack 230 including a deposited amorphous low melting point top layer 230A and a single crystalline bottom layer 230B, the laser beam will need to generate less heat and therefore operate at a lower power setting (e.g., 500 Joules), which is a reduction of about 50%.

[0034] In some embodiments, the amorphous low-melting top layer 230A is grown to occupy between about 30% and about 75% of the total thickness of the source / drain epitaxial stack 230. In other words, referring to Figure 2, the thickness T1 of the deposited amorphous low melting point top layer 230A may be between about 30% and about 75% of the total thickness T of the source / drain epitaxial stack 230 (e.g., 30%T≤T1≤75%T or 0.30≤T1 / T≤0.75). In some embodiments, the single crystalline high melting point bottom layer 230B acts as a diffusion barrier for dopants of the amorphous low melting point top layer 230A during the laser annealing process. This is because a melting front is not formed in the single crystalline high melting point bottom layer 230B, and thus the dopants diffusing from the amorphous low melting point top layer 230A into the single crystalline high melting point bottom layer 230B are slowed down (e.g., blocked). If the thickness T1 of the amorphous low-melting top layer 230A is greater than about 75% of the total thickness T of the source / drain epitaxial stack 230 (e.g., T1 / T>0.75), the single crystalline high-melting bottom layer 230B will not have sufficient thickness to prevent the diffusion of dopants from the amorphous low-melting top layer 230A. Therefore, less dopants within the amorphous low-melting top layer 230A will be activated, which in turn may increase the resistance of the source / drain epitaxial stack 230. In addition, the diffusion of dopants may form undesirable leakage paths between the source / drain epitaxial stack 230 and the doped regions of the semiconductor fins 210 and / or the semiconductor substrate 220. Furthermore, a thicker amorphous low-melting top layer 230A may require a longer dwell time or / and a higher laser beam power setting during the laser annealing process, both of which may adversely affect process time and cost. On the other hand, if the thickness T1 of the amorphous low-melting point top layer 230A is less than about 30% of the total thickness T (eg, T1 / T<30%), the amount of dopant activated in the top layer may be insufficient to provide acceptable resistance for the source / drain epitaxial stack 230 .

[0035] In some embodiments, the microstructure and thus the melting point of the deposited amorphous low melting point top layer 230A and the single crystal high melting point bottom layer 320B can be adjusted via their respective growth conditions, such as growth temperature and pressure. For example, and according to some embodiments, the single crystal high melting point bottom layer 230B can be grown at a temperature between about 650°C and about 800°C and at a pressure between about 20 Torr and about 300 Torr. Conversely, the amorphous low melting point top layer 230A can be grown at a temperature between about 450°C and about 600°C and at a pressure between about 300 Torr and about 400 Torr. In other words, a single crystal layer can be epitaxially grown at a "higher" temperature and a "lower" pressure compared to an amorphous epitaxial layer that can be grown at a "lower" temperature and a "higher" pressure. In some embodiments, the above conditions can be equally applied to the growth of p-type (e.g., B-doped SiGe) and n-type (e.g., P-doped SiC and SiP) source / drain epitaxial layers.

[0036] In some embodiments, the single crystal high melting point bottom layer 230B and the amorphous low melting point top layer 230A are grown in situ in the same process reactor (e.g., without vacuum break). For example, by using a heating lamp, a rapid process temperature change (e.g., within about 10 s to about 20 s) can be achieved. In some embodiments, the single crystal high melting point bottom layer 230B and the amorphous low melting point top layer 230A are grown by a chemical vapor deposition (CVD) process.

[0037] In some embodiments, the amorphous low-melting-point top layer 230A may be formed by a pre-amorphization implantation (PAI) process. For example, the source / drain epitaxial stack 230 may initially include only a single crystalline layer with a total thickness T, such as Figure 1 A single crystalline source / drain stack 120 is shown. The PAI process using implantation consumes a portion of the single crystalline layer and converts it into an amorphous layer via implant ion bombardment. The type of implantation, the amount of implantation, and the implantation energy are parameters that can be used to fine tune the thickness of the amorphous layer.

[0038] In some embodiments, Ge or tin (Sn) implantation may be used for SiGe source / drain epitaxial stacks, while Si implantation may be used for SiC or SiP source / drain epitaxial stacks. By way of example and not limitation, at an accelerating voltage between about 3 keV and about 20 keV, at about 1×10 14 cm -2 and about 5×10 14 cm -2 A Ge or Sn dosage between about 1×10 15 cm -2 and about 5×10 15 cm -2 In some embodiments, if the amorphous low melting point top layer 230A is formed using the PAI method, the amorphous low melting point top layer 230A and the single crystal high melting point bottom layer 230B may have different Si / Ge and Si / C or Si / P ratios.

[0039] After forming the amorphous low-melting top layer 230A, the source / drain epitaxial stack 230 is subjected to a laser annealing process, for example, via a scanning laser beam 250, to activate dopants in the amorphous low-melting top layer 230A. As described above, the amorphous low-melting top layer 230A has a low melting point (e.g., less than about 200K) compared to the bottom single crystal high melting point bottom layer 230B. In addition, the power of the laser beam 250 has been adjusted based on the melting point difference between the two layers so that a melting front is selectively formed on the amorphous low-melting top layer 230A while the bottom single crystal layer remains solid. In some embodiments, the laser beam 250 has a wavelength between about 308 nm and about 532 nm and an annealing depth between about 7 nm and about 1200 nm (e.g., measured from the top surface of the amorphous low-melting top layer 230A). In some embodiments, the annealing depth corresponds to the thickness T1 of the top amorphous layer 203A. As described above, the laser beam 250 covers about 25 mm. 2 and about 100mm 2 The area between (e.g., about 25 mm 2 To about 30mm 2 ) and has a scanning speed of about 100 mm / s. In addition, the laser beam 250 is pulsed between about 1 and 10 times at each position, and the duration of each pulse is between about 20 ns and 150 ns. As an example and not limitation, the annealing process can be implemented in nitrogen or another inert gas environment (e.g., argon, helium, xenon, etc.).

[0040] The above laser beam characteristics are not intended to be limiting, and values ​​outside these ranges may be used depending on conditions, such as: (i) the thickness of the amorphous low-melting top layer 230A and the bottom single-crystalline high-melting bottom layer 230B; and (ii) the melting point difference between the amorphous low-melting top layer 230A and the bottom single-crystalline high-melting bottom layer 230B. As an example and not a limitation, for thicker amorphous low-melting top layer 230A (e.g., when T1 / T is close to about 0.75), a combination of longer pulse duration (e.g., about 150 ns) and increased number of pulses (e.g., 10) may be used to achieve a higher annealing depth (e.g., 1200 nm); while for shallower annealing depths (e.g., about 7 nm), fewer and / or shorter pulses may be used.

[0041] The wavelength of the beam can also be adjusted based on other laser beam considerations (e.g., number of pulses, pulse duration, scanning speed, etc.) and layer characteristics (e.g., thickness and melting point of the amorphous low-melting top layer 230A) to achieve the desired heat output. For example, assuming all other laser beam characteristics are the same, a laser beam with a short wavelength (e.g., about 300 nm) with a low absorption depth can be used for a thin amorphous low-melting top layer 230A (e.g., about 10 nm), while a laser beam with a long wavelength (e.g., about 500 nm) with a higher absorption depth can be used for a thick amorphous low-melting top layer 230A (e.g., about 100 nm). In both cases, the laser power can be substantially the same and range, for example, between about 200 Joules and 400 Joules.

[0042] In some embodiments, the laser annealing process described above activates the dopant (e.g., B or P) in the amorphous low-melting top layer 230A. For p-type and n-type stacks (e.g., SiGe, SiC, or SiP), the activated carrier concentration in the top layer of the source / drain epitaxial stack 230 can be from about 1×10 20 cm -3 About 1×10 21 cm -3 In some embodiments, the dopant activation process occurs primarily in the low-melting top layer (e.g., the amorphous low-melting top layer 230A) and only partially in the single-crystal high-melting bottom layer (e.g., the single-crystal high-melting bottom layer 230B). In some embodiments, the low-melting top layer may produce an activated carrier concentration substantially equal to its chemical dopant concentration (e.g., an activation rate of about 100%), while the high-melting bottom layer may produce an activated carrier concentration less than its chemical dopant concentration (e.g., an activation rate less than 100%). For example, in the above case, the low-melting top layer 230A may produce an activated carrier concentration of up to about 1×10 21 cm -3 The activated carrier concentration of the high melting point bottom layer 230B can be limited to as high as about 1×10 20 cm -3 Thus, in some embodiments, even if dopant activation occurs throughout the source / drain epitaxial stack 230 (e.g., in both the low-melting point and high-melting point layers), the low-melting point top layer 230A will still produce a higher concentration of activated dopants (e.g., about an order of magnitude higher) than the high-melting point bottom layer 230B.

[0043] In some embodiments, Figure 3 This shows that dopants can be prevented from diffusing outside the source / drain epitaxial stack. Figure 3 It is a superposition of a secondary ion mass spectrometry (SIMS) curve represented by curve 300 and a spread resistivity curve (SRP) represented by curve 310 . Figure 3 The y-axis of is logarithmic and represents the concentration of dopants and activated dopants (eg, carriers). The x-axis represents the depth within the source / drain epitaxial stack 230. For example, Figure 3 The origin of the xy graph in corresponds to the top surface of the source / drain epitaxial stack 230. In some embodiments, curves 300 and 310 represent the top surface of the source / drain epitaxial stack 230, respectively. Figure 2 More specifically, SIMS curve 300 corresponds to the total dopant concentration (e.g., B or P) across the source / drain epitaxial stack 230, and SRP curve 310 corresponds to the activated dopant concentration across the source / drain epitaxial stack 230. Figure 3 As shown, both curves 300 and 310 show a sharp drop in dopant and carrier concentration near the interface with semiconductor fin 210. In some embodiments, slope 320 is about 2.6 nm / decade and demonstrates that the carrier and dopant concentration in source / drain epitaxial stack 230 does not diffuse into semiconductor fin 210.

[0044] In some embodiments, the deposited amorphous low-melting top layer 230A recrystallizes as it cools after the laser annealing process. For example, the amorphous low-melting top layer 230A may be transformed into a single crystal layer. Figure 4 Shown in Figure 2 2 , wherein the deposited amorphous low-melting-point top layer 230A has been transformed into a laser-annealed single-crystalline top layer 400. In some embodiments, the single-crystalline top layer 400 has a Figure 2 The as-deposited amorphous low-melting-point top layer 230A is shown to have a substantially equal thickness T1. In addition, the thickness T of the source / drain epitaxial stack 230 is substantially the same before and after the laser annealing process.

[0045] In some embodiments, the interface 410 (e.g., the interface between the top single crystal layer 400 and the bottom single crystal layer 230B of the laser annealed source / drain epitaxial stack) can have a rough (e.g., coarse) surface morphology, which can be detected by transmission electron microscopy (TEM) imaging. In some embodiments, the interface 410 also appears rougher (e.g., coarser) than the top surface 420 of the top single crystal top layer 400, which can also be detected by TEM imaging. In some embodiments, after the laser annealing process, the top surface roughness of the low melting point top layer 230A is reduced by about 6 times. For example, the root mean square (RMS) top surface roughness of the low melting point top layer 230A can be about 3 nm, and the RMS top surface roughness of the single crystal top layer 400 (e.g., the annealed top layer 230A) can be about 0.5 nm. In addition, the laser annealed single crystal top layer 400 has a higher defect density (e.g., the number of dislocations per unit area) than the bottom single crystal high melting point bottom layer 230B. This is because the laser annealed single crystal top layer 400 undergoes a recrystallization process when transforming from an amorphous or polycrystalline layer to a single crystal layer. For example, the single crystal top layer 400 may have a thickness of about 1×10 18 Dislocation / cm 2 , and the single crystal high melting point bottom layer 230B may have a thickness of about 1×10 16 Dislocation / cm 2 , for example, about two orders of magnitude fewer dislocations per unit area. In some embodiments, due to the defect density difference between the two layers in the source / drain epitaxial stack 230, the laser annealed single crystal top layer 400 generates compressive strain, while the single crystal high melting point bottom layer 230B generates tensile strain or less compressive strain compared to the laser annealed single crystal top layer 400. In other words, the strain type or strain magnitude between the laser annealed single crystal top layer 400 and the single crystal high melting point bottom layer 230B may be different.

[0046] In some embodiments, the low melting point top layer may include a different material than the high melting point bottom layer, or the same material but with a different stoichiometry. In addition, both the low melting point top layer and the high melting point bottom layer may be single crystal layers. As an example and not limitation, in the case of a p-type source / drain epitaxial stack, the low melting point top layer may include single crystal SiGe with a Ge concentration between about 20% and about 40%, while the high melting point bottom layer may include single crystal silicon without a significant amount of Ge. In some embodiments, incorporating Ge in Si reduces the melting point of the resulting SiGe layer. For example, the melting point of a SiGe layer with about 40% Ge is lower than the melting point of a SiGe layer with about 20% Ge, and the melting point of a SiGe layer with about 20% Ge is lower than Si without a significant amount of Ge.

[0047] According to some embodiments, in the case of an n-type source / drain epitaxial stack, the low melting point top layer may include a single crystal SiC layer with a low carbon concentration, and the high melting point bottom layer may include a single crystal SiC layer with a high carbon concentration, wherein the difference between the low carbon concentration and the high carbon concentration is approximately 2%.

[0048] In some embodiments, each of the above layers is grown by CVD at a temperature range between about 650° C. and about 800° C. and at a pressure between about 20 Torr and about 300 Torr. According to some embodiments, in order to grow single-crystalline high-melting point and low-melting point layers, a process temperature above about 650° C. and a process pressure below about 300 Torr are required. Due to the laser annealing process, both the low-melting point top layer and the high-melting point bottom layer can produce the same type of strain (e.g., compression or tension), and the activated dopant concentration in the single-crystalline top layer will be greater than the activated dopant concentration in the single-crystalline bottom layer. In some embodiments, the strain gain after annealing for compressive type stress is about 0.8 GPa.

[0049] In other embodiments, the low melting point top layer may include a different material from the high melting point bottom layer, or the same material but with a different stoichiometry. In addition, both the low melting point top layer and the high melting point layer may be polycrystalline or amorphous layers with appropriately adjusted melting points (e.g., a melting point difference of at least 200K). As an example and not limitation, in the case of a p-type source / drain epitaxial stack, the low melting point top layer may include a polycrystalline or amorphous SiGe having a Ge concentration between about 20% and about 40%, while the high melting point bottom layer may include a polycrystalline or amorphous Si without a significant amount of Ge. In some embodiments, as described above, incorporating Ge into Si reduces the melting point of the resulting SiGe layer. For example, the melting point of the amorphous Si layer is about 1420K, while the melting point of the amorphous Ge layer is between about 965K and 1024K. Therefore, by introducing Ge into the amorphous Si layer and controlling the Ge concentration, the melting point of the resulting layer can be adjusted to be higher than about 965K and lower than about 1420K. Therefore, as previously discussed, the concentration of Ge in the Si layer can be adjusted to achieve a desired melting temperature difference of greater than about 200K.

[0050] In the case of an n-type source / drain epitaxial stack, the low melting point top layer may include polycrystalline or amorphous SiC with a low carbon concentration, and the high melting point bottom layer may include polycrystalline or amorphous SiC with a high carbon concentration, wherein, according to some embodiments, the difference between the low carbon concentration and the high carbon concentration is about 2%. In some embodiments, a carbon concentration shift of about 2% is sufficient to achieve a melting point difference greater than about 200K.

[0051] In some embodiments, the above layers are grown by CVD at a temperature range between about 450° C. and about 600° C. and a pressure between about 300 Torr and about 400 Torr. According to some embodiments, in order to grow polycrystalline or amorphous high melting point and low melting point layers, a process temperature of less than about 600° C. and a process pressure of greater than about 300 Torr are required. Due to the laser annealing process, both the low melting point top layer and the high melting point bottom layer will produce the same type of strain (e.g., compression), and the activated dopant concentration in the top layer will be greater than the activated dopant concentration in the bottom layer. In some embodiments, the low melting point top layer exhibits an activation rate of about 100%, for example, all dopants in the top layer are activated (e.g., about 1x10 21 cm -3 ). In contrast, a high melting point bottom layer may exhibit an activation rate of about 10%.

[0052] In some embodiments, any arrangement of polycrystalline or amorphous and single crystal layers may be used for the top and bottom layers of the source / drain epitaxial stack and is within the spirit and scope of the present invention as long as the melting point of the top layer is lower than the melting point of the bottom layer, for example, as long as the melting point difference between the bottom layer and the top layer is greater than about 200 K. Furthermore, the low melting point top layer is between about 30% and about 75% of the total thickness of the source / drain epitaxial stack.

[0053] Figure 5 5 is a flow chart of an exemplary method 500 for manufacturing a source / drain epitaxial stack having a low melting point top layer and a high melting point bottom layer according to some embodiments. Other manufacturing operations may be performed between the various operations of method 500 and may be omitted for clarity only. In addition, the manufacturing operations of method 500 are not exclusive and optional operations may be performed in place of the operations in method 500. Embodiments of the present invention are not limited to method 500. Reference will be made to Figures 6 to 11 An exemplary method 500 is described.

[0054] The method 500 begins at operation 510 and a gate structure is formed on a fin disposed on a substrate. Figure 6 Cross-sectional views of the resulting structure along the x-axis (x-cut) and along the y-axis (y-cut) are shown. The direction along the x-axis coincides with the length of the fin, and the direction along the y-axis coincides with the width of the fin. For example, the y-cut view is generated by observing the structure along lines A-B of the x-cut in the y-axis direction, and the x-view is generated by observing the structure along lines C-D of the y-cut in the x-direction. According to operation 510, a fin 600 is formed on a substrate 610. In some embodiments, both the fin 600 and the substrate 610 include one or more semiconductor materials. For example, the fin 600 and the substrate 610 may include elemental semiconductor materials, such as Si or Ge, or semiconductor compounds, such as SiGe. In addition, the fin 600 and the substrate 610 may include Figure 6 The doped regions are not shown in FIG. A dielectric layer 620, such as silicon oxide, isolates the fin 600 from adjacent fins. In some embodiments, the dielectric layer 620 may be an isolation structure, such as a shallow trench isolation (STI) structure.

[0055] A gate structure 630 is formed on and around the fin 600 such that the gate structure 630 “wraps” a portion of the fin 600 that is not covered by the dielectric layer 620 , as shown in FIG. Figure 6 6. In some embodiments, the gate structure 630 includes a sacrificial gate electrode 630A, a sacrificial gate dielectric 630B, and one or more spacer layers 630C. In some embodiments, the sacrificial gate electrode 630A includes polysilicon and the sacrificial gate dielectric includes silicon oxide. In addition, the one or more spacer layers 630C may include a nitride, such as silicon nitride. In some embodiments, the sacrificial gate electrode 630A and the sacrificial gate dielectric 630B form a sacrificial gate stack that can be replaced by a metal gate stack in subsequent operations.

[0056] refer to Figure 5 , method 500 continues with operation 520, where a portion of fin 600 is recessed. According to some embodiments, recessed fin 600 facilitates formation of a source / drain epitaxial stack in a subsequent operation (eg, in operation 530 of method 500). By way of example and not limitation, Figure 7 The x-cut shows the resulting structure after the recessing process of operation 520. In some embodiments, a portion of the fin 600 is recessed to form a recessed fin portion 700. The recessed fin portion 700 is located adjacent to the spacer layer 630C of the gate structure 630. As an example and not limitation, the recessed fin portion 700 can be formed by masking the portion of the fin 600 to be protected and etching the remainder of the fin 600 (e.g., the exposed portion). Masking can be achieved using a hard mask layer (such as an oxide layer or a nitride layer), using a photoresist layer, or a combination thereof. The etching process can include an etchant, such as chlorine (Cl2), hydrogen bromide (HBr), tetrafluoromethane (CF4), or a combination thereof. In some embodiments, such as Fig.11 As shown by the x-cut, during operation 520 , all portions of the fin 600 not covered by the gate structure 630 are recessed. Figure 7 The y-cut view of FIGS. 1-60 and 1-70 shows the resulting structure along the x-cut line E-F in the y-direction. In the y-cut view, both the recessed portion (eg, 700) and the non-recessed portion (eg, 600) of the fin are visible.

[0057] refer to Figure 5, the method 500 continues with operation 530, and a source / drain epitaxial stack having a low melting point top layer and a high melting point bottom layer is formed on the recessed fin portion 700. As described above, in some embodiments, the low melting point top layer and the high melting point bottom layer include materials with substantially similar stoichiometry but different microstructures—for example, the low melting point top layer is amorphous, while the high melting point bottom layer is single crystalline. In this case, the difference in melting point between the two layers is attributed to the different microstructures of the two layers. In some embodiments, the low melting point top layer and the high melting point bottom layer include materials with different stoichiometry but substantially similar microstructures—for example, the low melting point top layer and the high melting point bottom layer are both single crystalline layers or polycrystalline layers or amorphous layers. In this case, the difference in melting point between the two layers is attributed to the different stoichiometry of the two layers. In some embodiments, the difference in melting point between the high melting point bottom layer and the low melting point top layer is greater than about 200K. In some embodiments, the melting point of the low melting point top layer is lower than the melting point of the surrounding structure (such as fin 600). In some embodiments, the fin 600 and the high melting point bottom layer have substantially similar melting points.

[0058] By way of example and not limitation, Figure 8 X-cut and y-cut views of the resulting structure after forming the source / drain epitaxial stack 800 are shown. Figure 8 The y-cut view of FIG. 1 shows the resulting structure along the x-cut line E–F in ​​the y direction, while Figure 8 The x-cut view of FIG. 8 shows the resulting structure along the y-cut line CD in the x-direction. In some embodiments, the source / drain epitaxial stack 800 has a diamond shape, such as Figure 8 The source / drain epitaxial stack 800 includes a low melting point top layer 810 and a high melting point bottom layer 820. In some embodiments, for simplicity, the high melting point bottom layer may include Figure 8 . As an example and not limitation, the low melting point top layer 810 and the high melting point bottom layer 820 are grown by a CVD process at a temperature range between 450°C and 800°C and a process pressure between about 20 Torr and about 400 Torr. In some embodiments, a combination of a low temperature range (e.g., between about 450°C and about 600°C) and a high pressure range (e.g., between about 300 Torr and about 400 Torr) produces an amorphous or polycrystalline layer, while a combination of a high temperature range (between about 600°C and about 800°C) and a low pressure range (e.g., between about 20 Torr and about 300 Torr) produces a single crystal layer. In some embodiments, the thickness ratio between the low melting point top layer 810 and the source / drain epitaxial stack 800 is between about 0.3 and about 0.75 (e.g., 0.30≤T1 / T≤0.75). In some embodiments, the laser annealing process does not change the thickness of the low-melting-point top layer 810 and the high-melting-point bottom layer 820 .

[0059] In some embodiments, the source / drain epitaxial stack 800 may be a B-doped SiGe stack, a P-doped SiC stack, or a P-doped SiP stack having a Ge concentration between about 20% and about 40%. In some embodiments, the dopant concentration of the low-melting-point top layer 810 is substantially similar to the dopant concentration of the high-melting-point bottom layer 820 (e.g., about 1×10 21 cm -3 ).

[0060] refer to Figure 5 and Figure 8 , the method 500 continues with operation 540, where a laser annealing process anneals the source / drain epitaxial stack 800 to activate the dopant. In some embodiments, a melting front is selectively formed in the low-melting top layer 810 by the passing laser beam 830. Due to this process, the low-melting top layer 810 can obtain a temperature of about 1×10 21 cm -3 In some embodiments, due to the laser annealing process, the high melting point bottom layer 820 has a lower activated dopant concentration (e.g., an activation rate of about 10%) than the low melting point top layer 810—for example, the activated dopant concentration of the high melting point layer 820 may be about 3×10 18 cm -3 and about 1×10 20 cm -3 In some embodiments, dopants are prevented from diffusing outside the source / drain epitaxial stack, as described above with respect to Figure 3 discussed.

[0061] In some embodiments, if the low-melting top layer 810 is an as-deposited amorphous layer, the laser annealing process recrystallizes the low-melting top layer 810. In addition, the recrystallized low-melting top layer has a higher defect density than the high-melting bottom layer 820 (e.g., about 2 orders of magnitude lower). In some embodiments, the interface between the low-melting top layer 810 and the high-melting layer 820 has a rough (e.g., non-planar or rough) surface morphology visible via TEM imaging. In some embodiments, the recrystallized low-melting top layer produces compressive strain, while the high-melting bottom layer 820 has tensile strain or less compressive strain than the recrystallized low-melting top layer.

[0062] refer to Figure 5 , the method 500 ends with operation 550 and forming a contact on the source / drain epitaxial stack 800. As an example and not limitation, the contact may be formed as follows. Fig. 9, a dielectric layer 900 is deposited on the dielectric layer 620 and then polished so that the top surface of the dielectric layer 900 is substantially coplanar with the top surface of the gate structure 630. In some embodiments, the sacrificial gate electrode 630A and the sacrificial gate dielectric 630B are replaced by a metal gate electrode stack 910 and a gate dielectric stack 920, respectively. In some embodiments, the gate electrode stack 910 includes metal layers, such as a work function layer (e.g., one or more titanium nitride layers), a barrier layer (e.g., a tantalum nitride layer), and a metal fill layer (e.g., a tungsten metal fill), which are not shown in the figure for simplicity. Fig. 9 In some embodiments, the gate dielectric stack 920 includes an interfacial dielectric layer (eg, silicon oxide) having a dielectric constant greater than about 3.9 and a high-k dielectric layer (eg, hafnium oxide), both of which are not shown in FIG. Fig. 9 Shown in.

[0063] In some embodiments, a contact opening is formed in the dielectric layer 900 to expose the laser annealed low-melting top layer 810. Once the laser annealed low-melting top layer 810 is exposed, a silicide 930 may be formed on the top surface of the laser annealed low-melting top layer 810. In some embodiments, the silicide 930 includes titanium, platinum, nickel, any other suitable metal, or a combination thereof. In some embodiments, a portion of the laser annealed low-melting top layer 810 is consumed to form the silicide 930. Subsequently, the contact opening is coated with a liner layer, such as titanium nitride. For simplicity, the contact opening is formed by coating the contact opening with a liner layer, such as titanium nitride. Fig. 9 The liner layer is not shown in the figure. The liner layer serves as an adhesion and barrier layer for the metal filler 940. In some embodiments, the planarization metal filler 940 and the liner layer ( Fig.10 ) to remove the deposited material from the top surface of the dielectric layer 900 and form the contact 950.

[0064] In some embodiments, the method 500 may be applied to Figures 6 to 9 The transistor structures shown are different from the transistor structures. For example, Figure 6 , the dielectric layer 620 may be grown such that its top surface is coplanar with the top surface of the gate structure 630, as shown in FIG. Fig.10 In some embodiments, Fig.10 The transistor structure shown can be Figure 6 A variation of the transistor structure shown. Fig.10 In the transistor structure of FIG. 6 , the dielectric layer 620 may cover the sidewalls and top surface of the fin structure 600 and the spacer layer 630C of the gate structure 630. In this exemplary transistor structure, the fin 600 is configured according to Figure 5 Operation 520 is to recess between the gate structure 630 and the dielectric layer 620, such as Fig.11For example, openings in the dielectric layer 620 may be formed on either side of the gate stack 630 to expose portions of the fin 600 that are not covered by the gate stack 630 . Fig.11 The y-cut shows the Fig.11 EF. By way of example and not limitation, this may be accomplished by photolithography and etching operations. Subsequently, the fin 600 may be formed as Figure 7 The other operations of method 500 (eg, 530 - 550 ) are performed without change.

[0065] The embodiments described herein are directed to the formation of a source / drain epitaxial stack having a low melting point top layer and a high melting point bottom layer. In some embodiments, the low melting point top layer and the high melting point bottom layer include materials having substantially similar stoichiometry but different microstructures—for example, the low melting point top layer may be amorphous, while the high melting point bottom layer may be single crystal. In this case, the melting point difference between the two layers is attributed to the different microstructures between the two layers. In other embodiments, the low melting point top layer and the high melting point bottom layer include materials having different stoichiometry but substantially similar microstructures—for example, the low melting point top layer and the high melting point bottom layer may both be single crystal layers or polycrystalline layers or amorphous layers. In this case, the melting point difference between the two layers is attributed to the different stoichiometry between the two layers. According to some embodiments, the melting point difference between the high melting point bottom layer and the low melting point top layer, regardless of its origin (e.g., microstructure or stoichiometry), is greater than 200K. In some embodiments, after the laser annealing process, the low melting point top layer and the high melting point bottom layer may have different strain types and / or different strain amplitudes. In some embodiments, a combination of a low growth temperature (e.g., between about 450° C. and about 600° C.) and a high growth pressure (e.g., between about 300 Torr and about 400 Torr) produces an amorphous or polycrystalline layer, while a combination of a high growth temperature (between about 600° C. and about 800° C.) and a low growth pressure (e.g., between about 20 Torr and about 300 Torr) produces a single crystalline layer. According to some embodiments, a thickness ratio between a low melting point top layer and a source / drain epitaxial stack is between about 0.3 and 0.75 (e.g., 0.3≤thickness ratio≤0.75). In some embodiments, the laser annealing process does not substantially change the thickness of the low melting point top layer and the high melting point bottom layer. In some embodiments, the melting point of the low melting point top layer is lower than the melting point of the surrounding structure (such as a semiconductor fin or a semiconductor substrate), so that fin deformation can be avoided during the laser annealing process. In some embodiments, the deposited amorphous low melting point top layer is recrystallized due to the laser annealing process and produces a higher defect density than the low melting point bottom layer. Furthermore, due to the laser annealing process, the low melting point top layer exhibits a higher activated dopant concentration than the high melting point bottom layer.

[0066] In some embodiments, the semiconductor structure includes a fin disposed on a substrate, wherein the fin and the substrate include semiconductor material. The semiconductor structure also includes a gate structure disposed on the fin, wherein the gate structure wraps around a portion of the sidewall surface of the fin. In addition, the semiconductor structure includes a groove formed in a portion of the fin and adjacent to the gate structure; and a source / drain epitaxial stack disposed in the groove, the source / drain epitaxial stack having a bottom layer and a top layer, wherein the activated dopant concentration of the top layer is higher than that of the bottom layer. Finally, the semiconductor structure includes a contact disposed on the top layer of the source / drain epitaxial stack and adjacent to the gate structure.

[0067] In some embodiments, a method includes forming a fin on a substrate; forming a sacrificial gate structure on the fin, the sacrificial gate structure wrapping a portion of a top surface of the fin and a portion of a sidewall surface of the fin; recessing a portion of the fin not covered by the sacrificial gate structure; forming a source / drain epitaxial stack in the recessed portion of the fin, wherein forming the source / drain epitaxial stack includes: growing a bottom layer having a crystalline microstructure, and growing a top layer having an amorphous microstructure on the bottom layer, wherein the top layer has a different melting point than the bottom layer. The method also includes annealing the source / drain epitaxial stack with a laser to form a melting front in the top layer.

[0068] In some embodiments, a method includes forming a fin on a substrate and forming a gate structure on the fin. The method also includes recessing a portion of the fin not covered by the gate structure and forming a source / drain epitaxial stack on the recessed portion of the fin; wherein forming the source / drain epitaxial stack includes: depositing a first layer having a first dopant, and depositing a second layer having a second dopant, wherein the second layer is disposed on the first layer and has a lower melting point than the first layer. The method also includes exposing the source / drain epitaxial stack to an annealing source to activate the first and second dopants in the first and second layers.

[0069] The present invention provides a semiconductor structure, comprising: a fin, arranged on a substrate, wherein the fin and the substrate include semiconductor material; a gate structure, arranged on the fin, wherein the gate structure wraps a portion of the sidewall surface of the fin; a groove, formed in a portion of the fin adjacent to the gate structure; a source / drain epitaxial stack, arranged in the groove and comprising: a bottom layer; and a top layer, having an activated dopant concentration higher than the bottom layer; and a contact structure, arranged on the top layer of the source / drain epitaxial stack, wherein the contact is adjacent to the gate structure. In some embodiments, the top layer has an activated dopant concentration of approximately 100%, while the bottom layer has an activated dopant concentration of approximately 10%. In some embodiments, the top layer has a defect density that is two orders of magnitude higher than the bottom layer. In some embodiments, the thickness of the top layer is between approximately 30% and approximately 75% of the thickness of the source-drain epitaxial stack. In some embodiments, the top layer introduces a higher compressive stress to the fin than the bottom layer. In some embodiments, the top layer has a defect density of approximately 1×10 21 cm -3 In some embodiments, each of the bottom layer and the top layer comprises boron-doped silicon germanium, phosphorus-doped silicon carbon, or phosphorus-doped silicon phosphorus.

[0070] The present invention also provides a method for forming a semiconductor structure, comprising: forming a fin on a substrate; forming a sacrificial gate structure on the fin, wherein the sacrificial gate structure wraps a portion of the top surface of the fin and a portion of the sidewall surface of the fin; recessing a portion of the fin not covered by the sacrificial gate structure; forming a source / drain epitaxial stack in the recessed portion of the fin, wherein forming the source / drain epitaxial stack comprises: growing a bottom layer having a crystalline microstructure; and growing a top layer having an amorphous microstructure on the bottom layer, wherein the top layer has a different melting point from the bottom layer; and annealing the source / drain epitaxial stack with a laser to form a melting front in the top layer. In some embodiments, annealing comprises recrystallizing the top layer. In some embodiments, after annealing, the top layer has about two orders of magnitude more defects per unit area than the bottom layer. In some embodiments, after annealing, the top layer has a higher compressive stress than the bottom layer. In some embodiments, growing the top layer comprises growing the top layer with a thickness between 30% and 75% of the thickness of the source / drain epitaxial stack. In some embodiments, growing the bottom layer and the top layer comprises obtaining a melting point difference between the bottom layer and the top layer that is greater than about 200 K. In some embodiments, annealing the source / drain epitaxial stack comprises transforming the amorphous microstructure of the top layer into a crystalline microstructure. In some embodiments, annealing the source / drain epitaxial stack comprises transforming the top layer into a crystalline layer having a higher defect density per unit area than the bottom layer. In some embodiments, annealing the source / drain epitaxial stack comprises transforming the top layer into a crystalline layer having a higher activated dopant concentration than the bottom layer.

[0071] The present invention also provides a method for forming a semiconductor structure, comprising: forming a fin on a substrate; forming a gate structure on the fin; recessing a portion of the fin not covered by the gate structure; and forming a source / drain epitaxial stack on the recessed portion of the fin, wherein forming the source / drain epitaxial stack comprises: depositing a first layer including a first dopant; and depositing a second layer including a second dopant, wherein the second layer is disposed on the first layer and has a lower melting point than the first layer; and exposing the source / drain epitaxial stack to an annealing source to activate the first dopant in the first layer and the second dopant in the second layer. In some embodiments, exposing the source / drain epitaxial stack to the annealing source comprises activating the second dopant in the second layer and activating a portion of the first dopant in the first layer. In some embodiments, depositing the first layer and the second layer comprises forming the first layer and the second layer having substantially similar microstructures and substantially different stoichiometries. In some embodiments, depositing the first layer and the second layer comprises forming the first layer and the second layer having substantially different microstructures and substantially similar stoichiometries.

[0072] It should be understood that the Detailed Description section, rather than the Abstract section, is intended to be used to interpret the claims. As intended by the inventors, the Abstract section of the disclosure may set forth one or more but not all possible embodiments of the present invention, and therefore, is not intended to limit the appended claims in any way.

[0073] The features of several embodiments are disclosed above so that those skilled in the art can better understand aspects of the present invention. It should be understood by those skilled in the art that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. It should also be appreciated by those skilled in the art that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: A fin disposed on a substrate, wherein the fin and the substrate include semiconductor material; a gate structure disposed on the fin, wherein the gate structure wraps around a portion of a sidewall surface of the fin; a groove formed in a portion of the fin adjacent to the gate structure; A source / drain epitaxial stack is disposed in the recess and comprises: an underlying layer having a first activated carrier concentration less than a chemical dopant concentration of the underlying layer; and a top layer having a higher activated dopant concentration than the bottom layer and having a second activated carrier concentration substantially equal to the chemical dopant concentration of the second layer; and a contact structure disposed on the top layer of the source / drain epitaxial stack, wherein the contact is adjacent to the gate structure, The interface between the top layer and the bottom layer is rougher than the top surface of the top layer.

2. The semiconductor structure according to claim 1, wherein: The top layer has an activated dopant concentration of about 100%, and the bottom layer has an activated dopant concentration of about 10%.

3. The semiconductor structure according to claim 1, wherein: The top layer has a defect density two orders of magnitude higher than the bottom layer.

4. The semiconductor structure according to claim 1, wherein: The thickness of the top layer is between about 30% and about 75% of the thickness of the source drain epitaxial stack.

5. The semiconductor structure according to claim 1, wherein: The top layer introduces higher compressive stress to the fin compared to the bottom layer.

6. The semiconductor structure according to claim 1, wherein: The top layer has approximately 1×10 21 cm -3 The activated dopant concentration.

7. The semiconductor structure according to claim 1, wherein: Each of the bottom layer and the top layer includes boron-doped silicon germanium, phosphorus-doped silicon carbon, or phosphorus-doped silicon phosphorus.

8. A semiconductor structure comprising: A fin disposed on a substrate, wherein the fin has a recessed portion; a gate structure disposed on the fin, wherein the gate structure wraps a portion of a top of the fin and a portion of a sidewall surface of the fin; and a source / drain epitaxial stack disposed in the recessed portion of the fin and comprising: an underlayer having a crystalline microstructure and having a first activated carrier concentration less than a chemical dopant concentration of the underlayer; and A top layer is disposed on the bottom layer and has a second activated carrier concentration substantially equal to the chemical dopant concentration of the second layer, wherein an interface between the top layer and the bottom layer is rougher than a top surface of the top layer.

9. The semiconductor structure according to claim 8, wherein: The recessed portion of the fin is not covered by the gate structure.

10. A semiconductor structure comprising: A fin disposed on a substrate, wherein the fin has a recessed portion and a non-recessed portion; a gate structure covering the non-recessed portion; and A source / drain epitaxial stack is disposed on the recessed portion and includes: a first layer having a first activated carrier concentration less than a chemical dopant concentration of the first layer; and A second layer is disposed on the first layer, the second layer having a second activated carrier concentration substantially equal to the chemical dopant concentration of the second layer.

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