Semiconductor device

Abstract

A semiconductor includes: a substrate; a first active pattern and a second active pattern on the substrate and extending in a first horizontal direction; a first gate electrode on the first active pattern and extending in a second horizontal direction; a second gate electrode on the second active pattern and extending in a second horizontal direction; an active cutting trench extending in the second horizontal direction and between the first gate electrode and the second gate electrode; an active dicing member including a first layer and a second layer on the first layer; a first source / drain region between the first gate electrode and the active cut and on the first active pattern; and a first source / drain contact portion on the first source / drain region, in which at least a portion of the first source / drain contact portion overlaps the first layer in the vertical direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0120444 filed in the Korean Intellectual Property Office on September 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device. Specifically, the present disclosure relates to a method for manufacturing a semiconductor device including an MBCFET. TM A method for a semiconductor device of a multi-bridge channel field effect transistor. Background Art

[0004] In one example scaling technology for increasing the density of semiconductor devices, a multi-gate transistor has been proposed in which a silicon body having a fin shape or a nanowire shape is formed on a substrate and a gate is formed on a surface of the silicon body.

[0005] Since such multi-gate transistors utilize a three-dimensional channel, scaling is easy to perform. In addition, the current control capability can be improved even without increasing the gate length of the multi-gate transistor. In addition, the SCE (short channel effect) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed. Summary of the invention

[0006] Aspects of the present disclosure provide a semiconductor device in which electrical characteristics are improved by forming the width of a source / drain contact to be relatively large.

[0007] According to some embodiments of the present disclosure, a semiconductor device is provided, including: a substrate; a first active pattern and a second active pattern, which are on the substrate and extend in a first horizontal direction, wherein the second active pattern is spaced apart from the first active pattern in the first horizontal direction; a first gate electrode, which is on the first active pattern and extends in a second horizontal direction different from the first horizontal direction; a second gate electrode, which is on the second active pattern and extends in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction; an active cut groove, which extends in the second horizontal direction and is between the first gate electrode and the second gate electrode, wherein the active cut groove separates the first active pattern and the second active pattern; an active cut member, including a first layer and a second layer on the first layer, wherein the first layer is on a sidewall and a bottom surface of the active cut groove; a first source / drain region, between the first gate electrode and the active cut member and on the first active pattern; and a first source / drain contact, which is on the first source / drain region and is electrically connected to the first source / drain region, wherein at least a portion of the first source / drain contact overlaps with the first layer in a vertical direction.

[0008] According to some embodiments of the present disclosure, a semiconductor device is provided, including: a substrate; a first active pattern on the substrate and extending in a first horizontal direction on the substrate; a gate electrode on the first active pattern and extending in a second horizontal direction different from the first horizontal direction; an active cutting piece spaced apart from the gate electrode in the first horizontal direction, wherein the active cutting piece extends in the second horizontal direction, wherein the active cutting piece contacts a sidewall of the first active pattern, and wherein the active cutting piece includes a first layer defining a sidewall and a bottom surface of the active cutting piece and a second layer on the first layer; a source / drain region between the gate electrode and the active cutting piece and on the first active pattern, wherein the source / drain region contacts the first layer; and a source / drain contact on the source / drain region and electrically connected to the source / drain region, wherein at least a portion of a lower surface of the source / drain contact contacts an upper surface of the first layer, and wherein an upper surface of the source / drain contact is coplanar with an upper surface of the second layer.

[0009] According to some embodiments of the present disclosure, a semiconductor device is provided, comprising: a substrate; a first active pattern and a second active pattern, which are on the substrate and extend in a first horizontal direction, wherein the second active pattern is spaced apart from the first active pattern in the first horizontal direction; a plurality of first nanosheets, which are on the first active pattern and spaced apart from each other in a vertical direction; a plurality of second nanosheets, which are on the second active pattern and spaced apart from each other in the vertical direction; a first gate electrode, which is on the first active pattern and extends in a second horizontal direction different from the first horizontal direction, wherein the first gate electrode at least partially surrounds the plurality of first nanosheets; a second gate electrode, which is on the second active pattern and extends in a second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction, and wherein the second gate electrode at least partially surrounds the plurality of second nanosheets; an active cutting groove, which extends in the second horizontal direction and is between the first gate electrode and the second gate electrode, wherein the active cutting groove divides the first active pattern from the second active pattern. an active cutting member including a first layer on a sidewall and a bottom surface of an active cutting groove, and a second layer on the first layer, wherein the first layer contacts a sidewall of each of the first active pattern and the second active pattern, and wherein the first layer and the second layer include materials different from each other; a first source / drain region between the first gate electrode and the active cutting member and on the first active pattern, wherein the first source / drain region contacts the first layer; a second source / drain region between the active cutting member and the second gate electrode and on the second active pattern, wherein the second source / drain region contacts the first layer; a first source / drain contact on the first source / drain region and electrically connected to the first source / drain region, wherein at least a portion of a lower surface of the first source / drain contact contacts the first layer, and wherein a sidewall of the first source / drain contact contacts the second layer; and a second source / drain contact on the second source / drain region and electrically connected to the second source / drain region, wherein at least a portion of a lower surface of the second source / drain contact contacts the first layer, and wherein a sidewall of the second source / drain contact contacts the second layer.

[0010] However, aspects of the present disclosure are not limited to the contents set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a layout diagram describing a semiconductor device according to some embodiments of the present disclosure;

[0013] Figure 2 is along Figure 1 A cross-sectional view taken along line AA';

[0014] Figure 3 is along Figure 1 A cross-sectional view taken along line BB';

[0015] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 is an intermediate process diagram describing a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0016] Fig.18 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present disclosure;

[0017] Fig.19 is a cross-sectional view illustrating a semiconductor device according to yet another embodiment of the present disclosure;

[0018] Fig. 20 is a cross-sectional view illustrating a semiconductor device according to yet another embodiment of the present disclosure;

[0019] Fig.21 is a cross-sectional view illustrating a semiconductor device according to yet another embodiment of the present disclosure; and

[0020] Fig. 22 and Fig.23 is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In order to clarify the present disclosure, parts not related to the description will be omitted, and the same elements or equivalents are referred to by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0022] It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on another element, or there may also be an intermediate element. In contrast, when an element is referred to as being "directly" "on" another element, there is no intermediate element. In addition, for ease of description, spatial relative terms (e.g., "below", "below", "below", "above", "on", etc.) may be used herein to describe the relationship between an element or feature and other elements or features as shown in the accompanying drawings. It will be understood that spatial relative terms, in addition to including the orientations shown in the accompanying drawings, are also intended to include different orientations of the device in use or in operation. For example, if the device in the accompanying drawings is flipped, the element described as being "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the term "below" may include both the orientations above and below. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0023] In addition, unless explicitly described to the contrary, the word "include" and variations such as "include" or "contain" will be understood to mean including the elements, but not excluding any other elements. As used herein, the phrase "at least one of A, B and C" refers to the logic (A "or" B "or" C) using the non-exclusive logic "or", and should not be interpreted as indicating "at least one of A, at least one of B and at least one of C". As used herein, the singular forms "one", "one" and "the" are intended to also include plural forms, unless the context clearly gives the opposite indication. It should also be understood that when the terms "include", "include", "include", and / or "include" are used in this article, the existence of the features, steps, operations, elements, and / or components is indicated, but the existence or addition of one or more other features, steps, operations, elements, components, and / or their combinations is not excluded. The term "and / or" includes any and all combinations of one or more of the items listed in the association. The term "connection" can be used in this article to refer to physical and / or electrical connections, and can refer to direct or indirect physical and / or electrical connections. Components or layers described with reference to “overlapping” in a specific direction may at least partially obscure each other when viewed along a line extending in the specific direction or in a plane perpendicular to the specific direction.

[0024] Although the drawings of the semiconductor device according to some embodiments illustrate that the semiconductor device includes a transistor (MBCFET) including a nanosheet TM(multi-bridge channel field effect transistor)), or a fin transistor (FinFET) including a channel region having a fin pattern shape, but the present disclosure is not limited thereto. Of course, in some other embodiments, the semiconductor device may include a tunneling transistor (tunneling FET) or a three-dimensional (3D) transistor. Of course, according to some other embodiments, the semiconductor device may include a bipolar junction transistor, a lateral diffused metal oxide semiconductor (LDMOS), etc.

[0025] In the following, reference will be made to Figures 1 to 3 A semiconductor device according to some embodiments of the present disclosure is described.

[0026] Figure 1 Detailed description of the invention is provided for describing a layout of a semiconductor device according to some embodiments of the present disclosure. Figure 2 is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 is along Figure 1 A cross-sectional view taken along line BB'.

[0027] refer to Figures 1 to 3 The semiconductor device according to some embodiments of the present disclosure includes a substrate 100, a first active pattern F1 and a second active pattern F2, a field insulating layer 105, a plurality of first nanosheets NW1 and a plurality of second nanosheets NW2, a first gate electrode G1 and a second gate electrode G2, a first gate spacer 111 and a second gate spacer 112, a first gate insulating layer 121 and a second gate insulating layer 122, a first capping pattern 131 and a second capping pattern 132, a first source / drain region SD1 and a second source / drain region SD2, a first etch stop layer 140, a first source / drain contact to a fourth source / drain contact CA1, CA2, CA3 and CA4, a silicide layer SL, a gate contact CB, an active cutting member 160, a second etch stop layer 170, a second interlayer insulating layer 180, and a first via hole V1 and a second via hole V2.

[0028] The substrate 100 may be a silicon substrate or a silicon on insulator (SOI). In some embodiments, the substrate 100 may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present disclosure is not limited thereto.

[0029] Hereinafter, each of the first horizontal direction DR1 and the second horizontal direction DR2 may be defined as a direction parallel to the upper surface of the substrate 100. The second horizontal direction DR2 may be defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 may be defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 may be defined as a direction perpendicular to the upper surface of the substrate 100.

[0030] The first active pattern F1 may extend in the first horizontal direction DR1 on the substrate 100. The second active pattern F2 may extend in the first horizontal direction DR1 on the substrate 100. The second active pattern F2 may be spaced apart from the first active pattern F1 in the first horizontal direction DR1. Each of the first active pattern F1 and the second active pattern F2 may protrude from the upper surface of the substrate 100 in the vertical direction DR3. For example, each of the first active pattern F1 and the second active pattern F2 may be a portion of the substrate 100 and may include an epitaxial layer grown from the substrate 100.

[0031] The field insulation layer 105 may be disposed on the upper surface of the substrate 100. The field insulation layer 105 may at least partially surround the sidewall of each of the first active pattern F1 and the second active pattern F2. For example, the upper surface of each of the first active pattern F1 and the second active pattern F2 may protrude or extend beyond the upper surface of the field insulation layer 105 in the vertical direction DR3. However, the present disclosure is not limited thereto. In some other embodiments, the upper surface of each of the first active pattern F1 and the second active pattern F2 may be formed on the same plane as the upper surface of the field insulation layer 105 (i.e., coplanar). The field insulation layer 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0032] A plurality of first nanosheets NW1 may be disposed on the first active pattern F1. The plurality of first nanosheets NW1 are disposed at the intersection between the first active pattern F1 and the first gate electrode G1. The plurality of first nanosheets NW1 may include a plurality of nanosheets stacked on the first active pattern F1 to be spaced apart from each other in the vertical direction DR3. A plurality of second nanosheets NW2 may be disposed on the second active pattern F2. The plurality of second nanosheets NW2 may be spaced apart from the plurality of first nanosheets NW1 in the first horizontal direction DR1. The plurality of second nanosheets NW2 may be disposed at the intersection between the second active pattern F2 and the second gate electrode G2. The plurality of second nanosheets NW2 may include a plurality of nanosheets stacked on the second active pattern F2 to be spaced apart from each other in the vertical direction DR3.

[0033] although Figure 2 and Figure 3It is shown that each of the plurality of first nanosheets NW1 and the plurality of second nanosheets NW2 includes three nanosheets stacked to be spaced apart from each other in the vertical direction DR3, but this is only for ease of explanation, and the present disclosure is not limited thereto. In some other embodiments, each of the plurality of first nanosheets NW1 and the plurality of second nanosheets NW2 may include four or more nanosheets stacked to be spaced apart from each other in the vertical direction DR3. For example, each of the plurality of first nanosheets NW1 and the plurality of second nanosheets NW2 may include silicon (Si). However, the present disclosure is not limited thereto. In some other embodiments, each of the plurality of first nanosheets NW1 and the plurality of second nanosheets NW2 may include silicon germanium (SiGe).

[0034] The first gate electrode G1 may extend in the second horizontal direction DR2 on the first active pattern F1 and the field insulating layer 105. The first gate electrode G1 may at least partially surround the plurality of first nanosheets NW1. The second gate electrode G2 may extend in the second horizontal direction DR2 on the second active pattern F2 and the field insulating layer 105. The second gate electrode G2 may be spaced apart from the first gate electrode G1 in the first horizontal direction DR1. The second gate electrode G2 may at least partially surround the plurality of second nanosheets NW2.

[0035] For example, each of the first gate electrode G1 and the second gate electrode G2 may include, but is not limited to, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), carbon nitride (CNT), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlC-N), titanium aluminum nitride (TiAlC), titanium carbide (TiC), titanium aluminum nitride (TiAlN ... At least one of tantalum (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof. Each of the first gate electrode G1 and the second gate electrode G2 may include a conductive metal oxide, a conductive metal oxynitride, etc., and may include an oxidized form of the foregoing materials.

[0036] The first gate spacer 111 may extend in the second horizontal direction DR2 on the upper surface of the uppermost nanosheet of the plurality of first nanosheets NW1 and the field insulating layer 105 along two sidewalls of the first gate electrode G1 in the first horizontal direction DR1. The second gate spacer 112 may extend in the second horizontal direction DR2 on the upper surface of the uppermost nanosheet of the plurality of second nanosheets NW2 and the field insulating layer 105 along two sidewalls of the second gate electrode G2 in the first horizontal direction DR1. Each of the first gate spacer 111 and the second gate spacer 112 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or at least one of a combination thereof. However, the present disclosure is not limited thereto.

[0037] The first source / drain region SD1 may be disposed on both sidewalls of the first gate electrode G1 on the first active pattern F1. The first source / drain region SD1 may contact both sidewalls of the plurality of first nanosheets NW1 in the first horizontal direction DR1. The second source / drain region SD2 may be disposed on both sides of the second gate electrode G2 on the second active pattern F2. The second source / drain region SD2 may contact both sidewalls of the plurality of second nanosheets NW2 in the first horizontal direction DR1.

[0038] The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the first gate spacer 111. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the first source / drain region SD1. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the first active pattern F1. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the plurality of first nanosheets NW1.

[0039] The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the second gate spacer 112. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the second source / drain region SD2. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the second active pattern F2. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the plurality of second nanosheets NW2.

[0040] For example, the first gate insulating layer 121 may be in contact with the first source / drain region SD1. In addition, the second gate insulating layer 122 may be in contact with the second source / drain region SD2. However, the present disclosure is not limited thereto. In some other embodiments, an internal spacer may be disposed between the first gate insulating layer 121 and the first source / drain region SD1, and / or between the second gate insulating layer 122 and the second source / drain region SD2. In this case, the internal spacer may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon oxycarbon (SiOC) or a combination thereof.

[0041] Each of the first gate insulating layer 121 and the second gate insulating layer 122 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, titanium strontium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0042] The semiconductor device according to some embodiments may include an NC (negative capacitance) FET using a negative capacitor.For example, each of the first gate insulating layer 121 and the second gate insulating layer 122 may include a ferroelectric material film having ferroelectric characteristics and a paraelectric material film having paraelectric characteristics.

[0043] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series, and the capacitance of each capacitor has a positive value, the total capacitance is reduced from the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may be greater than the absolute value of each individual capacitance while having a positive value.

[0044] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series can be increased. By using the increased total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than 60mV / decade at room temperature.

[0045] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0046] The ferroelectric material film may also include a dopant doped with. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) or tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0047] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), or yttrium (Y).

[0048] When the dopant is aluminum (Al), the ferroelectric material film may include 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0049] When the dopant is silicon (Si), the ferroelectric material film may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50at% to 80at% zirconium.

[0050] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide with a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example but not limited to, at least one of hafnium oxide, zirconium oxide, or aluminum oxide.

[0051] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film has ferroelectric properties, while the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0052] The ferroelectric material film may have a thickness with ferroelectric properties. The thickness of the ferroelectric material film may be, for example but not limited to, 0.5 nm to 10 nm. Since the thickness exhibiting ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0053] As an example, each of the first gate insulating layer 121 and the second gate insulating layer 122 may include a ferroelectric material film. As another example, each of the first gate insulating layer 121 and the second gate insulating layer 122 may include a plurality of ferroelectric material films spaced apart from each other. Each of the first gate insulating layer 121 and the second gate insulating layer 122 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0054] The first etch stop layer 140 may be disposed on the sidewall of the first gate spacer 111 in the first horizontal direction DR1. The first etch stop layer 140 may be disposed on the sidewall of the second gate spacer 112 in the first horizontal direction DR1. Although not shown, the first etch stop layer 140 may be disposed on the upper surface of the field insulating layer 105 in a region where each of the first gate electrode G1 and the second gate electrode G2 is not disposed. Although not shown, the first etch stop layer 140 may be disposed on the sidewall of each of the first source / drain region SD1 and the second source / drain region SD2 in the second horizontal direction DR2. For example, the first etch stop layer 140 may be conformally formed. The first etch stop layer 140 may include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0055] The first capping pattern 131 may extend in the second horizontal direction DR2 on each of the first gate spacer 111, the first gate insulating layer 121, and the first gate electrode G1. The second capping pattern 132 may extend in the second horizontal direction DR2 on each of the second gate spacer 112, the second gate insulating layer 122, and the second gate electrode G2. For example, the lower surface of each of the first capping pattern 131 and the second capping pattern 132 may contact the first etch stop layer 140. However, the present disclosure is not limited thereto. In some other embodiments, the sidewall of each of the first capping pattern 131 and the second capping pattern 132 may contact the first etch stop layer 140. Each of the first capping pattern 131 and the second capping pattern 132 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or at least one of a combination thereof. However, the present disclosure is not limited thereto.

[0056] although Figure 2 and Figure 3 Not shown, but the first interlayer insulating layer ( Fig.16 150) may be disposed on the first etch stop layer 140. Figure 2 and Figure 3 Not shown, but the first interlayer insulating layer ( Fig.16 The first to fourth source / drain contacts CA1, CA2, CA3, and CA4 may at least partially surround the sidewalls of each of the first to second capping patterns 131 and 132 in an area where each of the first to fourth source / drain contacts CA1, CA2, CA3, and CA4 is not provided. Figure 2 and Figure 3 Not shown, but the first interlayer insulating layer ( Fig.16 150) may cover or overlap each of the first source / drain region SD1 and the second source / drain region SD2 on the field insulating layer 105. For example, the first interlayer insulating layer ( Fig.16 An upper surface of the first capping pattern 150) may be formed on the same plane as an upper surface of each of the first capping pattern 131 and the second capping pattern 132.

[0057] The first interlayer insulating layer ( Fig.16 150) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant materials. The low dielectric constant material may include, for example, but not limited to, fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethylchlorotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tossilazane), FSG (fluorinated silicate glass), polyimide nanofoam (e.g., polypropylene oxide), CDO (carbon-doped silicon oxide), OSG (organosilicate glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or at least one of a combination thereof.

[0058] The active cut groove 160T may extend in the second horizontal direction DR2 between the first gate electrode G1 and the second gate electrode G2. The active cut groove 160T may extend in the second horizontal direction DR2 between the first active pattern F1 and the second active pattern F2. The active cut groove 160T may be formed between the first source / drain region SD1 and the second source / drain region SD2. The active cut groove 160T may separate the first active pattern F1 and the second active pattern F2 in the first horizontal direction DR1.

[0059] For example, the active cutting trench 160T may extend to the inside of the substrate 100. That is, the bottom surface of the active cutting trench 160T may be formed inside the substrate 100. Figure 2 The active cut groove 160T is shown to extend to the lower surface of each of the first source / drain contact CA1 and the second source / drain contact CA2 in the region where each of the first source / drain contact CA1 and the second source / drain contact CA2 is provided, but the present disclosure is not limited thereto. Although not shown, in the region where each of the first source / drain contact CA1 and the second source / drain contact CA2 is not provided, the active cut groove 160T may extend to the lower surface of the first interlayer insulating layer ( Fig.16 That is, at least a portion of each of the first source / drain contact CA1 and the second source / drain contact CA2 may be defined as being disposed inside the active cutting trench 160T.

[0060] The active cutting member 160 may be disposed inside the active cutting groove 160T. For example, the active cutting member 160 may extend in the second horizontal direction DR2 between the first gate electrode G1 and the second gate electrode G2. The active cutting member 160 may extend in the second horizontal direction DR2 between the first active pattern F1 and the second active pattern F2. The active cutting member 160 may be formed between the first source / drain region SD1 and the second source / drain region SD2. The active cutting member 160 may separate the first active pattern F1 and the second active pattern F2 in the first horizontal direction DR1.

[0061] For example, the active cutting member 160 may include a first layer 161 and a second layer 162. The first layer 161 may be disposed along the sidewall and bottom surface of the active cutting groove 160T. For example, the first layer 161 may be disposed in a linear shape. The first layer 161 may contact each of the substrate 100, the sidewall of the first active pattern F1 in the first horizontal direction DR1, and the sidewall of the second active pattern F2 in the first horizontal direction DR1. In addition, the first layer 161 may contact each of the first source / drain region SD1 and the second source / drain region SD2.

[0062] The second layer 162 may be disposed inside the active cut trench 160T on the first layer 161. The second layer 162 may fill the active cut trench 160T on the first layer 161, or may be disposed in the active cut trench 160T on the first layer 161. For example, the second layer 162 may extend to the first interlayer insulating layer ( Fig.16 For example, the upper surface of the second layer 162 may be formed on the first interlayer insulating layer ( Fig.16 150) is on the same plane as the upper surface.

[0063] For example, the first layer 161 may include oxide. The first layer 161 may include, for example, silicon oxide (SiO 2 ), silicon oxynitride (SiON), or silicon oxycarbonitride (SiOCN). The second layer 162 may include a material different from the first layer 161. The second layer 162 may include a material having an etching selectivity different from that of the first layer 161. For example, the second layer 162 may include a nitride. The second layer 162 may include, for example, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or silicon oxycarbonitride (SiOCN).

[0064] The first source / drain contact CA1 may be disposed at a first side of the first gate electrode G1 in the first horizontal direction DR1. The first source / drain contact CA1 may extend in the second horizontal direction DR2. The first source / drain contact CA1 may be electrically connected to the first source / drain region SD1 disposed at a first side of the first gate electrode G1 in the first horizontal direction DR1.

[0065] The second source / drain contact CA2 may be disposed at a second side of the first gate electrode G1 opposite to the first side of the first gate electrode G1 in the first horizontal direction DR1. The second source / drain contact CA2 may be disposed between the first gate electrode G1 and the active cutting member 160. The second source / drain contact CA2 may extend in the second horizontal direction DR2. The second source / drain contact CA2 may be electrically connected to the first source / drain region SD1 disposed between the first gate electrode G1 and the active cutting member 160.

[0066] For example, at least a portion of the second source / drain contact CA2 may overlap the active cutting member 160 in the vertical direction DR3. For example, at least a portion of the second source / drain contact CA2 may overlap the first layer 161 in the vertical direction DR3. For example, at least a portion of the lower surface of the second source / drain contact CA2 may contact the upper surface of the first layer 161. For example, a first sidewall of the second source / drain contact CA2 in the first horizontal direction DR1 may contact the first etch stop layer 140. In addition, a second sidewall of the second source / drain contact CA2 opposite to the first sidewall of the second source / drain contact CA2 in the first horizontal direction DR1 may contact the second layer 162. For example, the upper surface of the second source / drain contact CA2 may be formed on the same plane as the upper surface of the second layer 162.

[0067] The third source / drain contact CA3 may be disposed at a first side of the second gate electrode G2 in the first horizontal direction DR1. The third source / drain contact CA3 may be disposed between the active cutting member 160 and the second gate electrode G2. The third source / drain contact CA3 may extend in the second horizontal direction DR2. The third source / drain contact CA3 may be electrically connected to the second source / drain region SD2 disposed between the active cutting member 160 and the second gate electrode G2.

[0068] For example, at least a portion of the third source / drain contact CA3 may overlap with the active cutting member 160 in the vertical direction DR3. For example, at least a portion of the third source / drain contact CA3 may overlap with the first layer 161 in the vertical direction DR3. For example, at least a portion of the lower surface of the third source / drain contact CA3 may contact with the upper surface of the first layer 161. For example, a first sidewall of the third source / drain contact CA3 in the first horizontal direction DR1 may contact with the second layer 162. In addition, a second sidewall of the third source / drain contact CA3 opposite to the first sidewall of the third source / drain contact CA3 in the first horizontal direction DR1 may contact with the first etch stop layer 140. For example, the upper surface of the third source / drain contact CA3 may be formed on the same plane as the upper surface of the second layer 162.

[0069] The fourth source / drain contact CA4 is disposed at a second side of the second gate electrode G2 opposite to the first side of the second gate electrode G2 in the first horizontal direction DR1. The fourth source / drain contact CA4 may extend in the second horizontal direction DR2. The fourth source / drain contact CA4 may be electrically connected to the second source / drain region SD2 disposed at the second side of the second gate electrode G2 in the first horizontal direction DR1.

[0070] For example, the second source / drain contact CA2 may include a contact barrier layer CA2_1 and a contact filling layer CA2_2. The contact barrier layer CA2_1 may form the sidewall and bottom surface of the second source / drain contact CA2. The contact barrier layer CA2_1 may be provided in a linear shape. The contact barrier layer CA2_1 may contact the upper surface of the first layer 161. In addition, the contact barrier layer CA2_1 may contact the sidewall of the second layer 162 in the first horizontal direction DR1 and the first etch stop layer 140. The contact filling layer CA2_2 may be provided on the contact barrier layer CA2_1. The contact filling layer CA2_2 may form the inside of the second source / drain contact CA2. For example, similar to the second source / drain contact CA2, each of the first source / drain contact CA1, the third source / drain contact CA3, and the fourth source / drain contact CA4 may include a contact barrier layer CA2_1 and a contact filling layer CA2_2.

[0071] Each of the contact barrier layer CA2_1 and the contact filling layer CA2_2 may include a conductive material. The contact barrier layer CA2_1 may include, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh). The contact filling layer CA2_2 may include, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0072] The silicide layer SL may be disposed between each of the first source / drain contact CA1 and the second source / drain contact CA2 and the first source / drain region SD1. The silicide layer SL may be disposed along an interface between each of the first source / drain contact CA1 and the second source / drain contact CA2 and the first source / drain region SD1. In addition, the silicide layer SL may be disposed between each of the third source / drain contact CA3 and the fourth source / drain contact CA4 and the second source / drain region SD2. The silicide layer SL may be disposed along an interface between each of the third source / drain contact CA3 and the fourth source / drain contact CA4 and the second source / drain region SD2.

[0073] For example, at least a portion of the silicide layer SL disposed between the second source / drain contact CA2 and the first source / drain region SD1 may contact the first layer 161. In addition, at least a portion of the silicide layer SL disposed between the third source / drain contact CA3 and the second source / drain region SD2 may contact the first layer 161. The silicide layer SL may include, for example, a metal silicide material.

[0074] For example, the gate contact CB may pass through or extend through the first capping pattern 131 in the vertical direction DR3 and be connected to the first gate electrode G1. For example, the upper surface of the gate contact CB may be formed on the same plane as the upper surface of the first capping pattern 131, but the present disclosure is not limited thereto. In some other embodiments, the upper surface of the gate contact CB may be formed to be higher than the upper surface of the first capping pattern 131 (for example, the distance between the upper surface of the gate contact CB and the substrate 100 is greater than the distance between the upper surface of the first capping pattern 131 and the substrate 100). Although in Figure 3 The gate contact CB is shown as being formed of a single-layer film, but this is for ease of explanation and the present disclosure is not limited thereto. That is, the gate contact CB may be formed of a multi-layer film. The gate contact CB may include a conductive material.

[0075] The second etch stop layer 170 may be disposed between the first to fourth source / drain contacts CA1, CA2, CA3, and CA4, the gate contact CB, the first and second capping patterns 131 and 132, and the first interlayer insulating layer ( Fig.16 150). Although the second etch stop layer 170 is Figure 2 and Figure 3 In the figure, the second etch stop layer 170 is shown as being formed by a single layer, but the present disclosure is not limited thereto. In some other embodiments, the second etch stop layer 170 may be formed by a multilayer film. The second etch stop layer 170 may include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0076] The second interlayer insulating layer 180 may be disposed on the second etch stop layer 170. The second interlayer insulating layer 180 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The first via V1 may pass through or extend through the second interlayer insulating layer 180 and the second etch stop layer 170 in the vertical direction DR3, and may be connected to any one of the first source / drain contact to the fourth source / drain contact CA1, CA2, CA3, and CA4. The second via V2 may pass through or extend through the second interlayer insulating layer 180 and the second etch stop layer 170 in the vertical direction DR3, and may be connected to the gate contact CB. Although each of the first via V1 and the second via V2 is Figure 2 and Figure 3 In the figure, it is shown as being formed of a single-layer film, but this is for convenience of explanation, and the present disclosure is not limited thereto. That is, each of the first via hole V1 and the second via hole V2 may be formed of a multi-layer film. Each of the first via hole V1 and the second via hole V2 may include a conductive material.

[0077] The semiconductor device according to some embodiments of the present disclosure may be formed such that a portion of the second source / drain contact CA2 overlaps the active cutting piece 160 in the vertical direction DR3. Therefore, in the semiconductor device according to some embodiments of the present disclosure, the electrical characteristics of the semiconductor device may be improved by forming the width of the second source / drain contact CA2 to be relatively large.

[0078] In the following, reference will be made to Figures 2 to 17 A method for manufacturing a semiconductor device according to some embodiments of the present disclosure is described.

[0079] Figures 4 to 17 is a diagram for explaining intermediate steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0080] refer to Figure 4 and Figure 5, a stacked structure 10 may be formed on a substrate 100. The stacked structure 10 may include a first semiconductor layer 11 and a second semiconductor layer 12 alternately stacked on the substrate 100. For example, the first semiconductor layer 11 may be formed at the bottom of the stacked structure 10, and the second semiconductor layer 12 may be formed at the top of the stacked structure 10. However, the present disclosure is not limited thereto. In some other embodiments, the first semiconductor layer 11 may also be formed at the top of the stacked structure 10. The first semiconductor layer 11 may include, for example, silicon germanium (SiGe). The second semiconductor layer 12 may include, for example, silicon (Si).

[0081] Then, a portion of the stacked structure 10 may be etched. While etching the stacked structure 10, a portion of the substrate 100 may also be etched. Through such an etching process, an active layer F may be defined in a lower portion of the stacked structure 10 on the substrate 100. The active layer F may extend in the first horizontal direction DR1. Subsequently, a field insulation layer 105 may be formed on the substrate 100. The field insulation layer 105 may at least partially surround the sidewalls of the active layer F. For example, the upper surface of the active layer F may be formed to be higher than the upper surface of the field insulation layer 105. Subsequently, a pad oxide layer 20 may be formed to cover or overlap the upper surface of the field insulation layer 105, the exposed sidewalls of the active layer F, and the sidewalls and upper surface of the stacked structure 10. For example, the pad oxide layer 20 may be conformally formed. The pad oxide layer 20 may include, for example, silicon oxide (SiO 2 ).

[0082] refer to Figure 6 and Figure 7 , the first to third dummy gates DG1, DG2, and DG3 extending in the second horizontal direction DR2 on the pad oxide layer 20, and the first to third dummy capping patterns DC1, DC2, and DC3 may be formed on the stacked structure 10 and the field insulating layer 105. For example, the third dummy gate DG3 may be spaced apart from the first dummy gate DG1 in the first horizontal direction DR1. The second dummy gate DG2 may be spaced apart from the third dummy gate DG3 in the first horizontal direction DR1. The first dummy capping pattern DC1 may be disposed on the first dummy gate DG1. The second dummy capping pattern DC2 may be disposed on the second dummy gate DG2. The third dummy capping pattern DC3 may be disposed on the third dummy gate DG3.

[0083] While forming the first to third dummy gates DG1, DG2 and DG3 and the first to third dummy capping patterns DC1, DC2 and DC3, the remaining pad oxide layer 20 on the substrate 100 except for the portion overlapping with each of the first to third dummy gates DG1, DG2 and DG3 in the vertical direction DR3 may be removed.

[0084] Next, a spacer material layer SM may be formed to cover or overlap the sidewalls of each of the first to third dummy gates DG1, DG2, and DG3, the sidewalls and upper surfaces of each of the first to third dummy capping patterns DC1, DC2, and DC3, the exposed sidewalls and upper surfaces of the stacked structure 10, and the upper surface of the field insulating layer 105. For example, the spacer material layer SM may be conformally formed. The spacer material layer SM may include, for example, at least one of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or a combination thereof.

[0085] refer to Figure 8 , by using the first to third dummy gates DG1, DG2, and DG3, and the first to third dummy capping patterns DC1, DC2, and DC3 as masks to etch the stacked structure ( Figure 6 10), and the first source / drain trench ST1 and the second source / drain trench ST2 may be formed respectively. For example, the first source / drain trench ST1 may be formed between the first dummy gate DG1 and the third dummy gate DG3. In addition, the second source / drain trench ST2 may be formed between the third dummy gate DG3 and the second dummy gate DG2. For example, each of the first source / drain trench ST1 and the second source / drain trench ST2 may extend into the interior of the active layer F. While forming each of the first source / drain trench ST1 and the second source / drain trench ST2, the spacer material layer ( Figure 6 SM), and a portion of each of the first to third dummy capping patterns DC1, DC2, and DC3 may be etched.

[0086] For example, the spacer material layer ( ) remaining on the sidewalls of the first to third dummy capping patterns DC1, DC2, and DC3 and the first to third dummy gates DG1, DG2, and DG3. Figure 6 The dummy gates (SM) may be defined as the first to third gate spacers 111, 112, and 113. For example, after the first source / drain trench ST1 and the second source / drain trench ST2 are respectively formed, each second semiconductor layer ( Figure 6 12) in may be defined as each of the plurality of first to third plurality of nanosheets NW1, NW2, and NW3.

[0087] refer to Fig. 9, a first source / drain region SD1 may be formed inside the first source / drain trench ST1. For example, the first source / drain region SD1 may be formed between the plurality of first nanosheets NW1 and the third plurality of nanosheets NW3 on the active layer F. In addition, a second source / drain region SD2 may be formed inside the second source / drain trench ST2. For example, the second source / drain region SD2 may be formed between the third plurality of nanosheets NW3 and the plurality of second nanosheets NW2 on the active layer F.

[0088] refer to Fig.10 , a first etch stop layer 140 and a first interlayer insulating layer 150 may be sequentially formed to cover or overlap the first source / drain region SD1 and the second source / drain region SD2, the first to third gate spacers 111, 112, and 113, and the first to third dummy capping patterns ( Fig. 9 For example, the first etch stop layer 140 may have a linear shape. Then, the upper surface of each of the first to third dummy gates DG1, DG2, and DG3 may be exposed by a planarization process.

[0089] refer to Fig.11 and Fig.12 , the first dummy gate to the third dummy gate can be etched ( Fig.10 DG1, DG2 and DG3 in the pad oxide layer ( Fig.10 20) and the first semiconductor layer ( Fig.10 Each of 11) in the first dummy gate ( Fig.10 The portion of DG1) can be defined as the first gate trench GT1. The second dummy gate ( Fig.10 The portion of DG2) can be defined as the second gate trench GT2. The third dummy gate ( Fig.10 The portion DG3) can be defined as a third gate trench GT3.

[0090] refer to Fig.13 and Fig.14 , can be in the first gate trench ( Fig.11 A first gate insulating layer 121, a first gate electrode G1 and a first capping pattern 131 are sequentially formed inside the second gate trench ( Fig.11 A second gate insulating layer 122, a second gate electrode G2 and a second capping pattern 132 are sequentially formed inside the third gate trench (GT2). Fig.11 A third gate insulating layer 123, a third gate electrode G3 and a third capping pattern 133 are sequentially formed inside the GT3.

[0091] refer to Fig.15, an active cut trench 160T may be formed between the first gate electrode G1 and the second gate electrode G2. The third capping pattern ( Fig.13 133), the third gate spacer ( Fig.13 113), the third gate insulating layer ( Fig.13 123), the third gate electrode ( Fig.13 G3), a portion of the first etch stop layer 140, a plurality of third nanosheets ( Fig.13 NW3), and the active layer ( Fig.13 The active cutting groove 160T may be formed by each of the first interlayer insulating layer 150 and the second horizontal direction DR2. The active cutting groove 160T may extend from the upper surface of the first interlayer insulating layer 150 to the inside of the substrate 100.

[0092] After the active cut trench 160T is formed, the active layer ( Fig.13 The active cutting groove 160T may be formed by separating the first active pattern F1 and the second active pattern F2. The first active pattern F1 may be formed under the first gate electrode G1 and the first source / drain region SD1. The second active pattern F2 may be formed under the second gate electrode G2 and the second source / drain region SD2. The sidewall of each of the first source / drain region SD1 and the second source / drain region SD2 in the first horizontal direction DR1 and the sidewall of each of the first active pattern F1 and the second active pattern F2 in the first horizontal direction DR1 may be exposed by the active cutting groove 160T.

[0093] refer to Fig.16 , a first layer 161 and a second layer 162 may be formed inside the active cutting groove 160T. The first layer 161 may be formed along the sidewall and bottom surface of the active cutting groove 160T. For example, the first layer 161 may have a linear shape. The second layer 162 may fill the inside of the active cutting groove 160T on the first layer 161.

[0094] For example, the first layer 161 may contact each of a sidewall of each of the first source / drain region SD1 and the second source / drain region SD2 in the first horizontal direction DR1, a sidewall of each of the first active pattern F1 and the second active pattern F2 in the first horizontal direction DR1, the substrate 100, the first etch stop layer 140, and the first interlayer insulating layer 150. For example, each of the upper surfaces of the first layer 161 and the second layer 162 may be formed on the same plane as the upper surface of the first interlayer insulating layer 150.

[0095] refer to Fig.17, first to fourth source / drain contacts CA1, CA2, CA3, and CA4 may be formed inside the first interlayer insulating layer 150, respectively. For example, the first source / drain contact CA1 may be formed on the first source / drain region SD1 on the first side of the first gate electrode G1. The second source / drain contact CA2 may be formed on the first source / drain region SD1 between the second side of the first gate electrode G1 and the second layer 162. The third source / drain contact CA3 may be formed on the second source / drain region SD2 between the second layer 162 and the first side of the second gate electrode G2. The fourth source / drain contact CA4 may be formed on the second source / drain region SD2 on the second side of the second gate electrode G2.

[0096] For example, each of the second source / drain contact CA2 and the third source / drain contact CA3 may be formed in a portion in which the first layer 161 is partially etched. That is, each of the second source / drain contact CA2 and the third source / drain contact CA3 may overlap the first layer 161 in the vertical direction DR3. Each of the second source / drain contact CA2 and the third source / drain contact CA3 may contact the upper surface of the first layer 161. For example, a sidewall of each of the second source / drain contact CA2 and the third source / drain contact CA3 in the first horizontal direction DR1 may contact the second layer 162.

[0097] For example, an upper surface of each of the first to fourth source / drain contacts CA1, CA2, CA3, and CA4 may be formed on the same plane as an upper surface of each of the first and second capping patterns 131 and 132. For example, each of the first to fourth source / drain contacts CA1, CA2, CA3, and CA4 may include a contact barrier layer CA2_1 and a contact filling layer CA2_2 formed on the contact barrier layer CA2_1.

[0098] A silicide layer SL may be formed between each of the first source / drain contact CA1 and the second source / drain contact CA2 and the first source / drain region SD1. In addition, a silicide layer SL may be formed between each of the third source / drain contact CA3 and the fourth source / drain contact CA4 and the second source / drain region SD2. Although not shown, the gate contact ( Figure 3 The first gate electrode CB) may pass through or extend through the first capping pattern 131 in the vertical direction DR3 and may be connected to the first gate electrode G1.

[0099] refer to Figure 2 and Figure 3 , the first to fourth source / drain contacts CA1, CA2, CA3, and CA4, the gate contact CB, the first and second capping patterns 131 and 132, and the first interlayer insulating layer ( Fig.16 A second etch stop layer 170 and a second interlayer insulating layer 180 are sequentially formed on the upper surface of each of the first and second interlayer insulating layers 150). Subsequently, a first via hole V1 that passes through or extends through the second interlayer insulating layer 180 and the second etch stop layer 170 in the vertical direction DR3 and is connected to the first source / drain contact to one of the fourth source / drain contacts CA1, CA2, CA3, and CA4 may be formed. In addition, a second via hole V2 that passes through the second interlayer insulating layer 180 and the second etch stop layer 170 in the vertical direction DR3 and is connected to the gate contact CB may be formed. By performing such a manufacturing process, a Figure 2 and Figure 3 The semiconductor device shown in .

[0100] In the following, reference will be made to Fig.18 The semiconductor device according to some other embodiments of the present disclosure is described. The description will focus on Figures 1 to 3 The differences in the semiconductor devices shown in .

[0101] Fig.18 is a cross-sectional view for illustrating a semiconductor device according to some other embodiments of the present disclosure.

[0102] refer to Fig.18 In the semiconductor device according to some other embodiments of the present disclosure, each of the first to fourth source / drain contacts CA21, CA22, CA23, and CA24 may be formed of a single-layer film.

[0103] Each of the first to fourth source / drain contacts CA21, CA22, CA23, and CA24 may include a conductive material. For example, each of the first to fourth source / drain contacts CA21, CA22, CA23, and CA24 may include, for example, at least one of tantalum (Ta), titanium (Ti), nickel (Ni), zirconium (Zr), vanadium (V), platinum (Pt), iridium (Ir), rhodium (Rh), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0104] In the following, reference will be made to Fig.19 The semiconductor device according to some other embodiments of the present disclosure is described. The description will focus on Figures 1 to 3 The differences in the semiconductor devices shown in .

[0105] Fig.19 is a cross-sectional view for illustrating a semiconductor device according to some other embodiments of the present disclosure.

[0106] refer to Fig.19In the semiconductor device according to some other embodiments of the present disclosure, a lower surface of each of the second source / drain contact CA32 and the third source / drain contact CA33 may have a step.

[0107] For example, the active cutting member 360 may be disposed inside the active cutting groove 360T. The active cutting member 360 may include a first layer 361 disposed along the sidewall and bottom surface of the active cutting groove 360T, and a second layer 162 disposed on the first layer 361. For example, the second source / drain contact CA32 may include a first lower surface formed on the upper surface of the first source / drain region SD1, and a second lower surface formed on the upper surface of the first layer 361. The first lower surface of the second source / drain contact CA32 may contact the silicide layer SL3 formed on the upper surface of the first source / drain region SD1. The second lower surface of the second source / drain contact CA32 may contact the upper surface of the first layer 361.

[0108] For example, the third source / drain contact CA33 may include a first lower surface formed on the upper surface of the second source / drain region SD2, and a second lower surface formed on the upper surface of the first layer 361. The first lower surface of the third source / drain contact CA33 may contact the silicide layer SL3 formed on the upper surface of the second source / drain region SD2. The second lower surface of the third source / drain contact CA33 may contact the upper surface of the first layer 361.

[0109] The first lower surface of the second source / drain contact CA32 and the second lower surface of the second source / drain contact CA32 may have a step. For example, the first lower surface of the second source / drain contact CA32 may be formed to be higher than the second lower surface of the second source / drain contact CA32 (for example, the distance between the first lower surface of the second source / drain contact CA32 and the substrate 100 is greater than the distance between the second lower surface of the second source / drain contact CA32 and the substrate 100). In addition, the first lower surface of the third source / drain contact CA33 and the second lower surface of the third source / drain contact CA33 may have a step. For example, the first lower surface of the third source / drain contact CA33 may be formed to be higher than the second lower surface of the third source / drain contact CA33.

[0110] For example, each of the second source / drain contact CA32 and the third source / drain contact CA33 may include a contact barrier layer CA32_1 and a contact filling layer CA32_2. The contact barrier layer CA32_1 may form the sidewall and bottom surface of each of the second source / drain contact CA32 and the third source / drain contact CA33. The contact filling layer CA32_2 may be disposed on the contact barrier layer CA32_1. The contact filling layer CA32_2 may form the inside of each of the second source / drain contact CA32 and the third source / drain contact CA33.

[0111] In the following, reference will be made to Fig. 20 The semiconductor device according to some other embodiments of the present disclosure is described. The description will focus on Figures 1 to 3 The differences in the semiconductor devices shown in .

[0112] Fig. 20 is a cross-sectional view for illustrating a semiconductor device according to some other embodiments of the present disclosure.

[0113] refer to Fig. 20 In the semiconductor device according to some other embodiments of the present disclosure, a lower surface of each of the second source / drain contact CA42 and the third source / drain contact CA43 may have a step.

[0114] For example, the active cutting member 460 may be disposed inside the active cutting groove 460T. The active cutting member 460 may include a first layer 461 disposed along the sidewall and bottom surface of the active cutting groove 460T, and a second layer 162 disposed on the first layer 461. For example, the second source / drain contact CA42 may include a first lower surface formed on the upper surface of the first source / drain region SD1, and a second lower surface formed on the upper surface of the first layer 461. The first lower surface of the second source / drain contact CA42 may contact the silicide layer SL4 formed on the upper surface of the first source / drain region SD1. The second lower surface of the second source / drain contact CA42 may contact the upper surface of the first layer 461.

[0115] For example, the third source / drain contact CA43 may include a first lower surface formed on the upper surface of the second source / drain region SD2, and a second lower surface formed on the upper surface of the first layer 461. The first lower surface of the third source / drain contact CA43 may contact the silicide layer SL4 formed on the upper surface of the second source / drain region SD2. The second lower surface of the third source / drain contact CA43 may contact the upper surface of the first layer 461.

[0116] The first lower surface of the second source / drain contact CA42 and the second lower surface of the second source / drain contact CA42 may have a step. For example, the first lower surface of the second source / drain contact CA42 may be formed to be lower than the second lower surface of the second source / drain contact CA42. In addition, the first lower surface of the third source / drain contact CA43 and the second lower surface of the third source / drain contact CA43 may have a step. For example, the first lower surface of the third source / drain contact CA43 may be formed to be lower than the second lower surface of the third source / drain contact CA43.

[0117] For example, each of the second source / drain contact CA42 and the third source / drain contact CA43 may include a contact barrier layer CA42_1 and a contact filling layer CA42_2. The contact barrier layer CA42_1 may form the sidewall and bottom surface of each of the second source / drain contact CA42 and the third source / drain contact CA43. The contact filling layer CA42_2 may be disposed on the contact barrier layer CA42_1. The contact filling layer CA42_2 may form the interior of each of the second source / drain contact CA42 and the third source / drain contact CA43.

[0118] In the following, reference will be made to Fig.21 The semiconductor device according to some other embodiments of the present disclosure is described. The description will focus on Figures 1 to 3 The differences in the semiconductor devices shown in .

[0119] Fig.21 is a cross-sectional view for illustrating a semiconductor device according to some other embodiments of the present disclosure.

[0120] refer to Fig.21 In the semiconductor device according to some other embodiments of the present disclosure, at least a portion of the first layer 561 may be disposed between each of the second source / drain contact CA52 and the third source / drain contact CA53 and the second layer 162 .

[0121] For example, the active cutting member 560 may be disposed inside the active cutting groove 560T. The active cutting member 560 may include a first layer 561 disposed along the sidewall and bottom surface of the active cutting groove 560T, and a second layer 162 disposed on the first layer 561. For example, the sidewall of the second source / drain contact CA52 in the first horizontal direction DR1 may be spaced apart from the second layer 162 in the first horizontal direction DR1. The first layer 561 may be disposed between the sidewall of the second source / drain contact CA52 in the first horizontal direction DR1 and the second layer 162. In addition, the sidewall of the third source / drain contact CA53 in the first horizontal direction DR1 may be spaced apart from the second layer 162 in the first horizontal direction DR1. The first layer 561 may be disposed between the sidewall of the third source / drain contact CA53 in the first horizontal direction DR1 and the second layer 162.

[0122] For example, each of the second source / drain contact CA52 and the third source / drain contact CA53 may include a contact barrier layer CA52_1 and a contact filling layer CA52_2. The contact barrier layer CA52_1 may form the sidewall and bottom surface of each of the second source / drain contact CA52 and the third source / drain contact CA53. The contact filling layer CA52_2 may be disposed on the contact barrier layer CA52_1. The contact filling layer CA52_2 may form the interior of each of the second source / drain contact CA52 and the third source / drain contact CA53.

[0123] In the following, reference will be made to Fig. 22 and Fig.23 The semiconductor device according to some other embodiments of the present disclosure is described. The description will focus on Figures 1 to 3 The differences in the semiconductor devices shown in .

[0124] Fig. 22 and Fig.23 is a cross-sectional view for illustrating a semiconductor device according to some other embodiments of the present disclosure.

[0125] refer to Fig. 22 and Fig.23 , the semiconductor device according to some other embodiments of the present disclosure may include a fin transistor (FinFET). For example, the semiconductor device according to some other embodiments of the present disclosure may include a substrate 100, a first active pattern F61 and a second active pattern F62, a field insulating layer 105, a first gate electrode G61 and a second gate electrode G62, a first gate spacer 611 and a second gate spacer 612, a first gate insulating layer 621 and a second gate insulating layer 622, a first capping pattern 131 and a second capping pattern 132, a first source / drain region SD61 and a second source / drain region SD62, a first etch stop layer 140, an active cutting member 160, a first source / drain contact to a fourth source / drain contact CA1, CA2, CA3 and CA4, a silicide layer SL, a gate contact CB, a second etch stop layer 170, a second interlayer insulating layer 180, and a first via hole V1 and a second via hole V2. Hereinafter, the description of the etching method will be omitted. Figures 1 to 3 Description of the configuration described in .

[0126] Each of the first active pattern F61 and the second active pattern F62 may extend in the first horizontal direction DR1 on the substrate 100. The second active pattern F62 may be spaced apart from the first active pattern F61 in the first horizontal direction DR1. The first gate electrode G61 may extend in the second horizontal direction DR2 on the first active pattern F61 and the field insulating layer 105. The second gate electrode G62 may extend in the second horizontal direction DR2 on the second active pattern F62 and the field insulating layer 105. The first gate spacer 611 may extend in the second horizontal direction DR2 along both side walls of the first gate electrode G61 on the first active pattern F61. The second gate spacer 612 may extend in the second horizontal direction DR2 along both side walls of the second gate electrode G62 on the second active pattern F62.

[0127] The first gate insulating layer 621 may be disposed between the first gate electrode G61 and the first active pattern F61. The first gate insulating layer 621 may be disposed between the first gate electrode G61 and the first gate spacer 611. The second gate insulating layer 622 may be disposed between the second gate electrode G62 and the second active pattern F62. The second gate insulating layer 622 may be disposed between the second gate electrode G62 and the second gate spacer 612. The first source / drain region SD61 may be disposed on the first active pattern F61 at both sides of the first gate electrode G61 in the first horizontal direction DR1. The second source / drain region SD62 may be disposed on the second active pattern F62 at both sides of the second gate electrode G62 in the first horizontal direction DR1.

[0128] The active cutting groove 160T may separate the first active pattern F61 and the second active pattern F62. The active cutting member 160 may extend in the second horizontal direction DR2 inside the active cutting groove 160T. For example, the active cutting member 160 may include a first layer 161 and a second layer 162. The first layer 161 may be disposed along the sidewall and bottom surface of the active cutting groove 160T. The second layer 162 may fill the inside of the active cutting groove 160T on the first layer 161, or on the first layer 161 in the inside of the active cutting groove 160T.

[0129] Although the embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be manufactured in various forms. It will be understood by those skilled in the art that the present disclosure can be implemented in other specific forms without changing the technical spirit or features of the present disclosure. Accordingly, the above embodiments should be understood in all aspects to be illustrative rather than restrictive.

Claims

1. A semiconductor device, comprising: substrate; a first active pattern and a second active pattern on the substrate and extending in a first horizontal direction, wherein the second active pattern is spaced apart from the first active pattern in the first horizontal direction; a first gate electrode on the first active pattern and extending in a second horizontal direction different from the first horizontal direction; a second gate electrode on the second active pattern and extending in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction; an active cut trench extending in the second horizontal direction and between the first gate electrode and the second gate electrode, wherein the active cut trench separates the first active pattern and the second active pattern; an active cutting member, comprising a first layer and a second layer on the first layer, wherein the first layer is on the sidewalls and bottom surface of the active cutting groove; a first source / drain region between the first gate electrode and the active cutting member and on the first active pattern; and A first source / drain contact is on the first source / drain region and electrically connected to the first source / drain region, wherein at least a portion of the first source / drain contact overlaps the first layer in a vertical direction.

2. The semiconductor device according to claim 1, wherein The first source / drain region contacts the first layer.

3. The semiconductor device according to claim 1, wherein At least a portion of a lower surface of the first source / drain contact contacts the first layer.

4. The semiconductor device according to claim 1, further comprising a silicide layer between the first source / drain region and the first source / drain contact, wherein At least a portion of the silicide layer contacts the first layer.

5. The semiconductor device according to claim 1, wherein An upper surface of the second layer is coplanar with an upper surface of the first source / drain contact.

6. The semiconductor device according to claim 1, further comprising: a second source / drain region between the second gate electrode and the active cutting member and on the second active pattern; as well as A second source / drain contact is on the second source / drain region between the active cutting member and the second gate electrode and is electrically connected to the second source / drain region, wherein at least a portion of the second source / drain contact overlaps the first layer in the vertical direction.

7. The semiconductor device according to claim 1, wherein The first layer and the second layer include materials different from each other.

8. The semiconductor device according to claim 1, wherein A sidewall of the first source / drain contact contacts the second layer.

9. The semiconductor device according to claim 1, wherein: At least a portion of the first layer is between a sidewall of the first source / drain contact and the second layer.

10. The semiconductor device according to claim 1, wherein The first source / drain contact comprises: a contact barrier layer defining sidewalls and a bottom surface of the first source / drain contact; and A contact filling layer is on the contact barrier layer.

11. The semiconductor device according to claim 1, wherein The first source / drain contact comprises: a first lower surface on an upper surface of the first source / drain region and spaced apart from the substrate by a first distance in the vertical direction; and a second lower surface on the upper surface of the first layer and spaced apart from the substrate by a second distance in the vertical direction, and Wherein, the first distance is greater than the second distance.

12. The semiconductor device according to claim 1, further comprising: a plurality of first nanosheets on the first active pattern and spaced apart from each other in the vertical direction, wherein the first gate electrode at least partially surrounds the plurality of first nanosheets; and A plurality of second nanosheets are on the second active pattern and spaced apart from each other in the vertical direction, wherein the second gate electrode at least partially surrounds the plurality of second nanosheets.

13. A semiconductor device comprising: substrate; a first active pattern on the substrate and extending in a first horizontal direction on the substrate; a gate electrode on the first active pattern and extending in a second horizontal direction different from the first horizontal direction; an active cutting member spaced apart from the gate electrode in the first horizontal direction, wherein the active cutting member extends in the second horizontal direction, wherein the active cutting member contacts a sidewall of the first active pattern, and wherein the active cutting member includes a first layer defining a sidewall and a bottom surface of the active cutting member and a second layer on the first layer; a source / drain region between the gate electrode and the active cutting member and on the first active pattern, wherein the source / drain region contacts the first layer; and A source / drain contact is on the source / drain region and electrically connected to the source / drain region, wherein at least a portion of a lower surface of the source / drain contact contacts an upper surface of the first layer, and wherein an upper surface of the source / drain contact is coplanar with an upper surface of the second layer.

14. The semiconductor device according to claim 13, further comprising: A first gate spacer and a second gate spacer, respectively on a first sidewall and a second sidewall of the gate electrode; as well as An etch stop layer is on a sidewall of one of the first gate spacer and the second gate spacer, wherein the etch stop layer contacts the source / drain contact.

15. The semiconductor device according to claim 13, further comprising a second active pattern on the substrate and extending in the first horizontal direction, wherein The second active pattern is spaced apart from the first active pattern in the first horizontal direction, and wherein the active cutting piece separates the first active pattern and the second active pattern.

16. The semiconductor device according to claim 13, further comprising a silicide layer between the source / drain region and the source / drain contact, wherein: At least a portion of the silicide layer contacts the first layer.

17. The semiconductor device according to claim 13, wherein: The second layer contacts sidewalls of the source / drain contacts.

18. The semiconductor device according to claim 13, wherein: The source / drain contact includes a single-layer film.

19. The semiconductor device according to claim 13, wherein: The source / drain contact comprises: a first lower surface on the upper surface of the source / drain region and spaced apart from the substrate by a first distance in a vertical direction; and a second lower surface on the upper surface of the first layer and spaced apart from the substrate by a second distance in the vertical direction, and Wherein, the first distance is smaller than the second distance.

20. A semiconductor device comprising: substrate; a first active pattern and a second active pattern on the substrate and extending in a first horizontal direction, wherein the second active pattern is spaced apart from the first active pattern in the first horizontal direction; a plurality of first nanosheets on the first active pattern and spaced apart from each other in a vertical direction; a plurality of second nanosheets on the second active pattern and spaced apart from each other in the vertical direction; a first gate electrode on the first active pattern and extending in a second horizontal direction different from the first horizontal direction, wherein the first gate electrode at least partially surrounds the plurality of first nanosheets; a second gate electrode on the second active pattern and extending in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction, and wherein the second gate electrode at least partially surrounds the plurality of second nanosheets; an active cut trench extending in the second horizontal direction and between the first gate electrode and the second gate electrode, wherein the active cut trench separates the first active pattern and the second active pattern; an active cutting member including a first layer on a sidewall and a bottom surface of the active cutting groove, and a second layer on the first layer, wherein the first layer contacts a sidewall of each of the first active pattern and the second active pattern, and wherein the first layer and the second layer include different materials from each other; a first source / drain region between the first gate electrode and the active cutting member and on the first active pattern, wherein the first source / drain region contacts the first layer; a second source / drain region between the active cutting member and the second gate electrode and on the second active pattern, wherein the second source / drain region contacts the first layer; a first source / drain contact on the first source / drain region and electrically connected to the first source / drain region, wherein at least a portion of a lower surface of the first source / drain contact contacts the first layer, and wherein a sidewall of the first source / drain contact contacts the second layer; and A second source / drain contact is on the second source / drain region and electrically connected to the second source / drain region, wherein at least a portion of a lower surface of the second source / drain contact contacts the first layer, and wherein a sidewall of the second source / drain contact contacts the second layer.

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