Semiconductor device

Abstract

A semiconductor device includes: a substrate having a main surface and a back surface facing the main surface; a first transistor including a first source electrode, a first drain electrode, and a first gate electrode disposed between the first source electrode and the first drain electrode in the first direction; a second transistor including a second source electrode provided within the first source electrode when viewed from a second direction intersecting the first direction, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode disposed between the second source electrode and the second drain electrode in the first direction; a first gate wiring that has the second source electrode disposed between the first gate wiring and the second gate electrode, is provided within the first source electrode when viewed from the second direction, and is electrically connected to the first gate electrode; and a back surface metal layer electrically connected to the first source electrode and the second source electrode via a first via hole and a second via hole, respectively, the first via hole and the second via hole overlapping with the first source electrode and the second source electrode, respectively, when viewed from a thickness direction of the substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] It is known that in a field effect transistor (FET) having finger-shaped source electrodes, gate electrodes, and drain electrodes, a plurality of unit FETs having source electrodes, gate electrodes, and drain electrodes are arranged along the extending direction of the electrodes (for example, Patent Documents 1 and 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2002-299351

[0006] Patent Document 2: U.S. Patent Application Publication No. 2017 / 0271329

[0007] Patent Document 3: Japanese Patent Application Publication No. 2022-135899

[0008] By configuring multiple unit FETs along the extension direction of the electrode, the width of the gate electrode in the unit FET can be shortened. This can suppress the gate resistance. However, the source inductance will increase, or the gate / source parasitic capacitance will increase. This will deteriorate the performance. Summary of the invention

[0009] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress performance degradation.

[0010] One embodiment of the present disclosure is a semiconductor device, comprising: a substrate having a main surface and a back surface opposite to the main surface; a first transistor, provided on the main surface, comprising a first source electrode, a first drain electrode, and a first gate electrode arranged between the first source electrode and the first drain electrode in a first direction; a second transistor, provided on the main surface, comprising: a second source electrode provided in the first source electrode when viewed from a second direction intersecting the first direction, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode arranged between the second source electrode and the second drain electrode in the first direction; a first gate wiring, provided on the main surface, electrically connected to the first gate electrode, so that the second source electrode is arranged between the first gate wiring and the second gate electrode, and provided in the first source electrode when viewed from the second direction; and a back metal layer, provided on the back surface, electrically connected to the first source electrode and the second source electrode via a first via and a second via, respectively, wherein the first via and the second via overlap with the first source electrode and the second source electrode, respectively, when viewed from the thickness direction of the substrate.

[0011] One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a main surface and a back surface opposite to the main surface; a first gate wiring arranged on the main surface; a first transistor arranged on the main surface, comprising a first drain electrode, a first gate electrode, and a first source electrode arranged in sequence from the first gate wiring along a first direction, the first gate electrode being electrically connected to the first gate wiring; and a second transistor arranged on the main surface, comprising a second drain electrode, a second gate electrode, and a second source electrode arranged in sequence from the first gate wiring along a direction opposite to the first direction, the second gate electrode being electrically connected to the first gate wiring, and the second transistor overlapping with the first transistor when viewed from the first direction.

[0012] Effects of the Invention

[0013] According to the present disclosure, performance degradation can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 1 is a top view of the semiconductor device of Example 1.

[0015] Figure 2 yes Figure 1 A-A section view in.

[0016] Figure 3 yes Figure 1 B-B section view in.

[0017] Figure 4 3 is a top view of the semiconductor device of Comparative Example 1.

[0018] Figure 5 It is a top view of the semiconductor device of Example 2.

[0019] Figure 6 yes Figure 5 A-A section view in.

[0020] Figure 7 It is a top view of a semiconductor device according to a first variation of the second embodiment.

[0021] Figure 8 This is a top view of a semiconductor device according to a second variation of the second embodiment.

[0022] Fig. 9 yes Figure 8 A-A section view in.

[0023] Fig.10 yes Figure 8 B-B section view in.

[0024] Fig.11 It is a top view of the semiconductor device of Example 3.

[0025] Fig.12 yes Fig.11 A-A section view in.

[0026] Fig.13 yes Fig.11 B-B section view in.

[0027] Fig.14 It is a top view of a semiconductor device according to a first variation of the third embodiment.

[0028] Fig.15 This is an enlarged top view of a semiconductor device according to a second variation of the third embodiment.

[0029] Fig.16 yes Fig.15 A-A section view in.

[0030] Fig.17 yes Fig.15 B-B section view in.

[0031] Fig.18 It is a top view of a semiconductor device according to a third variation of the third embodiment, and is an enlarged top view of the transistor 35a and the transistor 35c.

[0032] Fig.19 yes Fig.18 A-A section view in.

[0033] Description of Reference Numerals

[0034] 10, 10a: substrate; 10b: semiconductor layer; 11a, 11c, 11d: active region; 12, 12a, 12c, 12d: source electrode; 13: inactive region; 14, 14a, 14b, 14c, 14d: gate electrode; 16, 16a, 16b, 16c, 16d: drain electrode; 24b: wiring layer; 20, 20a, 20b, 20c, 20d: via; 22, 22a, 22b, 22c: source wiring; 24, 25a, 25b: gate wiring; 24a: Gate metal layer; 26a, 26c, 26c: drain wiring; 27a, 27b, 27d: electrodes; 27c, 32: wiring; 28, 28a: metal layer; 30: insulating layer; 33: opening; 34: gate bus; 35, 35a, 35b, 35c, 35d: transistor; 36: drain bus; 38, 38a, 38b: transistor group; 50: main surface; 52: back surface; 100, 101, 102, 103, 104, 105, 106, 107, 110: semiconductor device. DETAILED DESCRIPTION

[0035] [Description of Embodiments of the Present Disclosure]

[0036] First, the contents of the embodiments of the present disclosure will be listed and described.

[0037] (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a main surface and a back surface opposite to the main surface; a first transistor provided on the main surface and comprising a first source electrode, a first drain electrode, and a first gate electrode arranged between the first source electrode and the first drain electrode in a first direction; a second transistor provided on the main surface and comprising: a second source electrode provided inside the first source electrode when viewed from a second direction intersecting the first direction, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode arranged between the second source electrode and the second drain electrode in the first direction; a first gate wiring provided on the main surface and electrically connected to the first gate electrode so that the second source electrode is arranged between the first gate wiring and the second gate electrode and provided inside the first source electrode when viewed from the second direction; and a back metal layer provided on the back surface and electrically connected to the first source electrode and the second source electrode via a first via hole and a second via hole, respectively, wherein the first via hole and the second via hole overlap with the first source electrode and the second source electrode, respectively, when viewed from the thickness direction of the substrate. Thus, the source inductances of the first transistor and the second transistor can be made uniform, and the high-frequency performance can be made uniform. Therefore, the high-frequency performance of the semiconductor device can be made uniform.

[0038] (2) In the above (1), a third transistor may be provided, the third transistor being provided on the main surface and comprising: a third source electrode provided inside the first source electrode and overlapping the second source electrode when viewed from the second direction, and electrically connected to the first source electrode and the second source electrode; a third drain electrode electrically connected to the first drain electrode and the second drain electrode; and a third gate electrode arranged between the third source electrode and the third drain electrode in the first direction. Thus, three or more transistors can be arranged along the second direction.

[0039] (3) In the above (2), the back metal layer may be electrically connected to the third source electrode via a third via hole overlapping the third source electrode when viewed from the thickness direction. This can make the source inductances of the first to third transistors uniform, and further make the high-frequency performance of the semiconductor device uniform.

[0040] (4) In any one of the above (1) to (3), a fourth transistor may be provided, the fourth transistor being provided on the main surface and comprising: a fourth source electrode, the first gate wiring being arranged between the fourth source electrode and the second source electrode, and being arranged inside the first source electrode when viewed from the second direction; a fourth drain electrode, the fourth source electrode being arranged between the fourth drain electrode and the first gate wiring; and a fourth gate electrode being arranged between the fourth source electrode and the fourth drain electrode in the first direction. Thus, a plurality of transistors can be arranged along the first direction.

[0041] (5) In the above (4), a fifth transistor may be provided, the fifth transistor being provided on the main surface and comprising: the first source electrode; a fifth drain electrode electrically connected to the fourth drain electrode; and a fifth gate electrode arranged between the first source electrode and the fifth drain electrode in the first direction and electrically connected to the first gate wiring. Thus, a plurality of transistors can be arranged along the second direction.

[0042] (6) In the above (4) or (5), the back metal layer may be electrically connected to the fourth source electrode via a fourth via hole overlapping the fourth source electrode when viewed from the thickness direction. This makes it possible to make the source inductances of the first to fourth transistors uniform, and further make the high-frequency performance of the semiconductor device uniform.

[0043] (7) In the above (4) or (5), no via hole is provided to electrically connect the fourth source electrode to the back metal layer, and the width of the fourth source electrode in the first direction is smaller than the width of the second source electrode in the first direction. This can make the semiconductor device smaller.

[0044] (8) In the above (7), a wiring may be provided, the wiring intersecting the first gate wiring without contact, and connecting the second source electrode to the fourth source electrode. This can make the source inductance of the second transistor and the fourth transistor uniform, and can further make the high-frequency performance of the semiconductor device uniform.

[0045] (9) In any of the above (1) to (8), the device may further include: a gate bus provided on the main surface and electrically connected to the second gate electrode and the first gate wiring; and a drain bus provided on the main surface and electrically connected to the first drain electrode and the second drain electrode, wherein the first transistor and the second transistor are arranged between the drain bus and the gate bus in the second direction. Thus, a gate potential can be provided from the gate bus to the first gate electrode and the second gate electrode, and a drain potential can be provided from the drain bus to the first drain electrode and the second drain electrode.

[0046] (10) One embodiment of the present disclosure is a semiconductor device, comprising: a substrate having a main surface and a back surface opposite to the main surface; a first gate wiring provided on the main surface; a first transistor provided on the main surface, comprising a first drain electrode, a first gate electrode, and a first source electrode arranged in sequence along a first direction from the first gate wiring, the first gate electrode being electrically connected to the first gate wiring; and a second transistor provided on the main surface, comprising a second drain electrode, a second gate electrode, and a second source electrode arranged in sequence along a direction opposite to the first direction from the first gate wiring, the second gate electrode being electrically connected to the first gate wiring, the second transistor overlapping the first transistor when viewed from the first direction. Thus, gate / source parasitic capacitance can be suppressed, and thus high-frequency performance degradation can be suppressed.

[0047] (11) In the above (10), a third transistor may be provided, the third transistor being provided on the main surface and having a third drain electrode, a third gate electrode, and a third source electrode arranged in sequence along the first direction, the third drain electrode overlapping the first drain electrode when viewed from a second direction intersecting the first direction, the third gate electrode being electrically connected to the first gate wiring, and the third source electrode overlapping the first source electrode when viewed from the first direction. Thus, a plurality of transistors can be arranged along the second direction.

[0048] (12) In the above (11), the device may also include: a drain wiring connecting the first drain electrode and the third drain electrode; and a second gate wiring intersecting the drain wiring between the first drain electrode and the third drain electrode without contact, and electrically connecting the third gate electrode and the first gate wiring. Thus, a gate potential can be provided to the third gate electrode.

[0049] (13) In the above (12), a first electrode may be provided between the first drain electrode and the third drain electrode, the first electrode being provided on the main surface between the second gate wiring and the first drain electrode or the third drain electrode and being provided with a reference potential. Thus, gate / drain parasitic capacitance can be suppressed, thereby suppressing degradation of high frequency performance.

[0050] (14) In the above (12) or (13), a second electrode may be provided, the second electrode being provided on the main surface between the first gate wiring and the first drain electrode and being supplied with a reference potential. This can suppress gate / drain parasitic capacitance, thereby suppressing degradation of high frequency performance.

[0051] (15) In any one of the above (10) to (14), a back metal layer may be provided, the back metal layer being provided on the back surface and being electrically connected to the first source electrode and the second source electrode via a first via hole and a second via hole, respectively, wherein the first via hole and the second via hole overlap with the first source electrode and the second source electrode, respectively, when viewed from the thickness direction of the substrate. Thus, the source inductance of the first transistor and the second transistor can be suppressed.

[0052] (16) In any of the above (10) to (15), the device may further include: a gate bus provided on the main surface and electrically connected to the first gate electrode, the second gate electrode, and the first gate wiring; and a drain bus provided on the main surface and electrically connected to the first drain electrode and the second drain electrode, wherein the first transistor and the second transistor are arranged between the drain bus and the gate bus in a second direction intersecting the first direction. Thus, a gate potential can be provided from the gate bus to the first gate electrode and the second gate electrode, and a drain potential can be provided from the drain bus to the first drain electrode and the second drain electrode.

[0053] [Details of the embodiments of the present disclosure]

[0054] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0055] [Example 1]

[0056] The following description will be given by taking, as an example, a semiconductor device of an amplifier for amplifying a high-frequency signal of 0.5 GHz to 10 GHz in a mobile communication base station. Figure 1 This is a top view of the semiconductor device of Example 1. Figure 2 yes Figure 1 A-A section view in. Figure 3 yes Figure 1 The thickness direction of the substrate 10 is set to the Z direction, the extension direction of the finger-shaped source electrode 12, the gate electrode 14 and the drain electrode 16 is set to the Y direction (a second direction intersecting the first direction), and the arrangement direction of the source electrode 12, the gate electrode 14 and the drain electrode 16 is set to the X direction (the first direction). It should be noted that Figure 1 and Figure 2 In the top view, when the source electrode 12 and the drain electrode 16 overlap with the source wiring 22 and the drain wiring 26, it is difficult to see. Therefore, the bold line diagram that sees through the source wiring 22 and the drain wiring 26 and only shows the outer periphery of the source wiring 22 and the drain wiring 26 is shown inside the source electrode 12 and the drain electrode 16.

[0057] In each figure, the source electrode 12, the gate electrode 14, the source wiring 22, and the transistor 35 (unit FET) represent general elements, and the active regions 11a, 11c, 11d, the source electrodes 12a, 12c, 12d, the gate electrodes 14a to 14d, the drain electrodes 16a to 16d, the source wirings 22a to 22c, the drain wiring 26a and the drain wiring 26b, and the transistors 35a to 35d represent specific elements included in the general elements. Hereinafter, the transistors 35a to 35d will be described mainly using the active regions 11a, 11c, 11d, the source electrodes 12a, 12c, 12d, the gate electrodes 14a to 14d, the drain electrodes 16a to 16d, the source wirings 22a to 22c, the drain wiring 26a and the drain wiring 26b.

[0058] like Figure 1 to Figure 3 As shown, in the semiconductor device 100 of the first embodiment, the substrate 10 has a main surface 50 and a back surface 52 opposite to the main surface 50. A plurality of transistors 35 and 35a to 35d are provided on the main surface of the substrate 10. The transistors 35, 35a to 35d arranged in the Y direction form transistor groups 38, 38a and 38b. In the Y direction, the drain bus 36 and the gate bus 34 are provided on the main surface 50, and the transistor groups 38, 38a and 38b are arranged between the two.

[0059] The transistors 35 closest to the drain bus 36 are transistors 35a and transistors 35b. The transistors 35 closer to the gate bus 34 than transistors 35a and transistors 35b are transistors 35c and transistors 35d. The transistor group 38a includes one transistor 35a and three transistors 35c. The transistor group 38b includes one transistor 35b and three transistors 35d. The number of transistors 35c is one or more, and the number of transistors 35d is one or more.

[0060] The substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In the XY plane parallel to the X direction and the Y direction, the region of the semiconductor layer 10b that is deactivated by ion implantation or the like is an inactive region 13, and the region that is not deactivated is an active region 11a, 11c, and 11d. The active region 11a extends along the X direction. The active region 11c and the active region 11d are arranged along the X direction. Three active regions 11c are arranged along the Y direction, and three active regions 11d are arranged along the Y direction. A transistor 35a and a transistor 35b are provided in the active region 11a. A transistor 35c and a transistor 35d are provided in the active region 11c and the active region 11d, respectively.

[0061] The transistor 35a includes a source electrode 12a, a gate electrode 14a, and a drain electrode 16a. The gate electrode 14a is disposed between the source electrode 12a and the drain electrode 16a in the X direction. The source electrode 12a, the gate electrode 14a, and the drain electrode 16a are arranged in this order in the + direction of the X direction.

[0062] The transistor 35b includes a source electrode 12a, a gate electrode 14b, and a drain electrode 16b. The source electrode 12a is disposed between the drain electrode 16b and the gate electrode 14a. The gate electrode 14b is disposed between the source electrode 12a and the drain electrode 16b in the X direction. The source electrode 12a, the gate electrode 14b, and the drain electrode 16b are arranged in sequence along the - direction of the X direction. The transistor 35a and the transistor 35b share the source electrode 12a.

[0063] The transistor 35c includes a source electrode 12c, a gate electrode 14c, and a drain electrode 16c. The gate electrode 14c is arranged between the source electrode 12c and the drain electrode 16c in the X direction. The source electrode 12c is provided inside the source electrode 12a when viewed from the Y direction. That is, when viewed from the Y direction, the source electrode 12c is not provided outside the source electrode 12a. When viewed from the Y direction, a plurality of source electrodes 12c overlap with each other. When viewed from the Y direction, a plurality of drain electrodes 16c overlap with each other. The source electrode 12c, the gate electrode 14c, and the drain electrode 16c are arranged in sequence along the + direction of the X direction.

[0064] The transistor 35d includes a source electrode 12d, a gate electrode 14d, and a drain electrode 16d. The gate wiring 24 is arranged between the source electrode 12d and the source electrode 12c, and is provided inside the source electrode 12a when viewed from the Y direction. That is, when viewed from the Y direction, the source electrode 12d is not provided outside the source electrode 12a. When viewed from the Y direction, a plurality of source electrodes 12d overlap each other. When viewed from the Y direction, a plurality of drain electrodes 16d overlap each other. In the X direction, the gate electrode 14d is arranged between the source electrode 12d and the drain electrode 16d. The source electrode 12d, the gate electrode 14d, and the drain electrode 16d are arranged in sequence along the - direction of the X direction.

[0065] A source wiring 22c is provided on the source electrode 12a in a contacting manner. A source wiring 22a (first source wiring) is provided on the source electrode 12c in a contacting manner. The source wiring 22a extends in the Y direction, electrically connects the plurality of source electrodes 12c to each other, and electrically connects the plurality of source electrodes 12c to the source wiring 22c. A source wiring 22b (second source wiring) is provided on the source electrode 12d in a contacting manner. The source wiring 22b extends in the Y direction, electrically connects the plurality of source electrodes 12d to each other, and electrically connects the plurality of source electrodes 12d to the source wiring 22c.

[0066] Drain wiring 26a is provided on drain electrode 16a and drain electrode 16c in a contacting manner. Drain wiring 26a extends in the Y direction, electrically connects multiple drain electrodes 16a and drain electrodes 16c to each other, and electrically connects multiple drain electrodes 16a and drain electrodes 16c to drain bus 36. Drain wiring 26b is provided on drain electrode 16b and drain electrode 16d in a contacting manner. Drain wiring 26b extends in the Y direction, electrically connects multiple drain electrodes 16b and drain electrodes 16d to each other, and electrically connects multiple drain electrodes 16b and drain electrodes 16d to drain bus 36.

[0067] A gate wiring 24 (first gate wiring) extending in the Y direction is provided on the inactive region 13 between the transistor 35c and the transistor 35d. The gate wiring 24 is provided inside the source electrode 12a when viewed from the Y direction. The gate wiring 24 is electrically connected to the gate bus 34. The gate wiring 24 includes a gate metal layer 24a provided on the substrate 10 and a wiring layer 24b provided in contact with the gate metal layer 24a.

[0068] A gate wiring 25a (second gate wiring) extending in the X direction is provided on the inactive region 13 between the transistor 35a and the transistor 35c and between the transistors 35c. The gate wiring 25a crosses the source wiring 22a without contact, and electrically connects the gate wiring 24 to the gate electrode 14a and the gate electrode 14c. A gate wiring 25b (third gate wiring) extending in the X direction is provided on the inactive region 13 between the transistor 35b and the transistor 35d and between the transistors 35d. The gate wiring 25b crosses the source wiring 22b without contact, and electrically connects the gate wiring 24 to the gate electrode 14b and the gate electrode 14d. Thus, the gate electrodes 14a to 14d are electrically connected to the gate bus 34 via the gate wirings 24, 25a, and 25b. The gate electrode 14c of the transistor 35c and the gate electrode 14d of the transistor 35d closest to the gate bus 34 are directly electrically connected to the gate bus 34 without passing through the gate wirings 24, 25a, and 25b.

[0069] The vias 20, 20a to 20d penetrate the substrate 10. The vias 20a and 20b overlap with the source electrode 12a and are electrically connected to the source electrode 12a when viewed from the Z direction. There may be one via 20a or one via 20b that overlaps with one source electrode 12a and is electrically connected to the source electrode 12a. The vias 20c and 20d overlap with the source electrodes 12c and 12d, respectively, when viewed from the Z direction, and are electrically connected to the source electrodes 12c and 12d, respectively. A metal layer 28 is provided on the back surface 52 of the substrate 10. A metal layer 28a is provided on the inner surfaces of the vias 20 and 20a to 20d. Thus, the metal layer 28 is electrically connected to the source electrode 12a via the vias 20a and 20b, and is electrically connected to the source electrodes 12c and 12d via the vias 20c and 20d, respectively. The planar shape of the via holes 20a to 20d may be an ellipse, an oblong, a rounded quadrilateral or a circle.

[0070] The source potential (e.g., a reference potential such as a ground potential) is provided from the metal layer 28 to the source electrodes 12a, 12c, and 12d, respectively, through the metal layer 28a in the vias 20a to 20d. The gate potential (e.g., a high-frequency signal and a gate bias voltage) is provided from the gate bus 34 to the gate electrodes 14a to 14d via the gate wirings 24, 25a, and 25b. The drain bias voltage is provided from the drain bus 36 to the drain electrodes 16a to 16d via the drain wirings 26a and 26b. The high-frequency signal amplified in each transistor 35a to 35d is output from the drain wirings 26a and 26b to the drain bus 36.

[0071] Alternatively, the + end of the gate electrode 14c in the Y direction may be connected to the - end of the gate electrode 14a in the Y direction, and the + end of the gate electrode 14d in the Y direction may be connected to the - end of the gate electrode 14b in the Y direction. However, in the case where the gate electrode 14c is directly connected to the gate electrode 14a and the gate electrode 14d is directly connected to the gate electrode 14b, in the transistor 35c and the transistor 35d, a high-frequency signal is input from the - end of the gate electrode 14c and the gate electrode 14d in the Y direction. When a high-frequency signal is input from both ends of the + end and the - end of the gate electrode 14c and the gate electrode 14d in the Y direction to the gate electrode 14c and the gate electrode 14d, the high-frequency performance of the transistor 35c and the transistor 35d deteriorates due to a phase difference or the like. Therefore, in Embodiment 1, the + end of gate electrode 14c in the Y direction is not connected to the - end of gate electrode 14a in the Y direction, and the + end of gate electrode 14d in the Y direction is not connected to the - end of gate electrode 14b in the Y direction. This can suppress the degradation of high frequency performance in transistors 35c and 35d.

[0072] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the transistors 35a to 35d are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may be a silicon semiconductor device such as LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0073] The source electrode 12a, the source electrode 12c, the source electrode 12d, and the drain electrodes 16a to 16d are metal films, such as titanium films and aluminum films from the substrate 10. The gate electrodes 14a to 14d and the gate metal layer 24a are metal films, such as nickel films and gold films from the substrate 10. The source wirings 22a to 22c, the drain wiring 26a, the drain wiring 26b, the wiring layer 24b, the metal layer 28, the metal layer 28a, and the drain bus 36 are, for example, gold layers, copper layers, or aluminum layers. The insulating layer 30 is, for example, an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer.

[0074] The width of the source electrode 12a in the X direction is, for example, 50 μm to 150 μm. The width of the source electrode 12c and the source electrode 12d in the X direction is, for example, 5 μm to 80 μm. The gate length of the gate electrodes 14a to 14d in the X direction is, for example, 0.10 μm to 2 μm. The width of the drain electrodes 16a to 16d in the X direction is, for example, 5 μm to 150 μm. The width of the gate wiring 24 in the X direction is, for example, 5 μm to 100 μm. The width of the gate wiring 25a and the gate wiring 25b in the Y direction is, for example, 3 μm to 20 μm. The gate width of the transistors 35a to 35d in the Y direction is, for example, 50 μm to 500 μm. The width of the vias 20a to 20d in the X direction is, for example, 10 μm to 60 μm.

[0075] The widths of the source wirings 22a to 22c, the drain wirings 26a and the drain wirings 26b in the X direction are the same as, slightly smaller than, or slightly larger than the widths of the source electrodes 12a, 12c, 12d, the drain electrodes 16a and the drain electrodes 16d in the X direction. The thicknesses of the source wirings 22a to 22c, the drain wirings 26a and the drain wirings 26c are, for example, 1 μm to 20 μm.

[0076] [Comparative Example 1]

[0077] Figure 4 is a top view of the semiconductor device of Comparative Example 1. Figure 4 As shown, in the semiconductor device 110 of the comparative example 1, the via hole 20c and the via hole 20d are not provided. The other structures are the same as those of the first embodiment.

[0078] In Comparative Example 1, gate potential is provided to gate electrodes 14a to 14d via gate wirings 24, 25a, and 25b, so that gate resistance can be reduced. Gate wiring 24 does not overlap source electrode 12c and source electrode 12d when viewed from above, so gate / source parasitic capacitance can be reduced compared to Patent Documents 1 and 2. However, source potential is provided to source electrode 12c and source electrode 12d via source wiring 22a and source wiring 22b, respectively. Therefore, the source inductance of transistor 35c and transistor 35d becomes larger. In particular, the source inductance of transistor 35c and transistor 35d closest to gate bus 34 becomes the largest. Therefore, uneven transistor performance is generated between transistor 35a and transistor 35c, and between transistor 35b and transistor 35d. Therefore, the high-frequency performance of transistor group 38a and transistor group 38b deteriorates.

[0079] As shown in Example 1, by connecting the vias 20c and 20d to the source electrodes 12c and 12d, respectively, the reference potential is provided to the source electrodes 12c and 12d through the vias 20c and 20d. As a result, the source inductance between the transistors 35a and 35c and between the transistors 35b and 35d can be made uniform, and the transistor performance can be made uniform. Therefore, the high-frequency performance of the transistor group 38a and the transistor group 38b can be suppressed from being deteriorated.

[0080] [Example 2]

[0081] Figure 5 It is a top view of the semiconductor device of Example 2. Figure 6 yes Figure 5 The A-A section view in the figure. Figure 5 and Figure 6As shown, in the semiconductor device 101 of the second embodiment, the via 20d is not connected to the source electrode 12d. The width of the source electrode 12d in the X direction is smaller than the width of the source electrode 12c in the X direction. The wiring 23 electrically connects the source wiring 22 and the source wiring 22a across the drain wiring 26a, and electrically connects the source wiring 22 and the source wiring 22b across the drain wiring 26b. The wiring 23 is provided on the inactive region 13 between the transistor groups 38, 38a and 38b and the gate bus 34, and crosses the gate electrodes 14, 14a and 14b without contact. The other structures are the same as those of the first embodiment, and their description is omitted.

[0082] In transistor group 38a, via 20c is connected to source electrode 12c, so high-frequency performance degradation can be suppressed. In transistor group 38b, via 20d is not connected to source electrode 12d, so high-frequency performance degradation cannot be suppressed, but high-frequency performance degradation can be suppressed as a whole. In addition, the width of source electrode 12d in the X direction can be reduced, so the chip size can be reduced compared with Example 1.

[0083] [Variation 1 of Example 2]

[0084] Figure 7 FIG. 1 is a top view of a semiconductor device according to a first variation of the second embodiment. Figure 7 As shown, in the semiconductor device 102 of the first modification of the second embodiment, the via 20c is not connected to the source electrode 12c other than the source electrode 12c closest to the gate bus 34. The other structures are the same as those of the second embodiment, and the description thereof is omitted.

[0085] In Comparative Example 1, the transistor 35c closest to the gate bus 34 has the largest source inductance. Therefore, the via 20c may be connected only to the source electrode 12c closest to the gate bus 34 among the source electrodes 12c. In Example 1, the via 20c may be connected only to the source electrode 12c closest to the gate bus 34 among the source electrodes 12c. The via 20d may be connected only to the source electrode 12d closest to the gate bus 34 among the source electrodes 12d. The source electrode 12c connected to the via 20 among the source electrodes 12c is a source electrode 12c other than the source electrode 12c closest to the gate bus 34, and the via 20c may not be connected to the source electrode 12c closest to the gate bus 34.

[0086] [Variation 2 of Example 2]

[0087] Figure 8 This is a top view of a semiconductor device according to a second variation of the second embodiment. Fig. 9 yes Figure 8 A-A section view in. Fig.10 yes Figure 8 The B-B section view in the figure. Figure 8 to Figure 10As shown, in the semiconductor device 103 of the second variation of the second embodiment, a wiring 32 is provided on the source wiring 22a and the source wiring 22b in a contacting manner. The wiring 32 crosses the gate wiring 24 via the insulating layer 30 in a non-contact manner, and electrically connects the source wiring 22a and the source wiring 22b. The wiring 32 has a plurality of openings 33 above the gate wiring 24. The plurality of openings 33 are arranged along the Y direction. The openings 33 are used to remove the photoresist under the wiring 32 when forming the wiring 32. The openings 33 may not be provided. The wiring 32 also has a function of suppressing the gate / drain parasitic capacitance generated between the gate wiring 24 and the drain wiring 26a and the drain wiring 26b.

[0088] In addition to the source wiring 22b, the source potential is also supplied to the source electrode 12d from the source wiring 22a via the wiring 32. This can reduce the source inductance of the transistor 35d. This can suppress the degradation of the high frequency performance of the transistor group 38b.

[0089] According to Embodiment 1, Embodiment 2 and its variation, transistor 35a is a first transistor, source electrode 12a, gate electrode 14a and drain electrode 16a are respectively a first source electrode, a first gate electrode and a first drain electrode. One of transistors 35c is a second transistor, source electrode 12c, gate electrode 14c and drain electrode 16c are respectively a second source electrode, a second gate electrode and a second drain electrode. Metal layer 28 (back metal layer) is electrically connected to source electrode 12a and source electrode 12c via via 20a (first via) and via 20c (second via), respectively. Thus, the source inductance of transistor 35a and transistor 35c can be made uniform. Thus, the high-frequency performance of transistor 35a and transistor 35c can be made uniform, so the high-frequency performance of semiconductor device can be made uniform.

[0090] The other transistor 35c is a third transistor, and the source electrode 12c, the gate electrode 14c, and the drain electrode 16c are a third source electrode, a third gate electrode, and a third drain electrode, respectively. Thus, three or more transistors can be arranged along the Y direction.

[0091] The metal layer 28 is electrically connected to the third source electrode through another via 20c (third via). Thus, the source inductance of the plurality of transistors 35c can be made uniform. Thus, the high-frequency performance of the plurality of transistors 35c can be made uniform, and thus the high-frequency performance of the semiconductor device can be made uniform.

[0092] One of the transistors 35d is a fourth transistor, and the source electrode 12d, the gate electrode 14d, and the drain electrode 16d are a fourth source electrode, a fourth gate electrode, and a fourth drain electrode, respectively. Thus, a plurality of transistors 35 can be arranged in the X direction.

[0093] The transistor 35b is a fifth transistor, and the source electrode 12a, the gate electrode 14b, and the drain electrode 16b are respectively a first source electrode, a fifth gate electrode, and a fifth drain electrode. Thus, a plurality of transistors 35 can be arranged along the Y direction.

[0094] As shown in the first embodiment, the metal layer 28 is electrically connected to the source electrode 12d through the via 20d (the fourth via). As a result, the source inductances of the transistors 35b and 35d can be made uniform. As a result, the high-frequency performance of the transistors 35b and 35d can be made uniform, and thus the high-frequency performance of the semiconductor device can be made uniform.

[0095] According to Embodiment 2 and its variation, a via hole electrically connecting the source electrode 12d to the metal layer 28 is not provided. The width of the source electrode 12d in the X direction is smaller than the width of the source electrode 12c in the X direction. Thus, the semiconductor device can be miniaturized. From the perspective of miniaturization, the width of the source electrode 12d in the X direction is, for example, 0.9 times or less, 0.7 times or less, or 0.5 times or less of the width of the source electrode 12c in the X direction. The width of the source electrode 12d in the X direction is, for example, 0.1 times or more of the width of the source electrode 12c in the X direction.

[0096] According to the second variation of the second embodiment, the wiring 32 crosses the gate wiring 24 without contact, and the source electrode 12c is electrically connected to the source electrode 12d. As a result, the source inductance of the transistor 35b and the transistor 35d can be made uniform. As a result, the high-frequency performance of the transistor 35b and the transistor 35d can be made uniform, and the high-frequency performance of the semiconductor device can be made uniform.

[0097] In the first and second embodiments and their modified examples, a gate bus bar 34 electrically connected to the gate wiring 24 and a drain bus bar 36 electrically connected to the drain wiring 26a and the drain wiring 26b are provided. Thus, a gate potential can be provided from the gate bus bar 34 to the gate electrodes 14a to 14d, and a drain potential can be provided from the drain bus bar 36 to the drain electrodes 16a to 16d.

[0098] In the first and second embodiments and their variations, four transistor groups 38, 38a and 38b are arranged in the X direction, but five or more transistor groups 38, 38a and 38b may be arranged in the X direction. It is sufficient if one or more transistors 35c and 35d are arranged in the Y direction.

[0099] In the first and second embodiments and their modified examples, the plurality of drain electrodes 16 (e.g., the drain electrode 16a and the drain electrode 16c) electrically connected to the same drain wiring 26 (e.g., the drain wiring 26a) are separated from each other in the inactive region 13. The plurality of drain electrodes 16 (e.g., the drain electrode 16a and the drain electrode 16c) electrically connected to the drain wiring 26 (e.g., the drain wiring 26a) may be connected to each other in the inactive region 13. In the transistor 35 (e.g., the transistor 35a), the source electrode 12 and the source wiring 22 (e.g., the source electrode 12a and the source wiring 22c) may also be collectively referred to as a source electrode, and the drain electrode 16 and the drain wiring 26 (e.g., the drain electrode 16a and the drain wiring 26a) may also be collectively referred to as a drain electrode.

[0100] [Example 3]

[0101] Fig.11 It is a top view of the semiconductor device of Example 3. Fig.12 yes Fig.11 A-A section view in. Fig.13 yes Fig.11 B-B section view in.

[0102] like Figure 11 to Figure 13 As shown, in the semiconductor device 104 of the third embodiment, in the transistor 35a, the drain electrode 16a, the gate electrode 14a and the source electrode 12a are arranged in sequence along the + direction of the X direction. In the transistor 35b, the drain electrode 16a, the gate electrode 14b and the source electrode 12b are arranged in sequence along the - direction of the X direction. The transistor 35a and the transistor 35b share the drain electrode 16a.

[0103] In transistor 35c, drain electrode 16c, gate electrode 14c and source electrode 12c are arranged in sequence from gate wiring 24 in the + direction of the X direction. In transistor 35d, drain electrode 16d, gate electrode 14d and source electrode 12d are arranged in sequence from gate wiring 24 in the − direction of the X direction.

[0104] Source wirings 22a to 22d are provided on the source electrodes 12a to 12d in a contact manner, respectively. A drain wiring 26c is provided on the drain electrode 16a in a contact manner. A drain wiring 26a (first drain wiring) is provided on the drain electrode 16c in a contact manner. The drain wiring 26a extends in the Y direction, electrically connects the plurality of drain electrodes 16c to each other, and electrically connects the plurality of drain electrodes 16c to the drain wiring 26c. A drain wiring 26b (second drain wiring) is provided on the drain electrode 16d in a contact manner. The drain wiring 26b extends in the Y direction, electrically connects the plurality of drain electrodes 16d to each other, and electrically connects the plurality of drain electrodes 16d to the drain wiring 26c.

[0105] Gate wiring 25a intersects drain wiring 26a without contact, and electrically connects gate wiring 24 to gate electrodes 14a and 14c. Gate wiring 25b intersects drain wiring 26b without contact, and electrically connects gate wiring 24 to gate electrodes 14b and 14d.

[0106] The via holes 20a to 20d are connected to the source electrodes 12a to 12d. The metal layer 28 is electrically connected to the source electrodes 12a to 12d through the via holes 20a to 20d, respectively. The other structures are the same as those in the first embodiment, and the description thereof is omitted.

[0107] [Comparative Example 1]

[0108] exist Figure 4 In Comparative Example 1, the gate wiring 24 is provided between the source electrode 12c and the source electrode 12d and between the source wiring 22a and the source wiring 22b. As a result, the gate / source parasitic capacitance increases, and the high frequency performance deteriorates.

[0109] In Example 3, the gate wiring 24 is provided between the drain electrode 16c and the drain electrode 16d and the drain wiring 26a and the drain wiring 26b. Thus, the increase of the gate / source parasitic capacitance can be suppressed. In Example 3, the gate / drain parasitic capacitance increases compared with Comparative Example 1. When the gate / source capacitance is suppressed, the frequency of switching from the maximum stable gain to the maximum available power gain can be increased. When the gate / drain capacitance is suppressed, the maximum stable gain at the same frequency can be increased. In order to increase the frequency of switching from the maximum stable gain to the maximum available power gain, Example 3 is particularly effective.

[0110] [Variation 1 of Example 3]

[0111] Fig.14 FIG. 1 is a top view of a semiconductor device according to a first variation of the third embodiment. Fig.14 As shown, in the semiconductor device 105 of the first variation of the third embodiment, a source wiring 22a is provided on the source electrode 12a and the plurality of source electrodes 12c in a contacting manner. A source wiring 22b is provided on the source electrode 12b and the plurality of source electrodes 12d in a contacting manner. The other structures are the same as those of the third embodiment, and their description is omitted.

[0112] As shown in the first variation of the third embodiment, the source wiring 22a may be provided in a common manner on the source electrode 12a and the plurality of source electrodes 12c, and the source wiring 22b may be provided in a common manner on the source electrode 12b and the plurality of source electrodes 12d. In this case, the vias 20a and 20c may not be connected to the source electrode 12a and some of the source electrodes in the plurality of source electrodes 12c. The vias 20b and 20d may not be connected to the source electrode 12b and some of the source electrodes in the plurality of source electrodes 12d. As shown in the third embodiment, by providing the source wirings 22a to 22d on each of the source electrodes 12a to 12d, respectively, the gate / source parasitic capacitance can be reduced.

[0113] [Variation 2 of Example 3]

[0114] Fig.15 This is an enlarged top view of a semiconductor device according to a second variation of the third embodiment. Fig.16 yes Fig.15 A-A section view in. Fig.17 yes Fig.15 B-B section view in.

[0115] like Figure 15 to Figure 17 As shown, in the semiconductor device 106 of the second modification of the third embodiment, an electrode 27a for electrically connecting the source electrodes 12c is provided between the source electrode 12a and the source electrode 12c. Electrodes 27b are provided on both sides of the gate wiring 25a in the Y direction between the drain electrode 16a and the drain electrode 16c and between the plurality of drain electrodes 16c. The wiring 27c crosses the gate electrode 14a without contact, and electrically connects the electrode 27a and the electrode 27b. The electrode 27b is electrically connected to the source electrode 12a and the source electrode 12c via the electrode 27a and is short-circuited. Thus, the reference potential to be provided to the source electrode 12a and the source electrode 12c is provided to the electrode 27b.

[0116] The electric field between the gate wiring 25a and the drain electrode 16a, the drain electrode 16c and the drain wiring 26a can be shielded by the electrode 27b. Therefore, the gate / drain parasitic capacitance can be reduced and the high frequency performance can be suppressed. The other structures are the same as those in the third embodiment and their description is omitted.

[0117] [Variation 3 of Embodiment 3]

[0118] Fig.18 It is a top view of a semiconductor device according to a third variation of the third embodiment, and is an enlarged top view of the transistor 35a and the transistor 35c. Fig.19 yes Fig.18 A-A section view in.

[0119] like Fig.18 and Fig.19As shown, in the semiconductor device 107 of the third modification of the third embodiment, an electrode 27d is provided between the drain electrode 16c and the drain wiring 26a and the gate wiring 24. The electrode 27d is electrically connected to the electrode 27b. Thus, the reference potential to be provided to the source electrode 12a and the source electrode 12c is provided to the electrode 27d.

[0120] The electrode 27d can shield the electric field between the gate wiring 24 and the drain electrode 16a and the drain wiring 26a. Therefore, the gate / drain parasitic capacitance can be reduced, and the high-frequency performance can be suppressed. The other structures are the same as those of the second modification of the third embodiment, and the description thereof is omitted.

[0121] According to Embodiment 3 and its variation, transistor 35c is a first transistor, and drain electrode 16c (first drain electrode), gate electrode 14c (first gate electrode) and source electrode 12c (first source electrode) are arranged in sequence from gate wiring 24 along the + direction of the X direction. Transistor 35d is a second transistor, and overlaps with transistor 35c when viewed from the X direction. In transistor 35d, drain electrode 16d (second drain electrode), gate electrode 14d (second gate electrode) and source electrode 12d (second source electrode) are arranged in sequence from gate wiring 24 along the - direction of the X direction (the direction opposite to the first direction). As a result, the distance between source electrode 12c and source wiring 22a and gate wiring 24 becomes longer, and the distance between source electrode 12d and source wiring 22b and gate wiring 24 becomes longer. As a result, gate / source parasitic capacitance can be suppressed, and thus high-frequency performance degradation can be suppressed.

[0122] The transistor 35a is a third transistor, and the drain electrode 16a (third drain electrode), the gate electrode 14a (third gate electrode), and the source electrode 12a (third source electrode) are arranged in sequence along the + direction of the X direction. When viewed from the Y direction, the drain electrode 16a and the source electrode 12a overlap with the drain electrode 16c and the source electrode 12c, respectively. Thus, a plurality of transistors 35a and transistors 35c can be arranged along the Y direction.

[0123] The drain wiring 26a electrically connects the drain electrode 16a and the drain electrode 16c. The gate wiring 25a (second gate wiring) intersects the drain wiring 26a without contact between the drain electrode 16a and the drain electrode 16c and electrically connects the gate electrode 14a and the gate wiring 24. Thus, a gate potential can be provided to the gate electrode 14a.

[0124] The metal layer 28 (back metal layer) is electrically connected to the source electrode 12c and the source electrode 12d through the via 20c (first via) and the via 20d (second via), respectively. This can suppress the source inductance of the transistor 35c and the transistor 35d.

[0125] A gate bus bar 34 electrically connected to the gate wiring 24 and a drain bus bar 36 electrically connected to the drain wiring 26a and the drain wiring 26b are provided. Thus, the gate bus bar 34 can provide a gate potential to the gate electrodes 14a to 14d, and the drain bus bar 36 can provide a drain potential to the drain electrodes 16a, 16c, and 16d.

[0126] As shown in Modification 2 and Modification 3 of Embodiment 3, between the drain electrode 16a and the drain electrode 16c in the Y direction, the electrode 27b (first electrode) is provided between the gate wiring 25a and the drain electrode 16a and the drain electrode 16c, and a reference potential is provided. Thus, the gate / drain parasitic capacitance can be suppressed, and thus the high-frequency performance can be suppressed. The electrode 27b only needs to be provided between the gate wiring 25a and the drain electrode 16a or the drain electrode 16c.

[0127] As shown in Modification 3 of Embodiment 3, the electrode 27d (second electrode) is provided between the gate wiring 24 and the drain electrode 16c, and a reference potential is supplied to the electrode 27d. This can suppress gate / drain parasitic capacitance, thereby suppressing degradation of high frequency performance.

[0128] In the third embodiment and its modified example, two transistor groups 38a and 38b are arranged in the X direction, but three or more transistor groups 38a and 38b may be arranged in the X direction. It is sufficient if one or more transistors 35c and 35d are arranged in the Y direction.

[0129] In the third embodiment and its modified example, a plurality of source electrodes 12 (e.g., source electrode 12a and source electrode 12c) electrically connected to the same source wiring 22 (e.g., source wiring 22a) are separated from each other in the inactive region 13. A plurality of source electrodes 12 (e.g., source electrode 12a and source electrode 12c) electrically connected to the source wiring 22 (e.g., source wiring 22a) may be connected to each other in the inactive region 13. In the transistor 35 (e.g., transistor 35a), the source electrode 12 and the source wiring 22 (e.g., source electrode 12a and source wiring 22a) may also be collectively referred to as a source electrode, and the drain electrode 16 and the drain wiring 26 (e.g., drain electrode 16a and drain wiring 26c) may also be collectively referred to as a drain electrode.

[0130] The embodiments disclosed herein are illustrative in all aspects and should not be considered restrictive. The scope of the present disclosure is indicated by the claims rather than the above meaning, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: A substrate having a main surface and a back surface opposite to the main surface; a first transistor provided on the main surface, comprising a first source electrode, a first drain electrode, and a first gate electrode arranged between the first source electrode and the first drain electrode in a first direction; a second transistor provided on the main surface, comprising: a second source electrode provided inside the first source electrode when viewed from a second direction intersecting the first direction; a second drain electrode electrically connected to the first drain electrode; and a second gate electrode arranged between the second source electrode and the second drain electrode in the first direction; a first gate wiring provided on the main surface so that the second source electrode is arranged between the first gate wiring and the second gate electrode, provided inside the first source electrode when viewed from the second direction, and electrically connected to the first gate electrode; as well as A back metal layer is provided on the back side and is electrically connected to the first source electrode and the second source electrode via a first via hole and a second via hole, respectively, wherein the first via hole and the second via hole overlap with the first source electrode and the second source electrode respectively when viewed from the thickness direction of the substrate.

2. The semiconductor device according to claim 1, wherein A third transistor is provided on the main surface and includes: a third source electrode provided inside the first source electrode and overlapping with the second source electrode when viewed from the second direction, and electrically connected to the first source electrode and the second source electrode; a third drain electrode, electrically connected to the first drain electrode and the second drain electrode; and a third gate electrode disposed between the third source electrode and the third drain electrode in the first direction.

3. The semiconductor device according to claim 2, wherein: The back metal layer is electrically connected to the third source electrode via a third via hole overlapping the third source electrode when viewed from the thickness direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein A fourth transistor is provided on the main surface, and comprises: a fourth source electrode, the first gate wiring is arranged between the fourth source electrode and the second source electrode, and is arranged inside the first source electrode when viewed from the second direction; and a fourth drain electrode, the fourth source electrode is arranged between the fourth drain electrode and the first gate wiring; and a fourth gate electrode disposed between the fourth source electrode and the fourth drain electrode in the first direction.

5. The semiconductor device according to claim 4, wherein: A fifth transistor is provided, the fifth transistor is provided on the main surface, and comprises: the first source electrode; a fifth drain electrode, electrically connected to the fourth drain electrode; and a fifth gate electrode disposed between the first source electrode and the fifth drain electrode in the first direction and electrically connected to the first gate wiring.

6. The semiconductor device according to claim 4, wherein: The back metal layer is electrically connected to the fourth source electrode via a fourth via hole overlapping the fourth source electrode when viewed from the thickness direction.

7. The semiconductor device according to claim 4, wherein: No via hole is provided to electrically connect the fourth source electrode to the back metal layer. A width of the fourth source electrode in the first direction is smaller than a width of the second source electrode in the first direction.

8. The semiconductor device according to claim 7, wherein: A wiring is provided, the wiring intersecting the first gate wiring in a non-contact manner and connecting the second source electrode and the fourth source electrode.

9. The semiconductor device according to any one of claims 1 to 3, wherein have: a gate bus bar, provided on the main surface and electrically connected to the second gate electrode and the first gate wiring; and A drain bus bar is provided on the main surface and is electrically connected to the first drain electrode and the second drain electrode, and the first transistor and the second transistor are arranged between the drain bus bar and the gate bus bar in the second direction.

10. A semiconductor device comprising: A substrate having a main surface and a back surface opposite to the main surface; A first gate wiring is provided on the main surface; a first transistor provided on the main surface, comprising a first drain electrode, a first gate electrode, and a first source electrode arranged in sequence along a first direction from the first gate wiring, wherein the first gate electrode is electrically connected to the first gate wiring; and A second transistor is arranged on the main surface, and comprises a second drain electrode, a second gate electrode and a second source electrode arranged in sequence from the first gate wiring in a direction opposite to the first direction, the second gate electrode is electrically connected to the first gate wiring, and the second transistor overlaps with the first transistor when viewed from the first direction.

11. The semiconductor device according to claim 10, wherein A third transistor is provided, wherein the third transistor is arranged on the main surface, and comprises a third drain electrode, a third gate electrode and a third source electrode arranged in sequence along the first direction, the third drain electrode overlaps with the first drain electrode when viewed from a second direction intersecting the first direction, the third gate electrode is electrically connected to the first gate wiring, and the third source electrode overlaps with the first source electrode when viewed from the first direction.

12. The semiconductor device according to claim 11, wherein have: a drain wiring connecting the first drain electrode and the third drain electrode; and The second gate wiring intersects the drain wiring between the first drain electrode and the third drain electrode without contacting with the drain wiring, and electrically connects the third gate electrode and the first gate wiring.

13. The semiconductor device according to claim 12, wherein: A first electrode is provided between the first drain electrode and the third drain electrode. The first electrode is provided on the main surface between the second gate wiring and the first drain electrode or the third drain electrode and is supplied with a reference potential.

14. The semiconductor device according to claim 12 or 13, wherein: A second electrode is provided, the second electrode being provided on the main surface between the first gate wiring and the first drain electrode and being supplied with a reference potential.

15. The semiconductor device according to any one of claims 10 to 13, wherein It has a back metal layer, which is arranged on the back side and is electrically connected to the first source electrode and the second source electrode via a first via hole and a second via hole, respectively, wherein the first via hole and the second via hole overlap with the first source electrode and the second source electrode respectively when observed from the thickness direction of the substrate.

16. The semiconductor device according to any one of claims 10 to 13, wherein have: a gate bus bar, provided on the main surface, electrically connected to the first gate electrode, the second gate electrode and the first gate wiring; and A drain bus bar is provided on the main surface and is electrically connected to the first drain electrode and the second drain electrode, and the first transistor and the second transistor are arranged between the drain bus bar and the gate bus bar in a second direction intersecting the first direction.

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