Array substrate and display panel

Abstract

The embodiment of the invention discloses an array substrate and a display panel, the array substrate comprises a substrate and a plurality of conductive layers, the plurality of conductive layers at least comprise a first conductive layer, a second conductive layer and a third conductive layer which are laminated, the first conductive layer comprises a grid electrode of a driving transistor and a first polar plate connected with the grid electrode of the driving transistor, and the second conductive layer comprises a second polar plate connected with the grid electrode of the driving transistor. The second conducting layer comprises a second polar plate, the third conducting layer comprises a third polar plate, and the vertical projection of the first polar plate on the substrate and the vertical projection of the second polar plate on the substrate are overlapped and respectively form an upper polar plate and a lower polar plate of the storage capacitor; and the vertical projection of the second polar plate on the substrate and the vertical projection of the third polar plate on the substrate are overlapped and respectively form an upper polar plate and a lower polar plate of the voltage-stabilizing capacitor. According to the technical scheme provided by the embodiment, through the storage capacitor and the voltage stabilizing capacitor which are stacked up and down, the layout space utilization rate is improved, the capacitance value of the storage capacitor is increased, and the display effect is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the development of display technology, people have higher and higher requirements on the performance of display panels.

[0003] Currently, existing display panels have the problem of poor display effects. Summary of the invention

[0004] Embodiments of the present invention provide an array substrate and a display panel to improve display effects.

[0005] According to one aspect of the present invention, there is provided an array substrate, comprising:

[0006] substrate;

[0007] A plurality of conductive layers stacked on one side of the substrate, wherein a plurality of pixel circuits are formed in the array substrate, and the pixel circuits include a driving transistor, a first leakage suppression transistor, a storage capacitor and a voltage stabilizing capacitor;

[0008] The multi-layer conductive layer at least includes a first conductive layer, a second conductive layer and a third conductive layer which are stacked, the first conductive layer includes a gate of the driving transistor and a first electrode plate connected to the gate of the driving transistor, the second conductive layer includes a second electrode plate, the third conductive layer includes a third electrode plate, and the first leakage suppression transistor is connected between the first electrode plate and the third electrode plate;

[0009] The vertical projection of the first electrode plate on the substrate overlaps with the vertical projection of the second electrode plate on the substrate, and respectively form the upper and lower electrodes of the storage capacitor; the vertical projection of the second electrode plate on the substrate overlaps with the vertical projection of the third electrode plate on the substrate, and respectively form the upper and lower electrodes of the voltage-stabilizing capacitor.

[0010] Optionally, a vertical projection of the third electrode plate on the substrate falls within a vertical projection of the first electrode plate and / or the second electrode plate on the substrate;

[0011] Optionally, an overlapping area between the first electrode plate and the second electrode plate is greater than an overlapping area between the second electrode plate and the third electrode plate.

[0012] Optionally, the array substrate also includes a first capacitor dielectric layer, which is located between the second conductive layer and the third conductive layer, and the thickness of the first capacitor dielectric layer between the second electrode plate and the third electrode plate is less than or equal to the thickness of the first capacitor dielectric layer not covered by the third electrode plate.

[0013] Optionally, the first capacitor dielectric layer includes a plurality of stacked sub-dielectric layers, and the number of sub-dielectric layers between the second electrode plate and the third electrode plate is less than the number of sub-dielectric layers at a position not covered by the third electrode plate.

[0014] Optionally, in the multi-layer sub-dielectric layer, the dielectric constant of the sub-dielectric layer close to the second electrode plate is greater than the dielectric constant of the remaining sub-dielectric layers;

[0015] Optionally, the sub-dielectric layer close to the second electrode plate and the remaining sub-dielectric layers are made of different dielectric materials.

[0016] Optionally, an active layer is further included on one side of the substrate, the first conductive layer further includes a first scanning line extending along a first direction, and the first scanning line overlaps with the active layer to form the first leakage suppression transistor;

[0017] Optionally, the third conductive layer further includes a first power line and a transition portion, the first power line extends along the second direction, the first power line is connected to the second electrode plate through a via, the first electrode of the first leakage suppression transistor is connected to the gate of the driving transistor through the transition portion, and the second electrode of the first leakage suppression transistor is connected to the third electrode plate through a via;

[0018] The first direction intersects with the second direction, and both are perpendicular to the thickness direction of the array substrate.

[0019] Optionally, the pixel circuit further includes a second leakage suppression transistor and a compensation transistor, the first conductive layer further includes a second scan line, a vertical projection of the second scan line on the substrate is located between a vertical projection of the gate of the driving transistor on the substrate and a vertical projection of the first scan line on the substrate, the first scan line overlaps with the active layer to form the second leakage suppression transistor, and the second scan line overlaps with the active layer to form the compensation transistor;

[0020] The second electrode of the first leakage suppression transistor is connected to the first electrode of the second leakage suppression transistor, the second electrode of the second leakage suppression transistor is connected to the first electrode of the compensation transistor, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor;

[0021] Optionally, the pixel circuit further includes a data writing transistor, the second scanning line overlaps with the active layer to form the data writing transistor, and the data writing transistor is connected between the data line and the first electrode of the driving transistor;

[0022] Optionally, the data line is located in the third conductive layer, and the data line extends along the second direction.

[0023] Optionally, the pixel circuit further includes a first initialization transistor and a second initialization transistor, and the array substrate further includes a third scan line, a fourth scan line, a first initialization signal line and a second initialization signal line, the third scan line overlaps with the active layer to form the first initialization transistor, and the fourth scan line overlaps with the active layer to form the second initialization transistor; the first initialization transistor is connected between the first initialization signal line and the first electrode or the second electrode of the second leakage suppression transistor, and is used to transmit the first initialization voltage on the first initialization signal line to the gate of the driving transistor; the second initialization transistor is connected between the second initialization signal line and the light-emitting element, and is used to transmit the second initialization voltage on the second initialization signal line to the light-emitting element;

[0024] Optionally, the third scan line and the fourth scan line are arranged in the same layer, and are arranged in different layers from the first initialization signal line and the second initialization signal line;

[0025] Optionally, the third scan line and the fourth scan line are located in the first conductive layer, and the initialization signal line and the second initialization signal line are located in the second conductive layer;

[0026] Optionally, the first initialization signal line is multiplexed as the second initialization signal line;

[0027] Optionally, the third scan line is multiplexed as the fourth scan line.

[0028] Optionally, the pixel circuit further includes a first light emission control transistor and a second light emission control transistor, the array substrate further includes a light emission control signal line, the light emission control signal line overlaps with the active layer to form the first light emission control transistor and the second light emission control transistor, the first light emission control transistor is connected between the first power line and the first electrode of the driving transistor, and the second light emission control transistor is connected between the second electrode of the driving transistor and the light emitting element;

[0029] Optionally, the light emitting control signal line is located in the first conductive layer;

[0030] Optionally, a vertical projection of the third scan line on the substrate is located on a side of a vertical projection of the first scan line on the substrate away from a vertical projection of the gate of the driving transistor on the substrate;

[0031] Optionally, a vertical projection of the light emitting control signal line on the substrate is located on a side of a vertical projection of the gate of the driving transistor on the substrate away from a vertical projection of the second scanning line on the substrate;

[0032] Optionally, a vertical projection of the fourth scan line on the substrate is located on a side of a vertical projection of the light emitting control signal line on the substrate away from a vertical projection of the gate of the driving transistor on the substrate.

[0033] According to another aspect of the present invention, a display panel is provided. The display panel includes the array substrate provided by any embodiment of the present invention.

[0034] The technical solution provided by the embodiment of the present invention is to set a first plate, a second plate and a third plate located in different conductive layers, and the vertical projection of the first plate on the substrate overlaps with the vertical projection of the second plate on the substrate, and respectively form the upper and lower plates of the storage capacitor; the vertical projection of the second plate on the substrate overlaps with the vertical projection of the third plate on the substrate, and respectively form the upper and lower plates of the voltage-stabilizing capacitor, thereby forming a storage capacitor and a voltage-stabilizing capacitor arranged in upper and lower layers. Compared with the related art, the technical solution provided by this embodiment can reduce the layout space occupied by the two capacitors through the storage capacitor and the voltage-stabilizing capacitor arranged in upper and lower layers, which is conducive to improving the utilization rate of the layout space, so that there can be a large enough space to layout the storage capacitor to increase the capacitance value of the storage capacitor, and then the gate potential of the driving transistor can be better maintained, which is conducive to improving the display effect. In addition, by using the second plate as the common plate of the storage capacitor and the voltage-stabilizing capacitor, the independence between the two capacitors can be guaranteed, and the mutual interference between the two can be reduced, thereby improving the reliability and stability of the storage capacitor and the voltage-stabilizing capacitor.

[0035] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic diagram of the structure of a pixel circuit provided by an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a planar structure of an array substrate provided by an embodiment of the present invention;

[0039] Figure 3 A schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the present invention;

[0040] Figure 4 A schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

[0041] Figure 5 A schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

[0042] Figure 6 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0043] Figure 7 A schematic diagram of a planar structure of another array substrate provided by an embodiment of the present invention;

[0044] Figure 8 A schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

[0045] Fig. 9 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0046] Fig.10 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0047] Fig.11 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0048] Fig.12 A schematic diagram of a planar structure of another array substrate provided by an embodiment of the present invention;

[0049] Fig.13 A schematic structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0051] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0052] As described in the background technology, the existing display panel has the problem of poor display effect. The inventors have found that the reasons for the above problems are as follows: the display panel includes a pixel circuit, the pixel circuit includes a plurality of thin film transistors, the thin film transistors include a driving transistor and a switching transistor, and due to various reasons such as the characteristics of the thin film transistor itself, the thin film transistor cannot be completely turned off, resulting in a leakage path between the gate of the driving transistor and the switching transistor connected to it, causing the gate voltage of the driving transistor to be unstable, causing the display brightness to be attenuated. In the related art, the gate leakage is usually reduced by adding a stabilizing capacitor to the node of the gate leakage path of the driving transistor, so that there are two larger capacitors in the pixel circuit, which increases the complexity of the pixel circuit layout, and affects the layout space of the original storage capacitor, resulting in a reduction in the storage capacitor, which is not conducive to the stability of the gate voltage of the driving transistor, thereby affecting the display effect.

[0053] In view of the above problems, an embodiment of the present invention provides an array substrate, which improves the display effect by optimizing the layout of pixel circuits. Figure 1 A schematic diagram of a pixel circuit according to an embodiment of the present invention is provided. Figure 2 A schematic diagram of a planar structure of an array substrate provided in an embodiment of the present invention, Figure 3 A schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the present invention, referring to Figure 1 , Figure 2 and Figure 3, the array substrate provided in this embodiment includes:

[0054] Base 10;

[0055] A plurality of conductive layers are stacked on one side of the substrate 10, and a plurality of pixel circuits are formed in the array substrate. The pixel circuits include a driving transistor Q1, a first leakage suppression transistor Q2, a storage capacitor C1, and a voltage stabilizing capacitor C2;

[0056] The multi-layer conductive layer at least includes a first conductive layer, a second conductive layer and a third conductive layer which are stacked, the first conductive layer includes a gate of the driving transistor Q1 and a first electrode plate 20 connected to the gate of the driving transistor Q1, the second conductive layer includes a second electrode plate 30, the third conductive layer includes a third electrode plate 40, a first leakage suppression transistor Q2 is connected between the first electrode plate 20 and the third electrode plate 40, and the first leakage suppression transistor Q2 is used to suppress the leakage current of the gate of the driving transistor Q1;

[0057] The vertical projection of the first electrode plate 20 on the substrate 10 overlaps with the vertical projection of the second electrode plate 30 on the substrate, and respectively form the upper and lower electrodes of the storage capacitor C1; the vertical projection of the second electrode plate 30 on the substrate 10 overlaps with the vertical projection of the third electrode plate 40 on the substrate 10, and respectively form the upper and lower electrodes of the voltage-stabilizing capacitor C2.

[0058] Specifically, the substrate 10 can be used to provide protection and support for the array substrate, wherein the substrate 10 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or a hard substrate formed of materials such as glass. The multiple conductive layers arranged on one side of the substrate 10 can be metal layers, and the multiple conductive layers are isolated from each other by insulating layers or dielectric layers.

[0059] A plurality of pixel circuits are formed on the array substrate, which are used to generate a driving current to drive the light-emitting element D1 connected to the pixel circuit to emit light. The pixel circuit is formed by at least a thin film transistor and a capacitor, the thin film transistor at least includes a driving transistor Q1 and a first leakage suppression transistor Q2, and the capacitor includes a storage capacitor C1 and a voltage-stabilizing capacitor C2. Among them, the storage capacitor C1 is used to store the gate voltage of the driving transistor Q1, the first leakage suppression transistor Q2 is used to suppress the leakage of the gate of the driving transistor Q1, and the voltage-stabilizing capacitor C2 is used to stabilize the voltage of the second electrode of the first leakage suppression transistor Q2 to reduce the voltage difference across the first leakage suppression transistor Q2, thereby reducing the leakage current of the gate of the driving transistor Q1.

[0060] The first electrode plate 20 located at the first conductive layer and the second electrode plate 30 located at the second conductive layer overlap to form the upper and lower electrodes of the storage capacitor C1. For example, the first electrode plate 20 can be the lower electrode plate of the storage capacitor C1, and the second electrode plate 30 can be the upper electrode plate of the storage capacitor C1. Since the first electrode plate 20 is connected to the gate of the driving transistor Q1, the first electrode plate 20 can be shared with the gate of the driving transistor Q1.

[0061] The overlapping part of the second electrode plate 30 located on the second conductive layer and the third electrode plate 40 located on the third conductive layer forms the upper and lower electrodes of the voltage-stabilizing capacitor C2. For example, the second electrode plate 30 can be the lower electrode plate of the voltage-stabilizing capacitor C2, and the third electrode plate 40 can be the upper electrode plate of the voltage-stabilizing capacitor C2.

[0062] In this embodiment, the vertical projection of the first plate 20 on the substrate 10 overlaps with the vertical projection of the second plate 30 on the substrate, and the vertical projection of the second plate 30 on the substrate 10 overlaps with the vertical projection of the third plate 40 on the substrate 10. That is, the first plate 20, the second plate 30 and the third plate 40 are stacked in the thickness direction (such as the Z direction) of the array substrate, so that the voltage-stabilizing capacitor C2 and the storage capacitor C1 can overlap each other, thereby reducing the layout space occupied by the two capacitors, which is conducive to improving the layout space utilization. At the same time, the storage capacitor C1 and the voltage-stabilizing capacitor C2 have a common plate, that is, the second plate 30 serves as both the upper plate of the storage capacitor C1 and the lower plate of the voltage-stabilizing capacitor C2. Therefore, the second plate 30 can be used as an electrical isolation layer to reduce the electromagnetic interference between the storage capacitor C1 and the voltage-stabilizing capacitor C2, reduce the capacitance change caused by external factors, and is conducive to ensuring the independence between the two capacitors, reducing mutual interference, thereby improving the reliability and stability of the storage capacitor C1 and the voltage-stabilizing capacitor C2.

[0063] The technical solution provided by the embodiment of the present invention is to set the first electrode plate 20, the second electrode plate 30 and the third electrode plate 40 located in different conductive layers, and the vertical projection of the first electrode plate 20 on the substrate 10 overlaps with the vertical projection of the second electrode plate 30 on the substrate, and respectively form the upper and lower electrodes of the storage capacitor C1; the vertical projection of the second electrode plate 30 on the substrate 10 overlaps with the vertical projection of the third electrode plate 40 on the substrate 10, and respectively form the upper and lower electrodes of the voltage-stabilizing capacitor C2, thereby forming the storage capacitor C1 and the voltage-stabilizing capacitor C2 arranged in upper and lower layers. Compared with the related art, the technical solution provided by this embodiment can reduce the layout space occupied by the two capacitors through the storage capacitor C1 and the voltage-stabilizing capacitor C2 arranged in upper and lower layers, which is conducive to improving the layout space utilization, so that there can be a large enough space to layout the storage capacitor C1, so as to increase the capacitance value of the storage capacitor C1, and then the gate potential of the driving transistor Q1 can be better maintained, which is conducive to improving the display effect. In addition, by using the second electrode plate 30 as the common electrode plate of the storage capacitor C1 and the voltage-stabilizing capacitor C2, the independence of the two capacitors can be ensured, and the mutual interference between the two can be reduced, thereby improving the reliability and stability of the storage capacitor C1 and the voltage-stabilizing capacitor C2.

[0064] Optionally, the vertical projection of the third electrode plate 40 on the substrate 10 falls within the vertical projection of the first electrode plate 20 and / or the second electrode plate 30 on the substrate 10. That is, the area of ​​the third electrode plate 40 is smaller than the area of ​​the second electrode plate 30, or smaller than the area of ​​the first electrode plate 20. That is, the overlapping area of ​​the first electrode plate 20 and the second electrode plate 30 is greater than the overlapping area of ​​the second electrode plate 30 and the third electrode plate 40. As a result, more other routings can be arranged on the third conductive layer, which is conducive to improving the layout space utilization and reducing the overall thickness of the film layer.

[0065] Figure 4 A schematic cross-sectional structure diagram of another array substrate provided in an embodiment of the present invention, referring to Figure 4 Based on the above embodiment, optionally, a first capacitor dielectric layer 12 is further included, and the first capacitor dielectric layer 12 is located between the second conductive layer and the third conductive layer. The first capacitor dielectric layer 12 is made of insulating material and is used to prevent current from directly passing through the capacitor and short-circuiting the upper and lower plates.

[0066] Since the area of ​​the third plate 40 is smaller than the area of ​​the second plate 30 or the first plate 20, in order to make the voltage-stabilizing capacitor C2 have a sufficiently large capacitance value, in this embodiment, the thickness of the first capacitor dielectric layer 12 between the second plate 30 and the third plate 40 is less than or equal to the thickness of the first capacitor dielectric layer 12 not covered by the third plate 40. Optionally, according to the capacitance formula, the capacitance of the capacitor is inversely proportional to the vertical distance between the upper and lower plates. Therefore, by thinning the first capacitor dielectric layer 12 between the second plate 30 and the third plate 40, it is beneficial to increase the capacitance value of the voltage-stabilizing capacitor C2, thereby compensating for the problem of capacitance value reduction caused by the small area of ​​the third plate 40 and the area of ​​the second plate 30, so as to ensure that the voltage-stabilizing capacitor C2 has a sufficiently large capacitance value, so as to improve the voltage-stabilizing effect of the voltage-stabilizing capacitor C2 on the second pole of the first leakage suppression transistor Q2.

[0067] Figure 5 A schematic cross-sectional structure diagram of another array substrate provided in an embodiment of the present invention, referring to Figure 5 On the basis of the above embodiment, optionally, the first capacitor dielectric layer 12 includes a plurality of sub-dielectric layers stacked, and the number of sub-dielectric layers between the second electrode plate 30 and the third electrode plate 40 is less than the number of sub-dielectric layers at the position not covered by the third electrode plate 40. That is, by etching away at least a portion of the sub-dielectric layer between the second electrode plate 30 and the third electrode plate 40, so that there is at least one sub-dielectric layer between the second electrode plate 30 and the third electrode plate 40, the purpose of thinning the first capacitor dielectric layer 12 between the second electrode plate 30 and the third electrode plate 40 is achieved.

[0068] Exemplarily, the first capacitor dielectric layer 12 includes four sub-dielectric layers stacked, namely, the first sub-dielectric layer 121, the second sub-dielectric layer 122, the third sub-dielectric layer 123 and the fourth sub-dielectric layer 124. After the first sub-dielectric layer 121, the second sub-dielectric layer 122, the third sub-dielectric layer 123 and the fourth sub-dielectric layer 124 are sequentially formed on the side of the second plate 30 away from the substrate 10, the fourth sub-dielectric layer 124, the third sub-dielectric layer 123 and / or the second sub-dielectric layer 122 at the position of the third plate 40 are etched to thin the sub-dielectric layer below the third plate 40. Among them, only the fourth sub-dielectric layer 124 can be etched, the fourth sub-dielectric layer 124 and the third sub-dielectric layer 123 can be etched at the same time, and the fourth sub-dielectric layer 124, the third sub-dielectric layer 123 and the second sub-dielectric layer 122 can also be etched at the same time. Among them, the thickness of the first sub-dielectric layer 121 is usually about 1000 angstroms, which can meet the needs of large capacitance. For example, at the same pixel density, such as 300PPI, by stacking the storage capacitor C1 and the voltage-stabilizing capacitor C2, the overlapping area of ​​the upper and lower plates of the storage capacitor C1 can be increased from the original 100μm^2 to 315μm^2, and accordingly, the capacitance value of the storage capacitor C1 is increased from the original 46fF to 145fF, which is increased by 3 times, effectively increasing the capacitance value of the storage capacitor C1. In addition, since the overlapping area of ​​the upper and lower plates of the voltage-stabilizing capacitor C2 is reduced, by thinning the first capacitor dielectric layer 12, the capacitance value of the voltage-stabilizing capacitor C2 can be maintained at the original value, and even the capacitance value of the voltage-stabilizing capacitor C2 can be increased to further meet the demand for large capacitance.

[0069] Continue to refer Figure 5 Optionally, the multiple sub-dielectric layers may all be inorganic film layers, for example, formed of SiNx, SiOx or SiNOx. In an optional implementation provided in this embodiment, the first sub-dielectric layer 121 is SiNx, the second sub-dielectric layer 122 is SiOx, the third sub-dielectric layer 123 is SiNx, and the fourth sub-dielectric layer 124 is SiOx.

[0070] In this embodiment, in the multi-layer sub-dielectric layer, the dielectric constant of the sub-dielectric layer close to the second electrode 30 is greater than the dielectric constant of the remaining sub-dielectric layers. That is, the dielectric constant of the first sub-dielectric layer 121 is greater than the dielectric constants of the second sub-dielectric layer 122, the third sub-dielectric layer 123 and the fourth sub-dielectric layer 124, and the dielectric material used in the first sub-dielectric layer 121 is different from the dielectric material used in the second sub-dielectric layer 122, the third sub-dielectric layer 123 and the fourth sub-dielectric layer 124. By setting the first sub-dielectric layer 121 and the third sub-dielectric layer 123 to be different types of SiNx, the difference in dielectric constants can be achieved. For example, the first sub-dielectric layer 121 can be narrow bandgap silicon nitride (boron-doped silicon nitride, B-SiNx), and the third sub-dielectric layer 123 can be thermal silicon nitride (thermal silicon nitride, T-SiNx). According to the capacitance formula, the capacitance value of the capacitor is also proportional to the dielectric constant of the dielectric layer. By increasing the dielectric constant of the dielectric layer, the capacitance value of the voltage-stabilizing capacitor C2 can be increased.

[0071] Figure 6 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, Figure 7 A schematic diagram of a planar structure of another array substrate provided in an embodiment of the present invention, referring to Figure 6 and Figure 7 On the basis of the above embodiments, optionally, an active layer 21 is further included on one side of the substrate 10, the first conductive layer further includes a first scan line 31 extending along the first direction X, and the first scan line 31 overlaps with the active layer 21 to form a first leakage suppression transistor Q2. The third conductive layer further includes a first power line 42 and a transition portion 51, the first power line 42 extends along the second direction Y, the first power line 42 is connected to the second electrode plate 30 through a via, the first electrode of the first leakage suppression transistor Q2 is connected to the gate of the driving transistor Q1 through the transition portion 51, and the second electrode of the first leakage suppression transistor Q2 is connected to the third electrode plate 40 through a via. Among them, the first direction X intersects with the second direction Y, and both are perpendicular to the thickness direction of the array substrate.

[0072] When the first leakage suppression transistor Q2 changes from on to off, the parasitic capacitance between the gate of the first leakage suppression transistor Q2 and the gate of the driving transistor Q1 is coupled, coupling the gate voltage of the driving transistor Q1, so that the gate potential of the driving transistor Q1 is close to the potential of the second electrode of the first leakage transistor Q2, thereby reducing the voltage difference between the first electrode and the second electrode of the first leakage transistor Q2, which is conducive to reducing the leakage current of the first leakage transistor Q2, and then maintaining the gate potential of the driving transistor Q1 stable. Here, the gate of the driving transistor Q1 is reused as the first plate 20 of the storage capacitor C1.

[0073] Optionally, the pixel circuit also includes a second leakage suppression transistor Q3 and a compensation transistor Q4, the first conductive layer also includes a second scan line 32, the vertical projection of the second scan line 32 on the substrate 10 is located between the vertical projection of the gate of the driving transistor Q1 on the substrate 10 and the vertical projection of the first scan line 31 on the substrate 10, the first scan line 31 overlaps with the active layer 21 to form the second leakage suppression transistor Q3, and the second scan line 32 overlaps with the active layer 21 to form the compensation transistor Q4; the second electrode of the first leakage suppression transistor Q2 is connected to the first electrode of the second leakage suppression transistor Q3, the second electrode of the second leakage suppression transistor Q3 is connected to the first electrode of the compensation transistor Q4, and the second electrode of the compensation transistor Q4 is connected to the second electrode of the driving transistor Q1.

[0074] Optionally, the second leakage suppression transistor Q3 may be a horizontal dual-gate transistor or a single-gate transistor.

[0075] Optionally, the pixel circuit further includes a data writing transistor Q5, the second scanning line 32 overlaps with the active layer 21 to form the data writing transistor Q5, and the data writing transistor Q5 is connected between the data line 41 and the first electrode of the driving transistor Q1. The data line 41 is located in the third conductive layer, and the data line 41 extends along the second direction Y.

[0076] Continue to refer Figure 6 and Figure 7 Optionally, the pixel circuit further includes a first initialization transistor Q8 and a second initialization transistor Q9, and the array substrate further includes a third scan line 33, a fourth scan line 34, a first initialization signal line 43 and a second initialization signal line 44, the third scan line 33 overlaps with the active layer 21 to form the first initialization transistor Q8, and the fourth scan line 34 overlaps with the active layer 21 to form the second initialization transistor Q9; the first initialization transistor Q8 is connected between the first initialization signal line 43 and the first electrode of the second leakage suppression transistor Q3, and is used to transmit the first initialization voltage Vref1 on the first initialization signal line 43 to the gate of the driving transistor Q1; the second initialization transistor Q9 is connected between the second initialization signal line 44 and the light emitting element D1, and is used to transmit the second initialization voltage Vref2 on the second initialization signal line 44 to the light emitting element D1. Among them, the first initialization transistor Q8 is a horizontal dual-gate transistor to reduce leakage current.

[0077] The third scan line 33 and the fourth scan line 34 are arranged in the same layer, and are arranged in different layers from the first initialization signal line 43 and the second initialization signal line 44, so as to facilitate layout. For example, the third scan line 33 and the fourth scan line 34 are located in the first conductive layer, and the initialization signal line 43 and the second initialization signal line 44 are located in the second conductive layer.

[0078] Optionally, the pixel circuit also includes a first light-emitting control transistor Q6 and a second light-emitting control transistor Q7, and the array substrate also includes a light-emitting control signal line 35, the light-emitting control signal line 35 overlaps with the active layer 21 to form a first light-emitting control transistor Q6 and a second light-emitting control transistor Q7, the first light-emitting control transistor Q6 is connected between the first power line 42 and the first electrode of the driving transistor Q1, and the second light-emitting control transistor Q7 is connected between the second electrode of the driving transistor Q1 and the light-emitting element D1; wherein the light-emitting control signal line 35 is located in the first conductive layer.

[0079] In this embodiment, the vertical projection of the third scan line 33 on the substrate 10 is located on a side where the vertical projection of the first scan line 31 on the substrate 10 is away from the vertical projection of the gate of the driving transistor Q1 on the substrate 10; the vertical projection of the light emitting control signal line 35 on the substrate 10 is located on a side where the vertical projection of the gate of the driving transistor Q1 on the substrate 10 is away from the vertical projection of the second scan line 32 on the substrate 10; the vertical projection of the fourth scan line 34 on the substrate 10 is located on a side where the vertical projection of the light emitting control signal line 35 on the substrate 10 is away from the vertical projection of the gate of the driving transistor Q1 on the substrate 10.

[0080] Figure 8 A schematic cross-sectional structure diagram of another array substrate provided in an embodiment of the present invention, specifically: Figure 7 The cross-sectional structure of the array substrate along the cutting line BB' is shown in FIG. Figure 7 and Figure 8 The data line 41, the first power line 42 and the third plate 40 are all located in the third conductive layer, and the data line 41, the first power line 42 and the third plate 40 are insulated from each other. In the first direction X, the width of the third plate 40 is set to be smaller than the width of the second plate 30 to avoid the layout space of the first power line 42, and the thickness of the first capacitor dielectric layer 12 under the third plate 40 is thinned so that the third plate 40 and the second plate 30 can still form a voltage-stabilizing capacitor C2 with a large capacitance value. A second capacitor dielectric layer 11 is provided between the second plate 30 and the first plate 20, and the second capacitor dielectric layer 11 is used to insulate the second plate 30 and the first plate 20 to prevent the second plate 30 and the first plate 20 from short-circuiting. Among them, the material of the second capacitor dielectric layer 11 can be the same as the material of the first capacitor dielectric layer 12.

[0081] The technical solution provided in this embodiment can reduce the layout space occupied by the two capacitors by stacking the storage capacitor C1 and the voltage-stabilizing capacitor C2 in an upper and lower layer, which is beneficial to improving the utilization rate of the layout space, so that there is enough space to layout the storage capacitor C1 to increase the capacitance value of the storage capacitor C1, and then the gate potential of the driving transistor Q1 can be better maintained, which is beneficial to improving the display effect. In addition, by using the second electrode plate 30 as the common electrode plate of the storage capacitor C1 and the voltage-stabilizing capacitor C2, the independence between the two capacitors can be guaranteed, and the mutual interference between the two can be reduced, thereby improving the reliability and stability of the storage capacitor C1 and the voltage-stabilizing capacitor C2.

[0082] Fig. 9 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention can be applied to Figure 6 The pixel circuit shown in FIG. 1 is based on the above embodiments and is combined with Figure 6 and Fig. 9 Taking the case where all transistors are P-type transistors as an example, the pixel circuit provided in this embodiment includes a writing frame and a holding frame in a display cycle, wherein the writing frame includes a first stage T11, a second stage T21, a third stage T31 and a fourth stage T41, and the holding frame includes a fifth stage T51, a sixth stage T61 and a seventh stage T71.

[0083] In the first stage T11 (corresponding to the initialization stage of writing the frame), the first scanning signal S1 is at a low level, the second scanning signal S2 is at a high level, the third scanning signal S3 is at a low level, the fourth scanning signal S4 is at a high level, and the light-emitting control signal EM is at a high level, so the first leakage suppression transistor Q2, the second leakage suppression transistor Q3 and the first initialization transistor Q8 are turned on, and the compensation transistor Q4, the data writing transistor Q5, the second initialization transistor Q9, the first light-emitting control transistor Q6 and the second light-emitting control transistor Q7 are turned off. The first initialization voltage Vref1 on the first initialization signal line 43 is transmitted to the gate of the driving transistor Q1 through the first initialization transistor Q8 and the first leakage suppression transistor Q2, and the gate of the driving transistor Q1 is initialized, and the driving transistor Q1 is turned on at the same time.

[0084] In the second stage T21 (corresponding to the data writing and compensation stage of the writing frame), the first scanning signal S1 is low level, the second scanning signal S2 is low level, the third scanning signal S3 is high level, the fourth scanning signal S4 is low level, and the light control signal EM is high level, so the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the compensation transistor Q4, the data writing transistor Q5 and the second initialization transistor Q9 are turned on, and the first initialization transistor Q8, the first light control transistor Q6 and the second light control transistor Q7 are turned off. The data voltage Vdata on the data line 41 is written to the gate of the driving transistor Q1 through the data writing transistor Q5, the driving transistor Q1, the compensation transistor Q4, the second leakage suppression transistor Q3 and the first leakage suppression transistor Q2. When the gate voltage of the driving transistor Q1 reaches Vdata+Vth1, the driving transistor Q1 is turned off to achieve data writing and threshold voltage compensation. The gate voltage of the driving transistor Q1 is stored in the storage capacitor C1, and the voltage stabilizing capacitor C2 is used to store the voltage of the second electrode of the first leakage suppression transistor Q2. Wherein, Vth1 is the threshold voltage of the driving transistor Q1.

[0085] When the first scanning signal S1 jumps from a low level to a high level, the first leakage suppression transistor Q2 changes from on to off. Under the coupling effect of the parasitic capacitance of the gate of the driving transistor Q1, the gate voltage of the driving transistor Q1 is pulled up to be close to the voltage stored on the voltage-stabilizing capacitor C2. Therefore, the voltage difference between the first electrode and the second electrode of the first leakage suppression transistor Q2 is small, so that the leakage current of the first leakage suppression transistor Q2 is small, thereby maintaining the gate voltage of the driving transistor Q1 stable.

[0086] Meanwhile, in the second stage T21 , the second initialization voltage Vref2 on the second initialization signal line 44 is transmitted to the first electrode of the light emitting element D1 via the second initialization transistor Q9 to initialize the first electrode of the light emitting element D1 .

[0087] In the third stage T31 (corresponding to the voltage bias stage of writing the frame), the first scanning signal S1 is at a high level, the second scanning signal S2 is at a low level, the third scanning signal S3 is at a high level, the fourth scanning signal S4 is at a high level, and the light-emitting control signal EM is at a high level. Therefore, the compensation transistor Q4 and the data writing transistor Q5 are turned on, and the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the first initialization transistor Q8, the second initialization transistor Q9, the first light-emitting control transistor Q6, and the second light-emitting control transistor Q7 are turned off. The data line 41 writes a bias voltage (the bias voltage may be different from the data voltage Vdata) to the first electrode of the driving transistor Q1 through the data writing transistor Q5. For example, the bias voltage may be a series of pulse voltages, which may be used to release stress in the driving transistor (especially stress in the driving transistor Q1 under low grayscale display), which is beneficial to improving the performance and reliability of the driving transistor Q1. Among them, the bias voltage is a positive voltage.

[0088] In the fourth stage T41 (corresponding to the light-emitting stage of the write frame), the first scanning signal S1 is high, the second scanning signal S2 is high, the third scanning signal S3 is high, the fourth scanning signal S4 is high, and the light-emitting control signal EM is low. Therefore, the first light-emitting control transistor Q6 and the second light-emitting control transistor Q7 are turned on, and the compensation transistor Q4, the data writing transistor Q5, the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the first initialization transistor Q8, and the second initialization transistor Q9 are turned off. The driving transistor Q1 generates a driving current to drive the light-emitting element D1 to emit light. Since the gate voltage of the driving transistor Q1 can remain stable for a long time, the uniformity of the driving current can be guaranteed, and the afterimage problem of the display screen can be improved.

[0089] In the fifth stage T51 (which may correspond to the initialization stage of maintaining the frame), the specific working process is the same as the working process of the second stage T21, and reference may be made to the above related description.

[0090] The specific working process in the sixth stage T61 (which may correspond to the voltage bias stage of the frame holding) is the same as the working process in the third stage T31, and reference may be made to the above related description.

[0091] The specific working process in the seventh stage T71 (which may correspond to the light-emitting stage of the holding frame) is the same as the working process in the fourth stage T41, and reference may be made to the above related description.

[0092] The technical solution provided in this embodiment, by setting a holding frame and setting the fifth stage T5 and the sixth stage T6 in the holding frame, is equivalent to increasing the number of times the light-emitting element D1 emits light in a display cycle, and can convert the low-frequency brightness components that are easily perceived by the human eye into high-frequency brightness components that are not easily perceived, thereby improving the flickering phenomenon of the display screen. In addition, the storage capacitor C1 in the pixel circuit can have a large capacitance value, which is conducive to improving the stability of the gate potential of the driving transistor Q1, and by periodically applying a positive bias voltage to the first electrode of the driving transistor Q1, the stress of the driving transistor Q1 can be released, thereby further improving the low grayscale display effect.

[0093] Fig.10 A schematic diagram of another pixel circuit structure provided by an embodiment of the present invention, compared to Figure 6 The pixel circuit shown in Fig.10 In the pixel circuit shown, the first initialization transistor Q8 is connected to the second electrode of the second leakage suppression transistor Q3. In the corresponding layout structure, it is only necessary to change the connection relationship between the first initialization transistor Q8 and the second leakage suppression transistor Q3.

[0094] Fig.11 Another driving timing diagram of a pixel circuit provided in an embodiment of the present invention can be applied to Fig.10 The pixel circuit shown, reference Fig.10 and Fig.11 The pixel circuit provided in this embodiment includes a writing frame and a holding frame in a display cycle, wherein the writing frame includes a first stage T12, a second stage T22, a third stage T32 and a fourth stage T42, and the holding frame includes a fifth stage T52, a sixth stage T62 and a seventh stage T72.

[0095] In the first stage T12 (corresponding to the first initialization stage of the write frame), the first scanning signal S1 is low, the second scanning signal S2 is low, the third scanning signal S3 is low, the fourth scanning signal S4 is high, and the light-emitting control signal EM is high, so the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the compensation transistor Q4, the data writing transistor Q5 and the first initialization transistor Q8 are turned on, and the second initialization transistor Q9, the first light-emitting control transistor Q6 and the second light-emitting control transistor Q7 are turned off. The first initialization voltage Vref1 on the first initialization signal line 43 is transmitted to the gate of the driving transistor Q1 through the first initialization transistor Q8, the second leakage suppression transistor Q3 and the first leakage suppression transistor Q2, and the storage capacitor C1 and the voltage-stabilizing capacitor C2 are initialized, and the initialization of the gate of the driving transistor Q1 is completed to turn on the driving transistor Q1.

[0096] In the second stage T22 (corresponding to the data writing and compensation stage of the writing frame), the first scanning signal S1 is low level, the second scanning signal S2 is low level, the third scanning signal S3 is high level, the fourth scanning signal S4 is low level, and the light control signal EM is high level, so the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the compensation transistor Q4, and the data writing transistor Q5 are turned on, and the first initialization transistor Q8, the second initialization transistor Q9, the first light control transistor Q6, and the second light control transistor Q7 are turned off. The data voltage Vdata on the data line 41 is written to the gate of the driving transistor Q1 through the data writing transistor Q5, the driving transistor Q1, the compensation transistor Q4, the second leakage suppression transistor Q3, and the first leakage suppression transistor Q2. When the gate voltage of the driving transistor Q1 reaches Vdata+Vth1, the driving transistor Q1 is turned off to achieve data writing and threshold voltage compensation. The gate voltage of the driving transistor Q1 is stored in the storage capacitor C1, and the voltage stabilizing capacitor C2 is used to store the voltage of the second electrode of the first leakage suppression transistor Q2. Wherein, Vth1 is the threshold voltage of the driving transistor Q1.

[0097] When the first scanning signal S1 jumps from a low level to a high level, the first leakage suppression transistor Q2 changes from on to off. Under the coupling effect of the parasitic capacitance of the gate of the driving transistor Q1, the gate voltage of the driving transistor Q1 is pulled up to be close to the voltage stored on the voltage-stabilizing capacitor C2. Therefore, the voltage difference between the first electrode and the second electrode of the first leakage suppression transistor Q2 is small, so that the leakage current of the first leakage suppression transistor Q2 is small, thereby maintaining the gate voltage of the driving transistor Q1 stable.

[0098] In the third stage T32 (corresponding to the second initialization stage of the write frame), the first scan signal S1 is at a high level, the second scan signal S2 is at a high level, the third scan signal S3 is at a high level, the fourth scan signal S4 is at a low level, and the light control signal EM is at a high level, so the second initialization transistor Q9 is turned on, the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the compensation transistor Q4, the data writing transistor Q5, the first initialization transistor Q8, the first light control transistor Q6, and the second light control transistor Q7 are turned off. The second initialization voltage Vref2 on the second initialization signal line 44 is transmitted to the first electrode of the light emitting element D1 through the second initialization transistor Q9 to initialize the first electrode of the light emitting element D1.

[0099] In the fourth stage T42 (corresponding to the light-emitting stage of the write frame), the first scanning signal S1 is at a high level, the second scanning signal S2 is at a high level, the third scanning signal S3 is at a high level, the fourth scanning signal S4 is at a high level, and the light-emitting control signal EM is at a low level. Therefore, the first light-emitting control transistor Q6 and the second light-emitting control transistor Q7 are turned on, and the compensation transistor Q4, the data writing transistor Q5, the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the first initialization transistor Q8, and the second initialization transistor Q9 are turned off. The driving transistor Q1 generates a driving current to drive the light-emitting element D1 to emit light. Since the gate voltage of the driving transistor Q1 can remain stable for a long time, the uniformity of the driving current can be guaranteed, and the afterimage problem of the display screen can be improved.

[0100] In the fifth stage T52 (which may correspond to the voltage bias stage of the holding frame), the first scanning signal S1 is at a high level, the second scanning signal S2 is at a low level, the third scanning signal S3 is at a low level, the fourth scanning signal S4 is at a high level, and the light-emitting control signal EM is at a high level, so the first initialization transistor Q8, the compensation transistor Q4, and the data writing transistor Q5 are turned on, and the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the second initialization transistor Q9, the first light-emitting control transistor Q6, and the second light-emitting control transistor Q7 are turned off. The data line 41, the data writing transistor Q5, the driving transistor Q1, the compensation transistor Q4, the first initialization transistor Q8, and the first initialization signal line 43 are connected, and a large current flows through the driving transistor Q1, which can be used to release the stress in the driving transistor, which is conducive to improving the performance and reliability of the driving transistor Q1. Among them, the voltage transmitted on the data line 41 is a positive voltage. Optionally, in some embodiments, the voltage transmitted on the data line 41 may be the same as the first power supply voltage VDD.

[0101] The specific working process in the sixth stage T62 (which may correspond to the initialization stage of maintaining the frame) is the same as the working process in the third stage T32, and reference may be made to the above related description.

[0102] The specific working process in the seventh stage T72 (which may correspond to the light-emitting stage of the holding frame) is the same as the working process in the fourth stage T42, and reference may be made to the above related description.

[0103] The pixel circuit provided in this embodiment is Figure 6 The pixel circuit shown has the same beneficial effects.

[0104] Optionally, in Figure 6 and Fig.10 In the pixel circuit shown, the first initialization signal line 43 can be multiplexed as the second initialization signal line 44, and the third scan line 33 can be multiplexed as the fourth scan line 34, so as to save the number of signal lines, reduce the layout space occupied, and help improve PPI. Fig.12 A schematic diagram of a planar structure of another array substrate provided in an embodiment of the present invention, referring to Fig.12 The third scanning line 33 overlaps with the active layer 21 to form a first initialization transistor Q8 and a second initialization transistor Q9, and the first initialization transistor Q8 is a horizontal double-gate transistor. The first initialization transistor Q8 and the second initialization transistor Q9 are connected to the first initialization signal line 43 via the switching portion 51. The connection method of other parts is the same as Figure 7 The structures shown are the same and will not be described in detail.

[0105] Optionally, an embodiment of the present invention further provides a display panel, which includes the array substrate provided by any embodiment of the present invention, so the display panel also has the beneficial effects described in any of the above embodiments. The display panel can be a flexible display panel or a rigid display panel. The display panel formed by using the array substrate provided by any of the above embodiments can effectively improve the display effect of AOD (Always On Display). Fig.13 A structural schematic diagram of a display panel provided in an embodiment of the present invention. In this embodiment, the display panel 200 can be a mobile phone panel, and can also be applied to any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals and other products. The embodiment of the present invention does not make any special limitations on this.

[0106] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0107] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of conductive layers stacked on one side of the substrate, wherein a plurality of pixel circuits are formed in the array substrate, and the pixel circuits include a driving transistor, a first leakage suppression transistor, a storage capacitor and a voltage stabilizing capacitor; The multi-layer conductive layer at least includes a first conductive layer, a second conductive layer and a third conductive layer which are stacked, the first conductive layer includes a gate of the driving transistor and a first electrode plate connected to the gate of the driving transistor, the second conductive layer includes a second electrode plate, the third conductive layer includes a third electrode plate, and the first leakage suppression transistor is connected between the first electrode plate and the third electrode plate; The vertical projection of the first electrode plate on the substrate overlaps with the vertical projection of the second electrode plate on the substrate, and respectively form the upper and lower electrodes of the storage capacitor; the vertical projection of the second electrode plate on the substrate overlaps with the vertical projection of the third electrode plate on the substrate, and respectively form the upper and lower electrodes of the voltage-stabilizing capacitor.

2. The array substrate according to claim 1, characterized in that: The vertical projection of the third electrode plate on the substrate falls within the vertical projection of the first electrode plate and / or the second electrode plate on the substrate; Preferably, an overlapping area between the first electrode plate and the second electrode plate is greater than an overlapping area between the second electrode plate and the third electrode plate.

3. The array substrate according to claim 1, characterized in that: It also includes a first capacitor dielectric layer, which is located between the second conductive layer and the third conductive layer, and the thickness of the first capacitor dielectric layer between the second electrode plate and the third electrode plate is less than or equal to the thickness of the first capacitor dielectric layer not covered by the third electrode plate.

4. The array substrate according to claim 3, characterized in that: The first capacitor dielectric layer includes a plurality of stacked sub-dielectric layers, and the number of sub-dielectric layers between the second electrode plate and the third electrode plate is less than the number of sub-dielectric layers at a position not covered by the third electrode plate.

5. The array substrate according to claim 4, characterized in that: In the multi-layer sub-dielectric layer, the sub-dielectric layer close to the second electrode plate and the remaining sub-dielectric layers are made of different dielectric materials; Preferably, the dielectric constant of the sub-dielectric layer close to the second electrode plate is greater than the dielectric constants of the remaining sub-dielectric layers.

6. The array substrate according to any one of claims 1 to 5, characterized in that: An active layer is further included on one side of the substrate, the first conductive layer further includes a first scanning line extending along a first direction, and the first scanning line overlaps with the active layer to form the first leakage suppression transistor; Preferably, the third conductive layer further includes a first power line and a transition portion, the first power line extends along the second direction, the first power line is connected to the second electrode plate through a via, the first electrode of the first leakage suppression transistor is connected to the gate of the driving transistor through the transition portion, and the second electrode of the first leakage suppression transistor is connected to the third electrode plate through a via; The first direction intersects with the second direction, and both are perpendicular to the thickness direction of the array substrate.

7. The array substrate according to claim 6, characterized in that: The pixel circuit further includes a second leakage suppression transistor and a compensation transistor, the first conductive layer further includes a second scan line, the vertical projection of the second scan line on the substrate is located between the vertical projection of the gate of the driving transistor on the substrate and the vertical projection of the first scan line on the substrate, the first scan line overlaps with the active layer to form the second leakage suppression transistor, and the second scan line overlaps with the active layer to form the compensation transistor; The second electrode of the first leakage suppression transistor is connected to the first electrode of the second leakage suppression transistor, the second electrode of the second leakage suppression transistor is connected to the first electrode of the compensation transistor, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor; Preferably, the pixel circuit further comprises a data writing transistor, the second scanning line overlaps with the active layer to form the data writing transistor, and the data writing transistor is connected between the data line and the first electrode of the driving transistor; Preferably, the data line is located in the third conductive layer, and the data line extends along the second direction.

8. The array substrate according to claim 7, characterized in that: The pixel circuit further includes a first initialization transistor and a second initialization transistor, and the array substrate further includes a third scan line, a fourth scan line, a first initialization signal line, and a second initialization signal line, wherein the third scan line overlaps with the active layer to form the first initialization transistor, and the fourth scan line overlaps with the active layer to form the second initialization transistor; the first initialization transistor is connected between the first initialization signal line and the first electrode or the second electrode of the second leakage suppression transistor, and is used to transmit the first initialization voltage on the first initialization signal line to the gate of the driving transistor; The second initialization transistor is connected between the second initialization signal line and the light emitting element, and is used to transmit the second initialization voltage on the second initialization signal line to the light emitting element; Preferably, the third scan line and the fourth scan line are arranged in the same layer, and are arranged in different layers from the first initialization signal line and the second initialization signal line; Preferably, the third scan line and the fourth scan line are located in the first conductive layer, and the initialization signal line and the second initialization signal line are located in the second conductive layer; Preferably, the first initialization signal line is multiplexed as the second initialization signal line; Preferably, the third scan line is multiplexed as the fourth scan line.

9. The array substrate according to claim 8, characterized in that: The pixel circuit further includes a first light emission control transistor and a second light emission control transistor, the array substrate further includes a light emission control signal line, the light emission control signal line overlaps with the active layer to form the first light emission control transistor and the second light emission control transistor, the first light emission control transistor is connected between the first power line and the first electrode of the driving transistor, and the second light emission control transistor is connected between the second electrode of the driving transistor and the light emitting element; Preferably, the light emitting control signal line is located in the first conductive layer; Preferably, a vertical projection of the third scanning line on the substrate is located on a side of a vertical projection of the first scanning line on the substrate away from a vertical projection of the gate of the driving transistor on the substrate; Preferably, a vertical projection of the light emitting control signal line on the substrate is located on a side where a vertical projection of the gate electrode of the driving transistor on the substrate is away from a vertical projection of the second scanning line on the substrate; Preferably, a vertical projection of the fourth scan line on the substrate is located on a side of a vertical projection of the light emitting control signal line on the substrate away from a vertical projection of the gate of the driving transistor on the substrate.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

Images