Image sensor and method for manufacturing same

Abstract

An image sensor and a method for manufacturing the same are provided. The image sensor includes: a substrate including a first surface and a second surface opposite to each other; a first pixel group in the substrate, the first pixel group including a first unit pixel, a second unit pixel, a third unit pixel, and a fourth unit pixel; a photoelectric conversion region in each of the first to fourth unit pixels; a first isolation trench in the substrate, the first isolation trench surrounding the first pixel group; a second isolation trench in the substrate, the second isolation trench between the first unit pixel and the fourth unit pixel and between the second unit pixel and the third unit pixel, in which the second isolation trench is in contact with the second surface of the substrate; and a first color filter on the second surface of the substrate, the first color filter covering the first pixel group.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0120247 filed in the Korean Intellectual Property Office on September 11, 2023 and all rights arising therefrom, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to image sensors and methods for manufacturing the same. More particularly, the present disclosure relates to CMOS type image sensors. Background Art

[0004] An image sensor is a semiconductor device that converts optical information into an electrical signal. The image sensor may include a CCD (Charge Coupled Device) image sensor and a CMOS (Complementary Metal Oxide Semiconductor) type image sensor.

[0005] The image sensor may be configured in the form of a package, wherein the package may be configured to protect the image sensor and at the same time may be configured to allow light to be incident on a light receiving surface photo or sensing area of ​​the image sensor. Summary of the invention

[0006] Aspects of the present disclosure provide image sensors with improved performance and integration.

[0007] Other aspects of the present disclosure provide methods for fabricating image sensors with improved performance and integration.

[0008] However, the aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0009] According to some aspects of the present invention, there is provided an image sensor, which includes: a substrate including a first surface and a second surface opposite to each other; a first pixel group located in the substrate, the first pixel group including a first unit pixel, a second unit pixel adjacent to the first unit pixel in a first direction in a plan view, a third unit pixel adjacent to the first unit pixel in a second direction perpendicular to the first direction in a plan view, and a fourth unit pixel adjacent to the second unit pixel in a second direction in a plan view and adjacent to the third unit pixel in the first direction in a plan view; a photoelectric conversion region located in each of the first to fourth unit pixels; a first isolation trench located in the substrate, the first isolation trench surrounding the first pixel group; a second isolation trench located in the substrate, the second isolation trench located between the first unit pixel and the fourth unit pixel and between the second unit pixel and the third unit pixel, wherein the second isolation trench contacts the second surface of the substrate; and a first color filter located on the second surface of the substrate, the first color filter covering the first pixel group.

[0010] According to some aspects of the present invention, there is provided an image sensor comprising: a substrate comprising a first surface and a second surface opposite to each other; a first isolation trench defining a plurality of pixel groups in the substrate, each of the pixel groups comprising a plurality of unit pixels; a second isolation trench located in each of the pixel groups, the second isolation trench extending from the second surface and spaced apart from the first surface; a photoelectric conversion region located in each of the unit pixels; a circuit element located on the first surface of the substrate; and a color filter located on the second surface of the substrate, wherein the plurality of unit pixels include a first unit pixel, a second unit pixel adjacent to the first unit pixel in a first direction, and a third unit pixel adjacent to the first unit pixel in a second direction intersecting the first direction, wherein the second isolation trench is located between the second unit pixel and the third unit pixel.

[0011] According to some aspects of the present invention, an image sensor is provided, which includes: a substrate including a first surface and a second surface opposite to each other; a first pixel group located in the substrate, the first pixel group including a first unit pixel, a second unit pixel adjacent to the first unit pixel in a first direction, a third unit pixel adjacent to the first unit pixel in a second direction intersecting the first direction, and a fourth unit pixel adjacent to the second unit pixel in the second direction and adjacent to the third unit pixel in the first direction; a photoelectric conversion region located in each of the first to fourth unit pixels; a first isolation trench located in the substrate, the first isolation trench surrounding the first pixel group ; a second isolation trench located in the substrate, the second isolation trench being located between the first unit pixel and the fourth unit pixel; a floating diffusion region extending from the first surface in the substrate, at least a portion of the floating diffusion region overlapping with the second isolation trench in a third direction intersecting the first direction and the second direction; a transfer transistor located on the first surface of each of the first to fourth unit pixels, the transfer transistor being adjacent to the floating diffusion region; a first color filter located on the second surface of the substrate, the first color filter covering the first pixel group and having a first color; and a microlens located on the first color filter, wherein the second isolation trench extends from the second surface and is spaced apart from the floating diffusion region. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0013] Figure 1 is an illustrative block diagram for illustrating an image sensor according to some example embodiments.

[0014] Figure 2 is an illustrative circuit diagram for illustrating a unit pixel of an image sensor according to some example embodiments.

[0015] Figure 3 is a layout diagram for illustrating an image sensor according to some example embodiments.

[0016] Figure 4 It is along Figure 3 Schematic cross-sectional view taken along line AA in FIG.

[0017] Figure 5 It is along Figure 3 Schematic cross-sectional view taken along line BB in FIG.

[0018] Figure 6 It is along Figure 3 Schematic cross-sectional view taken along line CC in FIG.

[0019] Figure 7 It is used to show Figures 3 to 6 A cross-sectional diagram of the effect of an image sensor.

[0020] Figures 8 to 10 is a cross-sectional view for illustrating an image sensor according to some example embodiments.

[0021] Fig.11 is a cross-sectional view for illustrating an image sensor according to some example embodiments.

[0022] Figure 12 to Figure 14 are various layout diagrams for illustrating image sensors according to some example embodiments.

[0023] Fig.15 is a schematic layout diagram for illustrating an image sensor according to some example embodiments.

[0024] Fig.16 It is used to show Fig.15 Schematic cross-sectional view of an image sensor in FIG.

[0025] Figures 17 to 24 are diagrams of intermediate structures corresponding to intermediate steps of a method of manufacturing an image sensor according to some example embodiments.

[0026] Figures 25 to 30 are diagrams of intermediate structures corresponding to intermediate steps of a method for manufacturing an image sensor according to some example embodiments. DETAILED DESCRIPTION

[0027] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be named as the second element, component, region, layer or part.

[0028] In the following, reference is made to Figures 1 to 16 , describing an image sensor according to some example embodiments.

[0029] Figure 1 is an illustrative block diagram for illustrating an image sensor according to some example embodiments.

[0030] Reference Figure 1According to some example embodiments, the image sensor includes an active pixel sensor array (APS) 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7, and an input / output buffer (I / O buffer) 8.

[0031] The active pixel sensor array 1 includes a plurality of unit pixels arranged two-dimensionally and can convert an optical signal into an electrical signal. The active pixel sensor array 1 can operate based on a plurality of driving signals (such as a pixel selection signal, a reset signal, and a charge transfer signal) from a row driver 3. In addition, the electrical signal generated from the active pixel sensor array 1 can be provided to a correlated double sampler 6.

[0032] The row driver 3 may provide a plurality of driving signals for driving a plurality of unit pixels to the active pixel sensor array 1 according to the decoding result from the row decoder 2. When the unit pixels are arranged in a matrix form, the driving signals may be provided on a per-row basis.

[0033] The timing generator 5 may provide timing signals and control signals to the row decoder 2 and the column decoder 4 .

[0034] The correlated double sampler (CDS) 6 may receive the electrical signal generated from the active pixel sensor array 1 and perform holding and sampling on the received electrical signal. The correlated double sampler 6 may double-sample a specific noise level and a signal level generated by the electrical signal and output a difference level corresponding to the difference between the noise level and the signal level.

[0035] The analog-to-digital converter (ADC) 7 may convert an analog signal corresponding to the difference level output from the correlated double sampler 6 into a digital signal and output the digital signal.

[0036] The input / output buffer 8 may latch the digital signal, and may sequentially output the latched digital signal to an image signal processor (not shown) according to the decoding result from the column decoder 4 .

[0037] Figure 2 is an illustrative circuit diagram for illustrating a unit pixel of an image sensor according to some example embodiments.

[0038] Reference Figure 2 , an image sensor according to some example embodiments includes a plurality of unit pixels PX.

[0039] A plurality of unit pixels PX may be arranged two-dimensionally (eg, in a matrix form). Each unit pixel PX may include a photoelectric conversion element PD, a transfer transistor TX, a floating diffusion region FD, a reset transistor RX, a drive transistor DX, and a selection transistor SX.

[0040] The photoelectric conversion element PD may generate a charge proportional to the amount of light incident from the outside. The photoelectric conversion element PD may be coupled to a transfer transistor TX that transfers the generated and accumulated charge to the floating diffusion region FD. The floating diffusion region FD is a region that converts the charge into a voltage. Since the floating diffusion region FD has a parasitic capacitance, the charge may be stored therein in an accumulated manner.

[0041] One end of the transfer transistor TX may be connected to the photoelectric conversion element PD, and the other end of the transfer transistor TX may be connected to the floating diffusion region FD. The transfer transistor TX may be implemented as a transistor that operates based on a predetermined (or alternative, desired, or selected) bias voltage (e.g., a transfer signal TG). In other words, the transfer transistor TX may transfer the charge generated from the photoelectric conversion element PD to the floating diffusion region FD based on the transfer signal TG.

[0042] The drive transistor DX may be implemented as a source follower buffer amplifier. The drive transistor DX may amplify a change in the potential of the floating diffusion region FD that has received the charge from the photoelectric conversion element PD and output the amplified change to the output line V OUT When the drive transistor DX is turned on, a predetermined (or alternative, desired or selected) potential (eg, power supply voltage V DD ) can be transferred to the drain region of the selection transistor SX.

[0043] The selection transistor SX may select a unit pixel PX to be read on a row basis. The selection transistor SX may be implemented as a transistor that operates based on a predetermined (or alternative, desired, or selected) bias (eg, a row selection signal SG) applied from a selection line.

[0044] The reset transistor RX may periodically reset the floating diffusion region FD. The reset transistor RX may be implemented as a transistor that operates based on a predetermined (or alternative, desired, or selected) bias voltage (e.g., a reset signal RG) applied from a reset line. When the reset transistor RX is turned on based on the reset signal RG, a predetermined (or alternative, desired, or selected) potential (e.g., a power supply V DD ) may be transmitted to the floating diffusion area FD so that the floating diffusion area FD may be reset.

[0045] Figure 3 is a layout diagram for illustrating an image sensor according to some example embodiments. Figure 4 It is along Figure 3 Schematic cross-sectional view taken along line AA in FIG. Figure 5 It is along Figure 3Schematic cross-sectional view taken along line BB in FIG. Figure 6 It is along Figure 3 Schematic cross-sectional view taken along line CC in FIG. Figure 7 It is used to show Figures 3 to 6 A cross-sectional diagram of the effect of an image sensor.

[0046] Reference Figures 3 to 7 According to some example embodiments, the image sensor includes a first substrate 100, a photoelectric conversion region 101, an element isolation film 110, a first circuit element CC, a first isolation pattern 120 (also referred to as a first isolation trench 120), a second isolation pattern 130 (also referred to as a second isolation trench 130), a first wiring structure 140, a surface insulating film 150, a grid pattern 160, a first protective film 166, color filters 180a to 180d, and a microlens 190.

[0047] The first substrate 100 may be a semiconductor substrate. For example, the first substrate 100 may be made of bulk silicon or SOI (silicon on insulator). The first substrate 100 may be a silicon substrate, or may include materials other than silicon, such as silicon germanium, indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first substrate 100 may have a base substrate and an epitaxial layer formed on the base substrate.

[0048] The first substrate 100 may include a first surface 100a and a second surface 100b opposite to each other. In some example embodiments as described later, the first surface 100a may also be referred to as a front surface of the first substrate 100, and the second surface 100b may also be referred to as a rear surface or back surface of the first substrate 100. In some example embodiments, the second surface 100b of the first substrate 100 may be a light receiving surface on which light is incident. That is, the image sensor according to some example embodiments may be a backside illumination (BSI) image sensor.

[0049] In some example embodiments, the first substrate 100 may contain impurities of the first conductivity type. In some example embodiments as described later, some example embodiments in which the first conductivity type is a p-type are described. However, this is only an example, and the inventive concept is not limited thereto, for example, the first conductivity type may be an n-type.

[0050] In some example embodiments, the thickness TH of the first substrate 100 may be in a range of about or exactly 2 μm to about or exactly 10 μm. In this regard, the thickness TH of the first substrate 100 refers to a thickness in a third direction Z intersecting the first surface 100a and / or the second surface 100b. In some example embodiments, the thickness TH of the first substrate 100 may be in a range of about or exactly 2 μm to about or exactly 5 μm.

[0051] A plurality of pixel groups may be formed in the first substrate 100. The plurality of pixel groups may be two-dimensionally arranged (eg, in a matrix form) on a plane including the first direction X and the second direction Y (or on a plane intersecting the third direction Z).

[0052] For example, the plurality of pixel groups may include first pixel groups G1 to G4, second pixel groups R1 to R4, third pixel groups B1 to B4, and fourth pixel groups G11 to G14 that are adjacent to each other. The second pixel groups R1 to R4 may be adjacent to the first pixel groups G1 to G4 in the first direction X. The third pixel groups B1 to B4 may be adjacent to the first pixel groups G1 to G4 in the second direction Y. The fourth pixel groups G11 to G14 may be adjacent to the second pixel groups R1 to R4 in the second direction Y, and may be adjacent to the third pixel groups B1 to B4 in the first direction X. That is, the fourth pixel groups G11 to G14 may be adjacent to the first pixel groups G1 to G4 in the diagonal direction between the first direction X and the second direction Y.

[0053] Each pixel group may include a plurality of unit pixels. For example, the first pixel groups G1 to G4 may include the first unit pixel G1 to the fourth unit pixel G4, the second pixel groups R1 to R4 may include the fifth unit pixel R1 to the eighth unit pixel R4, the third pixel groups B1 to B4 may include the ninth unit pixel B1 to the twelfth unit pixel B4, and the fourth pixel groups G11 to G14 may include the thirteenth unit pixel G11 to the sixteenth unit pixel G14.

[0054] A plurality of unit pixels G1 to G4, R1 to R4, B1 to B4, or G11 to G14 may be two-dimensionally arranged (eg, in a matrix form) in a plane including the first direction X and the second direction Y (or a plane intersecting the third direction Z).

[0055] In some example embodiments, the second unit pixel G2 may be adjacent to the first unit pixel G1 in the first direction X. The third unit pixel G3 may be adjacent to the first unit pixel G1 in the second direction Y. The fourth unit pixel G4 may be adjacent to the second unit pixel G2 in the second direction Y, and may be adjacent to the third unit pixel G3 in the first direction X. That is, the fourth unit pixel G4 may be adjacent to the first unit pixel G1 in a diagonal direction between the first direction X and the second direction Y.

[0056] The photoelectric conversion region 101 may be formed in the first substrate 100. The photoelectric conversion region 101 may be formed in each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14 arranged in the first substrate 100. For example, a plurality of photoelectric conversion regions 101 corresponding to the plurality of unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14 may be arranged two-dimensionally (e.g., in a matrix form) within the first substrate 100.

[0057] The photoelectric conversion region 101 can be connected to Figure 2 In other words, the photoelectric conversion region 101 can generate a charge proportional to the amount of light incident from the outside. For example, the photoelectric conversion region 101 may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof. However, the present disclosure is not limited thereto.

[0058] The photoelectric conversion region 101 may be of a second conductivity type different from the first conductivity type. For example, the photoelectric conversion region 101 may be formed by implanting n-type impurity ions into the p-type first substrate 100 .

[0059] The element isolation film 110 may be formed in the first substrate 100. The element isolation film 110 may define an active region 102 in each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14. The element isolation film 110 may extend along and on the first surface 100a of the first substrate 100, and may define the active region 102 extending on and along the first surface 100a in the first substrate 100. The element isolation film 110 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof. However, the present disclosure is not limited thereto.

[0060] The active region 102 may include a floating diffusion region FD. The floating diffusion region FD may have a second conductivity type different from the first conductivity type. For example, the floating diffusion region FD may be formed by implanting n-type impurity ions into the p-type first substrate 100 .

[0061] In some example embodiments, adjacent unit pixels of each pixel group may share a floating diffusion region FD. For example, the floating diffusion region FD may be interposed between unit pixels adjacent to each other in a diagonal direction. In some example embodiments, the floating diffusion region FD of the first pixel groups G1 to G4 may be interposed between the first unit pixel G1 and the fourth unit pixel G4 and / or between the second unit pixel G2 and the third unit pixel G3. That is, the floating diffusion region FD of the first pixel groups G1 to G4 may be located at the center of the first unit pixel G1 to the fourth unit pixel G4. The first unit pixel G1 to the fourth unit pixel G4 may share the floating diffusion region FD located at the center thereof.

[0062] The first circuit element CC may be formed on the first surface 100a of the first substrate 100. The first circuit element CC may include various transistors for processing electrical signals generated from each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14 within the first substrate 100. For example, the first circuit element CC may include the transistors described above. Figure 2 The transfer transistor TX, reset transistor RX, drive transistor DX and / or, selection transistor SX, etc. described in the description.

[0063] In some example embodiments, the first circuit element CC may include a vertical transfer transistor. Figure 4 and Figure 5 As shown in FIG. 1 , a portion of the transfer transistor TX of the first circuit element CC may extend into the first substrate 100 and toward the photoelectric conversion region 101. The transfer transistor TX may reduce the area size of a unit pixel, thereby contributing to high integration of the image sensor.

[0064] The first isolation pattern 120 may be formed in the first substrate 100. The first isolation pattern 120 may define a plurality of pixel groups within the first substrate 100. For example, the first isolation pattern 120 may surround each of the first pixel groups G1 to G4, the second pixel groups R1 to R4, the third pixel groups B1 to B4, and the fourth pixel groups G11 to G14 in a plan view.

[0065] The first isolation pattern 120 can prevent or reduce the photocharge generated from a specific pixel group (such as the first pixel groups G1 to G4) from migrating to another pixel group adjacent thereto (such as the second pixel groups R1 to R4) in a random drift manner. The first isolation pattern 120 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. However, the present disclosure is not limited thereto.

[0066] In some example embodiments, the first isolation pattern 120 may include a low refractive index material having a refractive index lower than that of silicon (Si), for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. The first isolation pattern 120 may refract or reflect light incident at a certain angle on the second surface 100b as a light receiving surface to improve light collection efficiency.

[0067] In some example embodiments, the first isolation pattern 120 may be formed not to exist in the center of adjacent unit pixels in each pixel group. For example, the first isolation pattern 120 may include first to fourth pixel isolation portions 120a to 120d (also referred to as first to fourth pixel isolation trenches 120a to 120d) and a group isolation portion 120e (also referred to as a group isolation trench 120e).

[0068] The group isolation portion 120e may surround the pixel group in a plan view. In some example embodiments, the group isolation portion 120e may surround the first pixel group G1 to G4. Each of the first to fourth pixel isolation portions 120a to 120d may protrude from the group isolation portion 120e to be interposed between adjacent unit pixels. In some example embodiments, the first pixel isolation portion 120a may extend from the group isolation portion 120e in the second direction Y to be interposed between the first unit pixel G1 and the second unit pixel G2. In some example embodiments, the second pixel isolation portion 120b may extend from the group isolation portion 120e in the first direction X to be interposed between the first unit pixel G1 and the third unit pixel G3. In some example embodiments, the third pixel isolation portion 120c may extend from the group isolation portion 120e in the first direction X to be interposed between the second unit pixel G2 and the fourth unit pixel G4. In some example embodiments, the fourth pixel isolation portion 120 d may extend from the group isolation portion 120 e in the second direction Y to be interposed between the third unit pixel G3 and the fourth unit pixel G4 .

[0069] In some example embodiments, the floating diffusion region FD may be interposed between the first pixel isolation portion 120 a and the fourth pixel isolation portion 120 d and between the second pixel isolation portion 120 b and the third pixel isolation portion 120 c .

[0070] In some example embodiments, the first isolation pattern 120 may extend from the first surface 100a of the first substrate 100. In some example embodiments, the width of the first isolation pattern 120 may decrease as the first isolation pattern 120 extends from the first surface 100a toward the second surface 100b. For example, the first isolation pattern 120 may be formed by burying an insulating material in a deep trench formed by patterning a portion of the first substrate 100 including the first surface 100a.

[0071] In some example embodiments, the first isolation pattern 120 may extend through the entire first substrate 100 in the third direction Z. For example, the first isolation pattern 120 may not be covered by the second surface 100 b of the first substrate 100 to be exposed.

[0072] In some example embodiments, the first isolation pattern 120 may include a filling pattern 122 and a spacer film 124 .

[0073] The filling pattern 122 may extend from the first surface 100a of the first substrate 100 toward the second surface 100b of the first substrate 100. The filling pattern 122 may include a conductive material, for example, polycrystalline silicon (poly-Si). However, the present disclosure is not limited thereto. In some example embodiments, a ground voltage or a negative voltage may be applied to the filling pattern 122. The filling pattern 122 may prevent or reduce the accumulation of charges generated under ESD (electrostatic discharge) on the surface (e.g., the second surface 100b) of the first substrate 100, so as to effectively prevent or reduce ESD bruise defects.

[0074] The spacer film 124 may extend along the side surface of the filling pattern 122. The spacer film 124 may include an insulating material such as at least one of silicon oxide, aluminum oxide, tantalum oxide, and a combination thereof. However, the present disclosure is not limited thereto. The spacer film 124 may be interposed between the filling pattern 122 and the first substrate 100 to electrically insulate the filling pattern 122 and the first substrate 100 from each other.

[0075] In some example embodiments, the spacer film 124 may be formed as a multi-layer. In some example embodiments, the multi-layer of the spacer film 124 may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and a combination thereof.

[0076] The second isolation pattern 130 may be formed in the first substrate 100. The second isolation pattern 130 may be located in each pixel group. The second isolation pattern 130 may be interposed between unit pixels adjacent to each other in a diagonal direction. In some example embodiments, the second isolation pattern 130 of the first pixel groups G1 to G4 may be interposed between the first unit pixel G1 and the fourth unit pixel G4 and / or between the second unit pixel G2 and the third unit pixel G3. That is, the second isolation pattern 130 of the first pixel groups G1 to G4 may be located in the center of the first unit pixel G1 to the fourth unit pixel G4.

[0077] The second isolation pattern 130 can prevent or reduce the photocharge generated from a specific unit pixel (such as the first unit pixel G1) from moving to another unit pixel (such as the fourth unit pixel G4) adjacent thereto in a diagonal direction in a random drift manner. The second isolation pattern 130 may include an insulating material such as at least one of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof. However, the present disclosure is not limited thereto.

[0078] In some example embodiments, the second isolation pattern 130 may include a low refractive index material having a refractive index lower than that of silicon (Si), for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. The second isolation pattern 130 may refract or reflect light incident at a certain angle to the second surface 100b as a light receiving surface to improve light collection efficiency.

[0079] In some example embodiments, the second isolation pattern 130 may be interposed between the first pixel isolation portion 120 a and the fourth pixel isolation portion 120 d and between the second pixel isolation portion 120 b and the third pixel isolation portion 120 c .

[0080] It is shown that the width of the second isolation pattern 130 in the first direction X is equal to the width of the first pixel isolation portion 120a in the first direction X (or the width of the fourth pixel isolation portion 120d in the first direction X), and the width of the second isolation pattern 130 in the second direction Y is equal to the width of the second pixel isolation portion 120b in the second direction Y (or the width of the third pixel isolation portion 120c in the second direction Y). However, this is only an example, and the inventive concept is not limited thereto. In another example, the width of the second isolation pattern 130 may be different from the width of each of the first pixel isolation portion 120a to the fourth pixel isolation portion 120d.

[0081] In addition, the second isolation pattern 130 is shown to be spaced apart from the first isolation pattern 120 in a plan view. However, this is merely an example, and the inventive concept is not limited thereto. In another example, a portion of the second isolation pattern 130 may overlap a portion of the first isolation pattern 120 in the third direction Z.

[0082] In some example embodiments, the second isolation pattern 130 may extend from the second surface 100b of the first substrate 100. The width of the second isolation pattern 130 may decrease as the second isolation pattern 130 extends from the second surface 100b to the first surface 100a. For example, the second isolation pattern 130 may be formed by burying an insulating material in a deep trench formed by patterning a portion of the first substrate 100 including the second surface 100b. For example, the depth D2 of the second isolation pattern 130 from the second surface 100b of the first substrate 100 may be about or exactly 0.5 μm or more (such as up to about or exactly 10 μm).

[0083] In some example embodiments, the second isolation pattern 130 may not extend through the entire first substrate 100. For example, the second isolation pattern 130 may be spaced apart from the first surface 100a of the first substrate 100. For example, the distance D1 by which the second isolation pattern 130 is spaced apart from the first surface 100a of the first substrate 100 may be approximately or exactly 1 μm or more (or such as up to approximately or exactly 10 μm).

[0084] In some example embodiments, at least a portion of the floating diffusion region FD may overlap the second isolation pattern 130 in the third direction Z. In some example embodiments, as described above, both the second isolation pattern 130 and the floating diffusion region FD of the first pixel groups G1 to G4 may be located in the center of the first to fourth unit pixels G1 to G4 in a plan view. In some example embodiments, the second isolation pattern 130 may be spaced apart from the active region 102 (e.g., the floating diffusion region FD) in the third direction Z.

[0085] In some example embodiments, the depth D2 of the second isolation pattern 130 may be in a range of about or exactly 50% to about or exactly 80% of the thickness TH of the first substrate 100. When the depth D2 of the second isolation pattern 130 is equal to or greater than about or exactly 50% (e.g., up to about or exactly 80%) of the thickness TH of the first substrate 100, the second isolation pattern 130 may effectively prevent or reduce optical crosstalk between unit pixels adjacent to each other in a diagonal direction. In addition, when the depth D2 of the second isolation pattern 130 is less than or equal to about or exactly 80% of the thickness TH of the first substrate 100, damage to an element (such as damage to the floating diffusion region FD) due to the formation of the second isolation pattern 130 may be effectively prevented or reduced. For example, when the thickness TH of the first substrate 100 is in a range of about or exactly 2 μm to about or exactly 5 μm, the depth D2 of the second isolation pattern 130 may be in a range of about or exactly 1 μm to about or exactly 4 μm.

[0086] The first wiring structure 140 may be formed on the first surface 100a of the first substrate 100. The first wiring structure 140 may include a plurality of wiring patterns. For example, the first wiring structure 140 may include a first inter-wiring insulating film 142 on the first surface 100a, and a first wiring pattern 144 within the first inter-wiring insulating film 142. Figures 4 to 6 In the embodiment, the number of layers and arrangement of the first wiring pattern 144 are merely illustrative and are not limited to Figures 4 to 6 The first wiring structure 140 may be electrically connected to the first circuit element CC, and may transmit and transfer an electrical signal with each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14 via the first circuit element CC.

[0087] The surface insulating film 150 may be formed on the second surface 100b of the first substrate 100. The surface insulating film 150 may conformally extend along the second surface 100b of the first substrate 100. The surface insulating film 150 may include an insulating material such as at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof. However, the present disclosure is not limited thereto.

[0088] The surface insulating film 150 can be used as an anti-reflection film, and can prevent or reduce the reflection of light incident on the second surface 100b as a light receiving surface. Therefore, the light receiving percentage of the photoelectric conversion region 101 can be improved. Alternatively, the surface insulating film 150 can be used as a planarization film to allow the color filters 180a to 180d and the microlens 190 to be described later to have a uniform height.

[0089] In some example embodiments, the surface insulating film 150 may be formed as a multilayer. In some example embodiments, unlike what is shown, the surface insulating film 150 may include an aluminum oxide film, a hafnium oxide film, a silicon oxide film, a silicon nitride film, and a hafnium oxide film sequentially stacked on the second surface 100b of the first substrate 100.

[0090] The grid pattern 160 may be formed on the surface insulating film 150. The grid pattern 160 may surround each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14 while being disposed on the first substrate 100. For example, the grid pattern 160 may be formed on the surface insulating film 150 in a grid manner and may surround each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14 arranged in a matrix form. In some example embodiments, the grid pattern 160 may be positioned to overlap the first isolation pattern 120 and the second isolation pattern 130 in the third direction Z.

[0091] In some example embodiments, the grid pattern 160 may include a metal pattern 162 and a low-refractive-index pattern 164. The metal pattern 162 and the low-refractive-index pattern 164 may be sequentially stacked on the surface insulating film 150.

[0092] The metal pattern 162 may include, but is not limited to, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof. The metal pattern 162 may prevent or reduce the accumulation of charges generated under ESD (electrostatic discharge) on a surface of the first substrate 100 (such as the second surface 100b), thereby effectively preventing or reducing ESD scratch defects.

[0093] The low refractive index pattern 164 may include a low refractive index material having a refractive index lower than that of silicon (Si). For example, the low refractive index pattern 164 may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and a combination thereof. However, the present disclosure is not limited thereto. The low refractive index pattern 164 may refract or reflect light incident at a certain angle to the second surface 100b as a light receiving surface to improve light collection efficiency.

[0094] The first protective film 166 may be formed on the surface insulating film 150 and the grid pattern 160. The first protective film 166 may conformally extend along the contour of each of the surface insulating film 150 and the grid pattern 160. The first protective film 166 may prevent or reduce damage to the surface insulating film 150 and the grid pattern 160. The first protective film 166 may include, for example, aluminum oxide (AlO). However, the present disclosure is not limited thereto.

[0095] Color filters 180a to 180d may be formed on the first protective film 166. The color filters 180a to 180d may have various colors according to the unit pixel. For example, the color filters 180a to 180d may include red filters, green filters, blue filters, yellow filters, magenta filters, and cyan filters, and may also include white filters.

[0096] In some example embodiments, the unit pixels of each pixel group may share a color filter of the same color. In addition, the color filter of one pixel group may have a color different from the color of the color filter of another pixel group adjacent thereto. For example, the color filters 180a to 180d may include a first color filter 180a, a second color filter 180b, a third color filter 180c, and a fourth color filter 180d adjacent to each other. The first color filter 180a may have a first color and cover the first unit pixel G1 to the fourth unit pixel G4. The second color filter 180b may cover the fifth unit pixel R1 to the eighth unit pixel R4 and have a second color different from the first color. The third color filter 180c may cover the 9th unit pixel B1 to the 12th unit pixel B4 and have a third color different from the first color. The fourth color filter 180d may cover the 13th unit pixel G11 to the 16th unit pixel G14 and have a fourth color different from the second color and the third color.

[0097] In some example embodiments, the color filters 180a to 180d may be arranged in a Bayer pattern. In some example embodiments, each of the first color filter 180a and the fourth color filter 180d may be a green color filter, the second color filter 180b may be a red color filter, and the third color filter 180c may be a blue color filter.

[0098] The microlens 190 may be formed on the color filters 180a to 180d. The microlens 190 has a convex shape and may have a predetermined (or replaceable, desired or selected) radius of curvature. Therefore, the microlens 190 may converge light to be incident on the photoelectric conversion region 101. The microlens 190 may include, for example, a light-transmitting resin. However, the present disclosure is not limited thereto.

[0099] In some example embodiments, the unit pixels of each pixel group may share one microlens 190. For example, the microlens 190 may be positioned to overlap each pixel group. Thus, each pixel group may provide an auto focus (AF) function. In some example embodiments, the first pixel groups G1 to G4 may provide a phase detection AF (PDAF) function using the divided photoelectric conversion regions 101 of the first unit pixel G1 to the fourth unit pixel G4.

[0100] The second protective film 195 may be formed on the microlens 190. The second protective film 195 may extend along the top surface of the microlens 190. The second protective film 195 may include an inorganic oxide film such as a silicon oxide film, a titanium oxide film, a zirconium oxide film, or a hafnium oxide film. However, the present disclosure is not limited thereto. In some example embodiments, the second protective film 195 may include a low temperature oxide (LTO).

[0101] The second protective film 195 may protect the microlens 190 from external influences. For example, the second protective film 195 may include an inorganic oxide film to protect the microlens 190 including an organic material. In addition, the second protective film 195 may improve the quality of the image sensor by improving the light converging efficiency of the microlens 190. For example, the second protective film 195 may fill the space between the microlenses 190 to reduce reflection, refraction, scattering, etc. of incident light reaching the space between the microlenses 190.

[0102] In order to improve the performance of the image sensor, a structure in which color filters of the same color are placed on a plurality of unit pixels adjacent to each other (e.g., a so-called Qcell (quad-cell) structure in which color filters of the same color are placed on four adjacent unit pixels) has been proposed. In this structure, the first isolation pattern 120 that does not exist in the center of the adjacent unit pixels can improve the area size of the light receiving surface on which light is incident, thereby further improving the sensitivity of the image sensor. However, the central area in which the first isolation pattern 120 of the adjacent unit pixels does not exist may cause optical crosstalk between the unit pixels adjacent to each other in the diagonal direction.

[0103] Therefore, in the image sensor according to some example embodiments, the second isolation pattern 130 may be disposed in a central region where the first isolation pattern 120 of an adjacent unit pixel does not exist, thereby effectively preventing or reducing optical crosstalk between unit pixels adjacent to each other in a diagonal direction. Figure 7 As shown in the first optical path LP1 in FIG. 1 , the first isolation pattern 120 may cause total reflection of light obliquely incident on the second surface 100b of the first unit pixel G1. Therefore, the second isolation pattern 130 can not only prevent or reduce the optical crosstalk between the first unit pixel G1 and the fourth unit pixel G4, but also improve the light converging efficiency of the first unit pixel G1. When the second isolation pattern 130 does not exist, as shown by Figure 7 As shown in the second optical path LP2 in FIG. 1 , light obliquely incident on the second surface 100 b of the first unit pixel G1 may pass through the first unit pixel G1 to the fourth unit pixel G4 . This may cause optical crosstalk between the first unit pixel G1 and the fourth unit pixel G4 .

[0104] In addition, the second isolation pattern 130 may extend from the second surface 100b and may be spaced apart from the first surface 100a. Therefore, even if the second isolation pattern 130 is located in the central area of ​​the adjacent unit pixel where the first isolation pattern 120 does not exist, the second isolation pattern 130 may provide an effective space in the central area of ​​the adjacent unit pixel. For example, as described above, at least a portion of the floating diffusion region FD may be located at the center of the first unit pixel G1 to the fourth unit pixel G4 to overlap with the second isolation pattern 130 in the third direction Z. The floating diffusion region FD may be shared by adjacent unit pixels, thereby reducing the area size of each of the unit pixels, and thereby contributing to the high integration of the image sensor. Therefore, an image sensor with improved performance and integration may be provided.

[0105] Figures 8 to 10 is a cross-sectional view for illustrating an image sensor according to some example embodiments. For ease of description, the above reference is briefly described or omitted. Figures 1 to 7 Describes the content of the duplicate content.

[0106] Reference Figures 8 to 10 , in the image sensor according to some example embodiments, the first isolation pattern 120 may extend from the second surface 100 b of the first substrate 100 .

[0107] The width of the first isolation pattern 120 may decrease as the first isolation pattern 120 extends from the second surface 100b to the first surface 100a. For example, the first isolation pattern 120 may be formed by filling an insulating material in a deep trench formed by patterning a portion of the first substrate 100 including the second surface 100b. For example, a depth D3 of the first isolation pattern 120 from the second surface 100b of the first substrate 100 may be about or exactly 2 μm or more (such as up to about or exactly 10 μm).

[0108] The first isolation pattern 120 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. However, the present disclosure is not limited thereto. The first isolation pattern 120 may include the same insulating material as the insulating material of the second isolation pattern 130, or may include an insulating material different from the insulating material of the second isolation pattern 130.

[0109] In some example embodiments, the first isolation pattern 120 may include a low refractive index material having a refractive index lower than that of silicon (Si), for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. The first isolation pattern 120 may refract or reflect light incident at a certain angle to the second surface 100b as a light receiving surface, thereby improving light converging efficiency.

[0110] In some example embodiments, the first isolation pattern 120 may not extend through the entire first substrate 100. For example, the first isolation pattern 120 may be spaced apart from the first surface 100a of the first substrate 100. In some example embodiments, the first isolation pattern 120 may be spaced apart from the element isolation film 110 in the third direction Z.

[0111] In some example embodiments, the second isolation pattern 130 may be formed to a depth D2 less than the first isolation pattern 120 is formed to a depth D3.

[0112] Fig.11 is a cross-sectional view for illustrating an image sensor according to some example embodiments. For ease of description, the above reference is briefly described or omitted. Figures 1 to 10 Describes the content of the duplicate content.

[0113] Reference Fig.11 In an image sensor according to some example embodiments, the depth D2 formed by the second isolation pattern 130 may be the same as the depth D3 formed by the first isolation pattern 120. As used herein, the term “same” not only means “exactly equal to” but also means including slight differences that may occur due to a process margin or the like.

[0114] In some example embodiments, the first isolation pattern 120 may include an insulating material different from that of the second isolation pattern 130. For example, the first isolation pattern 120 and the second isolation pattern 130 may be formed in different manufacturing processes.

[0115] Figure 12 to Figure 14 1 is a diagram for illustrating various layouts of image sensors according to some example embodiments. Figures 1 to 11 Describes the content of the duplicate content.

[0116] Reference Fig.12 and Fig.13 , in an image sensor according to some example embodiments, the second isolation pattern 130 may include a first extension portion 130y and a second extension portion 130x intersecting each other.

[0117] For example, the first extension portion 130y may extend in the second direction Y, and the second extension portion 130x may extend in the first direction X. Each of the first extension portion 130y and the second extension portion 130x may be interposed between adjacent unit pixels. In some example embodiments, the first extension portion 130y may be interposed between the first unit pixel G1 and the second unit pixel G2 and between the third unit pixel G3 and the fourth unit pixel G4. In some example embodiments, the second extension portion 130x may be interposed between the first unit pixel G1 and the third unit pixel G3 and between the second unit pixel G2 and the fourth unit pixel G4. The second isolation pattern 130 together with the first isolation pattern 120 may surround each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14.

[0118] In some example embodiments, Fig.12 As shown in , the first extension portion 130y and the second extension portion 130x may be interposed between the first pixel isolation portion 120a to the fourth pixel isolation portion 120d. For example, the first extension portion 130y may be interposed between the first pixel isolation portion 120a and the fourth pixel isolation portion 120d. The first pixel isolation portion 120a, the first extension portion 130y and the fourth pixel isolation portion 120d may be arranged in a line in the second direction Y. The second extension portion 130x may be interposed between the second pixel isolation portion 120b and the third pixel isolation portion 120c. The second pixel isolation portion 120b, the second extension portion 130x and the third pixel isolation portion 120c may be arranged in a line in the first direction X.

[0119] In some example embodiments, Fig.13 As shown in , the second isolation pattern 130 may isolate adjacent unit pixels from each other among the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14 while being disposed inside the first isolation pattern 120. For example, the first isolation pattern 120 may not include the first to fourth pixel isolation portions 120a to 120d as described above.

[0120] In some example embodiments, the second extension portion 130 x and the first extension portion 130 y may cross each other and overlap the floating diffusion region FD.

[0121] Reference Fig.14 , in an image sensor according to some example embodiments, each pixel group may include 9 unit pixels.

[0122] For example, each of the first pixel groups G1 to G9 , the second pixel groups R1 to R9 , the third pixel groups B1 to B9 , and the fourth pixel groups G11 to G19 may include 9 unit pixels arranged in a 3×3 matrix.

[0123] The second isolation pattern 130 may be located in each pixel group. In some example embodiments, the second isolation pattern 130 may be interposed between unit pixels adjacent to each other in a diagonal direction. In some example embodiments, the second isolation pattern 130 disposed in the first pixel groups G1 to G9 may include a second isolation pattern 130 disposed between the first unit pixel G1 and the 13th unit pixel G5, a second isolation pattern 130 disposed between the second unit pixel G2 and the 14th unit pixel G6, a second isolation pattern 130 disposed between the fourth unit pixel G4 and the 15th unit pixel G8, and a second isolation pattern 130 disposed between the 13th unit pixel G5 and the 16th unit pixel G9.

[0124] Although the description has been mainly based on some example embodiments in which the unit pixels are arranged in a 3×3 matrix form, this is only an example and the inventive concept is not limited thereto. Those skilled in the art of the present disclosure will understand that the second isolation pattern 130 can be applied to a 2×3 matrix form, a 3×4 matrix form and / or a 4×4 matrix with the same principle.

[0125] Fig.15 is a schematic layout diagram for illustrating an image sensor according to some example embodiments. Fig.16 It is used to show Fig.15 For ease of description, the above reference is briefly described or omitted. Figures 1 to 14 Describes the content of the duplicate content.

[0126] Reference Fig.15 and Fig.16 , an image sensor according to some example embodiments includes a sensor array region SAR, a connection region CR, and a pad region PR.

[0127] The sensor array area SAR may include Figure 1 The area corresponding to the active pixel sensor array 1 in the sensor array region SAR. For example, in the sensor array region SAR, a plurality of unit pixels arranged two-dimensionally (eg, in a matrix form) may be formed.

[0128] The sensor array area SAR may include a light receiving area APS and a light blocking area OB. Active pixels that receive light and generate active signals based on the received light may be arranged in the light receiving area APS. In the light blocking area OB, optical black pixels that block light to generate optical black signals may be arranged. For example, the light blocking area OB may be formed around the light receiving area APS. However, this is only an example, and the inventive concept is not limited thereto.

[0129] In some example embodiments, the photoelectric conversion region 101 may be formed in a portion of the light blocking region OB, and may not be formed in another portion of the light blocking region OB. For example, the photoelectric conversion region 101 may be formed in a portion of the light blocking region OB adjacent to the light receiving region APS, but may not be formed in another portion of the light blocking region OB spaced apart from the light receiving region APS.

[0130] In some example embodiments, a dummy pixel (not shown) may be formed in a portion of the light receiving region APS adjacent to the light blocking region OB.

[0131] The connection region CR may be formed around the sensor array region SAR. The connection region CR may be formed on one side of the sensor array region SAR. However, this is only an example, and the inventive concept is not limited thereto. Wiring may be formed in the connection region CR, and may transmit and receive electrical signals of the sensor array region SAR.

[0132] The pad region PR may be formed around the sensor array region SAR. The pad region PR may be formed adjacent to the edge of the image sensor according to some example embodiments. However, this is merely an example, and the inventive concept is not limited thereto. The pad region PR may be connected to an external device, etc., and may be configured to transmit electrical signals between the image sensor according to some example embodiments and the external device.

[0133] The connection region CR is shown to be interposed between the sensor array region SAR and the pad region PR. However, this is merely illustrative. The arrangement of the sensor array region SAR, the connection region CR, and the pad region PR may be changed as needed.

[0134] The first wiring structure 140 may include a first wiring pattern 144 in the sensor array region SAR and a second wiring pattern 145 in the connection region CR. The first wiring pattern 144 may be electrically connected to the unit pixel of the sensor array region SAR. At least a portion of the second wiring pattern 145 may be electrically connected to at least a portion of the first wiring pattern 144. Therefore, the second wiring pattern 145 may be electrically connected to the unit pixel of the sensor array region SAR.

[0135] An image sensor according to some example embodiments may include a second substrate 200 and a second wiring structure 240 .

[0136] The second substrate 200 may be made of bulk silicon or silicon on insulator (SOI). The second substrate 200 may be a silicon substrate, or may include materials other than silicon, such as silicon germanium, indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the second substrate 200 may have a base substrate and an epitaxial layer formed on the base substrate.

[0137] The second substrate 200 may include a third surface 200a and a fourth surface 200b opposite to each other. In some example embodiments as described later, the third surface 200a may also be referred to as a front surface of the second substrate 200, and the fourth surface 200b may also be referred to as a rear surface or back surface of the second substrate 200. In some example embodiments, the third surface 200a of the second substrate 200 may face the first surface 100a of the first substrate 100.

[0138] The second circuit element PC may be formed on the third surface 200a of the second substrate 200. The second circuit element PC may be electrically connected to the sensor array region SAR, and may transmit and receive electrical signals to and from each unit pixel of the sensor array region SAR. For example, the second circuit element PC may include a Figure 1 The electronic components include a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler 6, an analog-to-digital converter 7 or an input / output buffer 8.

[0139] The second wiring structure 240 may be formed on the third surface 200a of the second substrate 200. For example, the second wiring structure 240 may include a second inter-wiring insulating film 242, and various wiring patterns 244, 245, and 246 disposed in the second inter-wiring insulating film 242.

[0140] exist Fig.16 , the number of layers and arrangement of the wiring patterns 244, 245, and 246 are merely illustrative and are not limited thereto.

[0141] At least some of the wiring patterns 244, 245, and 246 of the second wiring structure 240 may be connected to the second circuit element PC. In some example embodiments, the second wiring structure 240 may include a third wiring pattern 244 in the sensor array region SAR, a fourth wiring pattern 245 in the connection region CR, and a fifth wiring pattern 246 in the pad region PR. In some example embodiments, the fourth wiring pattern 245 may be a top wiring among the plurality of wirings in the connection region CR, and the fifth wiring pattern 246 may be a top wiring among the plurality of wirings in the pad region PR.

[0142] The first wiring structure 140 and the second wiring structure 240 may be bonded to each other. Fig.16 As shown in FIG. 1 , the upper surface of the second wiring structure 240 may be attached to the lower surface of the first wiring structure 140. The first wiring structure 140 and the second wiring structure 240 may be bonded to each other via, for example, a wafer bonding process. However, the present disclosure is not limited thereto.

[0143] An image sensor according to some example embodiments may include a first connection structure 362 , a second connection structure 462 , and a third connection structure 562 .

[0144] The first connection structure 362 may be formed in the light blocking region OB. The first connection structure 362 may be formed on the surface insulating film 150 and in the light blocking region OB. The first connection structure 362 may contact a portion of the first isolation pattern 120. For example, a first trench T1 exposing the first isolation pattern 120 may be formed in the first substrate 100 and the surface insulating film 150 and in the light blocking region OB. The first connection structure 362 may be formed in the first trench T1 to contact the first isolation pattern 120 in the light blocking region OB. In some example embodiments, the first connection structure 362 may conformally extend along the contour of each of the side surface and the lower surface of the first trench T1.

[0145] The first connection structure 362 may include, for example, but is not limited to, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof.

[0146] In some example embodiments, the first connection structure 362 may be electrically connected to the filling pattern 122 of the first isolation pattern 120, and a ground voltage or a negative voltage may be applied to the filling pattern 122. Therefore, charges generated under ESD or the like may be discharged to the first connection structure 362 through the filling pattern 122. Therefore, ESD scratch defects may be effectively prevented or reduced.

[0147] In some example embodiments, a first pad 375 filling the first trench T1 may be formed on the first connection structure 362. The first pad 375 may include, for example, but is not limited to, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

[0148] In some example embodiments, the first protection film 166 may cover the first connection structure 362 and the first pad 375. For example, the first protection film 166 may conformally extend along the outline of each of the first connection structure 362 and the first pad 375.

[0149] The second connection structure 462 may be formed in the connection region CR. The second connection structure 462 may be formed on the surface insulating film 150 and in the connection region CR. The second connection structure 462 may electrically connect the first wiring structure 140 and the second wiring structure 240 to each other. For example, in the connection region CR, the second trench T2 may be formed to expose the second wiring pattern 145 and the fourth wiring pattern 245. The second connection structure 462 may be formed in the second trench T2 to connect the second wiring pattern 145 and the fourth wiring pattern 245 to each other. In some example embodiments, the second connection structure 462 may conformally extend along the contour of each of the side surface and the lower surface of the second trench T2.

[0150] The second connection structure 462 may include, but is not limited to, at least one of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof. In some example embodiments, the second connection structure 462 may be located at the same vertical level as the vertical level of the first connection structure 362.

[0151] In some example embodiments, the first protection film 166 may cover the second connection structure 462. For example, the first protection film 166 may extend along the outline of the second connection structure 462.

[0152] In some example embodiments, a first filling insulating film 465 may be formed on the second connection structure 462 to fill the second trench T2. The first filling insulating film 465 may include, for example, but is not limited to, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof.

[0153] In some example embodiments, a first capping pattern 470 may be formed on the first filling insulating film 465. The first capping pattern 470 may cover an upper surface of the first filling insulating film 465.

[0154] The third connection structure 562 may be formed in the pad region PR. The third connection structure 562 may be formed on the surface insulating film 150 and in the pad region PR. The third connection structure 562 may electrically connect the second wiring structure 240 and an external device to each other. For example, a third trench T3 may be formed in the first substrate 100 and in the pad region PR. The third connection structure 562 may be formed in the third trench T3 to be exposed. In addition, in the pad region PR, the fourth trench T4 may be formed to expose the fifth wiring pattern 246. The third connection structure 562 may be formed in the fourth trench T4 to contact the fifth wiring pattern 246. In some example embodiments, the third connection structure 562 may conformally extend along the contour of each of the side surfaces and the lower surface of each of the third trench T3 and the fourth trench T4.

[0155] The third connection structure 562 may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof. However, the present disclosure is not limited thereto. In some example embodiments, the third connection structure 562 may be located at the same vertical level as the vertical level of each of the first connection structure 362 and the second connection structure 462.

[0156] In some example embodiments, a second filling insulating film 565 may be formed on the third connection structure 562 to fill the fourth trench T4. The second filling insulating film 565 may include, but is not limited to, at least one of, for example, silicon oxide, aluminum oxide, tantalum oxide, and a combination thereof. In some example embodiments, the second filling insulating film 565 may be located at the same vertical level as the vertical level of the first filling insulating film 465. In some example embodiments, a second capping pattern 570 may be formed on the second filling insulating film 565. The second capping pattern 570 may cover the upper surface of the second filling insulating film 565.

[0157] In some example embodiments, a second pad 575 may be formed on the third connection structure 562 to fill the fourth trench T4. The second pad 575 may include, but is not limited to, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. In some example embodiments, the second pad 575 may be located at the same vertical level as the vertical level of the first pad 375.

[0158] In some example embodiments, the first protection film 166 may cover the third connection structure 562. For example, the first protection film 166 may conformally extend along the contour of the third connection structure 562. In some example embodiments, the first protection film 166 may not cover the second pad 575 to be exposed.

[0159] In some example embodiments, the third isolation pattern 320 may be formed in the first substrate 100. The third isolation pattern 320 is shown as being formed only around the second connection structure 462 and around the third connection structure 562, but this is merely an example and the inventive concept is not limited thereto. For example, the third isolation pattern 320 may also be formed around the first connection structure 362. The third isolation pattern 320 may include, but is not limited to, at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof.

[0160] In some example embodiments, the width of the third isolation pattern 320 may decrease as the third isolation pattern 320 extends from the second surface 100b of the first substrate 100 toward the first surface 100a of the first substrate 100. This may be due to the characteristics of the etching process of forming the third isolation pattern 320. For example, the third isolation pattern 320 may be implemented as a BDTI (backside deep trench isolation) formed by a DTI (deep trench isolation) process performed on the second surface 100b of the first substrate 100. In some example embodiments, the third isolation pattern 320 may be spaced apart from the first surface 100a of the first substrate 100.

[0161] In some example embodiments, the light blocking color filter 380 may be formed on the first connection structure 362 and the second connection structure 462. For example, the light blocking color filter 380 may be formed to cover at least a portion of the first protective film 166 located in the light blocking region OB and the connection region CR. The light blocking color filter 380 may prevent or reduce light from being incident on the first substrate 100.

[0162] In some example embodiments, the third protective film 390 may be formed on the light blocking color filter 380. For example, the third protective film 390 may be formed to cover at least a portion of the first protective film 166 located in the light blocking region OB, the connection region CR, and the pad region PR. In some example embodiments, the second protective film 195 may extend along the surface of the third protective film 390. The third protective film 390 may include, for example, a light-transmitting resin. However, the present disclosure is not limited thereto. In some example embodiments, the third protective film 390 may be located at the same vertical level as the vertical level of the microlens 190.

[0163] In some example embodiments, the second protection film 195 and the third protection film 390 may not cover the second pad 575 so that it is exposed. For example, an exposure opening OP exposing the second pad 575 may be formed in the second protection film 195 and the third protection film 390. Therefore, the second pad 575 may be connected to an external device, etc., and may be configured to transmit an electrical signal between the image sensor according to some example embodiments and the external device. That is, the second pad 575 may be used as an input / output pad of the image sensor according to some example embodiments.

[0164] In the following, reference is made to Figures 1 to 24 , describing methods for manufacturing an image sensor according to some example embodiments.

[0165] Figures 17 to 24 is a diagram of an intermediate structure corresponding to an intermediate step of a method for manufacturing an image sensor according to some example embodiments. For ease of description, the above referenced Figures 1 to 16 Describes the content of the duplicate content.

[0166] Reference Fig.17 and Fig.18 , a photoelectric conversion region 101, an element isolation film 110, and an active region 102 are formed in the first substrate 100. Subsequently, a first circuit element CC is formed on the first substrate 100.

[0167] For example, the photoelectric conversion region 101 may be formed by implanting n-type impurity ions into the p-type first substrate 100. The photoelectric conversion region 101 may be formed in each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14 arranged in the first substrate 100.

[0168] The element isolation film 110 may define an active region 102 in each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14. The element isolation film 110 may extend on and along the first surface 100a of the first substrate 100, and may define an active region 102 extending from the first surface 100a in the first substrate 100. For example, the element isolation film 110 may be formed by an STI shallow trench isolation process for the first surface 100a of the first substrate 100.

[0169] The active region 102 may include a floating diffusion region FD. For example, the floating diffusion region FD may be formed by implanting n-type impurity ions into the p-type first substrate 100. In some example embodiments, the floating diffusion region FD may be interposed between unit pixels adjacent to each other in a diagonal direction. In some example embodiments, the floating diffusion region FD of the first pixel groups G1 to G4 may be interposed between the first unit pixel G1 and the fourth unit pixel G4 and / or between the second unit pixel G2 and the third unit pixel G3.

[0170] The first circuit element CC may be formed on the first surface 100a of the first substrate 100. The first circuit element CC may include various transistors for processing electrical signals generated from each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14 in the first substrate 100. For example, the first circuit element CC may include the transistors described above. Figure 2 The transfer transistor TX, the reset transistor RX, the drive transistor DX and / or the selection transistor SX, etc. described in the description of .

[0171] Reference Fig.19 and Fig. 20 , a first isolation pattern 120 is formed in the first substrate 100 .

[0172] For example, the first isolation pattern 120 may be formed by burying an insulating material in a deep trench formed by patterning a portion of the first substrate 100 including the first surface 100a. In some example embodiments, the first isolation pattern 120 may include a filling pattern 122 and a spacer film 124.

[0173] The first isolation pattern 120 may define a plurality of pixel groups in the first substrate 100. For example, the first isolation pattern 120 may surround each of the first pixel groups G1 to G4, the second pixel groups R1 to R4, the third pixel groups B1 to B4, and the fourth pixel groups G11 to G14 in a plan view.

[0174] In some example embodiments, the first isolation pattern 120 may not exist in the center of adjacent unit pixels of each pixel group. For example, the first isolation pattern 120 may include a group isolation portion 120e and first to fourth pixel isolation portions 120a to 120d.

[0175] Reference Fig.21 , a first wiring structure 140 is formed on the first substrate 100 .

[0176] A first wiring structure 140 may be formed on the first surface 100a of the first substrate 100. The first wiring structure 140 may include a first inter-wiring insulating film 142 on the first surface 100a and a first wiring pattern 144 disposed in the first inter-wiring insulating film 142. The first wiring structure 140 may be electrically connected to the first circuit element CC, and may transmit an electrical signal to each of the unit pixels G1 to G4, R1 to R4, B1 to B4, and G11 to G14 via the first circuit element CC.

[0177] Reference Fig. 22 , the first wiring structure 140 is attached to the carrier substrate 400 .

[0178] For example, the carrier substrate 400 may be attached to Fig.21 The resulting structure. When the carrier substrate 400 is attached to Fig.21 After obtaining the structure of Fig.21 The resulting structure is turned upside down. For example, as shown, the second surface 100b of the first substrate 100 may face upward. In some example embodiments, the first wiring structure 140 may be attached to the carrier substrate 400 in an oxide-oxide bonding process.

[0179] Reference Fig.23 and Fig.24 , a second isolation pattern 130 is formed in the first substrate 100 .

[0180] For example, the second isolation pattern 130 may be formed by burying an insulating material in a deep trench formed by patterning a portion of the first substrate 100 including the second surface 100 b .

[0181] The second isolation pattern 130 may be interposed between unit pixels adjacent to each other in a diagonal direction. In some example embodiments, the second isolation pattern 130 of the first pixel groups G1 to G4 may be interposed between the first unit pixel G1 and the fourth unit pixel G4 and / or between the second unit pixel G2 and the third unit pixel G3.

[0182] Next, refer to Figure 3 and Figure 4 , a surface insulating film 150, a grid pattern 160, a first protective film 166, color filters 180a to 180d, and a microlens 190 are formed on the second surface 100b of the first substrate 100. Thus, the above-mentioned Figures 3 to 7 Description of the image sensor.

[0183] Figures 25 to 30 is a diagram of an intermediate structure corresponding to an intermediate step of a method for manufacturing an image sensor according to some example embodiments. For reference, Fig.25 is with Fig.18 Figures of intermediate structures corresponding to subsequent steps.

[0184] Reference Fig.25 , a first wiring structure 140 is formed on the first substrate 100. Since the first wiring structure 140 is formed in the same manner as that already used above Fig.21 The descriptions are similar, so the detailed description is omitted below.

[0185] Reference Fig.26 Attach the first wiring structure 140 to the carrier substrate 400. Attaching the first wiring structure 140 to the carrier substrate 400 is similar to the above-mentioned method. Fig. 22 Therefore, the detailed description thereof is omitted below.

[0186] Reference Fig. 27 and Fig.28 , a first isolation pattern 120 is formed in the first substrate 100 .

[0187] For example, the first isolation pattern 120 may be formed by burying an insulating material in a deep trench formed by patterning a portion of the first substrate 100 including the second surface 100 b .

[0188] The first isolation pattern 120 may define a plurality of pixel groups in the first substrate 100. For example, the first isolation pattern 120 may surround each of the first pixel groups G1 to G4, the second pixel groups R1 to R4, the third pixel groups B1 to B4, and the fourth pixel groups G11 to G14 in a plan view.

[0189] In some example embodiments, the first isolation pattern 120 may not exist in the center of adjacent unit pixels of each pixel group. For example, the first isolation pattern 120 may include a group isolation portion 120e and first to fourth pixel isolation portions 120a to 120d.

[0190] Reference Fig.29 and Fig.30 , a second isolation pattern 130 is formed in the first substrate 100. The second isolation pattern 130 is formed in the same manner as that already described above. Fig.23 and Fig.24 Therefore, the detailed description thereof is omitted below.

[0191] Next, refer to Figure 8 , a surface insulating film 150, a grid pattern 160, a first protective film 166, color filters 180a to 180d, and a microlens 190 are formed on the second surface 100b of the first substrate 100. Thus, the above-mentioned Figures 8 to 10 Description of the image sensor.

[0192] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing tolerance or an operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "substantially" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the freedom of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "approximately" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing tolerance or an operating tolerance (e.g., ±10%) around the stated numerical value or shape.

[0193] Although the exemplary embodiments of the present disclosure are described above with reference to the accompanying drawings, the present disclosure may not be limited to the exemplary embodiments and may be implemented in various different forms. A person of ordinary skill in the technical field to which the present disclosure belongs will be able to understand that the present disclosure may be implemented in other specific forms without changing the technical ideas or basic features of the present disclosure. Therefore, it should be understood that the exemplary embodiments described above are not restrictive but illustrative in all aspects.

Claims

1. An image sensor, comprising: a substrate including a first surface and a second surface opposite to each other; A first pixel group is located in the substrate, and the first pixel group includes: The first unit pixel, a second unit pixel which is adjacent to the first unit pixel in a first direction in a plan view, a third unit pixel adjacent to the first unit pixel in a second direction perpendicular to the first direction in the plan view, and a fourth unit pixel that is adjacent to the second unit pixel in the second direction in the plan view and is adjacent to the third unit pixel in the first direction in the plan view; a photoelectric conversion region located in each of the first to fourth unit pixels; A first isolation trench, located in the substrate, the first isolation trench surrounding the first pixel group; a second isolation trench located in the substrate, the second isolation trench being located between the first unit pixel and the fourth unit pixel and between the second unit pixel and the third unit pixel, wherein the second isolation trench contacts a second surface of the substrate; and A first color filter is located on the second surface of the substrate, and the first color filter covers the first pixel group.

2. The image sensor according to claim 1, wherein: The first isolation trench comprises: a first pixel isolation trench located between the first unit pixel and the third unit pixel, wherein the first pixel isolation trench extends in the first direction; and a second pixel isolation trench, which is located between the second unit pixel and the fourth unit pixel, wherein the second pixel isolation trench extends in the first direction, The second isolation trench is located between the first pixel isolation trench and the second pixel isolation trench, and is spaced apart from the first pixel isolation trench and the second pixel isolation trench.

3. The image sensor according to claim 2, wherein: A depth of the first pixel isolation trench from the second surface of the substrate in a third direction perpendicular to the first direction and the second direction is greater than a depth of the second isolation trench from the second surface of the substrate in the third direction.

4. The image sensor according to claim 3, wherein: The first pixel isolation trench contacts the first surface and the second surface of the substrate.

5. The image sensor according to claim 4, further comprising a floating diffusion region located on the first surface of the substrate, in, At least a portion of the floating diffusion region vertically overlaps the second isolation trench in the third direction.

6. The image sensor according to claim 4, wherein: The first pixel isolation trench includes a silicon oxide layer and an aluminum oxide layer.

7. The image sensor according to claim 4, wherein: The second isolation trench includes a low-refractive-index material having a refractive index lower than that of silicon.

8. The image sensor according to claim 7, wherein: The low refractive index material includes at least one of silicon oxide, aluminum oxide, tantalum oxide and combinations thereof.

9. The image sensor according to claim 4, further comprising: a second pixel group, which is adjacent to the first pixel group in the substrate, the second pixel group comprising: The fifth unit pixel, a sixth unit pixel, which is adjacent to the fifth unit pixel in the first direction in the plan view, a seventh unit pixel adjacent to the fifth unit pixel in the second direction in the plan view, and an eighth unit pixel that is adjacent to the sixth unit pixel in the second direction in the plan view and is adjacent to the seventh unit pixel in the first direction in the plan view; a third isolation trench located in the substrate, wherein the third isolation trench is located between the fifth unit pixel and the eighth unit pixel; and a second color filter, which is located on the second surface of the substrate, and the second color filter covers the second pixel group, The first color filter has a first color, and the second color filter has a second color different from the first color.

10. An image sensor, comprising: a substrate including a first surface and a second surface opposite to each other; a first isolation trench defining a plurality of pixel groups in the substrate, each of the pixel groups including a plurality of unit pixels; a second isolation trench located in each of the pixel groups, the second isolation trench extending from the second surface and spaced apart from the first surface; a photoelectric conversion region located in each of the unit pixels; a circuit element located on the first surface of the substrate; as well as a color filter located on the second surface of the substrate, The plurality of unit pixels include a first unit pixel, a second unit pixel adjacent to the first unit pixel in a first direction, and a third unit pixel adjacent to the first unit pixel in a second direction intersecting the first direction, The second isolation trench is located between the second unit pixel and the third unit pixel.

11. The image sensor according to claim 10, wherein: The plurality of pixel groups include a first pixel group, a second pixel group adjacent to the first pixel group in the first direction, and a third pixel group adjacent to the first pixel group in the second direction, and The color filter comprises: a first color filter having a first color and covering the first pixel group; a second color filter having a second color different from the first color and covering the second pixel group; and A third color filter has a third color different from the first color and the second color and covers the third pixel group.

12. The image sensor according to claim 10, wherein: A width of the first isolation trench decreases as the first isolation trench extends from the first surface toward the second surface.

13. The image sensor according to claim 12, wherein: The first isolation trench extends from the first surface to the second surface.

14. The image sensor according to claim 12, wherein: The first isolation trench comprises: a fill pattern comprising a conductive material; and A spacer film extends along side surfaces of the filling pattern.

15. The image sensor according to claim 14, wherein: A depth of the second isolation trench from the second surface is smaller than a depth of the first isolation trench from the second surface.

16. The image sensor according to claim 14, wherein: The first isolation trench and the second isolation trench include different materials from each other.

17. The image sensor according to claim 9, wherein: The second isolation trench comprises: a first extending portion extending in the second direction and located between the first unit pixel and the second unit pixel; and A second extending portion extends in the first direction and is located between the first unit pixel and the third unit pixel.

18. An image sensor, comprising: a substrate including a first surface and a second surface opposite to each other; a first pixel group, which is located in the substrate, the first pixel group comprising a first unit pixel, a second unit pixel adjacent to the first unit pixel in a first direction, a third unit pixel adjacent to the first unit pixel in a second direction intersecting the first direction, and a fourth unit pixel adjacent to the second unit pixel in the second direction and adjacent to the third unit pixel in the first direction; a photoelectric conversion region located in each of the first to fourth unit pixels; A first isolation trench, located in the substrate, the first isolation trench surrounding the first pixel group; A second isolation trench, located in the substrate, wherein the second isolation trench is located between the first unit pixel and the fourth unit pixel; a floating diffusion region extending from the first surface in the substrate, at least a portion of the floating diffusion region overlapping the second isolation trench in a third direction intersecting the first direction and the second direction; a transfer transistor located on a first surface of each of the first to fourth unit pixels, the transfer transistor being adjacent to the floating diffusion region; A first color filter, which is located on the second surface of the substrate, covers the first pixel group and has a first color; as well as a microlens located on the first color filter, The second isolation trench extends from the second surface and is spaced apart from the floating diffusion region.

19. The image sensor according to claim 18, wherein: A depth of the second isolation trench is in a range of 60% to 80% of a thickness of the substrate.

20. The image sensor according to claim 18, wherein: The interval between the second isolation trench and the first surface is between 1 μm and 10 μm.

Images