Method of porosity of (Al, In, Ga) N / (Al, In, Ga) N mesa

Abstract

The present description relates to a method of porosing a (Al, In, Ga) N / (Al, In, Ga) N mesa, and specifically discloses a structure (100) comprising a base substrate (110) covered with a (Al, In, Ga) N / (Al, In, Ga) N mesa (120), and a method of porosing a structure (100) comprising a porosing step during which the (Al, In, Ga) N / (Al, In, Ga) N mesa is electrochemically porosed, during which the (Al, In, Ga) N / (Al, In, Ga) N mesa is electrochemically porosed. The structure (100) also includes an electrically conductive wire (200) covered with an electrically insulating element (300) between the mesas (120) or between groups of mesas (120).

Description

Technical Field

[0001] The present disclosure relates generally to the field of color microdisplays, and in particular to the field of micro-LED based color microdisplays.

[0002] The present invention relates to a method for pore-forming (Al, In, Ga)N / (Al, In, Ga)N mesas.

[0003] The invention also relates to the structure obtained thereby comprising the porous (Al, In, Ga)N / (Al, In, Ga)N mesas. Background Art

[0004] The color microdisplay comprises a pixel formed by a blue sub-pixel, a green sub-pixel and a red sub-pixel (RGB pixel). In the remainder of this disclosure, for the sake of brevity, these sub-pixels will be more simply designated as pixels.

[0005] Blue pixels and green pixels can be made of nitride materials, while red pixels can be made of phosphide materials. In order to combine these three types of pixels on the same substrate, pick-and-place technology is usually used. However, for microdisplays with pixels smaller than 10μm, this technology can no longer be used, not only because of alignment problems, but also because of the time required to implement this technology on such specifications. For screens with a large number of pixels (high definition), this "pick-and-place" technology is problematic in terms of time. In addition, the pixels must be sampled from different wafers, which requires continuous transfer. Parallel transfer technology ("mass transfer") can also be used.

[0006] Another solution involves color conversion using quantum dots (QDs) or nanophosphors pumped by blue μLEDs originating from a single wafer, either transferred or in a monolithic array (the preferred case for microdisplays). However, controlled deposition of these materials is difficult on small pixel sizes, and their flux resistance is not robust enough.

[0007] It is therefore crucial to be able to natively obtain the three RGB pixels using the same family of materials and to perform their growth on the same substrate. To achieve this goal, InGaN is the most promising material. Depending on its indium concentration, this material can indeed theoretically cover the entire visible spectrum. Blue micro-LEDs based on InGaN already have high brightness levels, much higher than their organic counterparts. In order to emit green wavelengths, the quantum wells (QWs) of the LEDs must contain at least 25% indium, while for emitting red wavelengths, at least 35% indium. Unfortunately, the quality of InGaN materials with more than 20% In degrades due to the low miscibility of InN with GaN and the high compressive stress inherent in the growth of the InGaN-on-GaN active zone.

[0008] Therefore, being able to reduce the general stress in GaN / InGaN-based structures is crucial.

[0009] Currently, one of the most promising solutions consists in making the GaN layer porous, as described in two articles by Pasayat et al. (Materials 2020, 13, 213; Appl. Phys. Lett. 116 111101 (2020)). The methods described in these articles include the following steps:

[0010] - providing a stack comprising a sapphire substrate covered with a non-intentionally doped GaN (nid-GaN) layer, an n+ doped GaN (5e10 18 at / cm 3 ) layer and non-intentionally doped InGaN or GaN layer,

[0011] - partially etching the stack to form GaN / InGaN or GaN / GaN mesas; the thickness of the doped layers is only partially etched so that the residual doped layer at the bottom of the mesa allows for polarization of the doped layers of all mesas (e.g. polarization rings or wafer edge polarization),

[0012] - The electrochemical porosification step was carried out in an oxalic acid solution (0.3 M), the doped GaN layer acting as anode and the platinum wire acting as cathode.

[0013] The porous GaN layer thus obtained enables the growth of InGaN-based LED nitride structures with good crystal quality due to the relaxation of the generated porous mesas.

[0014] However, the quality of the LED depends not only on the pore size, but also on the porosity of the porous GaN layer. Therefore, it is necessary to be able to porosify all mesas of the same wafer uniformly.

[0015] All the mesas in these stacks may also have a common layer.The porosification step is then performed by polarizing this common layer with an anodic potential.

[0016] For example, Figures 1A to 1C show different steps of this method. More specifically, the method includes the following steps:

[0017] - providing a stack comprising in sequence a support layer 10, an unintentionally doped GaN layer 11, a doped or heavily doped GaN layer 12, and a nid InGaN or GaN layer 13 (FIG. 1A),

[0018] - building a mesa in the stack, the mesa comprising a nid InGaN or GaN layer 13 and a portion of a doped or heavily doped GaN layer 12 ( FIG. 1B ), another portion of the doped GaN layer acting as a mesa common layer,

[0019] - The obtained structure is immersed in an electrolyte and a voltage is applied between the doped or heavily impurity-doped GaN layer 12 and a counter electrode, thereby obtaining a porous GaN layer 12' (FIG. 1C).

[0020] It is known that the nid InGaN layer has intrinsic defects (“V-pits”), which contribute to the porosity of the mesa, because the electrolyte can penetrate from this upper layer 13 of the mesa all the way to the doped or heavily doped layer 12 through these defects and the flanks of the doped or heavily doped layer of the mesa 12.

[0021] However, nid-GaN layers do not have such a defect: they are dense layers. Therefore, in the GaN / GaN configuration, the doped or heavily doped layer of the mesa 12 is porous from the side of the mesa to the center of the mesa. This layer is not porous all the way to the center of the mesa. For example, the wafer edge / center effect is observed on a 2-inch wafer. Figures 2A and 2B show the mesa in the center of such a structure after porosification in a cross-sectional view and a top view, respectively. The mesa is partially porous.

[0022] This effect may be due to the decrease in lateral conductivity of the bottom layer of the residual doped mesa, polarization from the wafer periphery, thus producing a wafer edge / center effect.

[0023] Therefore, there is a real need for a method that can fully porosify the mesa and limit the center-edge effect on the wafer, especially on 2 inch (5.08 cm) wafers, and even more so on larger size (200 mm and 300 mm) wafers. Summary of the invention

[0024] There is a need to provide a method for porosifying (Al,In,Ga)N / (Al,In,Ga)N mesas, enabling all mesas on a wafer (regardless of whether they are at the edge or the center of the wafer) to be porosified identically (or uniformly), the method advantageously having to be applicable to large substrates (typically on substrates having a diameter of at least 5 cm, and preferably at least 10 cm).

[0025] This object is achieved by a method for porosifying a structure comprising a base substrate covered with (Al,In,Ga)N / (Al,In,Ga)N mesas, the method comprising a porosification step during which the (Al,In,Ga)N / (Al,In,Ga)N mesas are electrochemically porosified, during which conductive lines covered with electrically insulating elements are arranged on the base substrate between the mesas or between groups of mesas.

[0026] According to an advantageous embodiment, the base substrate comprises a support layer, a first undoped GaN layer and a second doped GaN layer.

[0027] Preferably, the (Al, In, Ga) N / (Al, In, Ga) N mesa comprises a third layer of heavily doped (Al, In, Ga) N and a fourth layer of undoped or lightly doped (Al, In, Ga) N. A portion of the second doped GaN layer extends in the mesa. During the porosification step, the conductive line is in direct contact with the second doped GaN layer.

[0028] During the porosification step, the third mesa layer of heavily doped (Al, In, Ga) N is porosified. The third mesa layer of heavily doped (Al, In, Ga) N may be partially or completely porosified during the porosification step.

[0029] According to an advantageous variant, the conductive wire is made of metal, preferably of titanium, or of a conductive polymer.

[0030] According to another advantageous variant, the conducting wires are made of heavily doped GaN.

[0031] According to this other advantageous variant, the method may comprise a step during which the conducting lines are formed by epitaxy.

[0032] Advantageously, the conductive wires form a grid.

[0033] Advantageously, the conductive line partially covers the base substrate, and the space between the conductive line and the mesa is in the range of 100 nm to 1 μm, preferably in the range of 200 nm to 500 nm.

[0034] One embodiment provides a structure comprising a base substrate covered with porous (Al, In, Ga) N / (Al, In, Ga) N mesas. The structure also comprises a conductive line covered with an electrically insulating element, the conductive line being arranged on the base substrate between the mesas or between groups of mesas.

[0035] Advantageously, the base substrate comprises a support layer, a first undoped GaN layer and a second doped GaN layer.

[0036] Preferably, the (Al, In, Ga) N / (Al, In, Ga) N mesa comprises a third heavily doped porous GaN layer and a fourth undoped or lightly doped (Al, In, Ga) N layer. A portion of the second doped GaN layer extends in the mesa.

[0037] The third mesa layer of heavily doped (Al,In,Ga)N can be partially or fully porous.

[0038] According to one embodiment, the conductive wires are made of heavily doped GaN, metal or conductive polymer. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above features and advantages and other features and advantages will be described in detail in the remainder of the specific embodiments which are given by way of example and not limitation and with reference to the accompanying drawings, in which:

[0040] 1A , 1B and 1C described above schematically illustrate different steps of a porosification method according to the prior art;

[0041] As mentioned above, FIG. 2A is an image of a (Al, In, Ga) N / (Al, In, Ga) N table obtained by scanning electron microscopy after the porosification step according to the prior art: the porosification is not complete,

[0042] As previously mentioned, FIG. 2B is an image obtained with a dark field optical microscope in the top through hole of different (Al, In, Ga) N / (Al, In, Ga) N mesas at the center of the wafer after the porosification step according to the prior art; the left part of the figure corresponds to a (Al, In, Ga) N / (Al, In, Ga) N mesa with a width of 3 μm, and the right part of the figure corresponds to a (Al, In, Ga) N / (Al, In, Ga) N mesa with a width of 5 μm,

[0043] Figure 3A , Figure 3B and Figure 3C Schematically showing different steps of a mesa porosity method according to a specific embodiment of the present invention;

[0044] Figure 4A structure including a porous (Al, In, Ga) N / (Al, In, Ga) N mesa and a conductive line according to an embodiment of the present invention is shown schematically and in cross section,

[0045] Figure 5A , Figure 5B , Figure 5C , Figure 5D Schematically showing different steps of a method for manufacturing a metal grid according to a specific embodiment of the present invention;

[0046] Fig. 6A , Figure 6B , Figure 6C , Fig.6D Schematically showing different steps of a method for manufacturing a metal grid according to another specific embodiment of the present invention;

[0047] Fig. 7A , Figure 7B , Figure 7C Schematically illustrates different steps of a method for covering a metal grid with an electrically insulating element according to a specific embodiment of the present invention; and

[0048] Fig. 8A , Figure 8B , Figure 8C , Fig.8D and Fig. 8E The different steps of a method for manufacturing a heavily doped GaN mesh covered with an electrically insulating element according to a specific embodiment of the invention are schematically shown. DETAILED DESCRIPTION

[0049] In the various drawings, similar features have been designated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals, and may be provided with the same structure, dimensions, and material properties.

[0050] For clarity, only those steps and elements that are useful for understanding the described embodiments are shown and described in detail.

[0051] In the following description, when reference is made to absolute position qualifiers (such as "front", "back", "up", "down", "left", "right", etc.), or relative position qualifiers (such as "top", "bottom", "above", "below", etc.), or orientation qualifiers (such as "horizontal", "vertical", etc.), unless otherwise specified, the reference is made to the orientation specified in the drawing or in the orientation specified in the normal use position.

[0052] Unless otherwise specified, the terms "approximately," "approximately," "substantially," and "about" mean plus or minus 10%, preferably plus or minus 5%.

[0053] Although this is by no means limiting, the invention is particularly applicable to the field of color microdisplays and more specifically to the manufacture of red, green and blue pixels. However, it can also be used in the field of photovoltaics or in the field of water splitting, since on the one hand InGaN absorbs in the entire visible spectrum and on the other hand its valence and conduction bands are in the stable range of water, which is a thermodynamic condition required for the water splitting reaction. The invention can also be advantageous for the manufacture of LEDs or lasers emitting at high wavelengths.

[0054] The method is particularly advantageous for producing structures comprising porous (Al, In, Ga) N / (Al, In, Ga) N mesas with a pitch of, in particular, less than 30 μm.

[0055] (Al, In, Ga) N refers to AlN, AlGaN, InGaN or GaN. In the following, it refers more specifically to porous GaN, but by this method, you can have, for example, porous InGaN or AlGaN. Regardless of its composition, a dense InGaN layer (under compression) or a dense AlGaN layer (under tension) will relax due to the porous structure.

[0056] refer to Figure 3A , Figure 3B and Figure 3C The method of porosification of the (Al, In, Ga) N / (Al, In, Ga) N mesa 120 will now be described in more detail. The method comprises the following steps:

[0057] i) providing a structure 100 comprising a base substrate 110 covered with (Al, In, Ga) N / (Al, In, Ga) N mesas 120, on which a conductive line 200 covered with an electrically insulating element 300 is arranged between groups of mesas or between the mesas 120 ( Figure 3A ),

[0058] ii) Porosified table 120 ( Figure 3B ),

[0059] iii) Optionally, remove the electrical insulating element 300 or remove the conductive line 200 and the insulating element 300 ( Figure 3C ).

[0060] The use of conductive lines 300 positioned between the mesas 120 makes it possible to obtain a structure in which each mesa 120 has an equivalent electrical configuration (potential losses between the mesas are sufficiently low). The polarization of the mesas 120 is uniform, so that the porosity of the mesas on each pattern is well controlled. This method not only makes it possible to make all mesas 120 on the wafer (whether they are at the edge or the center of the wafer) porosified identically (or uniformly), but also to make the entire volume of the doped layer of the mesas 120 porosified. The porosity of the mesas 120 can also be controlled so as to leave a non-porous central area for each mesa 120 that forms a conductive channel within the mesa.

[0061] The porosification has no edge-center effect. The method is fully applicable to patterns with sizes greater than 5 μm and / or large substrates (typically on substrates with a diameter of at least 5 cm and preferably at least 10 cm).

[0062] Furthermore, since the conduction is performed by means of the conductive wire 200, the upper layer of the substrate 110 in contact with the conductive wire 200 can be less doped. Therefore, not only is this layer less exposed to undesired porosity, but this layer is also less stressed.

[0063] By this method, the obtained structures show good crystalline quality. There is no risk of porosity of the underlying layers due to defects at the bottom of the mesas. Re-epitaxially grown layers can be easily deposited on the structure without the risk of stress-induced crack formation. The total re-epitaxial thickness can be high.

[0064] These wires are covered by an electrically insulating element which completely covers them and prevents them from coming into contact with the electrolyte during the porosification step. Therefore, during this step, the wires are not damaged; there is no loss of conductivity.

[0065] The different steps of the method will now be described in more detail.

[0066] like Figure 3A and Figure 4 As shown, the base substrate 110 of the structure 100 provided in step i) comprises in sequence: - a support layer 114,

[0067] - optionally, a (Al,Ga)N buffer layer, in particular in the case of a silicon support layer 114,

[0068] - a first undoped GaN layer 111,

[0069] - A second doped GaN layer 112 .

[0070] The (Al, In, Ga)N / (Al, In, Ga)N mesa 120 includes a third heavily doped (Al, In, Ga)N layer 123 and a fourth undoped or lightly doped (Al, In, Ga)N layer 124 .

[0071] At the end of the porosification step ii), the third (Al,In,Ga)N mesa layer 123 ′ is at least partially (ie partly or completely) porosified.

[0072] A portion 112b of the second doped GaN layer 112 extends in the mesa 120. Another portion 112a of the second doped GaN layer 112 forms an upper portion of the base substrate 110. This portion is in direct contact with the conductive line 200. In other words, there is no element between the portion 112a of the second doped GaN layer 112 and the conductive line 200. The portion 112a of the second doped GaN layer 112 forms the bottom of the mesa.

[0073] During step ii), the bottom of the mesa is preferably protected from porosification.

[0074] For example, the structure 100 provided in step i) is obtained by providing and then locally etching a stack comprising, in sequence:

[0075] - a support layer 114,

[0076] - optionally, a (Al,Ga)N buffer layer, in particular in the case of a silicon support layer 114,

[0077] - a first undoped GaN layer 111,

[0078] - a second doped GaN layer (GaN n) 112,

[0079] - a third heavily doped GaN layer (n+GaN or nn GaN) 123, and

[0080] A fourth layer 124 of non-intentionally doped (nid) or lightly doped AlN, InGaN or GaN (denoted as (Al, In, Ga)N).

[0081] Preferably, the stack is formed by the aforementioned layers. In other words, it does not include other layers.

[0082] The support layer 114 is made of, for example, sapphire or silicon.

[0083] For example, the support layer 114 has a thickness in the range from 250 μm to 2 mm. The thickness depends on the nature of the support layer 114 and its size. For example, for a sapphire support layer with a 2-inch diameter, the thickness may be 350 μm. For a sapphire support layer with a 6-inch diameter, the thickness may be 1.3 mm. For a silicon support layer with a 200 mm diameter, the thickness may be 1 mm.

[0084] "From X to Y" means that the value is between X and Y, inclusive.

[0085] In the case of a silicon support layer 114 , an (Al,Ga)N buffer layer is advantageously interposed between the support layer 114 and the nid GaN layer 111 .

[0086] The first layer 111 is a nid GaN layer. It is a non-intentionally doped (nid) layer and thus will not be porous. Non-intentionally doped GaN refers to a layer with a concentration of less than 1 e 17at / cm 3 .

[0087] For example, the first nid GaN layer 111 has a thickness ranging from 500 nm to 5 μm. Advantageously, its thickness is between 1 and 4 μm to absorb stress associated with the lattice mismatch between GaN and the substrate.

[0088] The second layer 112 is a doped GaN layer. Doped GaN means that the concentration is preferably greater than 1.10 17 at / cm 3 , and preferably less than 5.10 18 at / cm 3 , and even more preferably below 1.10 18 at / cm 3 The presence of conductive lines makes the concentration lower than 5.10 17 at / cm 3 And for example in 1.10 17 at / cm 3 and 5.10 17 at / cm 3 GaN layers between them.

[0089] The second GaN layer 112 has a thickness ranging, for example, from 200 nm to 1 μm, preferably between 400 nm and 700 nm. The minimum thickness varies depending on the doping level.

[0090] The third layer 123 is a heavily doped GaN layer. Heavily doped GaN refers to a GaN layer with a concentration greater than 5.10 18 at / cm 3 , preferably greater than 8.10 18 at / cm3 , or even greater than 10 19 at / cm 3 For example, it has a doping ten times greater than the second layer 112. It has a thickness in the range from 200 nm to 2 μm, preferably in the range from 500 nm to 1 μm. Preferably, the doping of the third layer 123 is 30 times or even 100 times greater than the doping of the second layer 112.

[0091] The fourth layer 124 is an unintentionally doped or lightly doped (Al, In, Ga) N layer. Lightly doped (Al, In, Ga) N refers to a layer with a doping rate of 1.10 17 at / cm 3 and 5.10 17 at / cm 3 Non-doping refers to doping levels below 1.10 17 at / cm 3 .

[0092] It can be an AlN, AlGaN, InGaN or GaN layer. For example, the thickness is between 10 nm and 200 nm, preferably between 50 nm and 200 nm. For this layer, the doping is low enough to be electrically insulating. During step d), it is not voided.

[0093] This layer 124 is little or not affected by the porosification and is used as a seed layer for the resumption of growth. This layer 124 is continuous to ensure the quality of the re-epitaxial layer (eg, (In,Ga)N layer) on the structure.

[0094] The doping of the different layers mentioned above, and in particular the doping of the second layer 112 and the third layer 123, will be chosen depending on the voltage applied during the porosification.

[0095] In particular, the corresponding doping rates are selected so that at a given potential, there is selectivity between heavily doped regions and lightly doped regions. For a given potential, the doping rate of the second layer 112 is selected so that the second layer 112 is not porosified during step d), and the doping rate of the third layer 123 is selected so that the third layer 123 is porosified during step d).

[0096] In the following, n-type doping is described, but p-type doping is also possible.

[0097] The stack described above is constructed such that the mesas 120 are formed, for example, by photolithography.

[0098] The terraces 120 (also called elevations) are raised elements. For example, they are obtained by etching a continuous layer or a plurality of stacked continuous layers so as to leave only a plurality of "reliefs" of the layer or layers. The etching is preferably carried out using a hard mask characterized by a favorable selectivity to the etching rate of the GaN layer (typically an etching rate ratio of >1 / 4). The hard mask is made of SiO2, for example. After etching the terraces, this hard mask is removed by a wet chemical process before porosification. The hard mask can also be removed after porosification by exposing it only in the polarization area for electrochemical polarization. Advantageously, the mask is removed before the porosification step.

[0099] Preferably, the flanks of the mesas 120 are perpendicular to the stacking of the layers.

[0100] The surface of the countertop can be round, hexagonal, square or rectangular.

[0101] The maximum surface dimension of the mesa 120 ranges from 500 nm to 500 μm. For example, the maximum dimension of a circular surface is its diameter.

[0102] The thickness of a mesa corresponds to the dimension of the mesa perpendicular to the underlying stack.

[0103] The spacing between two consecutive mesas 120 may be in the range from several micrometers to several tens of micrometers. The spacing is preferably in the range from 50 nm to 20 μm. For example, it is 5 μm. Even more preferably, it is in the range from 1 μm to 2 μm.

[0104] The mesas 120 can have the same or different doping levels. At a fixed potential, the higher the doping level, the greater the porosity. The relaxation of the fourth layer 124 of dense (Al, In, Ga) N depends on the porosity of the mesa. Therefore, during the re-epitaxy of InGaN on the dense layer 124, different amounts of indium can be incorporated (due to the reduction of the composition pull effect (i.e., In atoms are pushed to the surface, preventing them from being incorporated into the layer)). Therefore, after the epitaxy of the complete LED structure, if the distance between the relaxation levels of the mesas is sufficient, blue, green and red (RGB) mesas can be obtained in a single growth step on the same substrate.

[0105] The mesa 120 is formed by etching the stack, and more specifically by etching the fourth layer 124, the third layer 123 and the first portion 112a of the second doped layer 112. By stopping the etching in the doped layer 123, the entire height of the third n++ layer 123 is available for relaxation.

[0106] Thus, a structure 100 including a base substrate 110 having a plurality of (Al, In, Ga)N / (Al, In, Ga)N mesas 120 on the top is obtained.

[0107] Each mesa 120 includes, in order from the base, a second portion 112 b of the doped GaN layer 112 , a third heavily doped GaN layer 123 , and a fourth undoped or lightly doped (Al, In, Ga) N layer 124 .

[0108] By way of non-limiting illustration, structure 100 may include:

[0109] - Base substrate 110, which comprises in sequence: a sapphire or silicon support layer 114, an optional (Al, Ga) N buffer layer, a first non-doped GaN layer 111 of 4 μm, a first portion 112a (1.10 18 at / cm 3 ),

[0110] - a mesa 120 (Al, In, Ga) N / In, Ga), which in turn comprises: a second portion 112b of the second doped GaN layer 112 of 100 nm (1.10 18 at / cm 3 ), 800nm ​​third heavily doped GaN layer 123 (1.10 19 at / cm 3 ), and a 100nm nid layer (Al,In,Ga)N.

[0111] The structure 100 further includes conductive lines 200 positioned between the mesas 120 on the base substrate 110. During porosification, charges flow through the conductive lines 200 and are injected near each mesa 120. The distance between the conductive lines 200 and the mesas 120 is selected to be small enough to avoid porosification of the second doped layer 112. It can be adapted to control the porosity of the desired mesa.

[0112] Conductive means capable of allowing, for example, about 8 mA / cm 2 The conductivity of the current density.

[0113] Conductive line 200 runs along the bottom of mesa 120. Conductive line 200 may be a straight line (particularly in the case of a square mesa) or a dashed line (for example in the case of a hexagonal mesa).

[0114] The conductive lines 200 advantageously form a grid, i.e. the lines intersect. Each mesa 120 is advantageously positioned next to one or more conductive lines 200. Next to means that at least one space between mesas adjacent to one mesa 120 is covered by a conductive line 200. Preferably, at least two, and even more preferably at least four (e.g. six) spaces between mesas adjacent to one mesa are covered with a line.

[0115] It is also possible to position the conductive line 200 around a group formed by a plurality of mesas. For example, a group of 4 or more mesas may be formed.

[0116] The conductive lines 200 may partially or completely cover the bottom of the mesa. They do not form part of the mesa 120 or the base substrate 110.

[0117] For example, the conductive line 200 has a width in the range of 750 nm to 2 μm.

[0118] The width of the conductive line 200 is chosen according to the spacing between the mesas. For example, for a spacing between mesas ("grooves") of 1.5 μm, a line having a width of 1 μm may be chosen.

[0119] The thickness of the conductive line 200 is, for example, in the range from 100 nm to 200 nm.

[0120] Size and thickness will be selected based on the material and desired conductivity.

[0121] The conductive line 200 partially covers the base substrate 110 , and a gap between the conductive line 200 and the mesa 120 is in the range from 100 nm to 1 μm, preferably in the range from 200 nm to 500 nm.

[0122] According to a first advantageous embodiment, the conductive wire 200 is made of a metal, for example chosen from titanium and aluminum. Preferably, the conductive wire 200 is made of titanium.

[0123] According to a second alternative embodiment, the conductive wire 200 is made of heavily doped (Al, In, Ga) N, preferably heavily doped GaN. Heavily doped means that the concentration is greater than 5.10 18 at / cm 3 .

[0124] According to a third alternative embodiment, the conductive wire 200 is made of a conductive polymer.

[0125] The conductive wires 200 are covered with an electrically insulating element 300. The electrically insulating element 300 is chemically inert in the solution used for the porosification. The electrically insulating element 300 completely covers the conductive wires 200 so that they are not in contact with the electrolyte during the porosification step. The electrically insulating element 300 is not porosified. The electrically insulating element 300 is preferably a dielectric material. For example, the electrically insulating element 300 is made of silicon oxide (SiO2) or silicon nitride (SiN 34 It can also be made of polymers, such as photosensitive polymers.

[0126] Depending on the nature of conductive line 200 , multiple manufacturing steps may be performed.

[0127] As examples, two alternative embodiments for forming the conductive metal line 200 will be described.

[0128] FIG. 5A to FIG. 5D A first alternative embodiment is shown. The first alternative embodiment comprises the following steps:

[0129] -Providing a structure 100( Figure 5A ),

[0130] - Forming a metal layer 202 over the entire wafer surface (i.e., the metal layer 202 covers the mesas 120 and the spaces between the mesas 120), and then depositing a resin 201 between the mesas 120, the resin layer 201 having the shape of the line to be formed ( Figure 5B ),

[0131] - Etching the metal layer 202 not covered with the resin layer 201 ( Figure 5C ),

[0132] - Removal of the resin 201 ("stripping"), thereby obtaining the conductive metal lines 200 located between the mesas 120 ( Figure 5D ).

[0133] The grid pattern is defined by the resin 201. It can be formed by photolithography or screen printing.

[0134] FIG. 6A to FIG. 6D A second alternative embodiment is shown. The second alternative embodiment comprises the following steps:

[0135] -Providing a structure 100( Fig. 6A ),

[0136] - A resin layer 203 is formed on the mesas 120 and partially between the mesas 120 by photolithography, so that there are areas between the mesas that are not covered with the resin 203, and the uncovered areas have a line shape, especially a cross-line shape, preferably a grid shape ( Figure 6B ),

[0137] - depositing a metal layer 200 on the areas not covered with the resin 203, the metal layer 200 thus having the shape of a line, preferably a grid ( Figure 6C ),

[0138] - Removal of the resin 203 ("metal release by stripping"), thereby obtaining the conductive metal lines 200 ( Fig.6D ).

[0139] The metal layer can be deposited over the entire wafer surface.

[0140] According to another variant, not shown, the conductive line 200 is made of a conductive polymer. The conductive polymer can be deposited by screen printing, photolithography (exposure and development) or any other means capable of forming a line with this material.

[0141] After porosification, the conductive polymer line 200 may be removed by wet etching and / or dry etching.

[0142] Whatever alternative embodiment is implemented, an electrically insulating element 300 is then deposited on the electrically conductive lines 200 in order to protect them during the anodization step.

[0143] To achieve this, FIG. 7A to FIG. 7C As shown, the following steps can be performed:

[0144] - Deposition of an electrically insulating layer 301 over the entire wafer surface ( Fig. 7A ),

[0145] - Locally deposit resin 203 opposite to the conductive line 200 ( Figure 7B ),

[0146] - Etching the electrically insulating layer 301 not covered with the resin 203, and then removing the resin 203 (see Figure 7C ).

[0147] To form the conductive line 200 made of doped GaN (usually with a doping level above 1.10 18 at / cm 3 ), for example, a region for selective area growth (SAG) can be formed. The growth region is defined by a SAG layer, which is made of a material that is not conducive to GaN growth. The SAG layer covers the mesas 120 and partially covers the spaces between the mesas. The SAG layer has openings in the form of lines, preferably in the form of a grid, defining uncovered areas on which it is desired to form a doped GaN grid. The SAG layer has a shape complementary to the grid.

[0148] Unfavorable for GaN growth means that GaN cannot grow on this layer, or the GaN growth kinetics on this material are very slow compared to the GaN growth kinetics on the material accessible through the openings of the SAG layer (i.e. the material of the space between the mesas, i.e. the material forming the second layer 112: doped GaN).

[0149] More specifically, to form the conductive doped GaN wire 200, the following steps may be performed: FIG. 8A to FIG. 8D ):

[0150] - Deposition of a layer 315 made of a material that is not conducive to GaN growth (e.g., nitride or oxide, in particular silicon nitride and / or silicon oxide) over the entire wafer surface ( Fig. 8A ),

[0151] - Local deposition of resin 316 by photolithography so as to leave a portion of layer 315 made of a material that is not conducive to GaN growth that is contactable between the mesas ( Figure 8B ),

[0152] - The material 315 is then etched and the resin 316 is removed, thereby obtaining selective growth areas in the shape of lines between the mesas ( Figure 8C ),

[0153] - epitaxial n+-doped GaN growth to form conductive lines 200 made of n+-doped GaN between the mesas ( Fig.8D ).

[0154] Layer 315 is then removed.

[0155] As previously described, an electrically insulating element 300 is then deposited over the conductive lines 200 to protect them during the anodization step ( Fig. 8E ). For example, the steps described above may be performed, in particular FIG. 7A to FIG. 7C Follow the steps shown in .

[0156] Specifically, they can be the following steps:

[0157] - depositing an electrically insulating layer (e.g. made of dielectric material) over the entire wafer surface,

[0158] - local deposition of resin opposite the conductive lines,

[0159] - etching of the electrically insulating layer not covered with resin,

[0160] -Remove resin.

[0161] In step ii), the structure is porosified. The porosification can be performed according to the following sub-steps:

[0162] - electrically coupling the structure 100 and the counter electrode to a voltage generator or a current generator,

[0163] - immersing the structure 100 and the counter electrode in an electrolyte,

[0164] - Applying a voltage or current between the second doped GaN layer 112 and the counter electrode to make the third heavily doped (Al, In, Ga) N layer 123 of the mesa 120 porous.

[0165] The structure 100 and the counter electrode (CE) are electrically coupled to a voltage generator or a current generator. The device acts as a working electrode (WE). Hereinafter, it will be referred to as a voltage generator, but it can also be a current generator capable of applying a current between the device and the counter electrode.

[0166] Contact regions are formed on the structure 100 .

[0167] In particular, the contact region may be formed on the base substrate 110. The contact may be made on the second doped GaN layer 112. The contact may be made at the bottom of the mesa, at the level of the second layer 112, which enables the use of an etching step to form the contact region as well. Alternatively, the contact may be performed on the conductive line 200.

[0168] Contact can also be made on one of the other layers: on the lightly doped (Al, In, Ga) N fourth layer 124 or on the heavily doped (Al, In, Ga) N third layer 123. In the case of making a contact on a heavily doped layer, its opening will advantageously be limited to areas protected from the electrolyte.

[0169] The top of the contact area may also be covered with a metal layer to improve the contact for electrochemical polarization. This contact may be removed after porosification before resuming epitaxy.

[0170] The counter electrode is made of a conductive material such as, for example, a metal that has a large developed surface area and is chemically inert to the electrolyte, such as a platinum mesh.

[0171] The electrodes are immersed in an electrolyte, also called an electrolyte bath or electrolyte solution. The electrolyte can be acidic or alkaline. An example of an electrolyte is oxalic acid. It can also be KOH, HF, HNO3, NaNO3 or H2SO4.

[0172] For example, the voltage applied between the structure 100 and the counter electrode can be in the range of from 1V to 30V. Preferably, it is from 5V to 15V, and even more preferably from 6V to 12V, for example from 8V to 10V. The voltage is selected according to the doping level of the different layers so as to obtain the desired selectivity. For example, its application time varies from a few seconds to a few hours. When there is no further current under the applied potential, the porosification is completed. At this point, the entire doped structure is porosified and the electrochemical reaction stops.

[0173] For example, the porosification step is performed by applying a voltage of 9 V (non-pulsed) in an oxalic acid solution. The stop of the process is controlled by the current drop.

[0174] The electrochemical anodization step may be performed under ultraviolet (UV) light.

[0175] Advantageously, the porosification occurs throughout the volume of the third layer 123 of heavily doped GaN.

[0176] According to another advantageous embodiment, only a portion of the volume of the third layer 123 of heavily doped GaN is porosified. The porosification step may be stopped before the third layer 123 of heavily doped GaN is fully porosified. For example, a conductive channel may be left in the center of the mesa.

[0177] At the end of the porosification step, the porosity of the third heavily doped GaN layer 123 is advantageously at least 10%. It preferably ranges from 25% to 70%, more preferably from 25% to 50%, for example from 45% to 50%.

[0178] The maximum dimension (height) of the pores may vary from a few nanometers to a few micrometers. The minimum dimension (diameter) may vary from a few nanometers to a few hundred nanometers, in particular from 30 nm to 70 nm.

[0179] The porosity (porosity and pore size) obtained depends on the doping of the layers and on the parameters of the process (applied voltage, duration, nature and concentration of the electrolyte, chemical post-treatment or annealing). Porosity variations make it possible to control the incorporation / segregation rate. When epitaxy is resumed, the porosity (and in particular the pore size) may subsequently vary depending on the applied temperature.

[0180] Therefore, whether it is for a small or medium size substrate or for a large size substrate, the mesa 120 of the same plate is porous.

[0181] The underside of the countertop is intact.

[0182] The obtained structure is Figure 3B and Figure 4 shown.

[0183] The method may comprise a step iii) during which the electrically conductive wire and the electrically insulating element are removed ( Figure 3C ).

[0184] Advantageously, when the conductive lines are made of metal or conductive polymer, they are removed. This prevents any contamination during subsequent further epitaxy.

[0185] According to an advantageous alternative embodiment, these lines are made of doped GaN and remain. The insulating element can be retained or removed. The presence of the conducting lines is particularly advantageous in the case of large-format type structures. They can advantageously play a role in the final device, for example in the operation of large displays. In fact, this makes it possible to avoid any potential losses between the edge and the center and to have a uniform contact layer over the entire surface of the structure.

[0186] Advantageously, the method comprises a subsequent step iv) during which epitaxy is performed on the mesa 120 so as to obtain an at least partially relaxed, and preferably fully relaxed, epitaxial layer.

[0187] The relaxation rate corresponds to:

[0188] Δa / a =(a c2 -a c1 ) / a c1

[0189] where a c1 represents the grid parameters of the initial layer on which epitaxy is resumed (i.e., the grid parameters of layer 124), and

[0190] a c2 represents the mesh parameters of the relaxation layer,

[0191] If a c2 Corresponding to the grid parameters of a solid material having the same composition as the re-epitaxially grown layer, the layer is 100% relaxed.

[0192] when a c1 =a c2 , the layer is said to be stressed.

[0193] Partial relaxation refers to a relaxation rate greater than 50%.

[0194] For example, re-epitaxy can be used to form a re-epitaxially grown LED.

[0195] Re-epitaxy is performed on the fourth nid or lightly doped (Al, In, Ga) N / (Al, In, Ga) N layer 124 of the mesa 120. Since this layer is not porosified during the electrochemical anodization step, it remains continuous and dense. Thus, re-epitaxy is facilitated and the epitaxial layer has an improved durability. Defects due to pore agglomeration are avoided.

[0196] Advantageously, the layer epitaxially grown during this step iv) is made of gallium nitride or indium gallium nitride.

[0197] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will discover other variations.

[0198] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A method for porosification of a structure (100), the structure (100) comprising a base substrate (110) covered with an (Al, In, Ga) N / (Al, In, Ga) N mesa (120), the method comprising a porosification step, during which the (Al, In, Ga) N / (Al, In, Ga) N mesa is electrochemically porosified, in, During the porosification step, an electrically conductive line (200) covered with an electrically insulating element (300) is arranged on the base substrate (110) between the mesas (120) or between groups of the mesas (120).

2. The method according to claim 1, wherein: The base substrate (110) comprises a support layer (114), a first non-doped GaN layer (111), and a second doped GaN layer (112). The (Al, In, Ga) N / (Al, In, Ga) N mesa (120) comprises a third heavily doped (Al, In, Ga) N layer (123) and a fourth non-doped or lightly doped (Al, In, Ga) N layer (124); A portion (112b) of the second doped GaN layer (112) extends in the mesa (120); During the porosification stage, the conductive wire (200) is in direct contact with the second doped GaN layer (112); The third heavily doped (Al, In, Ga) N layer (123) is porosified during the porosification step.

3. The method according to any one of claims 1 and 2, wherein: The conductive wire (200) is made of metal, preferably titanium, or a conductive polymer.

4. The method according to any one of claims 1 and 2, wherein: The conductive wire (200) is made of heavily doped GaN.

5. The method according to the preceding claim, wherein: The method comprises a step during which the conductive line (200) is formed by epitaxy.

6. A method according to any one of the preceding claims, wherein: The conductive wires (200) form a grid.

7. A method according to any one of the preceding claims, wherein: The conductive line (200) partially covers the base substrate (110), and wherein the space between the conductive line (200) and the mesa (120) is in the range from 100 nm to 1 μm, preferably in the range from 200 nm to 500 nm.

8. A structure (100) comprising a base substrate (110) covered with a porous (Al, In, Ga) N / (Al, In, Ga) N mesa (120), The structure (100) further comprises a conductive line (200) which is covered with an electrical insulating element (300) and is arranged on the base substrate (110) between the mesas (120) or between groups of the mesas (120).

9. The structure (100) according to claim 8, wherein: The base substrate (110) comprises a support layer (114), a first non-doped GaN layer (111) and a second doped GaN layer (112); The (Al, In, Ga) N / (Al, In, Ga) N mesa (120) comprises a third heavily doped porous GaN layer (123) and a fourth non-doped or lightly doped (Al, In, Ga) N layer (124); A portion (112a) of the second doped GaN layer (112) extends in the mesa (120).

10. The structure according to any one of claims 8 and 9, wherein: The conductive wire (200) is made of heavily doped GaN, metal or conductive polymer.

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