Method for repairing P-type GaN dry etching damage

Abstract

The invention discloses a method for repairing P-type GaN dry etching damage, which is characterized by comprising the following steps of: providing a substrate for epitaxial growth; forming an epitaxial structure on the substrate, wherein the epitaxial structure comprises a P-type GaN layer and an N-type GaN layer; performing dry etching on the epitaxial structure until the P-type GaN layer is exposed; removing the P-type GaN layer with a specific depth; and the P type GaN is activated. According to the method, the P-type GaN layer is etched by using an etching program with low direct-current bias voltage until the P-type GaN layer is exposed, a surface damage layer of the P-type GaN layer is removed by using a non-damage or micro-damage mode, and then the activation effect can be achieved by high-temperature annealing, so that the aim of repairing the P-type GaN dry etching damage is finally achieved, and the preparation of a semiconductor device with a novel structure is promoted.

Description

Technical Field

[0001] The invention relates to the field of semiconductor optoelectronic technology, and in particular to a method for repairing P-type GaN dry etching damage. Background Art

[0002] Traditional P-type GaN is usually grown on the outermost layer due to its susceptibility to etching damage and the need for activation. However, with the vigorous development of semiconductor display technology and the increasingly complex structure of third-generation semiconductor devices, P-type GaN often appears in the inner layer. At this time, it is necessary to expose the P-type GaN through etching.

[0003] In order to achieve multi-primary color lighting or three-color full-color Micro LED, higher efficiency GaN-based yellow and red light are required. In the conventional Ga-polarity sequentially grown N-down LED structure, from bottom to top, there are substrate, Ga-polarity N-type GaN, InGaN / GaN multiple quantum wells and P-type GaN. When the InGaN / GaN quantum well has a strong polarization electric field due to lattice mismatch, it will cause the energy band of the quantum well to bend, and the overlap of electron and hole wave functions will be reduced, affecting its luminous efficiency. This effect is called the quantum confined Stark effect (QCSE). In order to overcome the adverse effects of QCSE in the quantum well, the Ga-polarity sequentially grown P-down LED structure, that is, from bottom to top, there are substrate, Ga-polarity P-type GaN, InGaN / GaN multiple quantum wells and N-type GaN. The P-down LED structure can increase the height of the well and barrier difference, reduce the leakage of electrons and holes, and promote the recombination of electrons and holes. At the same time, the barrier for carrier injection into the well is reduced, resulting in a reduction in the turn-on voltage, thereby improving the luminous efficiency. However, when preparing a P-down LED with a same-side structure, the surface of the P-type GaN will be etched during the mesa etching, making it difficult to form a P-type ohmic contact.

[0004] In the full-color solution of Micro-LED, epitaxial stacking or chip stacking can avoid massive transfer. And compared with the traditional RGB three-color layout, the stacking solution can achieve higher pixel density integration. In the epitaxial stacking solution, the chip process needs to electrically connect the different layers of P-type GaN, InGaN / GaN multiple quantum wells and N-type GaN respectively. When preparing the P electrode, it is necessary to expose the P-type GaN and N-type GaN corresponding to the three colors of R, G, and B in the stacked structure by etching, which will inevitably cause etching damage to the P-type GaN, forming a large number of nitrogen vacancies on the surface of the P-type GaN, and unable to form a P-type ohmic contact, which increases the operating voltage.

[0005] Not only limited to the LED field, with the development of GaN third-generation semiconductors, various GaN-based semiconductor devices have come to the fore, and there is an increasing need for a method to repair P-type GaN dry etching damage. Summary of the invention

[0006] In view of the problems existing in the above-mentioned prior art, the purpose of the present invention is to provide a method for repairing P-type GaN dry etching damage. Compared with the traditional high-temperature repair technology, the present invention reduces the impact of etching damage on P-type GaN, and combines with the repair technology to realize a method for repairing P-type GaN dry etching damage.

[0007] The object of the present invention is achieved by: a method for repairing P-type GaN dry etching damage, characterized in that it comprises the following steps: S1. providing a substrate for epitaxial growth; S2, forming an epitaxial structure on the substrate, wherein the epitaxial structure includes a P-type GaN layer and an N-type GaN layer; S3, dry etching the epitaxial structure until the P-type GaN layer is exposed; S4, removing the P-type GaN layer at a specific depth; S5. Activate the P-type GaN layer.

[0008] Preferably, between the steps S4 and S5, the method further includes: preparing a second P-type GaN layer on the surface of the P-type GaN layer; and step S5 is activating the P-type GaN layer and the second P-type GaN layer.

[0009] Preferably, the epitaxial structure has one or more inner P-type GaN layers; the upper layer and the lower layer of the inner P-type GaN layer are both heterogeneous structures.

[0010] Preferably, the dry etching is one or more combinations of inductively coupled plasma dry etching, electron cyclotron resonance plasma etching, and reactive ion etching; and the DC bias voltage of the dry etching is below 200 V.

[0011] Preferably, the specific depth is greater than 0 nm and less than 100 nm.

[0012] Preferably, the method for removing the P-type GaN layer is one or more combinations of wet etching, atomic layer etching (ALE), and digital etching.

[0013] Furthermore, the activation is performed by high temperature annealing at a temperature of 500°C to 900°C.

[0014] Preferably, the method for preparing the second P-type GaN layer is to grow the second P-type GaN layer by one or more combinations of metal organic chemical vapor deposition, molecular beam epitaxy, and hydrogen vapor phase epitaxy.

[0015] Preferably, the method for preparing the second P-type GaN layer is to first grow a whole layer of P-type GaN, and then etch the whole layer of P-type GaN to obtain the second P-type GaN layer.

[0016] Preferably, the thickness of the second P-type GaN layer is 0 nm to 300 nm.

[0017] The beneficial effects of the present invention are: using a low-power etching procedure to etch until the P-type GaN layer is exposed, removing the surface damage layer of the P-type GaN layer in a damage-free or micro-damage manner, and then annealing and activating, ultimately achieving the purpose of P-type GaN dry etching damage repair, thereby promoting the preparation of new structure semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of P-down GaN epitaxial layer.

[0019] Figure 2 Schematic diagram of P-down GaN mesa etching.

[0020] Figure 3 Schematic diagram of removing the P-type GaN damaged layer from P-down GaN.

[0021] Figure 4 Schematic diagram of P-down GaN regrowing a second P-type GaN.

[0022] Figure 5 Schematic diagram of etching the second P-type GaN from P-down GaN.

[0023] Figure 6 Schematic diagram of epitaxial three-color stacked GaN epitaxial layer.

[0024] Figure 7 Schematic diagram of the first mesa etching of epitaxial three-color stacked GaN.

[0025] Figure 8 Schematic diagram of the second mesa etching of epitaxial three-color stacked GaN.

[0026] Fig. 9 Schematic diagram of removing the P-type GaN damaged layer from the epitaxial three-color stacked GaN.

[0027] Fig.10 Schematic diagram of epitaxial three-color stacked GaN and re-growth of a second P-type GaN.

[0028] Fig.11 Schematic diagram of etching the second P-type GaN in the epitaxial three-color stacked GaN. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the implementation cases described below are only used to explain the invention and are not intended to limit the invention.

[0030] In the following, the terms "first", "second", etc. are used only for convenience of description and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0031] In order to facilitate the understanding of the technical solution, the technical terms involved in this application are explained below. Example 1

[0032] Combination Figure 1-5 This embodiment provides a method for repairing P-type GaN dry etching damage, comprising the following steps: Step S1, providing a substrate 14 for epitaxial growth; Step S2, forming an epitaxial structure on the substrate 14, wherein the epitaxial structure includes a P-type GaN layer 13 and an N-type GaN layer 11; Step S3, dry etching the epitaxial structure until the P-type GaN layer 13 is exposed; Step S4, removing the P-type GaN layer 13 at a specific depth; Step S5, preparing a second P-type GaN layer 16 on the surface of the P-type GaN layer 13; Step S6 , activating the P-type GaN 13 and the second P-type GaN layer 16 .

[0033] Specifically, Figure 1 As shown, a P-down epitaxial structure is prepared on a substrate 14, and the P-down epitaxial structure is N-type GaN layer 11, InGaN / GaN multi-quantum well layer 12 and P-type GaN layer 13 from top to bottom. Among them, the substrate 14 is a silicon substrate, the thickness of the N-type GaN layer 11 is 200 nm, the thickness of the InGaN / GaN multi-quantum well layer 12 is 100 nm, and the thickness of the P-type GaN layer 13 is 3000 nm.

[0034] Specifically, after a window is made on the surface of the N-type GaN layer 11 by using a standard photolithography process, an inductively coupled plasma dry etching (ICP) is used to perform mesa etching until the P-type GaN layer 13 is exposed. The structure after etching is as follows: Figure 2As shown. Dry etching can also use electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE) to complete mesa etching.

[0035] In this embodiment, inductively coupled plasma dry etching (ICP) uses Cl2 and BCl3 as etching gases, the etching rate is 24 nm / min, the DC bias is 53 V, and the low-power etching procedure has an etching time of about 800 s. Excessive plasma energy will cause deeper damage. The low DC bias etching procedure controls the DC bias voltage of the etching process to be below 200 V by reducing the RF source power. However, even if low-power etching is used, the P-type GaN layer 13 will still be thinned, and the P-type GaN layer 13 will be damaged and the damage has a certain depth. For the convenience of explanation, the etched P-type GaN 13 is divided into the upper P-type GaN damaged layer 131 and the lower P-type GaN undamaged layer 132.

[0036] Specifically, the purpose of removing the P-type GaN layer 13 at a specific depth is to remove the damaged P-type GaN layer 13, that is, it is necessary to remove the P-type GaN damaged layer 131. The specific depth is greater than 0 nm and less than 100 nm, and the specific value is set according to the process in step S3.

[0037] Preferably, wet etching (using KOH, NaOH, H3PO4, TMAH, etc.), atomic layer etching (ALE), digital etching or a combination of these methods can be used to remove the P-type GaN damaged layer 131. The above method can remove the surface damaged P-type GaN layer 13 without damage or with minimal damage. In this embodiment, the P-type GaN damaged layer 131 is treated with H3PO4 at 150°C for one minute and then cleaned. The structure after removing the P-type GaN damaged layer 131 is as follows: Figure 3 shown.

[0038] Specifically, a whole layer of P-type GaN 15 is grown on the surface of the epitaxial structure after step S4 by using metal organic chemical vapor deposition (MOCVD). The structure after the growth is as shown in FIG. Figure 4 After a window is made on the surface of the entire P-type GaN layer 15 by using a standard photolithography process, the regrown entire P-type GaN layer 15 is etched by inductively coupled plasma dry etching (ICP) until the P-type GaN undamaged layer 132 is reached, thereby obtaining a second P-type GaN layer 16 .

[0039] Since the dry etching in step S3 reduces the thickness of the P-type GaN layer 13, it is necessary to prepare a second P-type GaN layer 16 to supplement the thickness of the etched P-type GaN layer 13. The second P-type GaN layer 16 can be directly grown or the entire P-type GaN layer 15 is first grown and then etched to obtain the second P-type GaN layer 16. In this embodiment, the method of first growing and then etching is adopted.

[0040] Preferably, the growth temperature of the whole layer of P-type GaN 15 is 1100°C, the growth sources are TMGa and NH3, and the Mg doping concentration is 1E19 / cm 3 ~1E20 / cm 3 The thickness of the entire layer of P-type GaN 15 is between 0 nm and 300 nm. Molecular beam epitaxy (MBE) and hydrogen vapor phase epitaxy (HVPE) can also be used to grow the entire layer of P-type GaN 15.

[0041] Preferably, the entire layer of P-type GaN 15 is etched using Cl2 and BCl3 as etching gases, using a low-power etching program with an etching rate of 24 nm / min and a DC bias of 53 V, and etching for about 300 s. Electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE) can also be used to complete the etching of the entire layer of P-type GaN 15. The thickness of the second P-type GaN layer 16 is 100 nm.

[0042] Specifically, the P-type GaN undamaged layer 132 and the second P-GaN 16 are activated by high temperature annealing at 500°C to 900°C in N2 and O2 atmospheres. Unlike the traditional direct activation of the P-type GaN layer grown on the outermost layer, the inner P-type GaN layer must be etched to expose the inner P-type GaN layer to activate it, so that its surface is exposed to the N2 and O2 atmospheres for activation. Therefore, step S4 must be performed to remove the P-type GaN damaged layer 131, and annealing here can play an activation role.

[0043] Preferably, this embodiment uses an RTA rapid annealing furnace, in N2, O2 atmosphere, the temperature is raised to 550 ° C, and annealing is performed for 3 minutes. The P-GaN undamaged layer 132 and the second P-GaN layer 16 are activated. The P-down type P-type GaN mesa etching repair process is completed, and the completed structure is as follows Figure 5 shown. Example 2

[0044] Combination Figure 6-11 This embodiment provides a first method for repairing epitaxial three-color stacked P-type GaN etching damage, comprising the following steps: Step S1, providing a substrate 210 for epitaxial growth; Step S2, forming an epitaxial structure on the substrate 210, wherein the epitaxial structure includes an upper P-type GaN layer 21, a middle P-type GaN layer 24, a lower P-type GaN layer 27, an upper N-type GaN layer 23, a middle N-type GaN layer 26, and a lower N-type GaN layer 29; Step S3, dry etching the epitaxial structure until the middle P-type GaN layer 24 and the lower P-type GaN layer 27 are exposed; Step S4, removing the middle P-type GaN layer 24 and the lower P-type GaN layer 27 at a specific depth; Step S5, forming a second P-type GaN layer 212 on the surfaces of the upper, middle and lower P-type GaN layers; Step S6 , activating the upper P-type GaN layer 21 , the middle P-type GaN layer 24 , the lower P-type GaN layer 27 and the second P-type GaN layer 212 .

[0045] Specifically, Figure 6 As shown, a three-color stacked LED epitaxial structure is formed on a substrate 210, and the three-color stacked LED epitaxial structure is, from top to bottom, an upper P-type GaN 21, a red light InGaN / GaN multi-quantum well layer 22, an upper N-type GaN 23, a middle P-type GaN 24, a green light InGaN / GaN multi-quantum well layer 25, a middle N-type GaN 26, a lower P-type GaN 27, a blue light InGaN / GaN multi-quantum well layer 28, and a lower N-type GaN 29.

[0046] Preferably, the thickness of the upper P-type GaN 21, the middle P-type GaN 24 and the lower P-type GaN 27 is 50 nm. The thickness of the red light InGaN / GaN multi-quantum well layer 22, the green light InGaN / GaN multi-quantum well layer 25 and the blue light InGaN / GaN multi-quantum well layer 28 is 70 nm. The thickness of the upper N-type GaN 23, the middle N-type GaN 26 and the lower N-type GaN 29 is 340 nm.

[0047] Specifically, after a window is made on the surface of the upper P-type GaN 21 by using a standard photolithography process, an inductively coupled plasma dry etching (ICP) is used to perform table etching until the middle P-type GaN layer 24 is exposed. The structure after etching is as follows: Figure 7 Mesa etching can also be accomplished using electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE).

[0048] In this embodiment, Cl2 and N2 are used as etching gases when inductively coupled plasma dry etching (ICP) is used for mesa etching, the etching rate is 42 nm / min, the DC bias is 63 V, and the etching time is about 660 s. Excessive plasma energy will cause deeper damage. The etching procedure with low DC bias controls the DC bias voltage of the etching process below 200 V by reducing the power of the RF source. However, even if low-power etching is used, the middle-layer P-type GaN layer 24 will still be thinned, and the P-type GaN layer 24 will be damaged and the damage has a certain depth. For the convenience of explanation, the etched middle-layer P-type GaN layer 24 is divided into an upper middle-layer P-type GaN damaged layer 241 and a lower middle-layer P-type GaN undamaged layer 242.

[0049] Specifically, after a window is made on the surface of the middle P-type GaN layer 24 by using a standard photolithography process, the mesa is etched by using an inductively coupled plasma dry etching (ICP) method until the lower P-type GaN layer 27 is exposed. The structure after etching is as follows: Figure 8 Mesa etching can also be accomplished using electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE).

[0050] Preferably, Cl2 and N2 are used as etching gases, the etching rate is 42 nm / min, the DC bias voltage is 63 V, and the low-power etching process is used, and the etching time is about 660 s. As above, the etched lower P-type GaN layer 27 is divided into an upper lower P-type GaN damaged layer 271 and a lower lower P-type GaN undamaged layer 272.

[0051] Specifically, the middle P-type GaN layer 24 and the lower P-type GaN layer 27 are removed at a specific depth to remove the damaged middle P-type GaN layer 24 and the lower P-type GaN layer 27, namely, the middle P-type GaN damaged layer 241 and the lower P-type GaN damaged layer 271. The specific depth is greater than 0 nm and less than 100 nm, and the specific value is set according to the process in step S3.

[0052] Preferably, the middle P-type GaN damaged layer 241 and the lower P-type GaN damaged layer 271 can be removed by wet etching (using KOH, NaOH, H3PO4, TMAH, etc.), atomic layer etching (ALE), digital etching (Digital etching) or a combination of these. In this embodiment, the middle P-type GaN damaged layer 241 and the lower P-type GaN damaged layer 271 are treated with H3PO4 at 150°C for one minute and then cleaned. The structure after removal is as follows: Fig. 9 shown.

[0053] Specifically, a whole layer of P-type GaN 211 is grown on the surface of the epitaxial layer after step S4 by using metal organic chemical vapor deposition (MOCVD). The structure after the growth is as shown in FIG. Fig.10 After a window is made on the surface of the regrown whole layer of P-type GaN 211 by using a standard photolithography process, the regrown whole layer of P-type GaN 211 is etched by using inductively coupled plasma dry etching (ICP) to the surface of the middle layer of P-type GaN undamaged layer 242 and the lower layer of P-type GaN undamaged layer 272, to obtain a second P-type GaN 212, the specific structure of which is shown in FIG. Fig.11 shown.

[0054] The second P-type GaN layer 212 can be prepared by direct growth or by first growing a whole layer of P-type GaN 211 and then etching to obtain the second P-type GaN layer 212. In this embodiment, the method of first growing and then etching is adopted.

[0055] Preferably, the growth temperature for growing the entire layer of P-type GaN 211 is 1100°C, the growth sources are TMGa and NH3, and the Mg doping concentration is 1E19 / cm 3 ~1E20 / cm 3 The thickness of the entire P-type GaN layer 211 is 100 nm. Molecular beam epitaxy (MBE) and hydrogen vapor phase epitaxy (HVPE) can also be used to grow the entire P-type GaN layer.

[0056] Preferably, the entire layer of P-type GaN 211 is etched using Cl2 and N2 as etching gases, an etching rate of 42 nm / min, a low-power etching program with a DC bias of 63 V, and etching for about 150 s. Electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE) can also be used to etch the entire layer of P-type GaN 211 to obtain a second P-type GaN 212.

[0057] Specifically, the upper P-GaN layer 21, the middle P-type GaN undamaged layer 242, the lower P-type GaN undamaged layer 272 and the second P-type GaN 212 are activated by high temperature annealing at 500°C to 900°C in N2 and O2 atmospheres. Unlike the traditional direct activation of the P-type GaN layer grown on the outermost layer, the inner P-type GaN layer in the multi-layer heterostructure must be activated by etching to the inner P-type GaN layer so that its surface is exposed to the N2 and O2 atmospheres for activation. Step S4 removes the middle P-type GaN damaged layer 241 and the lower P-type GaN damaged layer 271, and annealing here can play a role in activation.

[0058] Preferably, this embodiment uses an RTA rapid annealing furnace, in N2, O2 atmosphere, the temperature is raised to 550°C, and annealing is performed for 3 minutes to activate the upper P-GaN layer 21, the middle P-type GaN undamaged layer 242, the lower P-type GaN undamaged layer 272 and the second P-type GaN 212.

[0059] The epitaxial three-color stacked P-type GaN etching damage repair process is completed. The completed structure is as follows Fig.11 shown. Example 3

[0060] Combination Figure 6-9 This embodiment provides a second method for repairing epitaxial three-color stacked P-type GaN etching damage, comprising the following steps: Step S1, providing a substrate 210 for epitaxial growth; Step S2, forming an epitaxial structure on the substrate 210, wherein the epitaxial structure includes an upper P-type GaN layer 21, a middle P-type GaN layer 24, a lower P-type GaN layer 27, an upper N-type GaN layer 23, a middle N-type GaN layer 26, and a lower N-type GaN layer 29; Step S3, dry etching the epitaxial structure until the middle P-type GaN layer 24 and the lower P-type GaN layer 27 are exposed; Step S4, removing the middle P-type GaN layer 24 and the lower P-type GaN layer 27 at a specific depth; Step S5 , activating the upper P-type GaN layer 21 , the middle P-type GaN layer 24 , and the lower P-type GaN layer 27 .

[0061] Specifically, Figure 6 As shown, a three-color stacked LED epitaxial structure is formed on a substrate 210, and the three-color stacked LED epitaxial structure is, from top to bottom, an upper P-type GaN 21, a red light InGaN / GaN multi-quantum well layer 22, an upper N-type GaN 23, a middle P-type GaN 24, a green light InGaN / GaN multi-quantum well layer 25, a middle N-type GaN 26, a lower P-type GaN 27, a blue light InGaN / GaN multi-quantum well layer 28, and a lower N-type GaN 29.

[0062] Preferably, the thickness of the upper P-type GaN 21, the middle P-type GaN 24 and the lower P-type GaN 27 is 50 nm. The thickness of the red light InGaN / GaN multi-quantum well layer 22, the green light InGaN / GaN multi-quantum well layer 25 and the blue light InGaN / GaN multi-quantum well layer 28 is 70 nm. The thickness of the upper N-type GaN 23, the middle N-type GaN 26 and the lower N-type GaN 29 is 340 nm.

[0063] Specifically, after a window is made on the surface of the upper P-type GaN 21 by using a standard photolithography process, an inductively coupled plasma dry etching (ICP) is used to perform table etching until the middle P-type GaN layer 24 is exposed. The structure after etching is as follows: Figure 7 Mesa etching can also be accomplished using electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE).

[0064] In this embodiment, when using inductively coupled plasma dry etching (ICP) for mesa etching, Cl2 and BCl3 are first used as etching gases, the etching rate is 102 nm / min, the DC bias is 129 V, and the low-power etching program has an etching time of about 213 s. Then Cl2 and BCl3 are used as etching gases, the etching rate is 2 nm / min~10 nm / min, and the DC bias is lower than 90V. The low-power etching program has an etching time of about 600 s~3000 s. Excessive plasma energy will cause deeper damage. The etching program with low DC bias reduces the power of the RF source and controls the DC bias voltage of the etching process to be below 200 V. However, even if low-power etching is used, the middle P-type GaN layer 24 will still be thinned, and the P-type GaN layer 24 will be damaged and the damage has a certain depth. For the convenience of description, the etched middle P-type GaN layer 24 is divided into an upper middle P-type GaN damaged layer 241 and a lower middle P-type GaN undamaged layer 242 .

[0065] Specifically, after a window is made on the surface of the middle P-type GaN layer 24 by using a standard photolithography process, the mesa is etched by using an inductively coupled plasma dry etching (ICP) method until the lower P-type GaN layer 27 is exposed. The structure after etching is as follows: Figure 8 Mesa etching can also be accomplished using electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE).

[0066] Preferably, Cl2 and BCl3 are used as etching gases, the etching rate is 102 nm / min, the DC bias is 129 V, and the low-power etching process is about 213 s. Then, Cl2 and BCl3 are used as etching gases, the etching rate is 2 nm / min~10 nm / min, the DC bias is lower than 90 V, and the low-power etching process is about 600 s~3000 s. As above, the etched lower P-type GaN layer 27 is divided into an upper lower P-type GaN damaged layer 271 and a lower lower P-type GaN undamaged layer 272.

[0067] Specifically, the middle P-type GaN layer 24 and the lower P-type GaN layer 27 are removed at a specific depth to remove the damaged middle P-type GaN layer 24 and the lower P-type GaN layer 27, namely, the middle P-type GaN damaged layer 241 and the lower P-type GaN damaged layer 271. The specific depth is greater than 0 nm and less than 100 nm, and the specific value is set according to the process in step S3.

[0068] Preferably, the middle P-type GaN damaged layer 241 and the lower P-type GaN damaged layer 271 can be removed by wet etching (using KOH, NaOH, H3PO4, TMAH, etc.), atomic layer etching (ALE), digital etching (Digital etching) or a combination of these. In this embodiment, the middle P-type GaN damaged layer 241 and the lower P-type GaN damaged layer 271 are treated with H3PO4 at 150°C for one minute and then cleaned. The structure after removal is as follows: Fig. 9 shown.

[0069] Specifically, the upper P-GaN layer 21, the middle P-type GaN undamaged layer 242 and the lower P-type GaN undamaged layer 272 are activated by high temperature annealing at 500°C to 900°C in N2 atmosphere. Unlike the traditional direct activation of the P-type GaN layer grown on the outermost layer, in order to activate the inner P-type GaN layer in the multi-layer heterostructure, it is necessary to etch to the inner P-type GaN layer so that its surface is exposed to the N2 atmosphere for activation. Step S4 removes the middle P-type GaN damaged layer 241 and the lower P-type GaN damaged layer 271, and annealing here can play a role in activation.

[0070] Preferably, this embodiment uses an RTA rapid annealing furnace, in a N2 atmosphere, to raise the temperature to 700°C to 900°C, and anneal for 10 min to 20 min to activate the upper P-GaN layer 21, the middle P-type GaN undamaged layer 242, and the lower P-type GaN undamaged layer 272.

[0071] The epitaxial three-color stacked P-type GaN etching damage repair process is completed. The completed structure is as follows Fig. 9 shown.

Claims

1. A method for repairing P-type GaN dry etching damage, characterized in that: The following steps are involved: S1. providing a substrate for epitaxial growth; S2, forming an epitaxial structure on the substrate, wherein the epitaxial structure includes a P-type GaN layer and an N-type GaN layer; S3, dry etching the epitaxial structure until the P-type GaN layer is exposed; S4, removing the P-type GaN layer at a specific depth; S5. Activate the P-type GaN layer.

2. The method for repairing P-type GaN dry etching damage according to claim 1, characterized in that: The step between step S4 and step S5 also includes: preparing a second P-type GaN layer on the surface of the P-type GaN layer; and step S5 is activating the P-type GaN layer and the second P-type GaN layer.

3. The method for repairing P-type GaN dry etching damage according to claim 1, characterized in that: The epitaxial structure has one or more inner P-type GaN layers; the upper layer and the lower layer of the inner P-type GaN layer are both heterogeneous structures.

4. The method for repairing P-type GaN dry etching damage according to claim 1, characterized in that: The dry etching is one or more combinations of inductively coupled plasma dry etching, electron cyclotron resonance plasma etching, and reactive ion etching; the DC bias voltage of the dry etching is below 200 V.

5. The method for repairing P-type GaN dry etching damage according to claim 1, characterized in that: The specific depth is greater than 0 nm and less than 100 nm.

6. The method for repairing P-type GaN dry etching damage according to claim 1, characterized in that: The method for removing the P-type GaN layer is one or more combinations of wet etching, atomic layer etching (ALE), and digital etching.

7. The method for low-damage etching of P-type GaN according to claim 1 or 2, characterized in that: The activation is performed by high temperature annealing at a temperature of 500°C to 900°C.

8. The method for repairing P-type GaN dry etching damage according to claim 2, characterized in that: The method for preparing the second P-type GaN layer is to grow the second P-type GaN layer by using one or more combinations of metal organic chemical vapor deposition, molecular beam epitaxy, and hydrogen vapor phase epitaxy.

9. The method for repairing P-type GaN dry etching damage according to claim 2, characterized in that: The method for preparing the second P-type GaN layer is to first grow a whole layer of P-type GaN, and then etch the whole layer of P-type GaN to obtain the second P-type GaN layer.

10. The method for repairing P-type GaN dry etching damage according to claim 8 or 9, characterized in that: The thickness of the second P-type GaN layer is 0 nm to 300 nm.

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