System and method for transferring memory mapping traffic between integrated circuit devices

Abstract

Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transfer memory mapping traffic between heterogeneous IC devices in a packetized, scalable, and configurable manner. The IC chip may include a functional circuit that exchanges memory mapping traffic with an off-chip device, an NoC that packetizes and depacketizes the memory mapping traffic and routes the packetized memory mapping traffic between the functional circuit and the off-chip device, and an NoC inter-chip bridge (NICE) circuit that interfaces between the NoC and the off-chip device through a C2C interconnect. The NICE circuitry may be configured in a full mode to map packetized memory mapping traffic to the C2C interconnect in a 1: 1 manner; and configured under compression to map the packetized memory mapping traffic to the C2C interconnect in a less than 1: 1 manner.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to communicating memory mapped traffic between integrated circuit devices. Background Art

[0002] A system on a chip (SoC) combines various subsystems in a single IC device. An SoC may include a packet-switched network-on-chip (NoC) to provide intra-chip communication between subsystems. Compared to multi-chip architectures, an SoC can provide several benefits.

[0003] The multi-chip architecture can be used for the replaceability and interchangeability of various subsystems and to separate the development cycles of various subsystems from each other. Separation may help to allow the mixing and matching of various subsystems of different types and versions.

[0004] Multi-chip architectures utilize various architectures for inter-chip or chip-to-chip (C2C) communications. Conventional C2C architectures are fixed or unchanging. Conventional C2C architectures are not configurable for communication between heterogeneous IC devices. Conventional C2C architectures handle memory mapped traffic in a restricted manner. Summary of the invention

[0005] Techniques for transmitting memory-mapped traffic between integrated circuit devices are described. One example is an integrated circuit (IC) chip that includes: functional circuits that exchange memory-mapped traffic with off-chip devices; network-on-chip (NoC) circuits that packetize and depacketize memory-mapped traffic received from and directed to the functional circuits and route the packetized memory-mapped traffic between the functional circuits and the off-chip devices; and NoC inter-chip bridge (NICB) circuits that interface between the NoC circuits and the off-chip devices to exchange packetized memory-mapped traffic with the off-chip devices over a chip-to-chip (C2C) interconnect.

[0006] Another example described herein is an IC device that includes: a functional circuit that sends memory-mapped data to and receives memory-mapped data from an off-chip device; a NoC circuit that provides the functional circuit with a virtual interface to other devices; and a NICB circuit that provides the NoC circuit with a virtual interface to the off-chip device.

[0007] Another example described herein is a method comprising: generating memory mapped traffic including memory access requests; packetizing the memory access requests; routing the packetized memory access requests through an on-chip packet switched communication network at a first transmission rate; and forwarding the packetized memory access requests from the on-chip packet switched communication network to an off-chip device in segments through a set of C2C interconnects at a second transmission rate; wherein the second transmission rate is equal to or greater than the first transmission rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to be able to understand in detail the manner in which the above features are described, a more specific description briefly summarized above may be obtained by reference to example implementations, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical example implementations and therefore should not be considered to limit the scope thereof.

[0009] Figure 1 is a block diagram of a system according to one embodiment.

[0010] Figure 2 is a block diagram of a portion of a system according to one embodiment.

[0011] Figure 3 is a block diagram of an on-chip network master unit (NMU) circuit according to one embodiment.

[0012] Figure 4 is a block diagram of a network-on-chip slave unit (NSU) circuit according to one embodiment.

[0013] Figure 5 is a block diagram of a portion of a chiplet according to one embodiment.

[0014] Figure 6 is a conceptual illustration of a network-on-chip inter-chip bridge (NICB) infrastructure according to one embodiment.

[0015] Figure 7 is a conceptual illustration of a framing inspection architecture for memory mapped traffic and streaming, according to one embodiment.

[0016] Figure 8 is a block diagram of an integrated circuit chip to illustrate features of a transmit NICB (TNICB) circuit according to one embodiment.

[0017] Fig. 9 According to an implementation scheme Figure 8 Another block diagram of an integrated circuit chip is provided to illustrate the features of the receive NICB (RNICB) circuit.

[0018] Fig.10is a conceptual illustration of a configurable virtual channel (VC) buffer and a VC start ID register in a first configuration according to one embodiment.

[0019] Fig.11 is a conceptual illustration of a configurable VC buffer and a VC start ID register in a second configuration according to one embodiment.

[0020] Fig.12 is a conceptual illustration of two VCs configured with unequal numbers of FIFO buffer entries according to one embodiment.

[0021] Fig.13 is an example Fig.12 A table of simplified read and write examples.

[0022] Fig.14 An example mapping between a write request (WR) and a streaming request according to one embodiment is illustrated.

[0023] Fig.15 A method of transferring memory mapped traffic to an off-chip device according to one embodiment is illustrated.

[0024] Fig.16 A method of receiving and processing memory mapped traffic from off-chip devices according to one embodiment is illustrated.

[0025] Fig.17 A table illustrating address decoder parameters according to one embodiment.

[0026] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples. DETAILED DESCRIPTION

[0027] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by similar reference numerals in all drawings. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended to be an exhaustive description of the features nor to limit the scope of the claims. In addition, the illustrated examples do not necessarily have all the aspects or advantages shown. The aspects or advantages described in conjunction with a particular example are not necessarily limited to that example, and may be practiced in any other example even if not so illustrated or so explicitly described.

[0028] Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transmit memory-mapped traffic between heterogeneous IC devices in a packetized, scalable, and configurable manner. The C2C interface architecture can act as a virtualized interface to off-chip devices. The C2C interface architecture can be configured as a plug-and-play architecture. Examples are provided below with reference to C2C communications between an anchor IC device or chip and one or more chiplets. However, the methods and systems disclosed herein are not limited to anchor / chiplet architectures.

[0029] Unless otherwise specified herein, the terms bandwidth, phit, and flit have the meanings provided below.

[0030] The network has a width w and a transfer rate f. The bandwidth (BW) of the network can be determined as BW = w*f. The amount of data transferred in a single cycle is called a physical unit or microblock. The width w of the network is also equal to the microblock size. The bandwidth of the network can also be defined in terms of microblocks / second.

[0031] Messages can be broken down into fixed-length physical segments called packets. Packets can be broken down into message flow control units or fragments. When messages are transmitted at the link level, a fragment is a unit of data. Inter-router transfers are built in terms of fragments. Switching technology is handled in terms of fragments.

[0032] Figure 1 is a block diagram of a system 100 according to one embodiment. The system 100 includes a first integrated circuit (IC) chip, illustrated here as anchor 102, connected to a plurality of heterogeneous IC chips, illustrated here as chiplets 104A-104C, through respective C2C interface circuits 118A, 118B, and 118C.

[0033] Anchor 102 may include, but is not limited to, a processor subsystem, a memory subsystem, and / or programmable / configurable circuits. Chiplets 104A-104C may include corresponding dedicated functional circuits, such as, but not limited to, an artificial intelligence engine (AIE) and / or memory.

[0034] exist Figure 1 , chiplet 104A includes functional circuitry 108 that sends and receives memory mapped traffic 110 to and from an off-chip device, illustrated here as anchor 102. Memory mapped traffic 110 may include memory write and / or memory read requests, which are collectively referred to herein as memory access requests.

[0035] For illustrative purposes, memory access requests are described below as originating at functional circuitry 108 and directed to functional circuitry 130 of anchor 102. Functional circuitry 130 may include, but is not limited to, a direct memory access (DMA) controller. The DMA controller may in turn access memory within anchor 102 and / or memory in chiplets 104B or 104C. In other embodiments, memory access requests may originate at anchor 102.

[0036] Memory mapped traffic 110 may be formatted according to the Advanced eXtensible Interface (AXI) on-chip communication bus protocol developed by ARM of Cambridge, England. Memory mapped traffic 110 may be formatted according to AXI3 or AXI4 memory mapping modes. However, memory mapped traffic 110 is not limited to the AXI protocol.

[0037] Chiplet 104A also includes a network-on-chip (NoC) circuit 112 that provides an on-chip packet-switched communication network. NoC circuit 112 may include one or more NoC packet switches (NPS). NoC circuit 112 may present a virtual interface to off-chip memory devices to functional circuits 108.

[0038] Anchor 102 , chiplet 104B, and chiplet 104C include respective NoC circuits 114 , 116 , and 118 to present a corresponding on-chip packet-switched communication network.

[0039] The on-chip packet-switched communication networks are independent of each other. In other words, each packet-switched communication network is local to a corresponding chip (anchor or chiplet) so that addressing of each NoC terminates within the corresponding IC chip. Addresses and other control structures (e.g., system management identifier (SMID) and / or destination identifier (DEST-ID)) for receiving transmissions may be regenerated at the corresponding C2C interface circuit, such as described in one or more examples herein.

[0040] C2C interface circuits 118A, 118B, and 118C interface between NoC circuitry 114 of anchor 102 and NoC circuitry of corresponding chiplets 104A-104C. C2C interface circuitry 118A includes NoC inter-chip bridge (NICB) circuitry 120, NICB circuitry 122, and interconnect 124. NICB circuitry 120 may provide NoC circuitry 112 with a virtual interface to anchor 102. NICB circuitry 122 may provide NoC circuitry 114 with a virtual interface to chiplet 104A.

[0041] The C2C interface circuits 118B and 118C may be similar or identical to the C2C interface circuit 118A.

[0042] Anchor 102, chiplets 104A, 104B, and / or 104C may include multiple sets of NICB circuits.

[0043] Figure 2 is a block diagram of a portion of a system 100 according to one embodiment.

[0044] exist Figure 2 In the example of , the NoC circuit 112 includes an NPS 202 , a NoC master unit (NMU) circuit 204 , and a NoC slave unit (NSU) circuit 206 .

[0045] NMU circuitry 204 interfaces between functional circuitry 108 and NPS 202 for memory access requests originating from functional circuitry 108. Among other tasks, NMU circuitry 204 packetizes memory access requests originating from functional circuitry 108 based on a NoC packet protocol (NPP) of NoC circuitry 112 and de-packetizes responses to the requests.

[0046] NSU circuitry 206 interfaces between functional circuitry 108 and NPS 202 for memory access requests originating from other devices, such as from anchor 102 or another chiplet. Among other tasks, NSU circuitry 206 depacketizes memory access requests originating from other devices and packets responses to the requests.

[0047] NoC circuitry 114 includes NPS 212, NMU circuitry 214, and NSU circuitry 216. NMU circuitry 214 interfaces between functional circuits 108 and NPS 212 for memory access requests originating from functional circuits 130. Among other tasks, NMU circuitry 214 groups memory access requests originating from functional circuits 130 based on the NPP of NoC circuitry 114.

[0048] NSU circuitry 216 interfaces between functional circuitry 130 and NPS 212 for memory access requests that originate off-chip, such as from chiplet 104A or another chiplet. Among other tasks, NSU circuitry 216 depacketizes memory access requests that originate off-chip.

[0049] In addition, Figure 2 1 , NICB circuit 120 includes receive NoC inter-chip bridge (RNICB) circuit 208 and transmit NoC inter-chip bridge (TNICB) circuit 210. NICB circuit 122 includes RNICB circuit 218 and TNICB circuit 220.

[0050] For a memory access request initiated at the functional circuit 108, the NMU circuit 204 groups the access request into j-bit microslices, the NPS 202 communicates the j-bit microslices to the TNICB circuit 210 via the interconnect 126, the TNICB circuit 210 communicates the content segments of the j-bit microslices to the RNICB circuit 218 via the interconnect 124, the RNICB circuit 218 combines the segments to recreate the j-bit microslices and forwards the j-bit microslices to the NoC circuit 114, where the NSU circuit 216 de-groups the memory access requests from the j-bit microslices, and the functional circuit 130 processes the memory access requests.

[0051] Functional circuit 130 may send responses to memory access requests to functional circuit 108 in a similar manner via NSU circuit 216 , NPS 212 , TNICB circuit 220 , RNICB circuit 208 , NPS 202 , and NMU circuit 204 .

[0052] NoC circuitry 112 may include one or more additional NPSs to provide an interface to the packet-switched communication network of NoC circuitry 112 for other functional circuitry of chiplet 104A.

[0053] The NoC circuit 114 may include one or more additional NPSs to provide an interface to the packet-switched communication network of the NoC circuit 114 for other functional circuits of the anchor 102 .

[0054] In one embodiment, the NoC circuit 112 and / or the NICB circuit 120 are provided as a pod of chiplets. The pod may be provided as code included in the manufacturing process or as a physical device. The pod may include an NMU, an NSU, and an NPS (e.g., a hybrid switch). In the NMU, address decoding may be established using a set of reduced remapping registers.

[0055] TNICB circuit 210 and / or TNICB circuit 220 may perform one or more of the following operations:

[0056] Flow control;

[0057] Signal mapping from the NPP to the interconnect 124; and

[0058] Error Correction Code (ECC) generation.

[0059] RNICB circuit 208 and / or RNICB circuit 218 may perform one or more of the following operations:

[0060] Flow control;

[0061] Signal mapping from interconnect 124 to NPP;

[0062] ECC checking and poison bit generation;

[0063] ECC generation for NPS (e.g., to comply with NoC requirements);

[0064] SMID remapping;

[0065] Address Translation

[0066] Destination ID generation;

[0067] Read interleaving and reordering; and

[0068] Write trace.

[0069] Figure 3 is a block diagram of NMU circuit 300 according to one embodiment. NMU circuit 204 and / or NMU circuit 214 may include one or more features of NMU circuit 300.

[0070] Figure 4 is a block diagram of NSU circuit 400 according to one embodiment. NSU circuit 206 and / or NSU circuit 216 may include one or more features of NSU circuit 400.

[0071] Figure 5 is a block diagram of a portion of a chiplet 104A according to one embodiment.

[0072] exist Figure 5 In the example of , interconnects 126 include a first set of j interconnects 502 that provide j-bit microslices from RNICB circuit 208 to NPS 550 of NoC circuit 112 .

[0073] Interconnect 126 also includes a second set of j interconnects 504 that provide j-bit microslices from NPS 552 of NoC circuit 112 to TNICB circuit 210 .

[0074] In addition, Figure 5 In the example of , interconnects 124 include a first set of interconnects 508 that provide transmissions to RNICB circuit 208 .

[0075] Interconnects 124 also include a second set of interconnects 512 that are routed from TNICB circuit 210 .

[0076] The remaining interconnects in interconnect 124 may be used by other NICB circuits (eg, NICB circuits 554, 556, and 558), such as for streaming data, or may not be used.

[0077] As a non-limiting example, in one embodiment:

[0078] Interconnect 502 may include approximately 288 interconnects to provide 288 bits of microchips from RNICB circuit 208 to NoC circuit 112;

[0079] Interconnect 504 includes approximately 288 interconnects to provide 288-bit microslices from NoC circuit 112 to RNICB circuit 208;

[0080] The interconnect 508 may include approximately 80 interconnects, of which 72 interconnects may be used to receive 288-bit flits in four 72-bit segments at the RNICB circuit 208; and

[0081] Interconnect 512 may include approximately 80 interconnects, of which 72 interconnects may be used to transfer the 288-bit flits from TNICB circuit 210 in four 72-bit segments.

[0082] The remaining interconnects 508 and 512 may be reserved for mapping, parity checking, and the like.

[0083] In one embodiment, NoC circuit and NICB circuit 120 communicate at a first transmission rate via interconnect 126, and NICB circuit 120 and NICB circuit 122 communicate at a second transmission rate via interconnect 124. The first transmission rate and the second transmission rate may be set such that the bandwidth of interconnect 126 measured over time is equal to the bandwidth of interconnect 124. For example, in Figure 5 In the example, TNICB circuit 210 may receive 288-bit flits from NoC circuit via 288 interconnects 502 at a first transmission rate of 1 GHz, and may transmit the 288-bit flits in four 72-bit segments via interconnects 508 at a second transmission rate of 4 GHz.

[0084] exist Figure 5 , interconnect 508 is illustrated as a pair of k-bit receive-side data words DW1 and DW2, designated here as 520 and 522, respectively. Similarly, interconnect 512 is illustrated as a pair of transmit-side data words DW1 and DW2, designated here as 524 and 526, respectively. With respect to the foregoing example, each data word may represent approximately 40 interconnects, of which 36 interconnects may be used to transmit memory-mapped data. The remaining interconnects may be used or reserved for mapping, parity checking, etc.

[0085] In addition, Figure 5 , NICB circuit 120 includes a protocol processing unit (PHU) 540 that includes receiver circuits 542 and 544 that respectively receive data words (DW) 520 and 522. PHU 540 also includes transmission circuits 546 and 548 that transmit DW 524 and 526, respectively.

[0086] exist Figure 5In the example of , NICB circuits 120, 554, 556, and 558 provide a total of 8 receive DWs and 8 transmit DWs. For example, at 256 bits per DW, NICB circuits 120, 554, 556, and 558 provide a bandwidth of 2 terabits per second (Tbps) in each direction. In another example, 16 DWs are provided in each direction, and the bandwidth in each direction is 16x256=4Tbps.

[0087] NICB signal mapping

[0088] The following references Figure 6 Describes NICB signal mapping.

[0089] Figure 6 606 and DW1 608. NICB infrastructure 600 includes virtual channels 610, arbiter circuitry 612, and NPP2DW circuitry 614 that maps NPP flits to DW0 606 and DW1 608.

[0090] In one embodiment, when the microchip 602 is mapped to DW0 606 and DW1 608, the signal mapping is 1:1 because all bits of the microchip 602 are directly mapped to DW0 606 and DW1 608 (e.g., the least significant bits (LSBs) to / from DWs 606 and 608). The signals may maintain their semantic definitions. The C2C protocol layer may use a subset of the signals internally, examples of which are provided in the following table.

[0091]

[0092]

[0093] When the flit 602 is mapped across the DWs 606 and 608, the circuits associated with the DWs 606 and 608 may operate in a lockstep mode. Arbitration may be performed for one of the DWs 606 and 608, and the payload may be carried by the other of the DWs 606 and 608.

[0094] On the receiving side, a framing check may be performed for alignment purposes. The framing check may be performed by the same circuitry that is also used for flow control streaming mode. Figure 7 An example is further provided.

[0095] The NICB circuit may use some bits (e.g., four bits) of DW0 606 or DW1, among other signals, to map virtual channel (VC) credits. VC credits may be transmitted over the C2C interconnect by piggybacking on adjacent (paired) DWs. This may be similar to streaming.

[0096] Figure 7 is a conceptual illustration of a framing check architecture 700 for memory mapped traffic and streaming according to one embodiment. In addition to conventional signals, the NICB circuit can use four bits of the DW to map VC credits. As with streaming, credits can be transferred to the other side by piggybacking on an adjacent (paired) DW.

[0097] Transmission side (TNICB)

[0098] Reference below Figure 8 Describe example TNICB features.

[0099] Figure 8 8 is a block diagram of an IC chip 800. The IC chip 800 may represent the anchor 102 or the chiplet 104A. The IC chip 800 includes a NICB circuit 802 that interfaces between a NoC circuit 804 and an off-chip device 801. The NICB circuit 802 includes an RNICB circuit 806 and a TNICB circuit 808.

[0100] TNICB circuit 808 includes VC buffers 810, which may operate as first-in, first-out (FIFO) buffers. Each VC buffer in VC buffers 810 may be associated with a corresponding transmit-side virtual channel (VC).

[0101] Flow control is achieved by sending per-VC credits 814 back to the NoC circuit 804 when there is a pop from a corresponding one of the VC buffers 810. The TNICB circuit 808 may be initialized with credits to match the corresponding RNICB FIFO size.

[0102] TNICB circuit 808 also includes arbiter circuit 812. When an incoming transfer is received from NoC circuit 804, arbiter circuit 812 performs a VC decode / arbitration operation to allocate the incoming transfer to one of the VC buffers 810 of the allocated VC. The arbitration may be similar to the deficit round robin process of NoC circuit 804. Other types of arbitration may also be employed, such as least recently used arbitration.

[0103] TNICB circuit 808 also includes mapping circuitry, illustrated here as NPP2DW circuit 816 , that performs signal mapping.

[0104] Receiving side (RNICB)

[0105] Reference below Fig. 9 Describe example RNICB features.

[0106] Fig. 9 is another block diagram of IC chip 800 illustrating example features of RNICB circuit 806 according to one embodiment.

[0107] RNICB circuit 806 includes VC buffers 910, which may operate as first-in, first-out (FIFO) buffers. Each VC buffer in VC buffers 910 may be associated with a corresponding receive-side VC.

[0108] RNICB circuit 806 also includes ECC check circuit 902 that generates poison bits 904 that indicate whether received data is corrupted.

[0109] RNICB circuit 806 also includes VC decoding circuit 906 that decodes VCs from transfers received from off-chip device 801 and loads the transfers into a corresponding one of VC buffers 910 .

[0110] The RNICB circuit 806 also includes an arbiter circuit 912, which may include a deficit round-robin arbiter circuit. The arbiter circuit 912 may receive additional input from a read-reorder buffer (RROB). In one embodiment, an RD request wins arbitration only if the RROB has room for at least one chop, and a WR request / data wins arbitration only if the WR buffer has room to hold at least one chop.

[0111] Address Mapping Translation and Destination ID Remapping

[0112] Address decoding

[0113] In one embodiment, incoming addresses are dynamically converted to outgoing addresses.

[0114] In one embodiment, the RNICB generates the destination ID and the SMID.

[0115] In one embodiment, RNICB may change the priority of a transaction.

[0116] In one embodiment, the RNICB includes a programmable address decoder. Fig.17 Table 1700 illustrates example address decoder parameters according to one embodiment.

[0117] The programmable registers of the RNICB may be similar to the remap registers of the NMU, but have different widths. An example implementation includes 32 remap registers of 64KB granularity, 32 remap registers of 1MB granularity, 16 remap registers of 64MB granularity, and 16 remap registers of 64MB granularity.

[0118] The address decoder may include a MASK register and an ADD register. The outgoing address may be calculated as follows:

[0119] If (address_hit_remap_register_X)Output_address=Input_address&MASK_X+ADD_X, where X represents the remap register hit by the input address.

[0120] SMID Mapping

[0121] In one embodiment, the NoC uses an SMID as a unique identifier for each master unit. Programmable registers can be used for SMID mappings (e.g., up to 64 SMID mappings or more). Each mapping can take an incoming SMID and map it to an outgoing SMID. If there is no matching ID, the incoming SMID can be used as the outgoing SMID as is.

[0122] Priority

[0123] The SMID lookup register may be used to set the priority bits (eg, AXPROT bits). If the SMID does not match the SMID of the (eg, 64) register, the priority (eg, AXPROT) bits may be maintained.

[0124] RD interleaving and RROB

[0125] The RNICB circuit 806 may support a read (RD) interleaved read-reorder buffer (RROB), such as described below.

[0126] In one embodiment, incoming DWs from off-chip devices 801 have an associated VC identifier (VC-ID). In one embodiment, RROB supports up to 8 RD VCs. Each VC may have a configurable register to set the maximum number of outstanding requests (e.g., in bytes). If the maximum number of outstanding requests is reached, NICB circuit 802 may suppress requests on the VC.

[0127] In one embodiment, a mapping is created to map incoming VCs to one of the read-reorder buffers (RROBs). For example, VC0, VC1, and VC2 may be mapped to RD_REQ. VC0, VC1, and VC2 may also be mapped to RD_RESP in the reverse direction (TNICB).

[0128] For requests occurring on VC0, NICB circuit 802 may eliminate the transaction, interleave if necessary, and store the RROB information in the RROB. On the response side, for responses occurring on VC0, the RROB is updated.

[0129] The entries in the RROB may include a key generated by concatenating identifiers received in the DW (e.g., VC-ID, SRC-ID, and TAG-ID) and a locally generated identifier (L-TAG-ID). The ordering of responses on a given concatenated identifier {VC-ID, SRC-ID, TAG-ID, L-TAG-ID} may be preserved. The NICB circuit 802 may use the {VC-ID, SRC-ID, TAG-ID} tuple similar to how the NMU uses identifiers.

[0130] In one embodiment, if (local_tag_id, VC, SRC-ID, TAG-ID) is occupied in the RROB, the NICB circuit 802 may add (local_tag_id, VC, SRC-ID, TAG-ID) to the candidates.

[0131] NICB circuitry 802 may arbitrate across the candidates, such as using NPS arbitration circuitry, and may send responses and update status (ie, accounting) over the C2C interface.

[0132] Write Tracking

[0133] The NICB circuit 802 may apply write tracking to multiple VCs. In one embodiment, the NICB circuit 802 applies tracking to up to 2 VCs. The NICB circuit 802 may apply write tracking in a manner similar to the write tracking applied by the NMU circuit.

[0134] The NICB circuit 802 may use the {SRC_ID,TAG_ID} tuple to index into the writer tracker. PROB may perform similarly.

[0135] RNIC Buffer

[0136] In one embodiment, VC buffers, such as VC buffer 910, have a fixed depth (i.e., a fixed number of entries) sufficient to cover the round trip delay. VC buffers 910 may each include, for example, approximately 25 FIFO entries. With 8 VCs, this corresponds to approximately 200 entries.

[0137] VC buffer 910 may include one or more optimizations, which may be implemented alone and / or in combination with each other.

[0138] In a first optimization, VC buffer 910 is implemented as a static random access memory (SRAM) cell.

[0139] In another optimization, a buffer pooling method is utilized to dynamically control the depth of each VC buffer in the VC buffer 910. The buffer pool allows for dynamic control of the allocation of VC to buffer entries. The buffer pool method can utilize a programmable register that specifies the next ID. In this way, each VC is assigned a virtual FIFO whose depth can be changed at runtime. This buffer pooling is referred to as dynamically configurable NICB buffering in this article.

[0140] In an additional optimization, another set of programmable registers can be used to dynamically specify the starting ID of each VC. This may help provide fine-grained redundancy (i.e., by moving pointers around). This may help bypass relatively independent FIFO entries rather than entire blocks of memory cells when one of the memory cells fails.

[0141] exist Fig. 9 In the embodiment, IC chip 800 includes a controller circuit that dynamically configures the RNICB buffer and dynamically specifies the start ID. Figures 10 to 13 Dynamically configurable RNICB buffers and dynamic assignment of start IDs are further described.

[0142] Fig.10 is a conceptual illustration of a configurable VC buffer and a VC start ID register in a first configuration according to one embodiment.

[0143] Fig.11 is a conceptual illustration of a configurable VC buffer and a VC start ID register in a second configuration according to one embodiment.

[0144] Fig.12 is a conceptual illustration of two VCs configured with unequal numbers of FIFO buffer entries according to one embodiment.

[0145] Fig.13 is an example Fig.12 Table 1300 of simplified RD and WR examples.

[0146] Fig.10 FIFO buffer entries 1002, next entry ID 1006, entry ID 1004, and VC start entry 1010 are illustrated. Each of FIFO buffer entries 1002 is associated with a corresponding one of entry IDs 1004 and a corresponding one of next entry IDs 1006.

[0147] The FIFO buffer entry 1002 holds the payload and may be implemented in SRAM. The next entry ID 1006 may be stored in a corresponding FIFO buffer entry 1002 or a register. The VC start entry 1010 may be stored in a corresponding register.

[0148] exist Fig.10 In the example of FIG. 1 , there are eight VC start entries 1010 , each of which is associated with a corresponding one of the eight VCs, denoted herein as VC0 to VC7 . Each of the VC start entries 1010 indicates a start entry ID of the corresponding VC.

[0149] In this example, VC0 starts at VC entry 0, VC1 starts at VC entry 5, and VC2 starts at VC entry 10. Therefore, VC0 includes 5 FIFO buffer entries, identified here as entry IDs 0, 1, 2, 3, and 4. VC1 also includes 5 FIFO buffer entries, identified here as entry IDs 5, 6, 7, 8, and 9.

[0150] The next entry ID 1006 is used as a pointer to the next available FIFO entry for the corresponding VC. The next entry ID 1006 essentially creates a circular linked list for each VC. For example, the next entry ID 1006 for VC0 cycles through entry IDs 0, 1, 2, 3, 4, and then back to 0. The next entry ID 1006 for VC1 cycles through entry IDs 5, 6, 7, 8, 9, and then back to 5.

[0151] Fig.10 The architecture of programmably allows reconfiguration of the VC buffer depth, as the next entry ID 1006 and VC start entry registers can be reprogrammed to increase or decrease the depth of the VC.

[0152] Fig.10 The architecture also allows the VC start entry 1010 to be changed without having to change the depth of any VC in the VC (i.e., maintaining the existing depth by changing the next entry ID). This may be helpful in bypassing a relatively small group or block of memory cells when a fault is detected within a block.

[0153] exist Fig.11 In, relative to Fig.10 , within VC start entry 1010, the VC start entry for VC1 changes from 5 to 4. The other VC start entries remain unchanged. In this example, VC0 now starts at VC entry 0, VC1 starts at VC entry 4, and VC2 starts at VC entry 10. VC0 now includes 4 FIFO buffer entries, identified here as entry IDs 0, 1, 2, and 3. This is better than Fig.10VC1 now contains six FIFO buffer entries, identified here as entry IDs 4, 5, 6, 7, 8, and 9. This is less than Fig.10 An additional entry is added to the VC0 and VC1. The next entry ID 1006 is updated accordingly.

[0154] exist Fig.12 In FIG. 1 , a first VC 1202, illustrated here as VC0, has two FIFO buffer entries 1204 and 1206, illustrated here as entries 0 and 1. A second VC 1208, illustrated here as VC1, has three FIFO buffer entries 1210, 1214, and 1216, illustrated here as entries 2, 3, and 4. The FIFO buffer entries of VC0 and VC1 are used in a round-robin manner, such as Fig.13 Examples of .

[0155] exist Fig.13 , all FIFO buffer entries are initially empty. As each WR / RD, RD and WR pointers (ie, RD next entry ID 1302 and WR next entry ID 1304) change as shown, a FULL / EMPTY signal is generated as shown.

[0156] Using the buffer pooling method disclosed herein, the NICB circuit can operate with fewer total buffer entries than an architecture using a fixed number of buffer entries. This is because, in a typical case, only a few VCs are active at any given time. By adjusting the VC buffers for a specific use case, buffer entries can be multiplexed across multiple VCs.

[0157] Streaming support

[0158] For streaming data, the RNICB circuit may support a mapping of an incoming identifier (e.g., TDEST-ID) to an outgoing destination identifier (destination ID). The NoC circuit may be configured or programmed to allow more than one destination ID to be routed to the TNICB circuit. Thus, each destination ID routed to the TNICB circuit may be mapped to a different destination ID in the RNICB circuit.

[0159] C2C / NICB compression mode

[0160] In one embodiment, the NICB circuitry operates in a compressed mode, where packetized memory-mapped traffic is mapped to interconnects 124 (eg, k interconnects 124) in a less than 1:1 manner.

[0161] In one embodiment, the NICB circuit is configurable in each of a plurality of modes. The NICB circuit may be configured in one of a plurality of selectable modes at startup. Example modes are described below with reference to the NICB circuit 120. However, the NICB circuit 120 is not limited to the following examples.

[0162] In a first mode, also referred to herein as a full mode or uncompressed mode, NICB circuitry 120 maps packetized memory-mapped traffic to interconnect 124 in a 1:1 fashion, such as described in the examples above. Figure 5 , NICB circuitry 120 maps packetized memory-mapped traffic to DWs 520 and 522 (ie, two sets of k interconnects 124).

[0163] In a second mode, also referred to herein as a compressed mode or high data word (DW) performance mode, NICB circuitry 120 maps packetized memory mapped traffic to fewer interconnects 124 than in the high performance mode (i.e., in a less than 1:1 manner). Figure 5 NICB circuitry 120 may map packetized memory-mapped traffic to DW 520 (i.e., a single set of k interconnects 124). Figure 5 In the example shown in FIG. 4 , the NICB circuit can pack 256-bit flits into 1 DW.

[0164] The NICB circuit 122 of the anchor 102 may be similar to the NICB configuration.

[0165] The compressed mode may provide efficient mapping of NPP traffic from interconnect 126 to interconnect 124 with relatively little added latency and computation.

[0166] Regarding the example above, Figure 5 In compressed mode:

[0167] RNICB circuit 208 may receive the 288-bit flits in eight 36-bit segments via DW 520;

[0168] and

[0169] The TNICB circuit 210 may transfer the 288-bit flits through the DW 524 in eight 36-bit segments.

[0170] As further described above, in one embodiment, NoC circuitry and NICB circuitry 120 communicate at a first transmission rate via interconnect 126, and NICB circuitry 120 and NICB circuitry 122 communicate at a second transmission rate via interconnect 124. The first transmission rate and the second transmission rate may be set such that the bandwidth of interconnect 126 measured over time is equal to the bandwidth of interconnect 124. For example, in Figure 5In the compressed mode, TNICB circuit 210 may receive 288-bit flits from NoC circuit via 288 interconnects 502 at a first transmission rate of 1 GHz, and may transmit the 288-bit flits in eight 36-bit segments via interconnects 508 at a second transmission rate of 8 GHz.

[0171] High performance mode may help maximize the performance of a single interface, perhaps at the expense of reduced aggregate bandwidth of the C2C interface, while high DW performance mode may help maximize DW utilization, perhaps at the expense of lower performance per memory-mapped interface.

[0172] Example mapping semantics are described below.

[0173] For a write request (WR REQ) initiated at the functional circuit 108, the TNICB circuit 210 may separate the WR REQ from the write data (WR DATA) and send the WR REQ and the WR DATA as separate flits.

[0174] For a WR REQ flitter, TNICB circuit 210 may save the TAG-ID of the write request to associate with the write response, calculate the ECC on the WR REQ flitter, and send the WR REQ flitter to RNICB circuit 218 via interconnect 124. Upon receiving the WR REQ flitter, RNICB circuit 218 stores the VC-ID and Tag-ID, and performs WR processing.

[0175] For the WR data flit, TNICB circuit 210 may calculate a strobe pulse (STRB) and ECC to be included with the WR data (eg, 256 bits) and send the WR data flit to RNICB circuit 218 via interconnect 124 .

[0176] In one embodiment, the TNICB circuit 210 attempts to encode the STRB into a predetermined number of bits (e.g., 10 bits, start-end). If the encoding is successful, the TNICB circuit 210 sends the encoded STRB, ECC, and WR data in a single WR data flit via the interconnect 124. If the encoding is unsuccessful (i.e., the STRB is encoded in more than the predetermined number of bits), the TNICB circuit 210 sends the encoded STRB, ECC, and WR data in multiple WR data flitlets with a flag included with at least the first WR data flit of the multiple WR data flitlets.

[0177] For example, the TNICB circuit 210 may set the VC-ID of the first WR data flit to a predetermined or reserved value to indicate that this is the first WR data flit of the plurality of WR data flit. The TNICB circuit 210 may include placing as many bits of WR data as possible that fit into the first WR data flit and placing the remaining bits of WR data in subsequent WR data flit.

[0178] At anchor 102, RNICB circuit 218 detects the predetermined or reserved VC-ID in the first WR data flit, stores the WR data of the first WR data flit, and waits for a subsequent WR data flit. When RNICB circuit 218 receives the subsequent WR data flit, RNICB circuit 218 concatenates the WR data flit, performs WR data processing, and forwards the concatenated WR data flit to NoC circuit 114 via interconnect 132.

[0179] For write requests involving streaming data in compressed mode (STRM data), the TNICB circuit 210 may attempt to encode the handshake signaling (e.g., TKEEP) into a predetermined number of bits (e.g., 6 bits). If unsuccessful, the TNICB circuit 210 may send the streaming data over the interconnect 124 in multiple microslices, such as described above for the WR data. The TNICB circuit 210 may, for example, set the VC-ID of the first streaming data microslice to a predetermined or reserved value to indicate that the current word is the first set of bits of streaming data (e.g., the first 288 bits), and provide the remaining bits of streaming data in subsequent streaming data microslices.

[0180] At anchor 102, RNICB circuit 218 detects a predetermined or reserved VC-ID in the first streaming data flit, stores data of the first streaming data flit, and waits for a subsequent streaming data flit. When RNICB circuit 218 receives the subsequent streaming data flit, RNICB circuit 218 concatenates the streaming data flit, performs STRM processing, and forwards the concatenated streaming data flit to NoC circuit 114 via interconnect 132.

[0181] TNICB circuitry 210 may remove one or more predetermined bits (e.g., DST and DST parity bits) from the streaming data flits, recalculate the ECC based on the remaining bits, and send the flits to RNICB circuitry 218 over interconnect 124 without an indication of the STRM traffic type. In this example, RNICB circuitry 218 uses the VC map to determine the STRM traffic type.

[0182] For STRM data, the C2C interface circuit 118A may support a predetermined number of handshake bits (eg, 4 bits of TDEST and 3 bits of TID).

[0183] TNICB circuit 210 may encode one or more handshake signals (e.g., VALID) into one or more VC numbers (e.g., VC numbers 9 to 14). This may help derive the STRM traffic type. In this example, RNICB circuit 218 may map the handshake signals back to the corresponding WR VC, such as Fig.14 exemplified.

[0184] Fig.14 An example mapping 1400 between WR 1402 and STRM 1406 is illustrated according to one embodiment. Fig.14 In the example of WR 1402, WR 1402 is configured on VCs 3 and 6. The corresponding VCs for STRM 1406 are 9 and 10, with 9 mapping back to 3 and 10 mapping back to 6.

[0185] When responding to a write request involving streaming data in compressed mode, TNICB circuit 220 may look up the source identifier (SRC ID) and recreate the DW flits. TNICB circuit 220 may send a write response (WRRESP) only for the last elimination. RNICB circuit 208 may send the flits to NoC circuit 112.

[0186] Read Request (RD REQ)

[0187] In one embodiment, for a read request (RD REQ) initiated at functional circuit 108, TNICB circuit 210 saves an incoming identifier (e.g., Tag-ID), such as by appending a source identifier (e.g., SRC-ID) and the least significant bits of the incoming identifier to calculate a local key, and stores the source identifier indexed by the incoming identifier. TNICB circuit 210 then creates a read request using the local key as a new tag ID, recalculates the ECC, and sends the microchip over interconnect 124.

[0188] At anchor 102, RNICB circuit 218 performs RD REQ processing.

[0189] TNICB circuit 220 receives a response microchip (e.g., an RD-RESP microchip) from functional circuit 130 via NoC circuit 114. In one embodiment, TNICB circuit 220 strips or removes the source identifier (e.g., SRC-ID) in the RD-RESP microchip, recalculates the ECC, and sends the microchip to chiplet 104A via interconnect 124.

[0190] At chiplet 104A, RNICB circuit 208 receives the RD-RESP microchip, uses the incoming identifier (e.g., TAG-ID) to recover the original Tag-ID and SRC-ID, updates the RD-RESP microchip, recalculates the ECC, and sends the RD-RESP microchip to the NoC circuit via interconnect 126.

[0191] Credit and validity

[0192] The NICB circuit may use the credit and valid signals to control the loading of the VC buffer. In one embodiment, only one credit signal is sent in a given cycle. In this example, the credit and valid signals may each be encoded into a predetermined number of dispatch bits (e.g., 4 dispatch bits each).

[0193] In compressed mode, the NICB circuit may map the flits types to the corresponding VCs. The NICB circuit may also send a WR request flits followed by all data flits corresponding to the WR REQ flits. In one embodiment, the NICB circuit does not perform interleaving within the VCs. In another embodiment, the NICB circuit performs interleaving within the VCs. In one embodiment, the NICB circuit also performs one or more of the foregoing features in full or uncompressed mode.

[0194] Additional example implementations of uncompressed / full mode and compressed mode are provided below.

[0195] In one embodiment, in full mode, a j-bit flit is mapped to 2 DWs (ie, 1:1 mapping). In compressed mode, a j-bit flit is mapped to one DW (ie, less than 1:1 mapping).

[0196] In one embodiment, in full mode, a WR flits occupies 2 DWs and data may accompany the WR in the same flits. In compressed mode, a WR request and WR data may be sent in consecutive flits.

[0197] In one embodiment, in full mode, valid bits (e.g., 8 bits) and credit bits (e.g., 8 bits) may be used for each flit. In compressed mode, the reference and credit bits may be encoded (e.g., as bits 1 to 15). In one embodiment, a valid value of 0 indicates "invalid" and a credit value of 0 indicates "no credit". VC-ID values ​​(e.g., VC-15) may be reserved to indicate a partial transfer. A set of VC-IDs (e.g., VC-IDs 9 to 14) may be reserved for STRM mapping.

[0198] In one embodiment, in full mode, the WR data STRB is not encoded. In compressed mode, the WR data STRB may be encoded (eg, encoded into 10 bits). If encoding is unsuccessful, the data flits may be sent in two consecutive flits.

[0199] In one embodiment, a STRM may combine one or more of the aforementioned features.

[0200] NICB-LITE

[0201] In one embodiment, the NICB circuit is configured as a "light" circuit (NICB-LITE) that utilizes a reduced number of VCs (e.g., 4 VCs compared to 8 VCs). The NICB circuit can be manufactured as a NICB-LITE circuit, or can be reconfigured between full VCs and a reduced number of VCs. In one embodiment, the NICB-LITE circuit operates only in compression mode. Alternatively, the NICB-LITE circuit can operate in full mode. The NICB-LITE circuit may include or utilize one or more features described above for compression mode and / or full mode. The NICB-LITE circuit may be useful for small chips / applications that do not necessarily require all VCs. In one embodiment, the NICB-LITE circuit utilizes a reduced size RROB (e.g., 16KB compared to 8KB).

[0202] Fig.15 A method 1500 of transferring memory mapped traffic to an off-chip device according to one embodiment is illustrated. The method 1500 is described below with reference to the chiplet 104A. However, the method 1500 is not limited to the example of the chiplet 104A.

[0203] At 1502 , the functional circuit 108 generates memory map traffic including a memory access request.

[0204] At 1504, the NMU circuit 204 groups the memory access requests.

[0205] At 1506 , the NPS 202 routes the packetized memory access request to the TNICB circuit 210 at the first transmission rate.

[0206] At 1508, TNICB circuitry 210 forwards the packetized memory access request from NPS 202 segment to anchor 102 over first set of interconnects 124 at a second transmission rate greater than the first transmission rate. TNICB circuitry 210 may utilize one or more features described in other examples herein.

[0207] At 1510, RNICB circuitry 208 receives responses in segments from anchor 102 over second set of interconnects 124 at a second transmission rate and combines the segments into flits. RNICB circuitry 208 may utilize one or more features described in other examples herein.

[0208] At 1512 , the NPS 202 routes the flits to the NMU circuit 204 at a first transmission rate.

[0209] At 1514, the NMU circuit 204 de-packetizes the flits.

[0210] At 1516, the functional circuit 108 processes the depacketized flits.

[0211] Fig.16 A method 1600 of receiving and processing memory mapped traffic from an off-chip device according to one embodiment is illustrated. The method 1600 is described below with reference to the anchor 102. However, the method 1600 is not limited to the example of the anchor 102.

[0212] At 1602, RNICB circuitry 218 receives packetized memory access requests from chiplet 104A segments over first set of interconnects 124 at a first transmission rate and combines the received segments into flits. RNICB circuitry 218 can utilize one or more features described in other examples herein.

[0213] At 1604 , the NPS 212 routes the flits to the NSU circuit 216 at a second transmission rate, wherein the first transmission rate is greater than the second transmission rate.

[0214] At 1606, the NSU circuit 216 depacketizes the flits and forwards the depacketized flits to the functional circuit 130 for processing.

[0215] At 1608 , the NSU circuit 216 packets the responses from the functional circuits 130 .

[0216] At 1610, NPS 212 routes the packetized response to TNICB circuit 220 at the second transmission rate.

[0217] At 1612, TNICB circuitry 220 forwards the packetized response segment to chiplet 104A over the second set of C2C interconnects at the first transmission rate. TNICB circuitry 220 can utilize one or more features described in other examples herein.

[0218] The above-described techniques may be expressed without limitation in the non-limiting examples provided below.

[0219] Embodiment 1: An integrated circuit (IC) chip, comprising: a functional circuit, the functional circuit being configured to exchange memory mapping traffic with an off-chip device; an on-chip network (NoC) circuit, the on-chip network circuit being configured to packetize and depacketize memory mapping traffic received from and directed to the functional circuit and to route the packetized memory mapping traffic between the functional circuit and the off-chip device; and a NoC inter-chip bridge (NICB) circuit, the NoC inter-chip bridge circuit being configured to interface between the NoC circuit and the off-chip device, including exchanging the packetized memory mapping traffic with the off-chip device via a chip-to-chip (C2C) interconnect.

[0220] Embodiment 2: The IC chip of Embodiment 1, wherein the NICB circuit is further configured to perform address mapping translation and destination identifier remapping based on a system management identifier (SMID) associated with the packetized memory mapped traffic.

[0221] Embodiment 3: An IC chip according to embodiment 1, wherein: the NoC circuit is also configured to route packetized memory access requests to the NICB circuit at a first transmission rate; and the NICB circuit is also configured to transmit the packetized memory access requests in 1:1 mapping segments through the C2C interconnect at a second transmission rate; wherein the second transmission rate is greater than the first transmission rate.

[0222] Embodiment 4: An IC chip according to embodiment 1, wherein: the NoC circuit is also configured to route packetized memory access requests to the NICB circuit at a first transmission rate; and the NICB circuit is also configured to transmit the packetized memory access at a second transmission rate through the C2C interconnect with a mapping segmentation less than 1:1; wherein the second transmission rate is greater than the first transmission rate.

[0223] Embodiment 5: An IC chip according to Embodiment 4, wherein the NICB circuit is further configured to: map the command portion of the packetized memory access request to a first micro-slice; map the data portion of the packetized memory access request to one or more additional micro-slices; and transmit the first micro-slice and the one or more additional micro-slices through the C2C interconnect segment at the second transmission rate.

[0224] Embodiment 6: An IC chip according to embodiment 5, wherein the packetized memory access request includes a write request and data, and wherein the NICB circuit is further configured to: place the write request in the first microchip; calculate an error code based on the first microchip; calculate a selection pulse based on the data; encode the selection pulse; place the data, the error code and the encoded selection pulse in the one or more additional microchips; and transmit the first microchip and the one or more additional microchips in segments through the C2C interconnect.

[0225] Embodiment 7: An IC chip according to Embodiment 6, wherein the NICB circuit is further configured to: if the length of the encoded select pulse is lower than a threshold, place the data, the error code and the encoded select pulse in a single additional microchip; and if the length of the encoded select pulse exceeds the threshold, place the data, the error code and the encoded select pulse across multiple additional microchips, and place a predetermined identifier in the first additional microchip among the additional microchips to indicate that the first additional microchip is one of the multiple additional microchips of the write request.

[0226] Embodiment 8: An IC chip according to embodiment 1, wherein the NICB is further configured to: receive a packetized memory access request from the NoC circuit; load the packetized memory access request in a first virtual channel buffer among a plurality of virtual channel (VC) buffers; map the contents of the first VC buffer to a first set of segments, and include an identifier in each segment of the first set of segments; and transmit the first set of segments to the off-chip device via the C2C interconnect.

[0227] Embodiment 9: An IC chip according to embodiment 8, wherein: the NICB circuit is also configured to receive a response to the memory access request from the off-chip device as a second group of segments, load the second group of segments into a second VC buffer in the VC buffer based on an identifier included in the segment of the second group of segments, concatenate the second group of segments into micro-slices, and forward the micro-slices to the NoC circuit; and the NoC circuit is also configured to route the micro-slices to the functional circuits and de-group the micro-slices.

[0228] Embodiment 10: According to the IC chip of embodiment 1, the NICB circuit is further configured to: receive the first microchip and the second microchip through the C2C interconnection; and concatenate the first microchip and the second microchip based on the determination that the first microchip includes a predetermined virtual channel identifier.

[0229] Embodiment 11: An IC chip according to embodiment 1, wherein the packetized memory access request includes a read request, and wherein the NICB circuit is further configured to: receive a response to the read request from the off-chip device segment; load the segment into a corresponding entry of a first virtual channel buffer in a plurality of virtual channel (VC) buffers based on an identifier included in the segment; reorder and concatenate the segments to provide micro-slices; and communicate the micro-slices to the NoC circuit.

[0230] Embodiment 12: An IC chip according to embodiment 1, wherein the NICB circuit is capable of being configured in each of a full mode and a compressed mode, and wherein: the NoC circuit is also configured to route packetized memory access requests to the NICB circuit at a first transmission rate; the NICB circuit is configured in the full mode so as to transmit the packetized memory access requests in first length segments with a 1:1 mapping through the C2C interconnect at a second transmission rate; the NICB circuit is configured in the compressed mode so as to transmit the packetized memory access in second length segments with a mapping less than 1:1 through the C2C interconnect at a third transmission rate.

[0231] Embodiment 13: An IC chip according to embodiment 12, wherein: the third transmission rate is greater than the second transmission rate; the second transmission rate is greater than the first transmission rate; and the first length is greater than the second length.

[0232] Embodiment 14: According to the IC chip of Embodiment 1, the IC chip further comprises: a controller circuit configured to dynamically configure a depth of each VC buffer of a plurality of VC buffers and a start position of the VC buffer.

[0233] Embodiment 15: An IC chip according to embodiment 1, wherein the NICB circuit is further configured to: map streaming data across a first microchip and a second microchip; include a predetermined identifier in the first microchip to indicate that the second microchip will follow closely; and transmit the first microchip and the second microchip to the off-chip device via the C2C interconnect.

[0234] Embodiment 16: According to the IC chip of embodiment 1, the NICB circuit is further configured to: receive a microchip through the C2C interconnect; and determine that the microchip is a streaming data microchip based on a virtual channel mapping encoded within the microchip.

[0235] Embodiment 17: An integrated circuit (IC) device, comprising: a functional circuit, the functional circuit being configured to send memory mapping data to an off-chip device and receive memory mapping data from an off-chip device; an on-chip network (NoC) circuit, the on-chip network circuit being configured to provide the functional circuit with a virtual interface to the off-chip device; and a NoC inter-chip bridge (NICB) circuit, the NoC inter-chip bridge circuit being configured to provide the NoC circuit with a virtual interface to the off-chip device.

[0236] Embodiment 18: A method, the method comprising: in an integrated circuit (IC) chip: generating memory mapping traffic including memory access requests; packetizing the memory access requests; routing the packetized memory access requests through an on-chip packet switching communication network at a first transmission rate; and forwarding the packetized memory access requests from the on-chip packet switching communication network to an off-chip device in segments through a set of chip-to-chip (C2C) interconnects at a second transmission rate; wherein the second transmission rate is greater than the first transmission rate.

[0237] Embodiment 19: The method of Embodiment 18, wherein the forwarding comprises performing address mapping translation and destination identifier remapping based on a system management identifier (SMID) associated with the packetized memory mapped traffic.

[0238] Embodiment 20: A method according to embodiment 18, wherein the forwarding comprises: mapping the content of the packetized memory access request to the C2C interconnect with a 1:1 mapping in full mode; or mapping the content of the packetized memory access request to the C2C interconnect with a mapping less than 1:1 in compression mode.

[0239] In the foregoing, reference is made to the embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to the specifically described embodiments. On the contrary, any combination of the described features and elements (whether or not involving different embodiments) is contemplated as implementing and practicing the contemplated embodiments. In addition, although the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit the scope of the present disclosure. Therefore, the foregoing aspects, features, embodiments and advantages are merely illustrative and are not considered to be elements or limitations of the appended claims unless expressly stated in the claims.

[0240] As will be appreciated by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Thus, various aspects may take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a "circuit," "module," or "system." Additionally, various aspects may take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0241] Any combination of one or more computer-readable media may be utilized. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or apparatus, or any suitable combination of the foregoing. More specific embodiments (not a complete list) of computer-readable storage media will include the following: an electrical connector having one or more wires, a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium is any tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device or apparatus.

[0242] A computer readable signal medium may include a propagated data signal having computer readable program code embodied therein (e.g., in baseband or as part of a carrier wave). Such a propagated signal may take any of a variety of forms, including but not limited to electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0243] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0244] The computer program code for performing operations for various aspects of the present disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Java, Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as "C" programming language or similar programming languages). The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or can be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0245] Aspects of the present disclosure are described below with reference to flowchart illustrations and / or block diagrams of the methods, devices (systems) and computer program products of the embodiments presented in the present disclosure. It should be understood that each frame of the flowchart illustration and / or block diagram and the combination of frames in the flowchart illustration and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that instructions executed by a processor of a computer or other programmable data processing device create components for implementing the functions / actions specified in one or more frames of a flowchart and / or block diagram.

[0246] These computer program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatus, or other device to function in a specific manner, so that the instructions stored in the computer-readable medium produce an article of manufacture including instructions for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0247] The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operating steps to be performed on the computer, other programmable apparatus, or other devices to produce a computer-implemented method, so that the instructions executed on the computer or other programmable apparatus provide a process for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0248] The flow chart and block diagram in the figure illustrate the possible concrete implementation architecture, functionality and operation of the system, method and computer program product according to various examples of the present invention.In this regard, each frame in the flow chart or block diagram may represent the module, segment or part of one or more executable instructions for realizing the specified logical function of the instruction.In some alternative implementations, the function pointed out in the frame may not occur in the order pointed out in the figure.For example, depending on the functionality involved, the two frames shown in succession can actually be performed substantially at the same time, or these frames can sometimes be performed in reverse order.It will also be noted that each frame in the block diagram and / or flow chart illustration and the combination of the frames in the block diagram and / or flow chart illustration can be realized by a system based on special hardware that performs a specified function or action or performs a combination of special hardware and computer instructions.

[0249] While the foregoing is directed to particular examples, other and further examples may be devised without departing from the basic scope of the invention, and the scope of the invention is determined by the following claims.

Claims

1. An integrated circuit (IC) chip, comprising: a functional circuit configured to exchange memory-mapped traffic with an off-chip device; a network-on-chip (NoC) circuit configured to packetize and depacketize memory-mapped traffic received from and directed to the functional circuits and to route the packetized memory-mapped traffic between the functional circuits and the off-chip devices; and A NoC inter-chip bridge (NICB) circuit is configured to interface between the NoC circuit and the off-chip device, including exchanging packetized memory mapped traffic with the off-chip device over a chip-to-chip (C2C) interconnect.

2. The IC chip according to claim 1, wherein the NICB circuit is further configured as: Address mapping translation and destination identifier remapping are performed based on a system management identifier (SMID) associated with the packetized memory mapped traffic.

3. The IC chip according to claim 1, wherein: The NoC circuitry is further configured to route packetized memory access requests to the NICB circuitry at a first transmission rate; and The NICB circuit is further configured to transmit the packetized memory access request in 1:1 mapping segments over the C2C interconnect at a second transmission rate; The second transmission rate is greater than the first transmission rate.

4. The IC chip according to claim 1, wherein: The NoC circuitry is further configured to route packetized memory access requests to the NICB circuitry at a first transmission rate; and The NICB circuit is further configured to transmit the packetized memory accesses at a second transmission rate over the C2C interconnect with less than 1:1 mapping segments; The second transmission rate is greater than the first transmission rate.

5. The IC chip according to claim 4, wherein the NICB circuit is further configured as: mapping a command portion of the packetized memory access request to a first flit; mapping a data portion of the packetized memory access request to one or more additional flits; and The first flits and the one or more additional flits are segmented and transmitted over the C2C interconnect at the second transmission rate.

6. The IC chip of claim 5, wherein the packetized memory access request comprises a write request and data, and wherein the NICB circuit is further configured to: placing the write request in the first microchip; calculating an error code based on the first microchip; calculating a strobe pulse based on the data; encoding the strobe pulse; placing the data, the error code, and the encoded strobe pulse in the one or more additional microchips; as well as The first flits and the one or more additional flits are segmented over the C2C interconnect.

7. The IC chip according to claim 1, wherein the NICB is further configured as: receiving a packetized memory access request from the NoC circuit; loading the packetized memory access request in a first virtual channel buffer of a plurality of virtual channel (VC) buffers; mapping the contents of the first VC buffer to a first set of segments and including an identifier within each segment of the first set of segments; and The first set of segments is transmitted to the off-chip device via the C2C interconnect.

8. The IC chip according to claim 7, wherein: The NICB circuitry is further configured to receive a response to the memory access request from the off-chip device as a second set of segments, load the second set of segments into a second one of the VC buffers based on an identifier included within the segment of the second set of segments, concatenate the second set of segments into a flits, and forward the flits to the NoC circuitry; and The NoC circuit is also configured to route the flits to the functional circuits and to depacketize the flits.

9. The IC chip according to claim 1, wherein the NICB circuit is further configured as: receiving a first microsheet and a second microsheet via the C2C interconnect; and The first and second flits are concatenated based on a determination that the first flite includes a predetermined virtual channel identifier.

10. The IC chip of claim 1, wherein the packetized memory access request comprises a read request, and wherein the NICB circuit is further configured to: receiving a response to the read request from the off-chip device segment; loading the segment in a corresponding entry of a first virtual channel (VC) buffer among a plurality of virtual channel buffers based on an identifier included within the segment; reordering and concatenating the segments to provide microchips; as well as The flits are communicated to the NoC circuit.

11. The IC chip of claim 1 , wherein the NICB circuit is configurable in each of a full mode and a compressed mode, and wherein: The NoC circuitry is further configured to route packetized memory access requests to the NICB circuitry at a first transmission rate; the NICB circuitry being configured in the full mode to transmit the packetized memory access requests in segments of a first length at a second transmission rate with a 1:1 mapping over the C2C interconnect; The NICB circuitry is configured in the compressed mode to transmit the packetized memory accesses in second length segments at a third transmission rate with less than 1:1 mapping over the C2C interconnect, wherein: The third transmission rate is greater than the second transmission rate; The second transmission rate is greater than the first transmission rate; and The first length is greater than the second length.

12. The IC chip according to claim 1, further comprising: A controller circuit is configured to dynamically configure a depth of each VC buffer of a plurality of VC buffers and a starting position of the VC buffer.

13. The IC chip according to claim 1, wherein the NICB circuit is further configured to: mapping streaming data across the first microslice and the second microslice; including a predetermined identifier in the first microflake to indicate that the second microflake will follow immediately thereafter; and The first microchip and the second microchip are transmitted to the off-chip device through the C2C interconnect.

14. The IC chip according to claim 1, wherein the NICB circuit is further configured to: receiving a microchip via the C2C interconnect; and The flit is determined to be a streaming data flit based on a virtual channel map encoded within the flit.

15. A method comprising: In an integrated circuit (IC) chip: generating memory map traffic including memory access requests; grouping the memory access requests; routing the packetized memory access requests through an on-chip packet-switched communications network at a first transmission rate; as well as forwarding the packetized memory access request from the on-chip packet-switched communication network segment to an off-chip device via a set of chip-to-chip (C2C) interconnects at a second transmission rate; The second transmission rate is greater than the first transmission rate.

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