Electronic device

Abstract

An electronic device according to an embodiment of the present invention comprises: a chip; a semiconductor substrate; a bump; an insulating film; and a metal film. The chip is provided with a semiconductor laser. The semiconductor substrate is provided with a drive circuit that drives the semiconductor laser. The bump connects a plurality of chip-side connection pads disposed on a main surface of the chip on a side opposite to the emission surface of the laser beam, and a plurality of substrate-side connection pads disposed on a main surface of the semiconductor substrate on a side opposite to the chip. The insulating film is provided on the same layer as the layer of the substrate-side connection pads, and insulates adjacent substrate-side connection pads from each other. The metal film is disposed on the insulating film.

Description

Technical Field

[0001] The present disclosure relates to an electronic device. Background Art

[0002] There is an electronic device including a semiconductor substrate and a chip, the semiconductor substrate being provided with a driving circuit for driving a semiconductor laser, the chip being stacked on the semiconductor substrate via bumps and being provided with a semiconductor laser, the electronic device emitting laser light from a main surface of the chip which is not opposite to the semiconductor substrate (for example, Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: JP 2022-519186 A Summary of the invention

[0006] Technical issues

[0007] However, in an electronic device that emits laser light from a main surface of a chip that is not opposed to a semiconductor substrate, if the laser light emitted from the chip is irregularly reflected by a lens provided on the chip and incident on a drive circuit, the operation of the drive circuit is adversely affected.

[0008] Therefore, the present disclosure proposes an electronic device capable of suppressing reflected light of laser light from being incident on a driving circuit.

[0009] Solution to the problem

[0010] An electronic device according to an embodiment includes a chip, a semiconductor substrate, a bump, an insulating film and a metal film. The chip is provided with a semiconductor laser. The semiconductor substrate is provided with a driving circuit for driving the semiconductor laser. The bumps are respectively connected to a plurality of chip-side connection pads arranged on the main surface of the chip opposite to the laser emission surface and a plurality of substrate-side connection pads arranged on the main surface of the semiconductor substrate on the side opposite to the chip. The insulating film is provided in the same layer as the substrate-side connection pads and insulates adjacent substrate-side connection pads. A metal film is provided on the insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is an explanatory cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0012] Figure 2 is an illustrative cross-sectional view taken along line AA of the electronic device according to an embodiment of the present disclosure.

[0013] Figure 3 are explanatory views showing a manufacturing process of a semiconductor substrate according to an embodiment of the present disclosure.

[0014] Figure 4 are explanatory views showing a manufacturing process of a semiconductor substrate according to an embodiment of the present disclosure.

[0015] Figure 5 are explanatory views showing a manufacturing process of a semiconductor substrate according to an embodiment of the present disclosure.

[0016] Figure 6 are explanatory views showing a manufacturing process of a semiconductor substrate according to an embodiment of the present disclosure.

[0017] Figure 7 are explanatory views showing a manufacturing process of a semiconductor substrate according to an embodiment of the present disclosure.

[0018] Figure 8 are explanatory views showing a manufacturing process of a semiconductor substrate according to an embodiment of the present disclosure.

[0019] Fig. 9 are explanatory views showing a manufacturing process of a semiconductor substrate according to an embodiment of the present disclosure.

[0020] Fig.10 are explanatory views showing a manufacturing process of a semiconductor substrate according to an embodiment of the present disclosure.

[0021] Fig.11 2 is an explanatory diagram showing a manufacturing process of a chip according to an embodiment of the present disclosure.

[0022] Fig.12 2 is an explanatory diagram showing a manufacturing process of a chip according to an embodiment of the present disclosure.

[0023] Fig.13 2 is an explanatory diagram showing a manufacturing process of a chip according to an embodiment of the present disclosure.

[0024] Fig.14 2 is an explanatory diagram showing a manufacturing process of a chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, in each of the following embodiments, the same reference numerals and the same hatching are given to the same parts, and repeated description is omitted.

[0026] [1. Cross-sectional structure of electronic device]

[0027] Figure 1 is an explanatory cross-sectional view of an electronic device according to an embodiment of the present disclosure. Figure 2 is along Figure 1 An illustrative cross-sectional view taken along line AA shown in FIG. Figure 1 As shown, the electronic device 1 according to the present disclosure includes a chip 2 , a semiconductor substrate 3 , bumps 4 , an insulating film 33 , and metal films 34 and 35 .

[0028] The chip 2 includes a semiconductor laser in a base material 21 such as GaAs (gallium arsenide). The base material of the chip 2 is a semi-insulating base material such as InP (indium phosphide).

[0029] In addition, the chip 2 has a main surface (on the Figure 1 A plurality of chip side connection pads (hereinafter referred to as "connection pads 22") are provided on the lower surface of the semiconductor laser 4. Each connection pad 22 is connected to the light emitting element of the semiconductor laser. A metal film 23 is provided between each connection pad 22 and each bump 4. The metal film 23 is composed of, for example, gold (Au).

[0030] The semiconductor substrate 3 is composed of, for example, a Si (silicon) substrate 31. A driving circuit for driving a semiconductor laser is provided inside the Si substrate 31. The semiconductor substrate 3 has one main surface (on the Figure 1 A plurality of substrate-side connection pads (hereinafter referred to as "connection pads 32") are provided on the upper surface of the semiconductor substrate 3. The connection pads 32 are connected to the drive circuit inside the semiconductor substrate 3. Note that the electronic circuit included in the semiconductor substrate 3 may be any electronic circuit other than the drive circuit of the semiconductor laser.

[0031] The bumps 4 connect a plurality of connection pads 22 provided on the main surface of the chip 2 opposite to the emission surface of the laser light 11 and a plurality of connection pads 32 provided on the main surface of the semiconductor substrate 3 opposite to the chip 2 .

[0032] The bump 4 includes a porous metal layer 41 and a metal film 42 covering the side surface and the bottom surface of the porous metal layer 41. The porous metal layer 41 and the metal film 42 are made of, for example, gold (Au). Each insulating film 33 is provided in the same layer as the connection pad 32 and insulates the adjacent connection pads 32. The insulating film 33 is made of, for example, SiN (silicon nitride).

[0033] The electronic device 1 is connected to the other main surface of the chip 2 (on the Figure 1 The electronic device 1 includes a lens 10 disposed above the chip 2 to deflect and diverge the laser light 11 emitted from each light emitting element and emit the deflected and diverged laser light.

[0034] Therefore, in the electronic device 1, the laser light 11 emitted from the chip 2 may be irregularly reflected by the lens 10 and incident on the semiconductor substrate 3. If the laser light 11 is incident on the drive circuit provided inside the semiconductor substrate 3, the operation of the drive circuit is adversely affected. For example, if the reflected light of the laser light 11 is incident on the drive circuit from the outside, the current value flowing through the circuit may change, the output of the laser may change, the control may change, and a malfunction may occur.

[0035] Therefore, metal films 34 and 35 are provided on the insulating film 33 in the electronic device 1. The metal film 34 is composed of, for example, Ti (titanium). The metal film 34 is provided on the insulating film 33. The metal film 35 is composed of, for example, Au (gold). The metal film 35 is provided on the metal film 34.

[0036] Therefore, even if the reflected light of the laser light 11 passes through the chip 2 from, for example, the gaps between the connection pads 22 in the chip 2 , the electronic device 1 can suppress the reflected light of the laser light 11 from being incident on the drive circuit by the metal films 34 and 35 .

[0037] Furthermore, the metal films 34 and 35 disposed on the insulating film 33 are made of the same type of metal as the metal films 34 and 35 respectively disposed between the connection pad 32 and the bump 4 , and are disposed in the same layer as the metal films 34 and 35 respectively disposed between the connection pad 32 and the bump 4 .

[0038] Therefore, in the process of forming the metal films 34 and 35 provided between the connection pads 32 and the bumps 4, the metal films 34 and 35 provided on the insulating film 33 are simultaneously formed. Therefore, the metal films 34 and 35 provided on the insulating film 33 can be easily formed only by changing the pattern of the glass mask used to pattern the metal films 34 and 35 without adding a special manufacturing process.

[0039] Furthermore, in the metal films 34 and 35 provided between the connection pads 32 and the bumps 4, the area of ​​the surface parallel to the main surface of the semiconductor substrate 3 is larger than the area of ​​the cross section of the bumps 4 parallel to the main surface of the semiconductor substrate 3. Therefore, the metal films 34 and 35 provided between the connection pads 32 and the bumps 4 can prevent reflected light from being incident on the semiconductor substrate 3 from the side of the bumps 4.

[0040] Furthermore, the metal films 34 and 35 disposed on the insulating film 33 and the metal films 34 and 35 disposed between the connection pads 32 and the bumps 4 are separated by the slits. Therefore, the electronic device 1 can prevent short circuits between the connection pads 32 via the metal films 34 and 35.

[0041] In addition, the electronic device 1 has a side wall portion 5 that annularly surrounds a region where the plurality of protrusions 4 are provided. The side wall portion 5 connects the chip 2 and the semiconductor substrate 3. The side wall portion 5 includes a porous metal layer 51 and a metal film 52 that covers the bottom surface and side surfaces of the porous metal layer 51. The porous metal layer 51 and the metal film 52 are made of, for example, gold (Au).

[0042] Furthermore, the metal films 34 and 35 disposed on the insulating film 33 are made of the same type of metal as the metal films 34 and 35 respectively disposed between the side wall portion 5 and the semiconductor substrate 3 , and are respectively disposed in the same layer as the metal films 34 and 35 respectively disposed between the side wall portion 5 and the semiconductor substrate 3 .

[0043] Thus, in the process of forming the metal films 34 and 35 provided between the side wall portion 5 and the semiconductor substrate 3, the metal films 34 and 35 provided on the insulating film 33 are simultaneously formed. Therefore, the metal films 34 and 35 provided on the insulating film 33 can be easily formed by simply changing the pattern of the glass mask used to pattern the metal films 34 and 35 without adding a special manufacturing process.

[0044] In addition, in the metal films 34 and 35 provided between the side wall portion 5 and the semiconductor substrate 3, the area of ​​the surface parallel to the main surface of the semiconductor substrate 3 is larger than the area of ​​the cross section of the side wall portion 5 parallel to the main surface of the semiconductor substrate 3. Thus, by providing the metal films 34 and 35 between the side wall portion 5 and the semiconductor substrate 3, it is possible to prevent reflected light from being incident on the semiconductor substrate 3 from the side of the side wall portion 5.

[0045] In addition, the metal films 34 and 35 provided between the side wall portion 5 and the semiconductor substrate 3 are grounded. As a result, the electronic device 1 can discharge the charge accumulated in the parasitic capacitance generated by the metal films 34 and 35 provided between the side wall portion 5 and the semiconductor substrate 3 to the ground, and can reduce electromagnetic interference (EMI) noise.

[0046] In the electronic device 1, the chip 2 is flip-chip mounted on the semiconductor substrate 3, and the drive circuit in the semiconductor substrate 3 and the chip 2 including the semiconductor laser are electrically connected through the bumps 4. In addition, in the electronic device 1, the space where the connection pads 22 and 32 and the bumps 4 are provided is hermetically sealed by the side wall portion 5.

[0047] Here, for example, in the case of manufacturing an electronic device by flip-chip mounting a chip 2 including a semiconductor laser on a semiconductor substrate 3 including a driving circuit for the semiconductor laser, first, in a general manufacturing method, a plurality of driving circuits are formed on a Si wafer.

[0048] Thereafter, the chip 2 is stacked on the corresponding driving circuit via block metal bumps, and the connection pads 22 and 32 respectively provided on the opposite main surfaces of the driving circuit and the chip 2 are connected to each other by the bumps. Then, the Si wafer is cut into individual pieces for each electronic device.

[0049] In the process of dividing the Si wafer into individual pieces for each electronic device, the Si wafer is cut while supplying cutting water. At this time, the cutting water intrudes between the semiconductor substrate 3 and the chip 2, which may have an adverse effect on the electronic device. Therefore, each electronic device is usually sealed with a resin, and the Si wafer is divided into individual pieces for each electronic device.

[0050] However, in the case of sealing electronic devices with resin, there are problems such as contamination of electrodes by the resin, extension of operating time due to injection of the resin for each electronic device, and increase in the amount of resin discarded after use time due to the extension of the operating time.

[0051] Therefore, there is a technology in which the connection pads 22 and 32 respectively arranged on the relative main surfaces of the semiconductor substrate 3 and the chip 2 are connected using bumps, and the area where the connection pads 22 and 32 and the bumps are arranged and need to be sealed is joined and sealed using the same connection method as the connection between the connection pads 22 and 32.

[0052] In addition, in conventional flip-chip mounting, the chip 2 is mounted on the semiconductor substrate 3 by pressing metal bumps such as block Au (gold), Cu (copper), solder, etc., which are arranged on the relative main surfaces of the semiconductor substrate 3 or the chip 2, while heating the metal bumps.

[0053] However, when the thermal expansion coefficients of the semiconductor substrate 3 and the chip 2 differ by, for example, 0.1 ppm / ° C. or more, the following problem occurs when bulk Au, Cu, or solder is used as the material of the bump.

[0054] For example, when block Au is used as the material of the bump, in order to stably connect the semiconductor substrate 3 and the chip 2 having different thermal expansion coefficients using the bump, it is necessary to heat at a high temperature of 300°C or above and apply a high pressure of 100 MPa or above between the semiconductor substrate 3 and the chip 2.

[0055] In addition, when bulk Cu is used as a material for the bump, heating is required at or above 380° C. In this way, when bulk Au or Cu is used as a material for the bump, connection through the bump needs to be performed at high temperature and high pressure, and the high temperature and high pressure may damage the chip 2 and may reduce the reliability of the electronic device.

[0056] On the other hand, when solder is used as the material of the bump, connection through the bump can be performed at low temperature and low pressure compared to Au and Cu, but the heat resistance and connection strength of the solder are inferior to those of Au and Cu. Therefore, when the chip 2 thermally expands due to the heat of electronic components such as a semiconductor laser mounted on the chip 2, for example, a circuit breaker failure may occur due to the difference in thermal expansion coefficients between the semiconductor substrate 3 and the chip 2, and the bump composed of solder causes a decrease in the reliability of the electronic device.

[0057] Furthermore, as described above, the semiconductor substrate 3 according to the present disclosure is a Si substrate and has a thermal expansion coefficient of 5.7 ppm / ° C. On the other hand, the base material of the chip 2 according to the present disclosure is GaAs and has a thermal expansion coefficient of 2.6 ppm / ° C.

[0058] Thus, in the electronic device 1 , the difference in thermal expansion coefficient between the semiconductor substrate 3 and the chip 2 is much larger than 0.1 ppm / ° C. Therefore, in the electronic device 1 , when the material of the bump is bulk Au, Cu or solder, there is a possibility that the above problem occurs and reliability is reduced.

[0059] Furthermore, in the case where the peripheral portion of the region to be sealed between the semiconductor substrate 3 and the chip 2 is surrounded, bonded, and sealed by a bulk metal having a plated surface, when the difference in thermal expansion coefficient between the semiconductor substrate 3 and the chip 2 is, for example, 0.1 ppm / ° C. or more, cracks occur in the sealed portion. As a result, the airtightness of the electronic device deteriorates.

[0060] Furthermore, if the semiconductor substrate 3 or the chip 2 has thickness variations or warps, when the semiconductor substrate 3 and the chip 2 are stacked, the semiconductor substrate 3 and the chip 2 can be bonded only to the protrusions on the convex surface of the plating film of the sealing portion.

[0061] As a result, gaps are dispersed in the sealed portion, deteriorating the airtightness of the electronic device. In addition, in order to prevent the generation of gaps in the sealed portion, if the semiconductor substrate 3 and the chip 2 are bonded to increase the temperature and pressure, a short circuit failure may occur between adjacent micro bumps of the electronic device.

[0062] Therefore, the bump 4 of the electronic device 1 includes a porous metal layer 41 of, for example, Au. The porous metal layer 41 contains Au particles having a particle size of 0.005 μm to 1.0 μm and a purity of 99.9 wt % or more. It should be noted that, for example, the composition of the porous metal layer 41 may be Cu, Ag (silver), or Pt (platinum) having a purity of 99.9 wt % or more.

[0063] Due to the size effect of the particle size, the porous metal layer 41 containing metal particles having a particle size of 0.005 μm to 1.0 μm can perform metal bonding at a temperature lower than the melting point of the bulk metal. For example, when the components are Au, Ag, and Cu, the porous metal layer 41 can connect the semiconductor substrate 3 and the chip 2 at temperatures of approximately 100° C., 250° C., and 150° C., respectively. As a result, the electronic device 1 can reduce damage to the chip 2 caused by heat and can improve reliability.

[0064] In addition, the porous metal layer 41 has elasticity, so even if the chip 2 expands with a thermal expansion coefficient different from that of the semiconductor substrate 3 due to heat generation of the semiconductor laser, the porous metal layer 41 elastically deforms, thereby suppressing the occurrence of open circuit failure. Therefore, the electronic device 1 can improve reliability compared to the case of using bumps made of solder, for example.

[0065] The electronic device 1 is manufactured by stacking the chip 2 on the semiconductor substrate 3 having the bumps 4 on the upper surface and connecting the porous metal layer 41 of the bumps 4 to the connection pads 22 without melting, thereby flip-chip mounting the chip 2 on the semiconductor substrate 3 .

[0066] Furthermore, the electronic device 1 can be manufactured by stacking the chips 2 provided with the bumps 4 each including the porous metal layer 41 on the lower surface on the semiconductor substrate 3 and connecting the porous metal layer 41 of the bumps 4 to the connection pads 32 without melting to flip-chip mount the chips 2 on the semiconductor substrate 3. In addition, the bumps 4 including the porous metal layer 41 can also be provided on both the semiconductor substrate 3 and the chips 2 before lamination.

[0067] When provided on the semiconductor substrate 3 side, the raised portion 4 includes a metal film 42 between the porous metal layer 41 and the connection pad 32 on the semiconductor substrate 3 side. In addition, when provided on the chip 2 side, the bump 4 includes a metal film 42 between the porous metal layer 41 and the connection pad 22 on the chip 2 side. In addition, the metal film 42 may be provided on at least one of the porous metal layer 41 on the semiconductor substrate 3 side and the connection pad 32 or the porous metal layer 41 on the chip 2 side and the connection pad 22.

[0068] In the present disclosure, by setting the ratio of the film thickness of the metal film 42 to the thickness of the protrusion 4 in the direction orthogonal to the main surface of the semiconductor substrate 3 to less than 10%, a fine pitch in which the pitch of the protrusion 4 is 20 μm or less can be achieved.

[0069] Furthermore, the ridge 4 further includes a metal film 42 on the side surface (side peripheral surface) of the porous metal layer 41. The material of the metal film 42 is desirably the same as that of the porous metal layer 41. For example, when the material of the porous metal layer 41 is Au, the metal film 42 is desirably an Au film.

[0070] As a result, the ridge 4 can prevent the particles of the porous metal layer 41 from collapsing and scattering because the side surface of the porous metal layer 41 is coated with the metal film 42. Therefore, the bump 4 can prevent adjacent bumps 4 from short-circuiting due to scattering of the particles of the porous metal layer 41.

[0071] In addition, in the case where the metal film 42 is not provided on the side surface of the porous metal layer 41 , surface roughness is generated on the side surface of the porous metal layer 41 whose surface is relatively soft, so that the shape varies between the protrusions 4 .

[0072] On the other hand, since the metal film 42 which is harder than the porous metal layer 41 is provided on the side of the porous metal layer 41 of the protrusion 4, the unevenness of the shape of the protrusion 4 is suppressed, and the shape of all the protrusions 4 is uniform. In addition, since the side of the protrusion 4 is covered with the harder metal film 42, further miniaturization can be achieved, and a finer pitch can be achieved.

[0073] In addition, when the chip 2 is flip-chip mounted on the semiconductor substrate 3, the bump 4 is slightly crushed in the thickness direction, but the particles of the porous metal layer 41 are prevented from leaking to the outside of the metal film 42. As a result, in the raised portion 4, the particle density of the porous metal layer 41 in the metal film 42 is increased, so that the connection resistance can be reduced.

[0074] In addition, the side wall portion 5 of the electronic device 1 has the same structure as the ridge portion 4. Specifically, the side wall portion 5 includes a porous metal layer 51 of Au. The porous metal layer 51 contains Au particles having a particle size of 0.005 μm to 1.0 μm and a purity of 99.9 wt % or more. It should be noted that, for example, the component of the porous metal layer 51 may be Cu, Ag (silver), or Pt (platinum) having a purity of 99.9 wt % or more.

[0075] As described above, due to the size effect of the particle size, the porous metal layer 51 can be metal-bonded at a temperature lower than the melting point of the bulk metal. As a result, the electronic device 1 can reduce the thermal damage to the chip 2 when forming the porous metal layer 51, and can improve reliability.

[0076] In addition, the porous metal layer 51 has elasticity, and therefore, for example, even if the chip 2 expands with a thermal expansion coefficient different from that of the semiconductor substrate 3 due to heat generation of the semiconductor laser, it is elastically deformed, so that cracks can be suppressed from occurring in the side wall portion 5. As a result, the electronic device 1 can improve the airtightness of the region where the connection pads 22 and 32 and the bump 4 are provided and which needs to be sealed.

[0077] Furthermore, since the porous metal layer 51 elastically deforms, even if the semiconductor substrate 3 or chip 2 has thickness variations or warps, the porous metal layer 51 deforms to follow the surface shape of the semiconductor substrate 3 or chip 2 when the semiconductor substrate 3 and chip 2 are bonded.

[0078] As a result, in the electronic device 1 , it is possible to suppress the occurrence of gaps at the connection portions between the side wall portion 5 and the semiconductor substrate 3 and the connection portions between the side wall portion 5 and the chip 2 , thereby improving airtightness.

[0079] In addition, the side wall portion 5 is provided to annularly surround the area where the connection pads 22 and 32 and the protrusion 4 are provided and to be sealed. Thus, when the semiconductor substrate 3 or the chip 2 thermally expands, the electronic device 1 can relieve the mechanical stress applied to the protrusion 4 provided at the corner.

[0080] Specifically, when the semiconductor substrate 3 or chip 2 thermally expands, the amount of expansion and contraction due to temperature change increases from the center toward the periphery of the main surface of the semiconductor substrate 3 or chip 2. Therefore, unless the side wall portion 5 is provided, mechanical stress is applied to the protrusion 4 provided at the corner.

[0081] On the other hand, in the electronic device 1, since the peripheral portions of the semiconductor substrate 3 and the chip 2 are sealed by the side wall portion 5, the expansion and contraction of the peripheral portions of the semiconductor substrate 3 and the chip 2 caused by temperature changes can be suppressed by the side wall portion 5. Thus, the electronic device 1 can reduce the mechanical stress applied to the protrusion 4 provided at the corner.

[0082] When the sidewall portion 5 is provided on the semiconductor substrate 3 side, the sidewall portion 5 includes a metal film 52 between the porous metal layer 51 on the main surface of the semiconductor substrate 3 and the connection pad 32. In addition, when the sidewall portion 5 is provided on the chip 2 side, the sidewall portion 5 has the metal film 52 between the porous metal layer 51 and the connection pad on the main surface of the chip 2. In addition, the metal film 52 may be provided on at least one of the porous metal layer 51 on the main surface of the semiconductor substrate 3 and the connection pad 32 or the porous metal layer 51 on the main surface of the chip 2 and the connection pad.

[0083] In the present invention, by setting the ratio of the film thickness of the metal film 52 to the thickness of the side wall portion 5 in the direction orthogonal to the main surface of the semiconductor substrate 3 to less than 10%, a fine pitch of the protrusion 4 of less than 20 μm can be achieved during the simultaneous formation of the side wall portion 5 and the protrusion 4.

[0084] Furthermore, the side wall portion 5 also includes a metal film 52 on the side surface (side peripheral surface) of the porous metal layer 51. The material of the metal film 52 is desirably the same as that of the porous metal layer 51. For example, when the material of the porous metal layer 51 is Au, the metal film 52 is desirably an Au film.

[0085] As a result, the sidewall portion 5 can prevent the particles of the porous metal layer 51 from collapsing and scattering because the side surface of the porous metal layer 51 is coated with the metal film 52. Therefore, the sidewall portion 5 can prevent the adjacent bumps 4 from short-circuiting due to scattering of the particles of the porous metal layer 51.

[0086] In addition, when the metal film 52 is not provided on the side surface of the porous metal layer 51 , surface roughness is generated on the side surface of the relatively soft porous metal layer 51 , so that the side surface shape of the side wall portion 5 changes.

[0087] On the other hand, since the metal film 52 harder than the porous metal layer 51 is provided on the side surface of the porous metal layer 51 in the side wall portion 5, the variation of the side surface shape is suppressed, and all the side surfaces have a uniform surface shape. In addition, since the side surface of the side wall portion 5 is covered with the harder metal film 52, further miniaturization is possible.

[0088] The electronic device 1 is manufactured by stacking the chip 2 provided with no bumps 4 on the semiconductor substrate 3 provided with the bumps 4 and connecting the porous metal layer 41 of the bumps 4 to the connection pads 22 without melting to flip-chip mount the chip 2 on the semiconductor substrate 3 .

[0089] In addition, the electronic device 1 can be manufactured by stacking the chip 2 provided with the protrusion 4 on the semiconductor substrate 3 without the protrusion 4, connecting the porous metal layer 41 of the protrusion 4 to the connection pad 32 without melting to flip-chip mount the chip 2 on the semiconductor substrate 3, each protrusion 4 including the porous metal layer 41 on the lower surface. In addition, the bump 4 including the porous metal layer 41 can also be provided on both the semiconductor substrate 3 and the chip 2 before stacking.

[0090] [2. Process of forming the ridge and side wall]

[0091] Next, we will refer to Figures 3 to 14 A process of forming the electronic device 1 according to the present disclosure is described. Figures 3 to 102 is an explanatory diagram showing a manufacturing process of the semiconductor substrate 3 according to the present disclosure. Figures 11 to 14 2 is an explanatory diagram showing a manufacturing process of the chip 2 according to the present disclosure.

[0092] like Figure 3 As shown, in the case of manufacturing the semiconductor substrate 3, first, the connection pad 32 is formed at a predetermined position on the Si substrate 31, and the insulating film 33 is formed in a region other than the position where the connection pad 32 is formed on the Si substrate 31. Thereafter, the metal film 34 and the metal film 35 are sequentially laminated on the connection pad 32 and the insulating film 33.

[0093] Then, if Figure 4 As shown, the glass mask 61 is stacked on the metal film 35 , and portions of the glass mask 61 corresponding to positions other than regions where the metal films 34 and 35 are to remain are removed to form slits in the glass mask 61 .

[0094] Then, if Figure 5 As shown, for example, dry etching is performed through the remaining glass mask 61 to remove the metal films 34 and 35 in the portion where the glass mask 61 is not stacked thereon. Figure 6 As shown, the glass mask 61 is removed.

[0095] Then, if Figure 7 As shown, a photoresist layer 62 is formed on the metal films 34 and 35 , and then through holes are formed in the photoresist layer 62 at positions where the protrusions 4 and the sidewall portions 5 are formed by photolithography to expose the surfaces of the metal films 34 and 35 .

[0096] At this time, the through holes are formed in such a way that the interval between the centers of adjacent through holes is 20 μm (pitch 20 μm). In the subsequent process, such through holes are filled with a paste containing metal particles that become the material of the porous metal layer 41, but due to the fine structure with a pitch of 20 μm, if the through holes are filled with the paste in this state, there is a possibility that the fine structure will be damaged or broken.

[0097] Therefore, if Figure 8 As shown, metal films 42 and 52 are formed on the upper surface of the photoresist layer 62, the side surface of the through hole, and the upper surface of the metal film 35 by sputtering, for example. As the material of the metal films 42 and 52, a metal having the same metal particle composition as that contained in the paste that will later fill the through hole is selected. Note that Au metal films 42 and 52 are formed here.

[0098] As a result, the photoresist layer 62 is cured by coating the metal films 42 and 52 on the surface of the photoresist layer 62 , and thus it is possible to prevent the microstructure from collapsing when the through hole is filled with the paste containing metal particles.

[0099] In addition, if the thickness of the formed metal film 42, 52 is too thick, the opening of the through hole becomes narrow, and it is difficult to fill the paste containing metal particles. Therefore, here, the metal film 42, 52 is formed relatively thin (for example, the thickness is less than 1 μm) in such a way that the ratio of the film thickness of the metal film 42, 52 to the depth of the through hole, that is, the thickness of the protrusion 4 in the direction perpendicular to the main surface of the semiconductor substrate 3 (the height of the protrusion 4) described later is less than 10%.

[0100] For example, when forming ridges 4 with a height of 10 μm arranged at a pitch of 20 μm, the thickness of the metal films 42 and 52 is set to 0.2 μm. As a result, even when the metal films 42 and 52 are formed, the opening of the through hole can be prevented from being narrowed, and the paste containing metal particles can be fully filled in the subsequent process.

[0101] Then, if Fig. 9 As shown in FIG. 1 , for example, the through holes formed in the photoresist layer 62 are filled with a paste containing Au particles having a purity of 99.9 wt % or more and a particle size of 0.005 μm to 1.0 μm to form the porous metal layers 41 and 51. As a method of filling the through holes with the paste, for example, any method such as screen printing or a method of applying a dripped paste with a doctor blade can be used.

[0102] After that, the slurry is dried and sintered, and then the photoresist layer 62 is peeled off by peeling using a stripping solution or the like. As a result, Fig.10 As shown, a protrusion 4 and a side wall 5 are formed on a semiconductor substrate 3 .

[0103] Next, the manufacturing process of the chip 2 is described. Fig.11 As shown, in the case of manufacturing the chip 2, first, the connection pad 22 is formed at a predetermined position on the substrate 21, and the metal films 23 and 24 are formed at a predetermined position on the upper surface of the substrate 21 and the exposed portion of the upper surface of the connection pad 22.

[0104] Then, a photoresist layer 63 is formed on the surface of the chip 2 on the side provided with the connection pads 22 and the metal films 23 and 24. Thereafter, through holes are formed in the photoresist layer 63 at positions where the bumps 4 and the sidewall portions 5 are to be formed to expose the surfaces of the metal films 23 and 24 by photolithography.

[0105] Afterwards, if Fig.12 As shown, metal films 42 and 52 are formed, for example, by sputtering, on the upper surface of the photoresist layer 63, the side surfaces of the through holes, and the upper surfaces of the metal films 23 and 24. As the material of the metal films 42 and 52, Au having the same composition as Au particles contained in the paste that will later fill the through holes is selected.

[0106] As a result, by coating the metal films 42 and 52 on the surface of the photoresist layer 63 and curing the photoresist layer 63 , it is possible to prevent the microstructure from collapsing when the through-holes are filled with the Au particle paste.

[0107] In addition, here, the thin (for example, thickness less than 1 μm) metal films 42, 52 are also formed so that the ratio of the film thickness of the metal films 42, 52 to the depth of the through hole, in other words, the thickness of the bump 4 described later in the direction orthogonal to the main surface of the chip 2 (the height D1 of the bump 4) is less than 10%.

[0108] For example, when forming ridges 4 with a height of 10 μm arranged at a pitch of 20 μm, the thickness of the metal films 42 and 52 is set to 0.2 μm. As a result, even when the metal films 42 and 52 are formed, the opening of the through hole can be prevented from being narrowed, and the paste containing metal particles can be fully filled in the subsequent process.

[0109] Then, if Fig.13 As shown, the through hole formed in the photoresist layer 63 is filled with, for example, a paste containing Au particles having a purity of 99.9 wt % or more and a particle size of 0.005 μm to 1.0 μm, thereby forming the ridge 4 and the side wall 5 .

[0110] After that, the slurry is dried and sintered, and then the photoresist layer 63 is peeled off by peeling using a stripping solution or the like. As a result, Fig.14 As shown, a protrusion 4 and a side wall 5 are formed on the chip 2 .

[0111] After that, Fig.10 The semiconductor substrate 3 and Fig.14 The chip 2 shown in FIG. 1 is arranged so that the respective connection pads 22 and 32 are opposite to each other, and the connection pads 22 are connected to each other, thereby completing Figure 1 The electronic device 1 shown in FIG.

[0112] For example, a chip 2 including a semiconductor laser and a semiconductor substrate 3 including a driving circuit of the semiconductor laser are mounted on a distance measuring device such as a ToF sensor or structured light. For example, when the semiconductor laser is mounted on the distance measuring device, the semiconductor laser is used as a light source of a ToF sensor or a light source of structured light.

[0113] It should be noted that the effects described in this specification are merely examples and do not limit the disclosure herein, and other effects not described herein may also be achieved.

[0114] It should be noted that the present technology can also have the following configurations. (1)

[0116] An electronic device, comprising:

[0117] A chip is provided with a semiconductor laser;

[0118] A semiconductor substrate provided with a driving circuit for driving the semiconductor laser;

[0119] a plurality of bumps, respectively connecting a plurality of chip-side connection pads and a plurality of substrate-side connection pads, wherein the plurality of chip-side connection pads are arranged on a main surface of the chip opposite to a laser emission surface, and the plurality of substrate-side connection pads are arranged on a main surface of the semiconductor substrate on a side facing the chip;

[0120] an insulating film provided in the same layer as the substrate-side connection pads and insulating adjacent substrate-side connection pads among the plurality of substrate-side connection pads; and

[0121] The metal film is disposed on the insulating film. (2)

[0123] The electronic device according to (1), wherein:

[0124] metal film

[0125] The substrate is made of the same type of metal as the metal film provided between each of the substrate-side connecting pads and each of the bumps, and is provided in the same layer as the metal film provided between each of the substrate-side connecting pads and each of the bumps. (3)

[0127] The electronic device according to (3), wherein:

[0128] in a metal film disposed between each substrate-side connection pad and each bump,

[0129] The area of ​​the surface parallel to the main surface is larger than the area of ​​the cross section of the bump parallel to the main surface. (4)

[0131] The electronic device according to (2) or (3), wherein

[0132] The metal film provided on the insulating film and the metal film provided between each substrate-side connection pad and each bump are separated by a slit. (5)

[0134] Claim 5. The electronic device according to any one of (1) to (4), further comprising:

[0135] a side wall portion, which is provided in a manner of annularly surrounding a region where the plurality of bumps are provided, and the side wall portion connects the chip and the semiconductor substrate,

[0136] Wherein, the metal film disposed on the insulating film

[0137] The semiconductor substrate is made of the same type of metal as the metal film provided between the side wall portion and the semiconductor substrate, and is provided in the same layer as the metal film provided between the side wall portion and the semiconductor substrate. (6)

[0139] The electronic device according to (5), wherein:

[0140] In the metal film provided between the side wall portion and the semiconductor substrate,

[0141] An area of ​​a surface parallel to the main surface is larger than an area of ​​a cross section of the side wall portion parallel to the main surface. (7)

[0143] The electronic device according to any one of (1) to (6), wherein:

[0144] The metal film disposed on the insulating film includes:

[0145] A titanium film is provided on the insulating film, and a gold film is provided on the titanium film.

[0146] Reference Numbers List

[0147] 1 Electronic devices

[0148] 2 Chip

[0149] 3 Semiconductor substrate

[0150] 4 Bumps

[0151] 5 Side wall

[0152] 10. Lens

[0153] 11. Laser

[0154] 21. Substrate

[0155] 22, 32 connection pads

[0156] 23, 24, 34, 35 metal film

[0157] 31 Si substrate

[0158] 33 Insulation film

[0159] 41, 51 porous metal layer

[0160] 42, 52 metal film

[0161] 61 Glass Mask

[0162] 62 Photoresist layer

[0163] 63 Photoresist layer.

Claims

1. An electronic device, comprising: A chip is provided with a semiconductor laser; A semiconductor substrate provided with a driving circuit for driving the semiconductor laser; a plurality of bumps, respectively connecting a plurality of chip-side connection pads and a plurality of substrate-side connection pads, wherein the plurality of chip-side connection pads are arranged on a main surface of the chip opposite to a laser emission surface, and the plurality of substrate-side connection pads are arranged on a main surface of the semiconductor substrate on a side facing the chip; an insulating film provided in the same layer as the substrate-side connection pads and insulating adjacent substrate-side connection pads among the plurality of substrate-side connection pads; as well as The metal film is disposed on the insulating film.

2. The electronic device according to claim 1, wherein: The metal film The substrate is made of the same type of metal as the metal film provided between each of the substrate-side connecting pads and each of the bumps, and is provided in the same layer as the metal film provided between each of the substrate-side connecting pads and each of the bumps.

3. The electronic device according to claim 2, wherein: In the metal film provided between each of the substrate-side connection pads and each of the bumps, An area of ​​a surface parallel to the main surface is larger than an area of ​​a cross section of the bump parallel to the main surface.

4. The electronic device according to claim 2, wherein: The metal film provided on the insulating film and the metal film provided between each of the substrate-side connecting pads and each of the bumps are separated by a slit.

5. The electronic device according to claim 1, further comprising: a side wall portion, which is provided in a manner of annularly surrounding a region where the plurality of bumps are provided, and the side wall portion connects the chip and the semiconductor substrate, Wherein, the metal film disposed on the insulating film The semiconductor substrate is made of the same type of metal as the metal film provided between the side wall portion and the semiconductor substrate, and is provided in the same layer as the metal film provided between the side wall portion and the semiconductor substrate.

6. The electronic device according to claim 5, wherein: In the metal film provided between the side wall portion and the semiconductor substrate, An area of ​​a surface parallel to the main surface is larger than an area of ​​a cross section of the side wall portion parallel to the main surface.

7. The electronic device according to claim 1, wherein: The metal film disposed on the insulating film includes: A titanium film is provided on the insulating film, and a gold film is provided on the titanium film.

Images