Semiconductor device

Abstract

The present invention provides a semiconductor device in which an IGBT is provided with a carrier discharge path when turned off to secure breakdown tolerance against avalanche, and in which an IE effect can be improved and an ON voltage can be reduced. A semiconductor device (1) is provided with: a first trench (7) in which a gate electrode (9) is formed via a gate insulating film (10); and a second trench (8) in which an in-trench emitter electrode (13) is formed via an in-trench insulating film (14), the emitter layer (11) is not in contact with the second trench (8), and Wg < = Wb and We / Wb > = 2 are satisfied, where Wg is the width of the first trench (7), We is the width of the second trench (8), and Wb is the width of the body layer (6) sandwiched between the first trench (7) and the second trench (8) in a longitudinal cross-section.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] One type of semiconductor device used in a power conversion device or the like is an IGBT (Insulated Gate Bipolar Transistor).

[0003] In order to cope with the increase in power and density of power modules using IGBTs as switching elements, there is a demand for semiconductor devices that can maintain high performance and high reliability while maintaining a withstand voltage.

[0004] For example, as a technique for improving the breakdown resistance, in Patent Document 1 Figure 7 The following technique is described in the text: a first trench (17) having a width of WT1 and a second trench (20) having a width of WT2 are formed by dry etching using mask patterns having different opening widths. The following technique is described here: since the width of the second trench (20) is wider than that of the first trench (17), dry etching is performed together, so that the depth of the second trench (20) can be formed deeper than that of the first trench (17). A first gate electrode (19) is formed in the first trench (17), and a second gate electrode (22) is formed in the second trench (20). In addition, the second gate electrode (22) is connected to the first gate electrode (19), but can also be connected to the emitter electrode (24) (see paragraph 0032). An N+ type emitter region (16) is formed around the first trench (17), and an N+ type emitter region (16) is not formed around the second trench (20). An N-type carrier accumulation layer (14) for accumulating carriers is formed under the P-type base region (15).

[0005] According to the technology of Patent Document 1, the following technology is described: when the depth of the second groove (20) is deeper than that of the first groove (17), the electric field intensity distribution when a reverse bias voltage of 600V is applied is compared with that when the depth is the same, as described in Patent Document 1. Figure 3 As shown in (b), the electric field intensity distribution near the second groove (20) becomes higher at the front end (bottom) of the groove than near the first groove (17). In addition, when the VCE waveform is turned off, the hole carrier distribution when the turn-off surge voltage becomes the maximum is compared with the case of the same depth, as shown in Patent Document 1. Figure 5 As shown in (b), the carrier density of holes in the upper part of the second trench (20) is greater than that in the first trench (17) (see paragraphs 0025 to 0026).

[0006] Furthermore, according to the technology of Patent Document 1, the following technology is described: in the case of the second trench (20), unlike the first trench (17), there is no N+ type emitter region (16) on its upper part, so that an npnp thyristor is not formed, and therefore even if the electric field intensity near the second trench (20) becomes high, it will not cause latch-up in the structure. Furthermore, the carrier density of holes near the first trench (17) decreases, and the base current of the npn transistor decreases, so the breakdown resistance is improved (see paragraph 0027).

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2008-21918 Summary of the invention

[0010] Problems to be solved by the invention

[0011] In Patent Document 1, since the N+ type emitter region (16) is not formed around the second trench (20), it is presumed to serve as a discharge path for holes generated by avalanche, thereby suppressing damage caused by avalanche.

[0012] However, in Patent Document 1, since the IGBT has the influence of the structure for hole discharge when it is turned off, it is difficult to maintain the IE (Injection Enhancement) effect when the IGBT is in the on state, and there is a possibility that the reduction of the on-voltage is insufficient. The IE effect refers to the effect of accumulating carriers (holes and electrons on one side) on the surface side of the semiconductor device, thereby promoting the injection of holes and electrons from the emitter side and reducing the on-voltage. The hole discharge effect and the IE effect of accumulating holes are in a trade-off relationship. In Patent Document 1, an N-type carrier accumulation layer (14) for carrier accumulation is formed under the P-type base region (15), and it is considered that an attempt is made to obtain the IE effect. However, in the case where the N-type carrier accumulation layer (14) is provided under the P-type base region (15) as in Patent Document 1, there is the following problem: when the IGBT is turned off, the depletion layer is difficult to extend downward from the PN junction boundary, so that the withstand voltage margin is reduced. In addition, since the N-type carrier storage layer (14) hinders the discharge of holes, there is also a problem that the discharge effect of holes becomes weak.

[0013] An object of the present invention is to provide a semiconductor device in which a carrier discharge path is provided in an IGBT when the device is turned off to ensure avalanche breakdown resistance and an IE effect is enhanced to reduce an on-voltage.

[0014] Solutions to Solve Problems

[0015] In order to solve the above-mentioned problems, the semiconductor device of the present invention comprises, for example: a drift layer of a first conductivity type; a collector layer of a second conductivity type, which is arranged on the back side of the drift layer; a collector electrode, which is electrically connected to the collector layer; a main layer of a second conductivity type, which is arranged on the surface side of the drift layer; a first trench and a second trench, which penetrate the main layer and reach the drift layer; a gate electrode, which is arranged inside the first trench; a gate insulating film, which is arranged between the side wall portion inside the first trench and the gate electrode and between the bottom portion and the gate electrode; an emitter electrode in the trench, which is arranged inside the second trench; an insulating film in the trench, which is arranged between the side wall portion inside the second trench and the upper between the emitter electrodes in the trenches and between the bottom portion and the emitter electrodes in the trenches; an emitter layer of a first conductivity type, which is arranged on the surface of the main layer, connected to the first trench and separated from the second trench; and an emitter electrode, which is electrically connected to the emitter layer, the main layer and the emitter electrode in the trenches, and the first trench and the two main layers are arranged between the two second trenches. The semiconductor device is characterized in that when the width of the first trench in the longitudinal section is set to Wg, the width of the second trench is set to We, and the width of the main layer sandwiched between the first trench and the second trench is set to Wb, Wg≤Wb, and We / Wb≥2.

[0016] Effects of the Invention

[0017] According to the semiconductor device of the present invention, since the emitter layer is not in contact with the side wall portion of the second trench, a carrier discharge path is formed when the device is turned off, and the second trench is formed with a wide width, and an in-trench emitter electrode is provided inside the second trench via an in-trench insulating film, so that more carriers can be accumulated under the wide second trench, and the IE effect can be improved. Therefore, according to the semiconductor device of the present invention, in the IGBT, a carrier discharge path is provided when the device is turned off, and the breakdown tolerance to avalanche is ensured, and the IE effect can be improved to reduce the on-voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a longitudinal sectional view of the semiconductor device of Example 1.

[0019] Figure 2 It is a longitudinal cross-sectional view of the semiconductor device of Example 2.

[0020] Figure 3 It is a longitudinal cross-sectional view of the semiconductor device of Example 3.

[0021] Figure 4 It is a longitudinal cross-sectional view of the semiconductor device of Example 4.

[0022] Figure 5 It is a longitudinal cross-sectional view of the semiconductor device of Example 5.

[0023] Figure 6 It is a longitudinal cross-sectional view of the semiconductor device of Example 6.

[0024] Figure 7 It is a longitudinal cross-sectional view of the semiconductor device of Example 7.

[0025] Figure 8 It is a longitudinal cross-sectional view of the semiconductor device of Example 8.

[0026] Fig. 9 It is a longitudinal cross-sectional view of the semiconductor device of Example 9.

[0027] Fig.10 This is a longitudinal sectional view of the semiconductor device of the tenth embodiment.

[0028] Fig.11 This is a longitudinal cross-sectional view of the semiconductor device of Example 11.

[0029] Fig.12 This is a longitudinal cross-sectional view of the semiconductor device of Example 12.

[0030] Fig.13 This is the process flow of the method for manufacturing a semiconductor device of Example 13.

[0031] Fig.14A It is a longitudinal cross-sectional view illustrating the method for manufacturing a semiconductor device according to the thirteenth embodiment.

[0032] Fig. 14B It is a longitudinal cross-sectional view illustrating the method for manufacturing a semiconductor device according to the thirteenth embodiment.

[0033] Fig. 14C It is a longitudinal cross-sectional view illustrating the method for manufacturing a semiconductor device according to the thirteenth embodiment.

[0034] Fig.14D It is a longitudinal cross-sectional view illustrating the method for manufacturing a semiconductor device according to the thirteenth embodiment.

[0035] Fig.14E It is a longitudinal cross-sectional view illustrating the method for manufacturing a semiconductor device according to the thirteenth embodiment.

[0036] Fig.14F It is a longitudinal cross-sectional view illustrating the method for manufacturing a semiconductor device according to the thirteenth embodiment. DETAILED DESCRIPTION

[0037] In the following, embodiments of the present invention are described using the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and repeated descriptions are omitted.

[0038] Example 1

[0039] Figure 1 It is a longitudinal sectional view of the semiconductor device of Example 1.

[0040] The semiconductor device 1 of the first embodiment has: a first conductivity type (in Figure 1 The drift layer 2 of the second conductivity type (in Figure 1 The semiconductor device 1 further includes a collector layer 4 (p-type in the embodiment) disposed on the back side of the drift layer 2, and a collector electrode 5 electrically connected to the collector layer 4. In addition, the semiconductor device 1 further includes a buffer layer 3 of the first conductivity type between the drift layer 2 and the collector layer 4, but the effect of the embodiment 1 can be obtained regardless of the presence or absence of the buffer layer 3, and thus it can also be applied to a structure in which the buffer layer 3 is omitted.

[0041] Furthermore, the semiconductor device 1 includes a second conductivity type body layer 6 provided on the surface side of the drift layer 2 , and a first trench 7 and a second trench 8 penetrating the body layer 6 to reach the drift layer 2 .

[0042] Here, the semiconductor device 1 includes: a gate electrode 9 provided inside the first trench 7; and a gate insulating film 10 provided between the sidewall portion inside the first trench 7 and the gate electrode 9 and between the bottom portion and the gate electrode 9. The gate electrode 9 is also called a trench gate. The gate electrode 9 is formed of, for example, polysilicon. Since a gate potential G is applied to the gate electrode 9, Figure 1 In FIG. 1 , the gate electrode 9 is denoted by a symbol G.

[0043] Furthermore, the semiconductor device 1 has: an emitter electrode 13 in the trench, which is arranged inside the second trench 8; an insulating film 14 in the trench, which is arranged between the side wall portion inside the second trench 8 and the emitter electrode 13 in the trench and between the bottom portion and the emitter electrode 13 in the trench; an emitter layer 11 of the first conductivity type, which is arranged on the surface of the main layer 6, is in contact with the first trench 7, and is separated from the second trench 8; and an emitter electrode 12, which is electrically connected to the emitter layer 11, the main layer 6, and the emitter electrode 13 in the trench. The emitter electrode 13 in the trench is formed of, for example, polysilicon. Since an emitter potential E is applied to the emitter electrode 13 in the trench, Figure 1 The in-trench emitter electrode 13 is denoted by the symbol E. The emitter layer 11 and the body layer 6 are connected to the emitter electrode 12 via one contact hole provided in the interlayer insulating film 15 , and the in-trench emitter electrode 13 is connected to the emitter electrode 12 via another contact hole provided in the interlayer insulating film 15 .

[0044] The drift layer 2, the buffer layer 3, the collector layer 4, the main layer 6 and the emitter layer 11 are formed of semiconductors, for example, each layer is formed in a semiconductor substrate such as a silicon substrate. In Example 1, the case where the first conductivity type is n-type and the second conductivity type is p-type is taken as an example for explanation, but it is not limited to this, and the first conductivity type may also be p-type and the second conductivity type may be n-type. In the case where the first conductivity type is p-type and the second conductivity type is n-type, the records related to the carriers in the embodiment can be reversed by exchanging holes and electrons. For example, the record of discharging holes in the carrier discharge path can be replaced by discharging electrons.

[0045] exist Figure 1 In the embodiment, as an example, since the impurity concentration of the drift layer 2 is low, it is recorded as n-, since the impurity concentration of the emitter layer 11 is high, it is recorded as n+, the buffer layer 3 is recorded as n, and the main layer 6 and the collector layer 4 are recorded as p, but it is not limited to this, and the impurity concentration can be appropriately changed within the range of being able to perform the desired operation. The description related to the impurity concentration in the embodiments after this embodiment is also the same.

[0046] The semiconductor device 1 of the first embodiment has a structure in which the first trench 7 and two body layers 6 are arranged between two second trenches 8 as a basic unit structure 16 .

[0047] As described above, the semiconductor device 1 of the first embodiment has the following structure, namely, it has: a first trench 7, in which a gate electrode 9 is formed via a gate insulating film 10; and a second trench 8, in which an intra-trench emitter electrode 13 is formed via an intra-trench insulating film 14, and the emitter layer 11 is not connected to the second trench 8.

[0048] Since the emitter layer 11 is not in contact with the side wall of the second trench 8, it becomes a carrier discharge path when disconnected, and the breakdown resistance to avalanche can be improved compared with the case where this is not the case. Specifically, the main body layer 6 in contact with the side wall of the second trench 8 becomes a discharge path for holes generated by avalanche, and the emitter layer 11 can discharge holes to the emitter electrode 12 without blocking the path. In addition, the longitudinal structure of this region is not a parasitic thyristor structure (npnp thyristor structure formed by n+ of the emitter layer 11 / p of the main body layer 6 / n- of the drift layer 2 / p of the collector layer 4), so it will not be locked, and the breakdown resistance is improved.

[0049] Furthermore, as described above, the semiconductor device 1 of the first embodiment has the following structure: a carrier discharge path is provided when the device is turned off to ensure the breakdown tolerance against avalanche, and the IE effect in a trade-off relationship is improved to reduce the on-voltage. Specifically, in the semiconductor device 1 of the first embodiment, when the width of the first trench 7 in the longitudinal section is set to Wg, the width of the second trench 8 is set to We, and the width of the main layer 6 sandwiched between the first trench 7 and the second trench 8 is set to Wb, Wg≤Wb, and We / Wb≥2.

[0050] The sizes of Wg and Wb are preferably within the generally used range of 0.5 μm ≤ Wg ≤ 1.8 μm and 0.5 μm ≤ Wb ≤ 1.8 μm, but are not limited thereto. In addition, Wb is generally preferably greater than Wg, so Wg ≤ Wb.

[0051] On this basis, We / Wb≥2, that is, the width (We) of the second groove 8 is at least twice the width (Wb) of the body layer 6. The upper limit is We / Wb≤20, but it is not limited thereto.

[0052] According to the semiconductor device 1 of the first embodiment, the wide second trench 8 can accumulate more holes as carriers from the collector side of the back side under the wide second trench 8 when the IGBT is in the on state, so that the IE effect can be improved, thereby promoting the injection of electrons from the emitter side of the surface, and the on-voltage can be reduced. That is, the wide second trench 8 can improve the IE effect and reduce the on-voltage. In addition, the accumulated holes are then discharged to the emitter electrode 12 via the main layer 6. In addition, even when the second trench 8 is set to a wide width, the accumulation ensures the carrier discharge path when it is turned off, thereby ensuring the destruction tolerance relative to avalanche, and the IE effect can be improved to reduce the on-voltage.

[0053] Furthermore, since the in-trench emitter electrode 13 functions as a field plate, there is also an effect of being able to maintain a high breakdown voltage even when the second trench 8 is made wide.

[0054] Furthermore, the in-trench emitter electrode 13 is insulated from the drift layer 2 by the in-trench insulating film 14 . Therefore, holes accumulated under the second trench 8 do not penetrate the in-trench insulating film 14 to the in-trench emitter electrode 13 , and the IE effect can be maintained.

[0055] As a technique for improving the IE effect, there is also a technique in which a portion where the trench gate has a narrower interval and a portion where the trench gate has a wider interval are provided, a floating layer (floating P layer) of a second conductivity type is provided in the portion where the trench gate has a wider interval, and holes are accumulated in the floating layer. However, in the case of a structure in which a floating layer is provided, when the IGBT is turned on, holes excessively flow into the floating layer, the potential of the floating layer rises, and the gate potential of the trench gate adjacent to the floating layer rises, which may cause the conduction speed to accelerate and cause a problem of a decrease in the controllability of the time rate of change dV / dt of the output voltage. In contrast, according to the semiconductor device 1 of the first embodiment, such a problem does not occur, and the dV / dt controllability can be ensured.

[0056] The semiconductor device 1 of the first embodiment also has an effect of high reliability of the insulating film. For example, at the time of shutdown, since the carrier (hole) discharge path in the high electric field is mainly on the second groove 8 side, the first groove 7 provided with the gate electrode 9 for switching operation is not easily affected by it, and the reliability of the gate insulating film 10 becomes higher than that of a case where it is not so. In addition, since the second groove 8 is a wide groove, the number of grooves as a whole is reduced compared to the case where a plurality of fine grooves are provided, and the total area of ​​the opposing area between the gate electrode 9 or the emitter electrode 13 in the groove and the drift layer 2 or the main layer 6 of the semiconductor substrate (the total area of ​​the opposing area of ​​all the grooves) is reduced, so the total area of ​​the insulating film (gate insulating film 10 and the insulating film in the groove 14) provided in the groove is also reduced, and it is considered that the margin for ensuring the reliability of the insulating film is improved compared to the case where a plurality of fine grooves are provided.

[0057] In the semiconductor device 1 of the first embodiment, the second trench 8 having the emitter electrode 13 in the trench is provided, so that the number of the first trenches 7 having the gate electrode 9 is reduced, thereby achieving an effect such as being able to reduce the feedback capacitance as the capacitance between the collector and the gate compared to a case where all the trenches are the first trenches 7 .

[0058] In order to further reduce the feedback capacitance, when the depth of the first groove 7 in the longitudinal section is set to td, it is preferably 1.0μm≤td≤2.0μm. The depth of the general groove is mostly 3μm to 8μm, but by setting it to a shallower groove than it, the feedback capacitance can be reduced. In addition, from the perspective of improving the IE effect, it is not necessary to set it as a shallow groove, so it can also be set to a groove with a depth other than the above. In addition, in order to manufacture the first groove 7 and the second groove 8 with the same process, it is preferred to make the depth of the first groove 7 and the second groove 8 the same.

[0059] In order to further reduce the feedback capacitance, when the thickness of the gate insulating film 10 of the side wall portion of the first trench 7 in the longitudinal section is set to ta and the thickness of the gate insulating film 10 of the bottom portion of the first trench 7 is set to tb, it is preferably ta<tb. In addition, from the perspective of improving the IE effect, ta<tb is not necessary, so ta=tb may also be used. In addition, in the case of ta<tb, the manufacturing process increases compared to the case of ta=tb, so it can be decided whether to adopt it according to necessity. In addition, in order to manufacture the gate insulating film 10 and the in-trench insulating film 14 by the same process, it is preferred to make the thickness of the in-trench insulating film 14 the same as the thickness of the gate insulating film 10.

[0060] With the structure described above, according to the semiconductor device 1 of the first embodiment, a semiconductor device can be provided, in which a carrier discharge path is provided in the IGBT when the device is turned off to improve the breakdown resistance against avalanche, and the IE effect can be improved to reduce the on-voltage. In addition, an IGBT with excellent overall balance including dV / dt controllability, reliability of the insulating film, and feedback capacitance can be realized.

[0061] Example 2

[0062] Embodiments 2 and thereafter are modified examples of Embodiment 1. Embodiments 2 and thereafter will be described mainly around the differences, and duplicate descriptions will be omitted.

[0063] Figure 2 It is a longitudinal cross-sectional view of the semiconductor device of Example 2.

[0064] The semiconductor device 1 of the second embodiment has a first barrier layer 17 of the first conductivity type, which is arranged between the main layer 6 and the drift layer 2 sandwiched between the first trench 7 and the second trench 8, and has an impurity concentration higher than that of the drift layer 2, which is different from the first embodiment.

[0065] The first barrier layer 17 serves as a barrier to holes flowing toward the emitter side when the IGBT is turned on. Therefore, the hole concentration under the first barrier layer 17 increases, and the on-voltage when the IGBT is turned on can be further reduced.

[0066] In Example 2, due to the influence of the first barrier layer 17, the breakdown resistance against avalanche is slightly reduced compared to Example 1, but the reduced breakdown resistance is ensured, and the IE effect can be improved by the wide second trench 8 to reduce the turn-on voltage, thereby obtaining the same effect as Example 1.

[0067] Example 3

[0068] Figure 3 It is a longitudinal cross-sectional view of the semiconductor device of Example 3.

[0069] The semiconductor device 1 of the third embodiment is different from the second embodiment in that it includes a second barrier layer 18 of the second conductivity type provided between the first barrier layer 17 and the drift layer 2 .

[0070] When the first barrier layer 17 is provided as in the second embodiment, there is a problem that the first barrier layer 17 has a higher impurity concentration than the drift layer 2 , so that when the IGBT is turned off, the depletion layer is difficult to extend downward from the PN junction boundary, thereby reducing the withstand voltage margin when the IGBT is turned off.

[0071] Therefore, in the third embodiment, by providing the second barrier layer 18 of the second conductivity type under the first barrier layer 17 , it is possible to relax the electric field and improve the withstand voltage margin when the IGBT is turned off.

[0072] Example 4

[0073] Figure 4 It is a longitudinal cross-sectional view of the semiconductor device of Example 4.

[0074] In the semiconductor device 1 of Example 4, the second trench 8 is divided into a third trench 20 and a fourth trench 21 in a partial area, and in the area sandwiched between the third trench 20 and the fourth trench 21, there is an inactive main layer 19 of the second conductivity type in which no first conductivity type layer is formed on the surface, and the inactive main layer 19 is electrically connected to the emitter electrode 12, which is different from Example 1.

[0075] That is, the semiconductor device 1 of the fourth embodiment has Figure 1 The area of ​​the longitudinal section and Figure 4 Therefore, the third trench 20 and the fourth trench 21 have an in-trench emitter electrode 13 and an in-trench insulating film 14 in the same manner as the second trench 8. Figure 4 Other places, Figure 1 Since the second trench 8 is connected to the third trench 20 and the fourth trench 21 , the in-trench emitter electrode 13 inside the third trench 20 and the fourth trench 21 also reaches the emitter potential E.

[0076] The inactive main layer 19 functions as a carrier discharge path, so the IE effect is reduced in the area where the inactive main layer 19 is provided, but the margin of the breakdown tolerance during shutdown can be further improved. In addition, the structure of Example 4 is the same process as the manufacturing process of Example 1, and can be achieved only by changing the layout.

[0077] When the width of the inactive main body layer 19 in the vertical section is represented by Wb′, it is preferably 0.5 μm ≤ Wb′ ≤ 1.8 μm, but the present invention is not limited thereto.

[0078] The width of the third trench 20 and the fourth trench 21 is preferably the same as that of the second trench 8, which is at least twice as large as Wb. However, as long as a sufficient IE effect is obtained in the second trench 8, the width of the third trench 20 and the fourth trench 21 may be smaller than twice as large as Wb.

[0079] In Example 4, due to the influence of the inactive main layer 19, compared with Example 1, the damage tolerance with respect to avalanche is improved and the IE effect is reduced, but the damage tolerance is ensured, and the IE effect can be improved by the wide second groove 8 (if necessary, the wide third groove 20 and the fourth groove 21 can also be used) to reduce the turn-on voltage. In this respect, the same effect as in Example 1 is obtained.

[0080] Example 5

[0081] Figure 5 It is a longitudinal cross-sectional view of the semiconductor device of Example 5.

[0082] Embodiment 5 is an embodiment in which the first barrier layer 17 of embodiment 2 is applied to embodiment 4. In addition, it is preferred that the first barrier layer 17 is not provided under the inactive main layer 19 so as not to become an obstacle to carrier discharge. Originally, the first barrier layer 17 can be selectively formed, so even if the first barrier layer 17 is not provided under the inactive main layer 19, the manufacturing process is not increased.

[0083] Example 6

[0084] Figure 6 It is a longitudinal cross-sectional view of the semiconductor device of Example 6.

[0085] Example 6 is an example in which the second barrier layer 18 of Example 3 is applied to Example 5.

[0086] Example 7

[0087] Figure 7 It is a longitudinal cross-sectional view of the semiconductor device of Example 7.

[0088] In the semiconductor device 1 of the seventh embodiment, the emitter layer 11 , the body layer 6 and the in-trench emitter electrode 13 are connected to the emitter electrode 12 via a contact hole 22 , and the bottom surface of the contact hole 22 is deeper than the bottom surface of the emitter layer 11 , which is different from the first embodiment.

[0089] Thus, since a contracted basic unit structure 16 can be adopted in which the width (Wb) of the main body layer 6 is reduced, miniaturization can be achieved, or the number of basic units manufactured in the same semiconductor substrate can be increased. In addition, since the carrier discharge path through the main body layer 6 is narrowed, the effect of accumulating carriers is improved compared to Example 1, and the IE effect can be improved.

[0090] The width (Wb) of the main body layer 6 is preferably 0.25 μm ≤ Wb ≤ 1.8 μm, but is not limited thereto. The upper limit of We / Wb is preferably We / Wb ≤ 40 as the lower limit of Wb decreases, but is not limited thereto.

[0091] Example 8

[0092] Figure 8 It is a longitudinal cross-sectional view of the semiconductor device of Example 8.

[0093] Example 8 is an example in which the first barrier layer 17 of Example 2 is applied to Example 7.

[0094] Example 9

[0095] Fig. 9 This is a longitudinal sectional view of the semiconductor device of Example 9.

[0096] Example 9 is an example in which the second barrier layer 18 of Example 3 is applied to Example 8.

[0097] Example 10

[0098] Fig.10 This is a longitudinal sectional view of the semiconductor device of the tenth embodiment.

[0099] Example 10 is an example in which the third trench 20 , the fourth trench 21 , and the inactive body layer 19 of Example 4 are applied to Example 7. The inactive body layer 19 is connected to the emitter electrode 12 via a contact hole formed in the same process as the contact hole 22 .

[0100] Embodiment 10 is the same as embodiment 4, and has Figure 7 The area of ​​the longitudinal section and Fig.10 The structure of the area in such a longitudinal section.

[0101] Furthermore, when the width of the inactive main body layer 19 in the vertical section is represented by Wb′, it is preferably 0.25 μm ≤ Wb′ ≤ 1.8 μm, but the present invention is not limited thereto.

[0102] Embodiment 11

[0103] Fig.11 This is a longitudinal cross-sectional view of the semiconductor device of Example 11.

[0104] Example 11 is an example in which the first barrier layer 17 of Example 2 is applied to Example 10.

[0105] Example 12

[0106] Fig.12 This is a longitudinal cross-sectional view of the semiconductor device of Example 12.

[0107] Example 12 is an example in which the second barrier layer 18 of Example 3 is applied to Example 11.

[0108] Embodiment 13

[0109] Fig.13 This is the process flow of the method for manufacturing a semiconductor device of Example 13.

[0110] Embodiment 13 is an embodiment for explaining an example of a method for manufacturing the semiconductor device 1 of Embodiments 1 to 12.

[0111] like Fig.13 As shown, the method is basically the same as the general method for manufacturing a semiconductor device. In the wafer preparation process of step S1, a semiconductor substrate wafer is prepared, and in the terminal region diffusion layer formation process of step S2, Figures 1 to 12 A second conductive type diffusion layer (also called a deep P-well layer) is formed in the terminal region not shown in the figure. In the trench forming process of step S3, a trench is formed. In the polysilicon electrode forming process of step S4, a gate electrode 9 and an emitter electrode 13 in the trench are formed by polysilicon. In the main layer and emitter layer forming process of step S5, a main layer 6 and an emitter layer 11 are formed.

[0112] In addition, since a shallow trench is assumed here, the body layer 6 is formed in step S5 , but in the case of a deep trench, it may be changed to be formed together with the body layer 6 in step S2 .

[0113] In the insulating film formation and contact opening process of step S6, an interlayer insulating film 15 and a contact hole are formed, in the metal electrode formation process of step S7, an emitter electrode 12 is formed, in the back process process of step S8, a back process including wafer thinning and back impurity injection is performed, in the back electrode formation process of step S9, a collector electrode 5 is formed, and in the wafer inspection process of step S10, a wafer inspection is performed, thereby completing the process.

[0114] FIG. 14A to FIG. 14F It is a longitudinal cross-sectional view illustrating the method for manufacturing a semiconductor device according to the thirteenth embodiment. FIG. 14A to FIG. 14F It is explained in Fig.13 In step S3 and step S4, a wide shallow trench like the second trench 8 is formed, and an insulating film and a polysilicon electrode are formed inside the trench. In addition, a shallow trench that is not as wide as the first trench 7 can also be made simultaneously by the same process.

[0115] First, if Fig.14A As shown, an oxide film 32, a silicon nitride film 33, a CVD insulating film 34, and a resist 35 are stacked in this order from the bottom on a semiconductor substrate 31 such as a silicon substrate to form a stacked film.

[0116] Then, if Fig. 14B As shown, after patterning and etching of the stacked film are performed, etching of the trench 36 is performed.

[0117] Then, if Fig. 14C As shown, after the resist 35 is removed, the silicon surface in the trench 36 is oxidized to form an in-trench oxide film 37 .

[0118] Then, if Fig.14D As shown in FIG. 1 , the formation of a polysilicon film 38 and the application and baking of a resist 35 are performed.

[0119] Then, if Fig.14E As shown, the entire surface of the resist 35 and the polysilicon 38 is etched back. Fig.14E This is an example showing a case where the etching rates of the resist 35 and the polysilicon 38 are substantially the same, but the present invention is not limited to this.

[0120] Finally, if Fig.14F As shown, the CVD insulating film 34 and the silicon nitride film 33 are removed. Thus, a wide shallow trench, and an in-trench insulating film and a polysilicon electrode provided inside the trench can be formed.

[0121] Although the embodiments of the present invention have been described above, the present invention is not limited to the structures described in the embodiments, and various changes can be made within the scope of the technical concept of the present invention. In addition, some or all of the structures described in the embodiments can also be combined for application.

[0122] Explanation of symbols

[0123] 1—semiconductor device, 2—drift layer, 3—buffer layer, 4—collector layer, 5—collector electrode, 6—body layer, 7—first trench, 8—second trench, 9—gate electrode, 10—gate insulating film, 11—emitter layer, 12—emitter electrode, 13—emitter electrode in trench, 14—insulating film in trench, 15—interlayer insulating film, 16—basic unit structure, 17—first barrier layer, 18—second barrier layer, 19—inactive body layer, 20—third trench, 21—fourth trench, 22—contact hole, 31—semiconductor substrate, 32—oxide film, 33—silicon nitride film, 34—CVD insulating film, 35—resist, 36—trench, 37—oxide film in trench, 38—polysilicon.

Claims

1. A semiconductor device comprising: a drift layer of a first conductivity type; A collector layer of a second conductivity type, which is provided on the back side of the drift layer; a collector electrode electrically connected to the collector layer; A second conductive type body layer provided on the surface side of the drift layer; A first trench and a second trench, which penetrate the main layer and reach the drift layer; A gate electrode disposed inside the first trench; a gate insulating film provided between a side wall portion inside the first trench and the gate electrode and between a bottom portion and the gate electrode; an in-trench emitter electrode disposed inside the second trench; an in-trench insulating film provided between a side wall portion inside the second trench and the in-trench emitter electrode and between a bottom portion and the in-trench emitter electrode; An emitter layer of the first conductivity type, which is provided on the surface of the body layer, is in contact with the first trench, and is spaced apart from the second trench; and an emitter electrode, which is electrically connected to the emitter layer, the main layer and the emitter electrode in the trench, The first trench and the two main body layers are arranged between the two second trenches. The semiconductor device is characterized in that When the width of the first groove in the longitudinal section is Wg, the width of the second groove is We, and the width of the main body layer sandwiched between the first groove and the second groove is Wb, Wg≤Wb, and We / Wb≥2.

2. The semiconductor device according to claim 1, wherein: 0.5μm≤Wg≤1.8μm.

3. The semiconductor device according to claim 1, wherein: When the depth of the first groove in the vertical section is td, 1.0 μm ≤ td ≤ 2.0 μm.

4. The semiconductor device according to claim 1, wherein: When the thickness of the gate insulating film at the side wall portion of the first trench in the vertical cross section is ta and the thickness of the gate insulating film at the bottom portion of the first trench is tb, ta<tb.

5. The semiconductor device according to claim 1, wherein: 0.5μm≤Wb≤1.8μm.

6. The semiconductor device according to claim 1, wherein: We / Wb≤20.

7. The semiconductor device according to claim 1, wherein: A first barrier layer of a first conductivity type is provided between the body layer and the drift layer sandwiched between the first trench and the second trench, and has an impurity concentration higher than that of the drift layer.

8. The semiconductor device according to claim 7, wherein: A second barrier layer of a second conductivity type is provided between the first barrier layer and the drift layer.

9. The semiconductor device according to claim 1, wherein: The second groove is divided into a third groove and a fourth groove in a part of the region. In a region sandwiched between the third trench and the fourth trench, there is an inactive main layer of the second conductivity type on the surface of which no layer of the first conductivity type is formed. The inactive body layer is electrically connected to the emitter electrode.

10. The semiconductor device according to claim 9, wherein: When the width of the inactive main body layer in the longitudinal section is Wb', 0.5μm≤Wb'≤1.8μm.

11. The semiconductor device according to claim 1, wherein: The emitter layer, the main layer and the emitter electrode in the trench are connected to the emitter electrode via a contact hole. A bottom surface of the contact hole is located deeper than a bottom surface of the emitter layer.

12. The semiconductor device according to claim 11, wherein: 0.25μm≤Wb≤1.8μm.

13. The semiconductor device according to claim 11, wherein: We / Wb≤40.

14. The semiconductor device according to claim 11, wherein: The second groove is divided into a third groove and a fourth groove in a part of the region. In a region sandwiched between the third trench and the fourth trench, there is an inactive main layer of the second conductivity type on the surface of which no layer of the first conductivity type is formed. The inactive body layer is electrically connected to the emitter electrode.

15. The semiconductor device according to claim 14, wherein: When the width of the inactive main body layer in the longitudinal section is Wb', 0.25μm≤Wb'≤1.8μm.

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