High voltage III-N devices and structures with reduced current degradation

Abstract

A lateral III-N device, such as an AlGaN / GaN HEMT, can have a structure for improved performance and reduced current degradation. In one embodiment, a III-N device can include a conductive substrate and a III-N material structure including a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, where a difference in composition causes a 2DEG channel therein. The first portion is in ohmic contact with the 2DEG channel, and the second portion extends over and in direct contact with a top surface of the III-N barrier layer. The device further includes a drain-to-substrate pinch-off voltage and a maximum rated drain-to-source operating voltage greater than the drain-to-substrate pinch-off voltage, and when the III-N device is biased at or above the maximum rated drain-to-source operating voltage, the 2DEG channel fully depletes charge below the second portion of the drain.

Description

Technical Field

[0001] The disclosed technology relates to semiconductor devices, particularly Group III nitrides and switches. Background Art

[0002] Currently, typical power semiconductor devices, including devices such as transistors, diodes, power MOSFETs, and insulated gate bipolar transistors (IGBTs), are manufactured from silicon (Si) semiconductor materials. Recently, wide bandgap materials (SiC, III-N, III-O, diamond) have been considered for use in power devices due to their excellent properties. Group III nitride or III-N semiconductor devices, such as gallium nitride (GaN) devices or AlGaN / GaN HEMT transistors, are now becoming attractive candidates for carrying large currents, supporting high voltages, and providing very low on-resistance and fast switching times.

[0003] Although high voltage GaN HEMT transistors are beginning to be commercialized, the design and fabrication of III-N transistors with high quality factors has proven difficult to date. Design improvements are needed to improve device size, efficiency, reliability and output characteristics in order to accelerate market adoption. Summary of the invention

[0004] Lateral III-N devices such as AlGaN / GaN HEMTs are described herein with structures for improved performance and reduced current degradation.

[0005] In a first aspect, a III-N device is described. The III-N device can include a conductive substrate and a III-N material structure. The III-N material structure includes a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein a composition difference induces a 2DEG channel therein. The device also includes a source electrode, a gate electrode electrically connected to the conductive substrate, and a drain electrode, wherein the drain electrode includes a first portion and a second portion. The first portion is in ohmic contact with the 2DEG channel, and the second portion extends above a top surface of the III-N barrier layer and is in direct contact with the top surface of the III-N barrier layer. The device also includes a drain-to-substrate pinch-off voltage and a maximum rated drain-to-source operating voltage, wherein the maximum rated drain-to-source operating voltage is greater than the drain-to-substrate pinch-off voltage, and when the III-N device is biased at or above the maximum rated drain-to-source operating voltage, the 2DEG channel is completely depleted of charge below the second portion of the drain electrode.

[0006] In a second aspect, a III-N device is described. The device includes a conductive substrate and a III-N material structure. The III-N material structure includes a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein a compositional difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein. The device further includes a source electrode, a gate electrode, and a drain electrode, wherein the drain includes a first portion and a second portion. The first portion of the drain electrode makes an ohmic contact with the 2DEG channel, and the second portion of the drain electrode extends on the top surface of the III-N barrier layer and makes direct contact with the top surface. The III-N device includes a drain-to-substrate pinch-off voltage and a maximum rated drain-to-source operating voltage, wherein the maximum rated drain-to-source operating voltage is at least 50 V greater than the drain-to-substrate pinch-off voltage. When the drain-to-source voltage is held constant at a low voltage, the device has a first on-state resistance, and when the drain-to-substrate voltage is scanned from the low voltage to the maximum rated drain-to-source voltage, held at the voltage for at least 2 minutes, and scanned back to the low voltage, the device has a second on-state resistance, and the first on-state resistance is within 25% of the second on-state resistance.

[0007] In a third aspect, a III-N device is described. The device includes a conductive substrate and a III-N material structure. The III-N material structure includes a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein a compositional difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein. The III-N buffer layer includes at least five different layers that increase sequentially from a first side of the III-N buffer layer adjacent to the substrate to a second side of the III-N buffer layer adjacent to the III-N channel layer. The first layer is an AlN nucleation layer, and the second layer has a thickness between 0.2 μm and 1.0 μm of , where 70% < x < 90%, the third layer has a thickness between 0.2 μm and 1.0 μm of , where 40% < x < 70%, the fourth layer has a thickness between 0.5 μm and 1.5 μm and includes a repetition of an AlN / stack layer, where the thickness of the AlN layer is between 0.5 nm and 5 nm, and the layer has a thickness between 10 nm and 50 nm and 5% < x < 20%, the fifth layer has a thickness between 0.5 μm and 1.5 μm and includes a repetition of an AlN / GaN stack layer, where the thickness of the AlN layer is between 0.5 nm and 5 nm and the thickness of the GaN layer is between 10 nm and 50 nm. The device further includes a source electrode, a gate electrode, and a drain electrode, wherein the gate electrode is electrically connected to the conductive substrate, and when the III-N device is biased at the maximum rated drain-source operating voltage, the 2DEG channel is not completely depleted of charge.

[0008] Each of the electronic devices, transistors, and methods described herein can include one or more of the following features. The device has a maximum rated drain-to-source operating voltage greater than 600V and a drain-to-substrate pinch-off voltage less than 600V, or the device has a maximum rated drain-to-source operating voltage of at least 650V and a drain-to-substrate pinch-off voltage of 600V or less. When the III-N device is biased at the maximum rated drain-to-source pinch-off voltage, the 2DEG channel is completely depleted of charge below the second portion of the drain electrode. The device intentionally lacks any dielectric or insulating material between the drain electrode and the III-N material structure. The device can include a gate dielectric layer formed between a top surface of the III-N barrier layer and a gate electrode, wherein the gate dielectric layer includes a first end extending toward the drain electrode and a second end extending toward the source electrode, a spacing between the first end and the drain electrode is between 0.1 μm and 2 μm, and the spacing is filled with an insulating material having a different composition than the gate dielectric layer. The source electrode includes a first portion and a second portion, the first portion being in ohmic contact with the 2DEG channel and the second portion extending above and in direct contact with the top surface of the III-N barrier layer. When the drain-to-source voltage is at a maximum rated operating voltage, the 2DEG channel under the second portion of the drain electrode is depleted from a vertical electric field between the drain electrode and the conductive substrate. The first on-state resistance In the second on-state resistance The III-N material structure is less than 6 μm thick, and the III-N material structure has a breakdown voltage greater than 750 V. The III-N material structure is formed on a conductive silicon substrate, and a first side of the III-N buffer layer is adjacent to the conductive silicon substrate.

[0009] As used herein, the term III-nitride or III-N material, layer, device, etc. refers to a material composed of a stoichiometric A material or device composed of a compound semiconductor material of , wherein w+x+y+z is about 1, wherein 0≤w≤1, 0≤x≤1, 0≤y≤1, and 0≤z≤1. III-N materials, layers, or devices can be formed or prepared by growing directly on a suitable substrate (e.g., by metal organic chemical vapor deposition), or growing on a suitable substrate, separating from the original substrate, and bonding to another substrate.

[0010] As used herein, two or more contacts or other items (such as conductive channels or components) are "electrically connected" if they are connected by a sufficiently conductive material to ensure that the potential at each contact or other item is always the same (e.g., approximately the same) under any bias conditions.

[0011] As used herein, "blocking voltage" refers to the ability of a transistor, device, or component to prevent significant current (such as a current greater than 0.001 times the operating current during normal conduction) from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, when the transistor, device, or component blocks the voltage applied thereto, the total current through the transistor, device, or component will be no greater than 0.001 times the operating current during normal conduction. Devices with off-state currents greater than this value exhibit high losses and low efficiency and are generally unsuitable for many applications, particularly power switching applications.

[0012] As used herein, a "depletion-mode device" refers to a transistor that has a negative threshold voltage and is considered to be in the "on" state when the gate of the depletion-mode transistor is biased above the negative threshold voltage, so that the device will conduct when the gate is biased at zero volts. An "enhancement-mode device" refers to a transistor that has a positive threshold voltage and is considered to be in the "off" state when the gate of the enhancement-mode transistor is biased at zero volts. The "on-resistance" of a transistor refers to the resistance between the source and drain contacts of the transistor when the transistor is biased in the on state (i.e., As used herein, the on-resistance is measured when the device is considered to be in saturation mode.

[0013] As used herein, a "high voltage device," e.g., a high voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS), is an electronic device optimized for high voltage applications. That is, when the device is off, it is capable of blocking high voltages, such as about 300 V or more, about 600 V or more, or about 1200 V or more, and when the device is on, it has a sufficiently low on-resistance (OR) for the application in which it is used. ), for example, when a large amount of current passes through the device, it experiences sufficiently low conduction losses. The high voltage device is capable of blocking at least a voltage equal to the maximum voltage in the high voltage supply or circuit it is used in. The high voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, 2500V, 3300V, or other suitable blocking voltages required by the application. In other words, the high voltage device is capable of blocking 0V and at least All voltages between is the maximum voltage that can be supplied by a circuit or power supply, and It can be, for example, 300V, 600V, 1200V, 1700V, 2500V, 3300V or other suitable blocking voltage required by the application. For a bidirectional or four-quadrant switch, when the switch is turned off, the blocked voltage can be any polarity less than a certain maximum value (± , such as ±300V or ±600V, ±1200V, etc.), and when the switch is on, the current can be in either direction.

[0014] As used herein, an electrode refers to a metal layer within a device or transistor that is connected to the source, gate, or drain of the device. A "pad," such as a "source pad, drain pad, or gate pad," refers to the uppermost, unpassivated portion of an electrode that is used to electrically connect a device or transistor to a package, such as with solder, epoxy, wire bonds, and / or metal clips.

[0015] As used herein, a "III-N device" is a device based on or substantially including III-N materials (including III-N heterostructures). III-N devices can be designed to operate as transistors or switches, where the state of the device is controlled by a gate terminal, or as two-terminal devices that block current flow in one direction and conduct in the other direction without a gate terminal. III-N devices can be high-voltage devices suitable for high-voltage applications. In such high-voltage devices, when the device is biased off (e.g., the voltage on the gate relative to the source is less than the device threshold voltage), it can at least support all source-drain voltages less than or equal to the high voltage in the application in which the device is used, which can be, for example, 100V, 300V, 600V, 1200V, 1700V, 2500V or higher. When the high-voltage device is biased on (e.g., the voltage on the gate relative to the source or associated power supply terminal is greater than the device threshold voltage), it can conduct a large amount of current at a low turn-on voltage (i.e., a low voltage between the source and drain terminals or between the relative power supply terminals). The maximum allowable on-state voltage is the maximum on-state voltage that can be sustained in the application in which the device is used.

[0016] As used herein, a "III-polar" or "Group III polar" III-N material is a III-N material having a Group III face (i.e., the

[0001] face) opposite to the substrate on which the material is grown. In a "III-polar" or "Group III polar" lateral III-N device, at least some device contacts (e.g., source and / or drain contacts) are typically formed on the

[0001] face of the III-N material (e.g., on the side opposite to the [000-1] face).

[0017] As used herein, an "N-polarity" III-N material is a III-N material that has its nitrogen face (i.e., the [000-1] face) opposite the substrate on which the material is grown. In an "N-polarity" lateral III-N device, at least some device contacts (e.g., source and / or drain contacts) are typically formed on the [000-1] face of the III-N material (e.g., on the side opposite the

[0001] face).

[0018] As used herein, a "regrowth" of a III-N layer structure or III-N material structure refers to an additional material deposition process performed after a previous material deposition process. Between subsequent growth and regrowth processes, the device can be unloaded from the deposition tool and the vacuum environment can be interrupted. Thus, the regrown III-N material structure may need to be inserted into the III-N material structure deposition equipment separately from the initial III-N material structure insertion. For example, the regrown III-N layer can be deposited after removing at least a portion of the initial III-N material structure. The removal of a portion of the initial III-N material structure typically occurs in an environment external to the main III-N material structure deposition equipment.

[0019] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one layer with respect to other layers. Thus, for example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Furthermore, a layer disposed between two layers may be in direct contact with the two layers, or may have one or more intervening layers. Conversely, a first layer "above" a second layer is in contact with the second layer. Additionally, assuming that operations are performed relative to a substrate without regard to the absolute orientation of the substrate, a relative position of a layer with respect to other layers is provided.

[0020] Details of one or more disclosed embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Additional features and variations may also be included in the embodiments. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A-Figure 1C is a cross-sectional view of a III-N device.

[0022] Figure 2A is a cross-sectional view of a III-N device with an engineered III-N buffer layer.

[0023] Figure 2B is a schematic diagram of a test circuit for measuring current degradation.

[0024] Figure 2C and Figure 2D Graphical data comparing measurement results of back-gate measurements of III-N devices are shown.

[0025] Figure 2E is a box plot of the on-state resistance of III-N devices during HTRB.

[0026] Figure 3A is a cross section of a III-N device.

[0027] Figure 3BGraphical data showing back-gate measurements of III-N devices.

[0028] Figure 3C Graphical data comparing the on-resistance of III-N devices after HTRB is shown.

[0029] Figure 4A and Figure 4B is a cross-sectional view of a III-N device with an n-type ohmic contact.

[0030] Figure 5 is a cross-sectional view of a III-N device with two 2DEG channels.

[0031] Figure 6 is a cross-sectional view of a III-N device with a p-type electrode contact.

[0032] Figure 7 is a cross-sectional view of a III-N device with an insulating substrate.

[0033] Figure 8 (a)-(d) illustrate a method for fabricating a III-N device.

[0034] Fig. 9 (a)-(d) illustrate a method of fabricating source / drain electrodes.

[0035] Fig. 10A is a cross-sectional view of a III-N device.

[0036] Fig. 10B Graphical data showing measurement results of a back-gate measurement of a III-N device 110 . DETAILED DESCRIPTION

[0037] Lateral III-N devices such as AlGaN / GaN HEMTs are described herein. These devices have structures for improving performance and reducing current degradation, particularly when the device is operated at or near the maximum rated voltage of the device. Due to the very high conductivity of the two-dimensional electron gas (2DEG) channel inherent within lateral III-N devices such as AlGaN / GaN HEMT devices, III-N power devices can have superior performance compared to their silicon counterparts. However, the performance and reliability of these devices can be further improved by eliminating or reducing a phenomenon known as current collapse during power switching operations. Current collapse can be caused by electron trapping that can occur in / on the device layers or buried within the III-N material structure. When the gate of the device is biased in the off state, electrons can be trapped. These trapped electrons cannot be removed quickly as the gate voltage is suddenly changed to the on state. These trapped electrons will deplete an equal portion of the 2DEG channel charge. This will cause the device channel on-state resistance to increase under switching conditions and the overall current level degradation is observed.

[0038] Figure 1A A cross-sectional view of a high voltage III-N device 101, such as an AlGaN / GaN HEMT device, is shown in FIG. The III-N device 101 can be an enhancement mode device (i.e., normally off) or a depletion mode device (i.e., normally on). In the case where the device 101 is a depletion mode device (D-mode), the device 101 can be in a cascode configuration with a low voltage enhancement mode device 21 (e.g., a silicon-FET) to form a normally-off hybrid device 100 that can operate in a manner similar to a single enhancement mode III-N device.

[0039] Figure 1A The III-N device 101 includes a III-N material structure 20, such as a combination of GaN and AlGaN, grown on a suitable substrate 10, which can be a conductive semiconductor such as silicon (e.g., p-type or n-type Si), GaN, or any other sufficiently conductive substrate. For example, the substrate can be p-type doped with a hole concentration greater than Hole / , or the substrate can be n-doped, with an electron concentration greater than electronic / The substrate can have a high thermal conductivity or a low thermal conductivity; in the case of a low thermal conductivity substrate, the substrate can be thinned to improve heat dissipation. The substrate can have a lattice constant and / or thermal expansion coefficient that is similar to or different from that of any material layer of the III-N material structure 20.

[0040] III-N material structure 20 can include a III-N buffer layer 11, such as GaN or AlGaN, grown over substrate 10. Buffer layer 11 can be made insulating or substantially free of unintentional n-type mobile carriers by including dislocations or point defects in the layer, or by doping the layer with compensating elements such as Fe, C, and / or Mg. The buffer layer can have a substantially uniform composition, or the composition can vary. For example, in some embodiments, the buffer layer is compositionally graded, such as by grading the aluminum composition in the buffer layer (e.g., the substrate can be , where x varies throughout the substrate). In other embodiments, the buffer layer is composed of GaN and The buffer layer 11 is formed by a "superlattice" structure of alternating layers. The thickness and composition of the buffer layer 11 can be optimized for high voltage applications. That is, the buffer layer can block voltages equal to and / or greater than the maximum voltage of the high voltage power supply or the circuit in which it is used. For example, the buffer layer 11 can be capable of blocking voltages greater than 600V, 900V, or 1200V in the vertical direction between the drain electrode 17 and the substrate 10. The thickness of the buffer layer 10 can be greater than 4μm, for example, the thickness of the III-N buffer layer can be between 5μm and 8μm.

[0041] The III-N material structure can also include a III-N channel layer 12 (e.g., GaN) over the III-N buffer layer 11 and a III-N barrier layer 13 (e.g., AlGaN, AlInN, or AlGaInN) over the III-N channel layer 12. The band gap of the III-N barrier layer 13 is larger than the band gap of the III-N channel layer 12. The III-N channel layer 12 has a different composition than the III-N barrier layer 13, and the thickness and composition of the III-N barrier layer 12 are selected so as to induce a two-dimensional electron gas (2DEG) channel 19 (caused by the III-N channel layer 12) in the III-N channel layer 12 adjacent to the interface between the layers 13 and 12. Figure 1A ). When the device 101 is a depletion mode device, when a zero voltage bias is applied to the device, the 2DEG channel 19 extends continuously between the source electrode 16 and the drain electrode 17. The III-N barrier layer 13 can have a first side and a second side, wherein the first side is adjacent to the III-N channel layer 12 and the second side is opposite to the first side.

[0042] Typically, III-N high electron mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) in a reactor or other technique. The III-N material structures can be grown in a Group III polar (e.g., Ga polar) orientation, such as a

[0001] (C-plane) orientation, as Figure 1AThat is, the source electrode, gate electrode and drain electrode of the HEMT are formed over the -III group plane (eg,

[0001] plane) of the III-N material structure, which is usually on the side of the III-N material structure opposite to the substrate on which the III-N layer is formed.

[0043] Alternatively, the III-N HEMT can be formed on a III-N material structure grown in an N-polarity (i.e., N-face) orientation (such as a [000-1] orientation). In this case, the source electrode, the gate electrode, and the drain electrode of the HEMT are formed over the N-face (e.g., [000-1] face) of the III-N material structure. Here, the III-N material structure can include a III-N barrier layer over the III-N buffer layer and a III-N channel layer 12 over the III-N barrier layer 13. The band gap of the III-N barrier layer 13 is greater than the band gap of the III-N channel layer 12, and the thickness and composition of the III-N barrier layer 13 are selected so as to induce a two-dimensional electron gas (2DEG) channel 19 in the III-N channel layer 12 adjacent to the interface between the III-N channel layer 12 and the III-N barrier layer 13. N-polar III-N materials have a polarization field that is opposite in direction from Group III-polar III-N materials, thus enabling implementations of III-N devices that cannot be fabricated using Group III-polar structures.

[0044] The gate dielectric layer 14 is grown or deposited over the top surface of the III-N material structure 20 and is formed in direct contact with the second side of the III-N barrier layer 14. The gate dielectric 14 can be made of, for example, aluminum oxide ( )、Silica( )、 , , , or any other wide bandgap insulator formed of or containing aluminum oxide ( )、Silica( )、 , , , Or any other wide bandgap insulator.

[0045] Source electrode 16 and drain electrode 17 are formed on the side of device 101 opposite substrate 10, so that device 101 is characterized as a lateral III-N device (i.e., the source and drain are on the same side of the device, and current flows laterally through the device between source 16 and drain 17). Source electrode 16 and drain electrode 17 are ohmically contacted and electrically connected to the device 2DEG channel 19 formed in layer 12. Source electrode 16 and drain electrode 17 (e.g., source electrode and drain electrode) can be formed by a metal stack. Recesses can be formed in III-N barrier layer 13 to allow for improved ohmic contact of source electrode 16 and drain electrode 17 to 2DEG channel 19. The metal stack can be Ti / Al / Ni / Au, Ti / Al or other suitable metals. Source electrode 16 and drain electrode 17 can be formed by sputtering and dry etching processes or other techniques such as metal evaporation and post-deposition annealing processes.

[0046] An insulating layer 15 can be formed over the gate dielectric layer 14, which is shown as a single layer. It can alternatively be formed of several layers deposited during different processing steps to form a single combined insulator layer 15. The insulating layer 15 can be formed of SiN, SiON, SiO2 or other suitable insulating materials.

[0047] A gate recess is formed in the insulating layer 15 to expose the top surface of the gate dielectric layer 14. A gate electrode 18 (e.g., a gate contact) may be at least partially formed in the recess, wherein a portion 18a of the gate electrode 18 is in direct contact with the top surface of the gate dielectric layer 14. The gate recess can include a plurality of steps extending toward the drain electrode 17, wherein a gate metal is formed above the steps to produce a field plate 18b; the field plate 18b is vertically separated from the gate dielectric layer 14 by a portion of the insulating layer 15 (e.g., the step portion). The field plate 18b can help manage the electric field in the drain-side access region. Multiple field plates may be required for effective electric field management. For example, the field plate 18b includes at least 3 different step heights (i.e., FP1, FP2, FP3), each step height increasing as the field plate extends toward the drain 17. The gate electrode 18 may be formed of a suitable conductive material such as a metal stack, for example, titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au), and can be deposited by metal evaporation or sputtering or chemical vapor deposition or various atomic layer deposition (ALD). The gate electrode 18 may alternatively be another conductive material or material stack containing one or more materials with a large work function, such as a semiconductor material with a large work function (e.g., p-type polysilicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride).

[0048] When the device 101 is a depletion mode device, a dielectric layer 14 is formed between the gate electrode 18 and the III-N barrier layer 13. The thickness of the dielectric layer 14 determines the threshold voltage of the device (ie, ), such that the threshold voltage of the device 101 becomes more negative as the thickness of the dielectric layer 14 increases. Alternatively, the gate recess can extend through the gate dielectric layer 14 so that the gate electrode 18 contacts the III-N material structure 24 (not shown) or is recessed within the III-N material structure 24 to create an enhancement mode device.

[0049] As previously described, when device 101 is a depletion mode device, it can be arranged in a cascode configuration with a low voltage enhancement mode FET device 21 to form a hybrid device 100. The hybrid device 100 can be arranged and assembled into a discrete electronic component package 102. The electronic component package 102 can have at least three terminals. A first terminal 25 is electrically connected to the drain electrode 17. A second terminal 23 is electrically connected to the source of the FET device 21 and the gate electrode 18 of the device 101. The third terminal 22 of the device is electrically connected to the gate of the FET device 21.

[0050] The source electrode 16 and the drain electrode 17 can be formed on the III-N device 101 using a variety of techniques. One common method is to deposit a continuous ohmic metal layer (e.g., by sputtering deposition) on the top surface of the device 101. Next, the ohmic metal layer is patterned with a photoresist to cover and protect the source and drain electrode regions, and the remaining unprotected metal layer is etched away (e.g., by a dry etching process) to form the source electrode 16 and the drain electrode 17.

[0051] Due to the limitations of photolithography tolerance and etching technology, generally, the extended portions of the source electrode and the drain electrode remain above the gate dielectric layer 14 and / or the insulating layer 15. Figure 1A As shown, the extended drain electrode portion 17' extends into the drain side access region 27 towards the gate electrode 18, and the extended source electrode portion 16' extends into the source side access region 26 towards the gate electrode 18. Typically for power devices manufactured in conventional CMOS manufacturing, the lengths of the extension portions 16' and 17' can be in the range between 0.25 μm and 1 μm (along the channel length). Figure 1A As shown, a portion of gate dielectric layer 14 and a portion of insulating layer 15 are formed between drain electrode extension 17' and III-N barrier layer 12. In addition, a portion of gate dielectric layer 14 and a portion of insulating layer 15 are formed between source electrode extension 16' and III-N barrier layer 12.

[0052] In some configurations, a portion of the insulating layer 15 may not exist under the extended electrode portion 16' or 17'. In such a configuration, the bottom surface of the extended portion can be in direct contact with the top surface of the dielectric layer 14. For example, if the dielectric layer 14 is formed of in-situ MOCVD SiN, the thickness of the SiN under the drain protrusion 17' will be approximately equal to the thickness of the MOCVD SiN layer 14. However, maintaining the high integrity of the MOCVD SiN layer is an important factor in device performance. One way to maintain the integrity of the gate dielectric is to deposit a sacrificial etch stop SiN layer on top of the gate dielectric layer 14. One manufacturing technique is to use an etch stop layer that is approximately equal to the step height of the first field plate (i.e., FP1) of the multi-field plate system 18b. In this case, the thickness of the insulating layer 15 and the portion of the dielectric layer 14 under the drain protrusion 17' will be approximately equal to the thickness of the SiN under FP1 plus the thickness of the gate dielectric 14. The thickness of the portion of the insulating layer 15 and the dielectric layer 14 under the drain protrusion 17 ′ can be 200 nm, 100 nm, or less.

[0053] For the purposes of this specification, the source side access region 26 is defined as the region between the portion of the source electrode 16 in contact with the 2DEG channel 19 and the portion of the gate electrode 18a in contact with the gate dielectric layer 14, as measured at the plane of the top surface of the dielectric layer 14. Figure 1A Similarly, the drain side access region 27 is defined as the region between the portion of the gate electrode 18a in contact with the gate dielectric layer and the portion of the drain electrode 17 in contact with the 2DEG channel 19, measured at the plane of the top surface of the dielectric layer 14, as shown in FIG. Figure 1A shown.

[0054] refer to Figure 1B , when III-N device 101 is a depletion mode device, it can operate as follows: gate electrode 18 and substrate 10 are electrically connected to circuit ground. Source electrode 16 is biased to a voltage higher than the gate-to-source threshold voltage ( ), the 2DEG channel 19 is depleted, thereby forming a depletion region 19a under the gate electrode 18. The 2DEG channel 19 is no longer continuous between the source electrode 16 and the drain electrode 17, and the device is considered to be "off". Applying a positive drain-to-source voltage (i.e., ), as the drain-source voltage further increases, the 2DEG channel 19 is further depleted in the drain-side access region 27. Figure 1B As shown, a portion 19 ′ of the 2DEG channel can remain in the drain side access region 27 near the drain electrode 17 , and a portion 19 ″ can remain in the source side access region 26 near the source electrode 16 .

[0055] When the drain-to-source voltage is high enough, the 2DEG channel is fully depleted, i.e., the depletion region 19a reaches the drain electrode. The drain voltage at which the 2DEG is fully depleted depends on at least three factors: (1) the 2DEG charge density - higher 2DEG charge density requires higher drain voltage to achieve full depletion, (2) the buildup of lateral electric fields due to capacitive coupling between the drain electrode 17 and the gate electrode 18, which is determined by the design of the field plate 18 and the length of the drain-side access region 27, and (3) the buildup of vertical electric fields due to capacitive coupling between the drain electrode 17 and the conductive substrate 10, a phenomenon hereinafter referred to as "back gating". The amount of 2DEG depletion caused by the back gating effect is determined by the applied drain-to-substrate potential ( ), the thickness and resistivity uniformity of the III-N buffer layer 11 are determined. For a given applied For a given thickness of the III-N buffer layer 11, the back-gate effect is stronger, i.e., there is more 2DEG depletion if the lower part of the III-N buffer layer 11 is less insulating and less resistive than the upper part of the III-N buffer layer 11. In this case, charge redistribution occurs within the III-N buffer layer 11, and for a given applied , the stronger capacitive coupling between the drain electrode 17 and the substrate 10 leads to more 2DEG depletion. This effect is known in the literature as the Maxwell-Wagner effect (see Digital Object Identifiers 10.1109 / TED.2017.2706090 and Digital Object Identifiers 10.1109 / TED.2006.877700). The drain-to-substrate voltage at which the 2DEG is fully depleted ( ) is hereafter referred to as the drain-to-substrate pinch-off voltage ( ).

[0056] If the III-N device 101 (specifically, the III-N buffer layer 11 ) is designed so that the drain to substrate pinch-off voltage ( ) is less than the device's maximum rated source-to-drain operating voltage ( V TR(DSS) ), then if Greater than The voltage bias of 2DEG channel 19 / 19' (such as Figure 1B As shown) will be completely depleted to the drain electrode 17. V TR(DSS) Can be compared at least 50V higher. When this operating condition occurs (see Figure 1C), the dielectric layer 14 and the insulating layer 15 are forward-biased, and negative charges 28 are injected into the dielectric layer 14 and / or the insulating layer 15 under the drain electrode extension 17', as shown by the dashed region 30. Some of the negative charges 28 can be "trapped" in the insulating layer and are not easily removed. Next, when the III-N device 101 is switched "on", the 2DEG channel charge under the extension 17' decreases, resulting in an overall increase in the on-resistance of the device 101. Significant current collapse can be observed during high-voltage switching operations at or near the maximum drain-to-source rated voltage of the device.

[0057] A possible solution to prevent complete 2DEG depletion (pinch-off) and mitigate charge trapping under the drain electrode extension 17' is to increase the 2DEG charge density. However, due to the higher 2DEG charge, this solution will lead to other reliability issues associated with the increased electric field, resulting in premature failure of the gate electrode 18 during lifetime operation. Therefore, other solutions may be required.

[0058] Figure 2A A cross-sectional view of a III-N device 201 similar to Figure 1A is shown. The III-N device 201 can be an enhancement-mode device (i.e., normally-off) or a depletion-mode device (i.e., normally-on). In the case where the device 201 is a depletion-mode device (D-type), the device 201 can be in a cascode configuration with a low-voltage enhancement-mode device 21 (e.g., a silicon-FET) to form a normally-off hybrid device 200 that can operate in a manner similar to a single enhancement-mode III-N device.

[0059] Figure 2A The III-N device 201 of Figure 1A differs from the III-N device 101 of in that the III-N device 201 includes an engineered III-N buffer structure 220 to increase the drain-to-substrate pinch-off voltage to greater than the maximum rated operating voltage of the device. The engineered III-N buffer structure 220 can include a nucleation layer 221, such as AlN grown at low temperature, high temperature, or a stack thereof. The III-N buffer structure 220 can further include a high aluminum composition III-N layer 222 (such as ), and a medium aluminum composition III-N layer 223 (such as ). For example, the layer 222 can have a Ratio, where 40% < x < 70%. Layers 222 and 223 can have a thickness between 0.2 μm and 1.0 μm. For example, the high-aluminum-component III-N layer 222 can have a thickness of ~0.5 μm, and the medium-aluminum-component III-N layer 223 can have a thickness of ~0.6 μm. The III-N buffer structure 220 can also include a III-N stack 224 / 225, where the stack 224 / 225 is a structure of repeating stacked layers including AlN / GaN, AlN / or / GaN or any combination thereof. For example, the thickness of the III-N stack 224 can be between 0.5 μm and 1.5 μm, including AlN / repetition of stacked layers, where the thickness of the AlN layer can be between 0.5 nm and 5 nm, and the thickness of the layer can be between 10 nm and 50 nm, where the x component is between 5% and 20%. The thickness of the III-N stack 225 can be between 0.5 μm and 1.5 μm, including repetition of AlN / GaN stacked layers, where the thickness of the AlN layer can be between 0.5 nm and 5 nm, and the thickness of the GaN layer can be between 10 nm and 50 nm. The III-N stack 224 / 225 can be doped with iron, carbon, or other deep donor or deep acceptor agents to prevent the formation of parasitic 2DEG and 2DHG at the interfaces between AlN / GaN, AlN / or / GaN layers.

[0060] Compared with the standard III-N buffer layer 11 described in Figure 1A , the engineered III-N buffer structure 220 can increase the drain-to-substrate pinch-off voltage. For example, the drain-to-substrate pinch-off voltage can be greater than 750 V and the maximum rated drain-to-source operating voltage can be less than 750 V. The implementation of the buffer structure 220 can prevent the complete depletion of the 2DEG channel 19' in the region below the drain electrode extension 17', and prevent the forward biasing of the gate dielectric layer 14 and / or the insulating layer 15 to reduce negative charge trapping and current degradation. The thickness of the engineered III-N buffer structure 220 can be less than 6 µm. The engineered III-N material structure can have a breakdown voltage greater than 750 V.

[0061] To measure the effects of 2DEG depletion and current collapse caused by the back-gate effect and subsequent electron trapping into the dielectric layer 14 and / or the insulating layer 15 below the drain electrode extension 17', a test circuit as shown in Figure 2B can be used. Using a simplified circuit schematic 210 that does not require connection of the gate electrode 18 (for simplicity, Figure 2B1 ). In addition, for simplicity, the engineered III-N buffer structure 220 is not shown. The drain-to-source potential is set to a low voltage (e.g., 1V), a first drain-source current is measured, and a first on-state resistance is calculated. The magnitude of the drain-source current gives an indication of the 2DEG channel density. The voltage between the drain electrode 17 and the substrate 10 is swept from 0V (sweep 1) to the maximum drain-to-source operating voltage (V TR(DSS) ), while measuring the current between the drain and source ( ). The voltage scan rate can be greater than 1 V / s. Since V is kept constant, in order to increase the drain-to-substrate potential during the test, the voltage of substrate 10 is scanned to a negative value relative to the voltage of drain electrode 17. The drain-to-substrate voltage can be maintained at V TR(DSS) The hold time is for a minimum of 2 minutes. This hold time is to ensure sufficient operating stress on the device. Next, the substrate voltage is scanned (Scan 2) back to 0V, a second drain-source current is measured, and a second on-state resistance is calculated. For the purposes of this specification, it is assumed that the first drain-source current measurement and the second drain-source current measurement are completed within 1 hour of each other.

[0062] Figure 2C and Figure 2D Shows the comparison based on Figure 1A The device 101 is manufactured according to the device Figure 2A The graphical data of the measurement results of the actual back gate measurement between the devices manufactured by the device 201. Specifically refer to Figure 2C , the drain-to-substrate voltage gradually increases from 0V to the maximum rated voltage of 252 (V TR(DSS) = e.g., 725V) (forward sweep 250) and from V TR(DSS) The drain-source current is recorded during the forward scan 250 and the backward scan 251. During the forward scan 250, the drain-source current reaches 0A around 600V, indicating back gate pinch-off 253 and Reach V TR(DSS) The previous full 2DEG is depleted. This situation causes the forward bias of the dielectric layer 14 and the insulating layer 15 under the drain electrode extension 17, and the charge is trapped in the dielectric layer 14 and / or the insulating layer 15 under the drain electrode extension 17', resulting in the severe current degradation observed in the backward scan 251. Figure 2C As shown, the starting Id is -0.05 A / mm and the ending Id is -0.015 A / mm, indicating that the current is reduced by more than 50% and the on-state resistance is increased by more than 100%.

[0063] Figure 2D2 shows back gate test results of a device manufactured according to the device 201 with the engineered III-N buffer structure 220. Figure 2D As shown, when the voltage sweep reaches 252, the 2DEG is never fully depleted ( > V TR(DSS) ), as shown by the current > 0 when the voltage sweep reaches 252. Charge trapping mechanisms are prevented and virtually no current degradation is observed for device 201. However, the development of an engineered III-N buffer structure such as structure 220 can be expensive and time consuming. Furthermore, an engineered III-N buffer structure such as structure 220 does not prevent charge trapping issues beneath the drain electrode extension 17' if the 2DEG is completely depleted due to the buildup of lateral electric fields caused by capacitive coupling between the drain electrode 17 and the gate electrode 18. This situation can occur in aggressively designed devices with highly scaled gate-drain side access regions 27 aimed at reducing specific on-resistance and overall chip size. Therefore, other solutions may be needed.

[0064] Figure 2E Box plot data of additional test results are shown, which also illustrate the performance of devices fabricated according to device 201 . Figure 2E shows the on-resistance (i.e., ) increases with the time of a particular stress test. Devices manufactured according to device 201 were subjected to high temperature reverse bias (i.e., HTRB) testing. The test conditions were as follows: the source to drain voltage was biased at 750V, while the gate to source voltage was biased less than the threshold voltage; the temperature was maintained at 175°C; the voltage was maintained for 1,000 hours. The test was performed as follows. The on-resistance of the device was measured before HRB (time = 0), the HTRB stress was then performed, and the on-resistance of the device was measured again with intervals of 250 hours, 500 hours, and 1,000 hours. The on-resistance ( ) drawn on Figure 2E In. Figure 2E As shown, the median on-resistance increase of the device at time 0 is ~30mΩ. After 250 hours of HTRB stress, the median on-resistance increases, but is still below 35mΩ and the on-resistance increase is less than 20%. After 500 hours and 1000 hours of stress, respectively, the median on-resistance is still below 35mΩ, and the on-resistance increase of all tested devices after HTRB stress is less than 20% under the conditions described previously. These results confirm the effectiveness of the present invention.

[0065] Figure 3A Shows something like Figure 1A1 is a cross-sectional view of a III-N device 301 of the III-N device 101. The III-N device 301 can be an enhancement mode device (i.e., normally off) or a depletion mode device (i.e., normally on). In the case where the device 301 is a depletion mode device (D-type), the device 301 can be in a cascode configuration with a low voltage enhancement mode device 21 (e.g., a silicon-FET) to form a normally-off hybrid device 300 that can operate in a manner similar to a single enhancement mode III-N device.

[0066] Figure 3A The III-N device 301 with Figure 1A The III-N device 101 is different in that, as shown in the dashed area 30, the III-N device 301 does not include the gate dielectric layer 14 and / or the insulating layer 15 formed below the drain electrode extension 17'. Instead, the drain electrode extension 17' is formed "on" the III-N barrier layer 13 and is in direct contact with the second side of the III-N barrier layer 13. In addition, the III-N device 301 can optionally not include the gate dielectric layer 14 and / or the insulating layer 15 formed below the source electrode extension 16'. Instead, the source electrode extension 16' is formed on the second side of the III-N barrier layer 13 and is in direct contact with the second side of the III-N barrier layer 13. By removing the gate dielectric layer 14 and / or the insulating layer 15 below the extensions 16' / 17', negative charge is no longer trapped, thereby eliminating or reducing current degradation. Since there is no source electrode extension 16', the negative charge is no longer trapped, thereby eliminating or reducing current degradation. Figure 1A The 2DEG channel can be fully depleted from the substrate all the way to the drain electrode without causing current degradation. Therefore, it is possible to manufacture devices with a substrate-to-drain pinch-off voltage that is lower than the maximum operating voltage of the device without causing performance issues.

[0067] Although not shown for simplicity, the device 301 can also include a conductive interlayer formed between the drain and / or source extensions 16' / 17' and the III-N barrier layer 13. The interlayer can be an etch stop layer to assist the manufacturing process of the source electrode and / or the drain electrode. When etched under similar conditions, the etch rate of the etch stop layer can be less than the etch rate of the source electrode and / or the drain electrode. The etch stop layer should be a conductive material to allow a path for charge to move between the drain electrode and the III-N barrier layer. The etch stop layer can be, for example, TiN, TiW, Ni, or silicon (e.g., sputtered silicon). The etch stop layer can have a thickness between 5nm and 100nm. The etch stop layer can have a thickness of less than 100nm.

[0068] Figure 3BThe back gate test results on the device 301 with the modified drain electrode region 17' are shown. The drain-to-substrate voltage is gradually increased from 0V to the maximum rated voltage 352 (V TR(DSS) = e.g., 1100V) (forward sweep 350), and from V TR(DSS) The drain-source current is recorded during the forward scan 350 and the backward scan 351. During the forward scan 350, the drain-source current reaches 0A around 650V, indicating back gate pinch-off 353 and Reach V TR(DSS) The previous full 2DEG is depleted. Figure 3B As shown, V TR(DSS) 352 However, since the dielectric layer 14 and / or the insulating layer 15 are not present under the drain electrode extension 17', the charge trapping mechanism is prevented, resulting in a significant reduction in current degradation. Figure 3B As shown, the starting Id is ~0.155A / mm and the ending Id is ~0.125A / mm, indicating that the current decrease is less than 20% and the on-state resistance increase is less than 25%. Figure 2C The results demonstrate a significant improvement in performance when compared to the results shown for device 101.

[0069] This result is unexpected. As previously mentioned, the length of drain electrode extension 17 can typically be 0.5 μm, and the length range is between 0.25 μm-1.0 μm. In a high voltage III-N power device such as device 101, this represents less than 2% of the total source to drain spacing. At the time of the present invention, it is not obvious that such a small drain / insulator overlap area could cause such a large current degradation. However, Figure 3B The results shown in clearly demonstrate that current collapse can be reduced.

[0070] Figure 3C A box plot of the test results is shown, which also shows the Figure 3A The device 301 is manufactured according to Figure 1A The device 100 has performance benefits compared to the device manufactured. Figure 3C shows the on-resistance after a specific stress test (i.e., ) percentage increase. Device 301 and device 100 were subjected to high temperature reverse bias (ie, HTRB) testing. The test conditions were as follows: source to drain voltage biased at 750V, while gate to source voltage biased less than the threshold voltage; temperature maintained at 175°C; voltage bias maintained for 1,000 hours. The test was performed as follows. The on-resistance of the device was measured before HTRB stress, the HTRB test was then performed, and the on-resistance of the device was measured again (after HTRB). Figure 3C As shown, the median on-resistance of device 100 increased by more than 70%. However, when device 301 was tested under the same conditions, the median on-resistance increased by less than 20%, and all devices showed an on-resistance increase of less than 30% after HTRB. These results confirm the effectiveness of the present invention.

[0071] Figure 4A Shows something like Figure 3A 4 is a cross-sectional view of a III-N device 401 of the III-N device 301 of FIG. The III-N device 401 can be an enhancement mode device (i.e., normally off) or a depletion mode device (i.e., normally on). In the case where the device 401 is a depletion mode device (D-type), the device 401 can be in a cascode configuration with a low voltage enhancement mode device 21 (e.g., a silicon-FET) to form a normally off hybrid device 400 that can operate in a manner similar to a single enhancement mode III-N device. The III-N device 401 differs from the III-N device 301 in that the device 401 includes an n-type III-N contact layer 40 formed under the drain electrode 17 and an n-type III-N contact layer 40' formed under the source electrode 16. The n-type III-N contact layer 40 / 40' can be formed by implantation or by regrowth using a dopant such as silicon. The source electrode 16 and the drain electrode 17 form an ohmic contact with the n-type III-N contact layer 40 / 40', which can be a high quality ohmic contact with very low resistance. The length of the n-type contact layer 40 can be greater than the length of the drain electrode 17 (both measured along the channel length). The n-type contact layer 40 can include a first portion directly below and in ohmic contact with the drain electrode 17 and a second portion extending into the drain side access region 27, so that there is no drain electrode extension portion 17' in the device 401. Figure 4A As shown, when the n-type III-N contact layer 40 is extended into the drain side access region and the drain electrode extension portion is eliminated, charge trapping near the drain electrode can be eliminated and current collapse can be reduced.

[0072] Figure 4B Shows something like Figure 1A4 is a cross-sectional view of a III-N device 402 of the III-N device 101. However, the III-N device 402 includes a drain extension portion 17' and a source electrode extension portion 16'. The n-type III-N contact layer has a first end extending into the drain side access region 27 toward the gate electrode 18. The first end of the n-type III-N layer 40 extends further into the drain side access region than the drain electrode extension portion 17'. The first end of the n-type III-N layer 40' extends further toward the gate 18 than the source electrode extension portion 16'. The 2DEG channel 19 extends between the first end of the n-type III-N layer 40' and the first end of the n-type III-N layer 40. Therefore, no portion of the 2DEG channel 19 is formed under the source electrode extension portion 16' or the drain electrode extension portion 17'. As shown in FIG. Figure 4B As shown, an insulating layer 15 can be formed between the drain electrode extension portion 17' and the n-type III-N layer 40, however, since the device design has no 2DEG channel under the extension portion, negative charge capture in the insulating layer 15 under the portion 17' will be prevented and current degradation will be prevented.

[0073] Figure 5 Shows something like Figure 1A1 . A cross-sectional view of a III-N device 501 of the III-N device 101 of FIG. 1 . The III-N device 501 can be an enhancement mode device (i.e., normally off) or a depletion mode device (i.e., normally on). In the case where the device 501 is a depletion mode device (D-type), the device 501 can be in a cascode configuration with a low voltage enhancement mode device 21 (e.g., a silicon-FET) to form a normally-off hybrid device 500 that can operate in a manner similar to a single enhancement mode III-N device. The III-N device 501 differs from the III-N device 101 in that the device 501 includes a second 2DEG channel under the drain electrode extension 17 ′ and optionally a second 2DEG channel under the source electrode extension 16 ′. The second 2DEG channel is caused by a composition mismatch between the second III-N channel layer 52 and the second III-N barrier layer 51. The layers 51 and 52 can be initially formed or grown continuously over the first III-N barrier layer 13 and extend between the drain electrode 17 and the source electrode 16 . Then, the second channel layer 52 and the second barrier layer 51 can be removed or etched away in the region inserted from the source extension 16' and the drain extension 17', so that the remaining end of the layer 51 / 52 is closer to the gate electrode 18 than the extension 16' / 17'. The gate dielectric 14 can be formed in the inserted region. A second 2DEG channel is formed under the extension, which will shield the portion of the insulating layer 15 under the drain electrode extension 17' from becoming forward biased when the main 2DEG channel 19 is fully depleted. In addition, the second 2DEG channel formed in the second channel layer will significantly increase the drain to substrate pinch-off voltage. When the device 501 is operated at the maximum rated drain to source voltage, this will prevent the main 2DEG channel 19 from becoming fully depleted under the drain extension 17'.

[0074] Figure 6 Shows something like Figure 1A6 is a cross-sectional view of a III-N device 601 of the III-N device 101 of FIG. The III-N device 601 can be an enhancement mode device (i.e., normally off) or a depletion mode device (i.e., normally on). In the case where the device 601 is a depletion mode device (D-type), the device 601 can be in a cascode configuration with a low voltage enhancement mode device 21 (e.g., a silicon-FET) to form a normally-off hybrid device 600 that can operate in a manner similar to a single enhancement mode III-N device. The III-N device 601 differs from the III-N device 101 in that the device 601 includes a III-N spacing layer 61 (e.g., UID GaN) formed over the III-N channel layer 13 and a p-type III-N layer 62. Portions of the p-type III-N layer 61 can be etched away in the source and drain access regions. The remaining portion 62 is directly below and in direct contact with the drain extension 17'. The portion 62' is directly below and in direct contact with the gate electrode 18. Portion 62" is directly below and in direct contact with source electrode extension portion 61'. A first end of retained portion 62 extends further toward gate electrode 18 in drain-side access region 27 than drain extension portion 17', and a first end of retained portion 62" extends further toward gate electrode 18 than source-side extension portion 16'. III-N spacing layer 61 acts as a diffusion barrier to prevent / limit p-type dopants of III-N layer 62 from reducing 2DEG channel charge. Figure 1A As shown in the device 101, the device can be without a gate dielectric layer 14. The gate dielectric 14 is usually grown in situ in a MOCVD reactor and also causes significant maintenance and throughput issues for MOCVD. Having a device without a gate dielectric can greatly reduce the cost and time of the manufacturing process. Device 601 is a JFET type device.

[0075] Figure 7 Shows something like Figure 3A 7 is a cross-sectional view of a III-N device 701 of the III-N device 301. The III-N device 701 can be an enhancement mode device (i.e., normally off) or a depletion mode device (i.e., normally on). In the case where the device 701 is a depletion mode device (D-mode), the device 701 can be in a cascode configuration with a low voltage enhancement mode device 21 (e.g., a silicon-FET) to form a normally-off hybrid device 700 that can operate in a manner similar to a single enhancement mode III-N device. The III-N device 701 differs from the III-N device 301 in that the III-N material structure 20 is formed on an insulating substrate 70 (e.g., a sapphire or SiC substrate) rather than a substrate. Figure 3A On the conductive silicon substrate 10 described in . Figure 1ADevice 101 can also be fabricated on an insulating substrate (such as substrate 70), but severe current degradation may occur. Insulating substrates are advantageous for reducing the electric field in the buffer layer and enabling high voltage lateral GaN HEMT devices with a voltage rating >650V, for example greater than 1200V, without the need for thick epitaxial III-N buffer layer growth (such as buffer layer 11). However, such devices require lateral high voltage blocking regions which can increase the die size and therefore the die cost. One way to reduce the die size is to increase the 2DEG channel charge density, however this can lead to reliability issues due to the increased electric field. Another way is to reduce the length of the drain side access region 27 (measured along the channel length). This increases the capacitive coupling between the gate electrode 18 and the drain electrode 17. Due to this increased coupling, the 2DEG may become fully depleted when a high voltage is applied to the drain terminal, resulting in the trapping of negative charges in layer 14 and / or layer 15 under the drain electrode extension 17'. This may result in the device increases, thus increasing the current degradation under operation. Figure 7 The device 701 shown in FIG. 7 , in which layer 14 and / or layer 15 are eliminated under the drain electrode extension 17 ′, can solve this potential problem and help realize reliable and low-cost high voltage lateral GaN devices on insulating substrates.

[0076] Figure 8 (a)-(d) show Figure 3A The method for manufacturing the device 301 is as follows. Figure 8 As shown in (a), a III-N material structure is formed on a substrate (not shown). The III-N material structure includes a III-N buffer layer 11 (e.g., AlGaN / GaN), a III-N channel layer 12 (e.g., UID GaN), and a III-N barrier layer 13 (e.g., AlGaN). A gate dielectric layer 14 is continuously formed on the top surface of the III-N material structure. Figure 8 As shown in (b), the gate dielectric layer is removed or etched (for example, dry etching in the region where the source electrode and the drain electrode are to be formed). Figure 8 As shown in (c), a portion of the III-N barrier layer can be removed or etched away. The remaining portion of the gate dielectric layer 14 is smaller than the remaining portion of the III-N channel layer 13. The recess formed in the III-N barrier layer can help improve the ohmic contact of the source / drain connection with the 2DEG. Figure 8(d) of FIG. 1 . The source electrode 16 and the drain electrode 17 are formed in the removed portion of the III-N barrier layer 13. The drain extension 17 ′ and the source extension 16 ′ are formed above the top surface of the III-N barrier layer 13. The device can be further annealed at a high temperature (e.g., greater than 500° C.) to form an ohmic contact with the 2DEG. A gap 81 is between the end of the extension 17 ′ and the end of the gate dielectric layer 14 closest to the drain electrode 17. The gap 81 can be between 0.1-2 μm, but is ideally kept as small as possible.

[0077] Fig. 9 (a)-(d) show a method 901 for manufacturing a drain electrode 91 without Figure 1A The drain electrode extension portion 17' shown in FIG. Fig. 9 As shown in (a), a III-N material structure is formed on a substrate (not shown). The III-N material structure includes a III-N buffer layer 11 (e.g., AlGaN / GaN), a III-N channel layer 12 (e.g., UID GaN), and a III-N barrier layer 13 (e.g., AlGaN). A gate dielectric layer 14 is continuously formed over the top surface of the III-N material structure 20. An insulating layer 15 is continuously formed over the top surface of the gate dielectric layer 14.

[0078] like Fig. 9 As shown in (b), a recess is formed in the insulating layer 15, the dielectric layer 14 and the III-N barrier layer 13 (e.g., by dry etching). A metal contact layer (e.g., Ti / Al) is deposited within the recess and continuously deposited over the top surface of the insulating layer 15. The metal contact layer is then patterned and etched to form a drain electrode 91 having a drain electrode extension 91'. The drain electrode 19 is patterned in such a way that the top width of the drain is greater than the width of the recess in order to ensure good metal coverage within the recess and high quality ohmic contact of the drain electrode with the 2DEG channel 19. The insulating layer 15 is used to protect the gate dielectric layer 14 during the metal etching step for forming the drain electrode 91.

[0079] However, as previously mentioned, having insulating material between the drain electrode extension 91' and the 2DEG channel 19 may lead to negative charge trapping and current degradation. Another way to reduce this current degradation is to remove the drain extension 19'. Fig. 9 As shown in (c), a photoresist layer 93 is patterned over the drain electrode 91 and inserted from the drain electrode extension portion 91 ′.

[0080] Then, if Fig. 9As shown in (d), the device is subjected to an isotropic chemical wet etching process that is selective to the drain electrode metal stack. The corners of the drain extension 19' are etched at a faster rate than the sidewalls, thereby creating a concave profile under the photoresist layer 93. The photoresist layer 93 is then removed and a drain electrode without a protrusion is formed, and current degradation is reduced. Although Fig. 9 The process 901 shown in (a)-(c) describes a method of forming a drain electrode, but the same process can be used simultaneously to form a source electrode without an extension portion.

[0081] Alternatively, another embodiment and manufacturing method can be used to achieve similar performance improvements as those described in device 301. Although Figure 3A Device 301 of FIG. 3 shows a drain extension 17 ′ in direct contact with the III-N barrier layer 13 , but also shows improved on-resistance by significantly increasing the thickness of the insulating portion 15 formed below the drain extension 17 ′.

[0082] Fig. 10A Shows something like Figure 1A 1 is a cross-sectional view of a III-N device 110 of the III-N device 100. The III-N device 110 can be an enhancement mode device (i.e., normally off) or a depletion mode device (i.e., normally on). In the case where the device 110 is a depletion mode device (D-type), the device 110 can be in a cascode configuration with a low voltage enhancement mode device 21 (e.g., a silicon-FET) to form a normally-off hybrid device 700 that can operate in a manner similar to a single enhancement mode III-N device. The III-N device 110 differs from the III-N device 100 in that, unlike the Figure 1A Compared to device 100 of the present invention, the thickness of insulating portions 15 and / or 14 formed under drain extension portion 17 ″ is significantly increased. For example, the total thickness of the insulating material (i.e., layer 14 plus layer 15) formed under the drain extension portion of device 100 can be less than 100 nm. However, in device 110, the total thickness of the insulating material formed under drain extension portion 17 ′ can be more than 500% greater than that of device 100. The total thickness of the insulating material can be greater than 300 nm, greater than 500 nm, for example, between 500 nm and 1,000 nm.

[0083] like Fig. 10AAs shown, the device 110 includes a multi-field plate structure 18b. The field plate structure 18b includes a first portion c' (i.e., a first field plate), a second portion d' (i.e., a second field plate), and a third portion e' (i.e., a third field plate), wherein each field plate has an increasing step height between the corresponding field plate and the top of the III-N barrier layer 13 as the field plate extends toward the drain electrode. The third field plate e' has a step height h' above the barrier layer 13. The step height h'' of the drain protrusion 17' of the device 110 is at least equal to or greater than the step height h' of the third field plate. The device 110 can also have more than three field plates, for example, the device 110 can have four field plates (not shown), and the step height h'' can be less than the fourth field plate step height, but greater than the third field plate step height.

[0084] Fig. 10B 1 shows the back gate test results on device 110. The drain-to-substrate voltage is gradually increased from 0V to the maximum rated voltage 452 (V TR(DSS) = e.g., 1000V) (forward sweep 450) and from V TR(DSS) The drain-source current is recorded during the forward scan 450 and the backward scan 451. During the forward scan 450, the drain-source current reaches 0A around 650V, indicating back gate pinch-off 453 and Reach V TR(DSS) The previous full 2DEG is depleted. Fig. 10B As shown, V TR(DSS) 452 453 is greater than 100 V. However, since the dielectric layer 14 and / or the insulating layer 15 are relatively thick below the drain electrode extension 17 ′, the charge trapping mechanism is reduced, resulting in a significant improvement in current degradation. Fig. 10B As shown, the starting normalized Id is 1 and the ending Id is ~0.9, which indicates that the current decrease is less than 20% and the on-state resistance increase is less than 25%. Figure 2C The results demonstrate a significant improvement in performance when compared to the results shown for device 101.

[0085] A number of implementations have been described. However, it will be appreciated that various modifications can be made without departing from the spirit and scope of the techniques and apparatus described herein.

Claims

1. A III-N device, comprising: Conductive substrate; as well as a III-N material structure comprising a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein a composition difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein; a source electrode, a gate electrode and a drain electrode; wherein The gate electrode is electrically connected to the conductive substrate, and the drain electrode includes a first portion and a second portion; The first portion of the drain electrode is in ohmic contact with the 2DEG channel, and the second portion of the drain electrode extends over and in direct contact with a top surface of the III-N barrier layer; wherein The device includes a drain-to-substrate pinch-off voltage and a maximum rated drain-to-source operating voltage, wherein the maximum rated drain-to-source operating voltage is greater than the drain-to-substrate pinch-off voltage; and The 2DEG channel is fully depleted of charge under the second portion of the drain electrode when the III-N device is biased at the maximum rated drain-to-source operating voltage.

2. The III-N device of claim 1, wherein: The device also includes a gate dielectric layer formed between the top surface of the III-N barrier layer and the gate electrode, wherein the gate dielectric layer includes a first end extending toward the drain electrode and a second end extending toward the source electrode, a spacing between the first end and the drain electrode is between 0.1 μm and 2 μm, and the spacing is filled with an insulating material having a composition different from that of the gate dielectric layer.

3. The III-N device of claim 2, wherein: The device intentionally lacks any dielectric or insulating material between the drain electrode and the III-N material structure.

4. The III-N device of claim 1, wherein: The device has a maximum rated drain-to-source operating voltage greater than 600V and a drain-to-substrate pinch-off voltage less than 600V.

5. The III-N device of claim 4, wherein: The device has a first on-state resistance when the drain-to-source voltage is held constant at a low voltage, wherein the device has a second on-state resistance when the drain-to-substrate voltage is swept from the low voltage to the maximum rated drain-to-source voltage and back to the low voltage, and the first on-state resistance is within 25% of the second on-state resistance.

6. The III-N device of claim 4, wherein: The first on-state resistance I DS In the second on-state resistance I DS Within 20%.

7. The III-N device of claim 1, wherein: The source electrode includes a first portion and a second portion, the first portion being in ohmic contact with the 2DEG channel and the second portion extending above and in direct contact with the top surface of the III-N barrier layer.

8. The III-N device of claim 7, wherein: The device is a depletion mode device, and the enhancement mode low voltage Si-FETs are arranged in a cascode configuration to form a hybrid enhancement mode III-N device.

9. The III-N device of claim 1, wherein: The 2DEG channel under the second portion of the drain electrode is depleted from a vertical electric field between the drain electrode and the conductive substrate when the drain-to-source voltage is at the maximum rated operating voltage.

10. A III-N device comprising: Conductive substrate; as well as a III-N material structure comprising a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein a composition difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein; a source electrode, a gate electrode and a drain electrode; wherein The drain electrode comprises a first portion and a second portion; The first portion of the drain electrode is in ohmic contact with the 2DEG channel, and the second portion of the drain electrode extends over and in direct contact with a top surface of the III-N barrier layer; wherein The device includes a drain-to-substrate pinch-off voltage and a maximum rated drain-to-source operating voltage, wherein the maximum rated drain-to-source operating voltage is at least 50V greater than the drain-to-substrate pinch-off voltage; and The device has a first on-state resistance when the drain-to-source voltage is maintained constant at a low voltage, wherein the device has a second on-state resistance when the drain-to-substrate voltage is swept from the low voltage to the maximum rated drain-to-source voltage, maintained at the maximum rated voltage for at least 2 minutes, and swept back to the low voltage, and the first on-state resistance is within 25% of the second on-state resistance.

11. The III-N device of claim 10, wherein: The device has a maximum rated drain-to-source operating voltage of at least 650 V and a drain-to-substrate pinch-off voltage of 600 V or less.

12. The device according to claim 10, wherein The first on-state resistance I DS In the second on-state resistance I DS Within 20%.

13. The device according to claim 10, wherein The 2DEG channel is fully depleted of charge under the second portion of the drain electrode when the III-N device is biased at the maximum rated drain-to-source pinch-off voltage.

14. A III-N device comprising: Conductive substrate; as well as a III-N material structure comprising a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein a composition difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein; and The III-N buffer layer includes at least five different layers increasing in sequence from a first side of the III-N buffer layer adjacent to the substrate to a second side of the III-N buffer layer adjacent to the III-N channel layer; wherein The first layer is the AlN nucleation layer; The second layer is a layer having a thickness between 0.2 μm and 1.0 μm , of which 70% <x<90%; The third layer is a layer having a thickness between 0.2 μm and 1.0 μm , of which 40% <x<70%; The fourth layer has a thickness between 0.5 μm and 1.5 μm and comprises AlN / The stacked layers are repeated, wherein the thickness of the AlN layer is between 0.5 nm and 5 nm, and the The thickness of the layer is between 10nm and 50nm and 5% <x<20%; The fifth layer has a thickness between 0.5 μm and 1.5 μm and comprises a repetition of an AlN / GaN stacked layer, wherein the AlN layer has a thickness between 0.5 nm and 5 nm and the GaN layer has a thickness between 10 nm and 50 nm; a source electrode, a gate electrode and a drain electrode; wherein The gate electrode is electrically connected to the conductive substrate; and When the III-N device is biased at the maximum rated drain-to-source operating voltage, the 2DEG channel is not fully depleted of charge.

15. The III-N device of claim 14, further comprising a drain-to-source pinch-off voltage, wherein: The drain-to-source pinch-off voltage is greater than the maximum rated drain-to-source operating voltage.

16. The III-N device of claim 15, further comprising a gate dielectric layer, and the drain electrode comprises a first portion and a second portion, wherein: The first portion of the drain electrode is in ohmic contact with the 2DEG channel, and the second portion of the drain electrode extends above a top surface of the gate dielectric layer.

17. The III-N device of claim 14, wherein: The III-N material structure is less than 6 μm, and the drain to substrate pinch-off voltage is greater than 750V.

18. A III-N material structure comprising: a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein a composition difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein; and The III-N buffer layer comprises at least five different layers sequentially increasing from a first side of the III-N buffer layer to a second side of the III-N buffer layer; wherein The first layer is the AlN nucleation layer; The second layer is a layer having a thickness between 0.2 μm and 1.0 μm , of which 70% <x<90%; The third layer is a layer having a thickness between 0.2 μm and 1.0 μm , of which 40% <x<70%; The fourth layer has a thickness between 0.5 μm and 1.5 μm and comprises AlN / The stacked layers are repeated, wherein the thickness of the AlN layer is between 0.5 nm and 5 nm, and the The thickness of the layer is between 10nm and 50nm and 5% <x<20%; The fifth layer has a thickness between 0.5 μm and 1.5 μm and comprises a repetition of an AlN / GaN stacked layer, wherein the AlN layer has a thickness between 0.5 nm and 5 nm and the GaN layer has a thickness between 10 nm and 50 nm; and The III-N channel layer is formed over the fifth layer.

19. The III-N device of claim 18, wherein: The III-N material structure has a thickness less than 6 μm and a breakdown voltage greater than 750V.

20. The III-N device of claim 19, wherein: The III-N material structure is formed on a conductive silicon substrate, and the first side of the III-N buffer layer is adjacent to the conductive silicon substrate.

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