Gas sensor based on silicon through hole technology and preparation method

Abstract

The invention relates to a gas sensor based on a silicon through hole technology and a preparation method, and belongs to the technical field of gas sensors. The conductive material grows from bottom to top on the premise that the seed layer grows at the bottom and the growth area of the seed layer is limited, electrical interconnection of the front face and the back face of the device is achieved, the sensor packaging structure has the highest space utilization arrangement mode, and the highest stacking density of the device in the vertical direction can be achieved. The integration level of the gas sensor is improved, electrodes are led out from the back of the sensor, and a basis is provided for vertical interconnection of intelligent gas sensors.

Description

Technical Field

[0001] The present invention relates to the technical field of gas sensors, and more specifically, to a gas sensor based on through silicon via technology and a preparation method thereof. Background Art

[0002] As an extension of human sense of smell, gas sensors are widely used in automobile exhaust, environment, medical and food fields. Traditional gas sensors are usually prepared by coating sensitive materials. With the development of science and technology, this type of sensor has exposed many problems, such as poor consistency of devices, low production efficiency, poor sensor performance and reliability, and difficulty in integration with other chips. At present, there is still a certain gap between domestic sensor technology and the world level, which is specifically manifested in the low level of automation of manufacturing technology, weak comprehensive performance of devices, lack of sufficient scale, and lack of competitiveness in the global sensor field. Existing gas sensors are large in size and low in integration. They are in an embarrassing position in the application of high-performance integrated circuits. It is urgent to develop a highly reliable interconnection solution to realize the integrated interconnection of gas sensors. Summary of the invention

[0003] In response to the needs in the field of intelligent gas identification, the present invention provides a gas sensor based on through silicon via technology and a preparation method to solve the needs of miniaturization and high integration of sensors in the field of gas sensor packaging. The back lead-out electrode realizes the test of the gas-sensitive performance of the sensor. The present invention realizes the electrical interconnection between the front and back sides of the device by growing a seed layer at the bottom and growing a conductive material from bottom to top under the premise of limiting its growth area. The sensor packaging structure has the highest space utilization arrangement mode and can achieve the highest device stacking density in the vertical direction. The gas sensor prepared by the present invention realizes the back lead-out of the surface test electrode. In the subsequent test process, the back bump can be used for ball planting to realize the direct interconnection between the sensor and the test circuit, thereby reducing the complexity of the test process and improving the stability of the test process.

[0004] According to a first aspect of the present invention, a method for preparing a gas sensor based on through silicon via technology is provided, comprising the following steps:

[0005] (1) Etching a silicon wafer using a mask to obtain a through-silicon via;

[0006] (2) depositing a first insulating layer on the inner wall of the through silicon via obtained in step (1) and on the upper surface of the silicon wafer, then depositing a barrier layer on the surface of the first insulating layer, and then depositing a seed layer on the surface of the barrier layer;

[0007] (3) thinning the silicon wafer to expose the bottom of the through silicon via, then using the seed layer as a growth substrate, filling the through silicon via and the lower surface of the silicon wafer with a conductive material so that the through silicon via is sealed, and then thinning the lower surface of the silicon wafer again to expose the through silicon via filled with the conductive material;

[0008] (4) inverting the lower surface of the silicon wafer exposed through silicon vias filled with conductive material obtained in step (3) to face upward, then depositing a second insulating layer, and etching to expose the through silicon vias filled with conductive material;

[0009] (5) A gas-sensitive material layer is deposited on the second insulating layer, and the gas-sensitive material layer covers the conductive material of each through-silicon via, thereby obtaining a gas sensor.

[0010] Preferably, in step (1), the etching depth is 200 μm-250 μm.

[0011] Preferably, in step (1), the diameter of the through silicon via is 5 μm-50 μm.

[0012] Preferably, in step (1), the aspect ratio of the through silicon via is (3-10):1.

[0013] Preferably, the first insulating layer is made of silicon oxide and has a thickness of 500nm-1000nm.

[0014] Preferably, the material of the barrier layer is titanium nitride, and the thickness is 100nm-200nm.

[0015] Preferably, the seed layer is made of copper with a thickness of 300nm-500nm; and the conductive material is copper.

[0016] Preferably, the gas-sensitive material layer is made of metal oxide semiconductor material with a thickness of 800nm-1000nm.

[0017] Preferably, the metal oxide semiconductor material is WO3, SnO2 or NiO.

[0018] According to another aspect of the present invention, a gas sensor prepared by the present invention is provided.

[0019] In general, the above technical solution conceived by the present invention has the following technical advantages compared with the prior art:

[0020] (1) The present invention prepares the gas sensor structure at the wafer level based on the through silicon via technology, and realizes the high consistency and high efficiency preparation of MEMS gas sensors. The present invention uses the scheme of growing a seed layer at the bottom to grow conductive materials from bottom to top under the premise of limiting its growth area, so as to realize the electrical interconnection between the front and back sides of the device. The sensor packaging structure has the highest space utilization arrangement mode, and can achieve the highest device stacking density in the vertical direction. It is the best choice for sensors pursuing high integration and has significant advantages in the subsequent interconnection integration field. Through silicon via technology forms conductive holes inside the silicon wafer through corresponding process equipment to realize the interconnection between the chip, wafer and packaging base in the vertical direction. Compared with the traditional gas sensor packaging technology, through silicon via technology (TSV technology) leads out electrodes on the back of the sensor to realize inter-chip interconnection, greatly reducing the characteristic size of the package, and providing good compatibility for the optimization of subsequent chip manufacturing technology. The shorter interconnection line length of TSV has certain advantages in signal transmission, and its stacking density in three-dimensional space is the highest.

[0021] (2) Since the traditional sensor packaging structure requires the gas-sensing performance of the sensor to be tested by drawing out the electrode, this step cannot be ignored in the packaged gas sensor. In the gas sensor prepared by the TSV structure, the back lead of the surface test electrode is realized by the TSV conductive column (such as a copper column). In the subsequent test process, the back bump can be used to realize the direct interconnection between the sensor and the test circuit, reducing the complexity of the test process and improving the stability of the test process. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a flow chart of a bottom-up through silicon via filling method based on a bottom seed layer provided in Example 1 of the present invention.

[0023] Figure 2 This is a schematic flow chart of a bottom-up through silicon via filling method based on a bottom seed layer in Example 2 of the present invention, wherein: 1-silicon wafer, 2-photolithography mask, 3-through silicon via, 4-silicon oxide layer, 5-titanium nitride layer, 6-copper layer, 7-conductive material.

[0024] Figure 3 It is a schematic diagram of the sensor structure after thinning prepared in Example 2 of the present invention, wherein 8 is a silicon wafer, and 9 is a through silicon via filled with a conductive material.

[0025] Figure 4 It is a schematic diagram of depositing an insulating layer on the surface of the sensor in Example 2 of the present invention, wherein 10 is the insulating layer.

[0026] Figure 5 It is a schematic diagram of the deposition of the gas-sensitive film in Example 2 of the present invention, wherein 11 is the gas-sensitive film. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] The gas sensor array preparation of the present invention includes: a TSV array prepared on a wafer; an insulating layer located on the TSV structure; a gas sensitive material deposited on the insulating layer; and an electrode deposited on the back of the device. The TSV array wafer that has been prepared is diced to obtain a TSV array chip, and the subsequent sensor structure is prepared on the chip.

[0029] First, the substrate surface needs to be patterned with a mask for protection through photolithography to ensure that only the through-hole area is etched. After the mask layer is made, the sample needs to be deep etched to form a through-silicon via. A first insulating layer (such as silicon oxide) is deposited on the inner wall of the through-silicon via and the surface of the silicon wafer to achieve electrical isolation between the through-silicon via metal column and the substrate. Then, a diffusion barrier layer (such as titanium nitride) is deposited on the first insulating layer to prevent the diffusion of conductive materials in the first insulating layer, and then a seed layer (such as copper) is covered on the surface of the first insulating layer by sputtering deposition to facilitate subsequent electroplating filling of metal columns (such as copper columns). The through-silicon vias are exposed at the bottom of the through-silicon vias by thinning the silicon wafer, and then the seed layer is used as a growth substrate to fill the through-silicon vias and the lower surface of the silicon wafer with conductive materials so that the through-silicon vias are sealed. The lower surface of the silicon wafer is thinned again to expose the through-silicon vias filled with conductive materials; the lower surface of the silicon wafer with the through-silicon vias filled with conductive materials exposed is inverted upward, and then a second insulating layer is deposited and etched to expose the through-silicon vias filled with conductive materials; a gas-sensitive material layer is deposited on the second insulating layer, and the gas-sensitive material layer covers the conductive material of each through-silicon via, so as to obtain a gas sensor.

[0030] The silicon oxide insulating layer is usually deposited by low pressure chemical vapor deposition (LPCVD) at a process temperature of 850° C. to 1050° C. For through silicon vias with a high aspect ratio, the silicon oxide insulating layer prepared by LPCVD may have a large stress.

[0031] Among them, for high aspect ratio silicon vias, the TiN barrier layer must achieve uniform distribution in depth and high coverage. Generally, a plasma enhanced atomic layer deposition (PEALD) process is used with a process temperature of 300°C.

[0032] For high aspect ratio through silicon vias, the Cu seed layer must be uniformly distributed in depth and deposited with high coverage. Traditional physical vapor deposition (PVD) processes are difficult to achieve highly conformal seed layer deposition for high aspect ratio through silicon vias.

[0033] To solve the above technical problems, the embodiment of the present invention provides a bottom-up through silicon via filling method based on a bottom seed layer, which can simplify the process steps of through silicon vias. The cost is low and the technology can be applied in a wide range of application scenarios. Based on this technology, a gas sensor structure based on TSV technology is provided.

[0034] The present invention provides a gas sensor prepared based on TSV technology, which may include: a TSV structure, an insulating layer, a test electrode and a gas-sensitive material film. A single TSV structure includes an insulating layer, a barrier diffusion layer, a bottom seed layer, and a conductive filling material.

[0035] The method for preparing a gas sensor based on through silicon via technology of the present invention specifically comprises the following steps:

[0036] The mask layer is prepared on the silicon wafer based on the preset pattern, using AR-P 3250 photoresist as the mask layer with a thickness of 11-12μm;

[0037] Deep silicon etching is performed based on a preset pattern and a preset depth, and the preset depth is 200-250μm;

[0038] Depositing insulating material on the inner wall of the through silicon via and on the surface of the silicon wafer at the wafer level to form an insulating layer covering the TSV structure;

[0039] Depositing metal on the insulating layer at a wafer level to form a diffusion barrier layer covering the surface of the insulating layer;

[0040] Depositing a conductive material on the surface of the diffusion barrier layer at a wafer level to form a seed layer covering the surface of the wafer;

[0041] Thinning the TSV wafer to thin the back of the wafer to where the TSV structure is located;

[0042] The bottom seed layer is used as a growth substrate to seal the TSV hole on this side, limiting the electroplating process to fill the TSV structure from bottom to top;

[0043] After overfilling, the copper protrusions on the surface are thinned, and the metal pillars (such as copper pillars) are thinned to the plane position of the substrate;

[0044] Depositing an insulating material on the surface of the sensor to form a second insulating layer covering the surface of the sensor;

[0045] Perform photolithography masking on the surface of the insulating layer, and perform masking protection on the area outside the metal pillar (such as copper pillar), with a preset depth of 1.5 μm;

[0046] Etching the surface of the device until the copper pillar is exposed;

[0047] A gas-sensitive material is deposited on the surface of the device to form a sensitive layer.

[0048] In the method for preparing the sensor based on TSV technology, wherein:

[0049] The insulating layer material is silicon oxide, specifically, the thickness of the silicon oxide is about 500nm-1000nm;

[0050] The diffusion barrier layer material is titanium nitride, and specifically, the thickness of the titanium nitride is about 100nm-200nm;

[0051] The seed layer material is copper, specifically, the copper thickness is about 300nm-500nm;

[0052] The gas-sensitive film material can be a variety of metal oxide semiconductor materials such as WO3, SnO2, NiO, etc. Specifically, the thickness of the gas-sensitive film is about 800-1000nm.

[0053] Figure 1 A flow chart of a bottom-up through silicon via filling method based on a bottom seed layer according to an embodiment of the present invention is shown. Figure 2 FIG. 2 is a schematic diagram showing a process of a bottom-up through silicon via filling method based on a bottom seed layer according to an embodiment of the present invention. Figure 1 , Figure 2 As shown, the method includes: step S1-step S7. Those skilled in the art can set the diameter and aspect ratio of the silicon through hole according to actual needs, and the present invention does not limit this. For example, the diameter of the silicon through hole can be 5μm to 50μm, and the aspect ratio of the silicon through hole can be 3:1 to 10:1, etc.

[0054] The following are specific embodiments

[0055] Example 1

[0056] A mask layer is prepared on the surface of the silicon substrate to form a preset mask pattern.

[0057] The silicon substrate is etched to form a through silicon via of a preset size on the first surface of the silicon substrate.

[0058] In this embodiment, the preset size of the through silicon via 3 can be set according to the size of the through silicon via to be manufactured, and the present invention is not limited to this. In the process of manufacturing the blind hole 3, an etching process such as the Bosch process can be used, and the present invention is not limited to this. Those skilled in the art can set the size of the silicon substrate according to actual needs, and the present invention is not limited to this. For example, the silicon substrate can be a 4-12 inch silicon wafer substrate.

[0059] The silicon oxide layer 4 is formed on the inner wall of the through silicon via 3 and the upper surface of the silicon wafer by LPCVD, and the silicon oxide layer 4 serves as the first insulating layer of the through silicon via 3 to be prepared. The inner wall of the through silicon via 3 refers to the side wall and the bottom surface of the through silicon via 3.

[0060] A titanium nitride layer is generated on the surface of the first insulating layer by PEALD, and the titanium nitride layer 5 serves as a barrier layer for the through silicon via to be prepared.

[0061] A copper layer is generated on the surface of the titanium nitride layer by magnetron sputtering, and the copper layer 6 serves as a seed layer for the through silicon via to be prepared.

[0062] The blind hole is exposed at the bottom of the through silicon via by means of wafer thinning.

[0063] The conductive filling material is generated on the surface of the copper layer by electroplating, wherein an insulating substrate is used on one side of the blind hole seed layer to limit the growth area. Those skilled in the art can set the type of conductive filling material according to actual needs, and the present invention does not limit this. For example, the conductive material 7 can be tungsten, nickel, etc.

[0064] After overfilling, the copper protrusions on the surface are thinned, and the metal pillars (such as copper pillars) are thinned to the plane position of the substrate;

[0065] Depositing insulating material on the surface of the sensor to form a second insulating layer covering the surface of the sensor;

[0066] Perform photolithography masking on the surface of the insulating layer to protect the area outside the metal pillar (such as copper pillar);

[0067] Etching the device surface until the copper pillars are exposed;

[0068] Gas-sensitive materials are deposited on the surface of the device to form a sensitive layer.

[0069] Example 2

[0070] like Figure 5 As shown, a specific embodiment of the present invention provides a TSV-based gas sensor structure, which includes: a silicon wafer, a TSV structure, an insulating layer, a test electrode, and a gas-sensitive material.

[0071] The thinned silicon wafer 8 is a gas sensor substrate. Figure 3 As shown, the periphery includes four through silicon vias 9 filled with conductive material. The through silicon vias 9 filled with conductive material are used to lead the test electrodes to the lower surface of the thinned silicon wafer 8.

[0072] The insulating layer 10 is disposed on the thinned silicon wafer 8. Figure 4 As shown, the insulating layer is used to achieve electrical insulation between the sensitive material and the silicon substrate.

[0073] The silicon through via 9 filled with conductive material completely penetrates the insulating layer 10 and the thinned silicon wafer 8. Figure 5 As shown, the silicon through via 9 filled with conductive material is used to lead the test electrode to the lower surface of the thinned silicon wafer 8, and the upper gas-sensitive film 11 has a corresponding connection area at the location of the silicon through via, and the overall packaging is achieved through metal interconnection.

[0074] The gas-sensitive material 11 is disposed on the surface of the insulating layer. Figure 5 As shown, the gas-sensitive material is prepared in the central area of ​​the insulating layer surface and is directly connected to the test electrode. Under a certain gas atmosphere, the material resistance will change significantly, realizing the judgment and acquisition of information such as gas type and concentration. There is no restriction on the specific type, coating method, and gas-sensitive characteristics of the gas-sensitive material, and the size and formation position correspond to the test electrode.

[0075] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a gas sensor based on through silicon via technology, characterized in that: The following steps are involved: (1) Etching a silicon wafer using a mask to obtain a through-silicon via; (2) depositing a first insulating layer on the inner wall of the through silicon via obtained in step (1) and on the upper surface of the silicon wafer, then depositing a barrier layer on the surface of the first insulating layer, and then depositing a seed layer on the surface of the barrier layer; (3) Thinning the silicon wafer to expose the bottom of the through silicon via, then using the seed layer as a growth substrate, filling the through silicon via and the lower surface of the silicon wafer with a conductive material so that the through silicon via is sealed, and then thinning the lower surface of the silicon wafer again to expose the through silicon via filled with the conductive material; (4) inverting the lower surface of the silicon wafer exposed through silicon vias filled with conductive material obtained in step (3) to face upward, then depositing a second insulating layer, and etching to expose the through silicon vias filled with conductive material; (5) A gas-sensitive material layer is deposited on the second insulating layer, and the gas-sensitive material layer covers the conductive material of each through-silicon via, thereby obtaining a gas sensor.

2. The method for preparing a gas sensor based on through silicon via technology according to claim 1, characterized in that: In step (1), the etching depth is 200 μm-250 μm.

3. The method for preparing a gas sensor based on through silicon via technology according to claim 1, characterized in that: In step (1), the diameter of the through silicon via is 5 μm-50 μm.

4. The method for preparing a gas sensor based on through silicon via technology according to claim 1, characterized in that: In step (1), the aspect ratio of the through silicon via is (3-10):

1.

5. The method for preparing a gas sensor based on through silicon via technology according to claim 1, characterized in that: The material of the first insulating layer is silicon oxide, and the thickness is 500nm-1000nm.

6. The method for preparing a gas sensor based on through silicon via technology according to claim 1, characterized in that: The material of the barrier layer is titanium nitride, and the thickness is 100nm-200nm.

7. The method for preparing a gas sensor based on through silicon via technology according to claim 1, characterized in that: The seed layer is made of copper, with a thickness of 300nm-500nm; and the conductive material is copper.

8. The method for preparing a gas sensor based on through silicon via technology according to claim 1, characterized in that: The gas-sensitive material layer is made of metal oxide semiconductor material with a thickness of 800nm-1000nm.

9. The method for preparing a gas sensor based on through silicon via technology according to claim 8, characterized in that: The metal oxide semiconductor material is WO3, SnO2 or NiO.

10. A gas sensor prepared according to any one of claims 1 to 9.

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