Integrated circuit device and built-in self-test method

Abstract

An exemplary integrated circuit device has a built-in self-test circuit design and a built-in self-test method. One disclosed integrated circuit device includes an analog circuit block configured to be powered by current from a first power rail and an intermediate node; a current sensor configured to provide a digital measurement of the current; and a built-in self-test circuit configured to set the analog circuit block into a sequence of modes of operation and coupled to the current sensor to capture a corresponding one of the digital measurements for each mode of operation.

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuit device testing, and more particularly to efficient built-in self-test methods and designs for quiescent current-based or operating current-based verification of analog circuit components. Background Art

[0002] The manufacturing process of integrated circuit devices involves applying repeated patterning, deposition and etching steps to semiconductor wafers or other substrates to form interconnect structures that operate as analog and / or digital components of electronic circuits. Despite continuous improvement methods, the manufacturing process is still subject to statistical variations in pressure, temperature and composition, not to mention equipment power, vibration, wear and tear, any of which may cause variations in layer alignment, thickness and composition. Although the manufacturing process includes some tolerance for such variations, the complexity and number of integrated devices formed from each wafer results in a non-negligible proportion of device operation being impaired or failing.

[0003] A variety of techniques have been developed to enable faulty devices to be detected and discarded or reused, including automatic test equipment (ATE), which can be used alone, but is more commonly used in combination with built-in self-test (BIST) circuits. When used without a BIST circuit, the ATE applies various signals to the external input terminals of the device under test (DUT), and compares the resulting external output of the DUT with their expected values. In the absence of a BIST circuit, the test process is limited to the external terminals of the DUT, often preventing the test process from providing sufficient test coverage (meaning that many defects may not be detected by the test). Using a BIST circuit, the test process can access internal nodes and achieve better test coverage, and is not limited to the clock rate that supports off-chip communication. Typically, the test results are exported to an external tester (i.e., ATE) via a serial bus for evaluation.

[0004] Various standards have been developed to enable ATE to access BIST circuits, including the Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1 (commonly referred to as "JTAG"). These standards employ a serial bus combined with one or more internal "scan chains". A scan chain is a shift register that transfers its contents from one memory cell to the next to load test input data and later derive test result data. The various internal components of the DUT are configured to operate on portions of the shift register contents and typically return their results to the same shift register position. The ATE retrieves and evaluates the test results, checking for error bits that would indicate improper operation of digital circuit components.

[0005] While attempts have been made to develop similar testing procedures for analog circuits, they have been slow, complex, and / or prohibitively expensive relative to the area requirements of the circuits being tested. Summary of the invention

[0006] Thus, disclosed herein are illustrative built-in self-test circuit design and verification methods for integrated circuit devices.

[0007] According to one aspect of the present application, an integrated circuit device is provided, characterized in that it includes: an analog circuit block, which is configured to be powered by a current between a first power rail and an intermediate node; a current sensor, which is configured to provide a digital measurement of the current; and a built-in self-test circuit, which is configured to set the analog circuit block to an operating mode in an operating mode sequence and is coupled to the current sensor to capture a corresponding one of the digital measurements for each operating mode in the sequence.

[0008] In one embodiment, the integrated circuit device is characterized in that the current sensor includes: a resistor group, which couples the intermediate node to the second power rail and is configured to convert the current into a voltage drop; a comparator, which is configured to provide an output indicating whether the voltage drop exceeds a fixed reference voltage; and a controller, which is configured to iteratively adjust the resistor group based on the output of the comparator to provide the digital measurement of the current.

[0009] In one embodiment, the integrated circuit device is characterized in that the analog circuit block is one of a plurality of analog circuit blocks, each analog circuit block having a corresponding sequence of operating modes to be set by the built-in self-test circuit, and each of the plurality of analog circuit blocks is configured to be powered by a current from the first power rail to the intermediate node.

[0010] In one embodiment, the integrated circuit device is characterized in that the built-in self-test circuit is configured to capture the digital measurement of a given analog circuit block of the plurality of analog circuit blocks while disabling all other analog circuit blocks of the plurality of analog circuit blocks.

[0011] In one embodiment, the integrated circuit device is characterized in that: the operating mode sequence is specified by a test pattern input to the built-in self-test circuit, the built-in self-test circuit is configured to output a device signature including the digital measurement, the built-in self-test circuit includes a memory configured to store the test pattern and the digital measurement, and the built-in self-test circuit includes a sequencer, which is configured to iterate the operating mode sequence of the analog circuit block and store the corresponding one of the digital measurements in the memory.

[0012] According to another aspect of the present application, a built-in self-test method is provided, characterized in that a plurality of integrated circuit devices from a given manufacturing batch are tested, and for each of the plurality of integrated circuit devices, the test comprises: powering an analog circuit block with current from a first power rail; iterating a sequence of operation modes of the analog circuit block; for each operation mode in the sequence, storing a digital measurement of the current corresponding to the operation mode; transmitting a device signature including the stored digital measurement to an external tester; and failing the integrated circuit device if the device signature is inconsistent with device signatures of other integrated circuit devices in the plurality of integrated circuit devices.

[0013] In one embodiment, the built-in self-test method is characterized in that the given manufacturing batch comprises the plurality of integrated circuit devices patterned on a given wafer.

[0014] In one embodiment, the built-in self-test method is further characterized in that it obtains the digital measurement by the following steps: comparing a reference voltage with a voltage drop from a resistor group, the resistor group coupling the intermediate node to the second power rail; and iteratively adjusting the resistor group based on the comparison.

[0015] In one embodiment, the built-in self-test method is characterized in that: the analog circuit block is one of multiple analog circuit blocks in the integrated circuit device, and the method also includes importing a test mode, which specifies a corresponding operation mode sequence for each analog circuit block in the multiple analog circuit blocks.

[0016] In one embodiment, the built-in self-test method is characterized in that the method comprises disabling the other analog circuit blocks of the plurality of analog circuit blocks during the iteration of the sequence of operation modes of the analog circuit blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a block diagram of an illustrative integrated circuit device with low-side current measurement.

[0018] Figure 2 is a block diagram of an illustrative integrated circuit device with high-side current measurement.

[0019] Figure 3 is a circuit schematic of an exemplary current sensor.

[0020] Figure 4 is a flow chart of an exemplary built-in self-test method.

[0021] Figure 5 An external tester coupled to a plurality of devices under test is shown. DETAILED DESCRIPTION

[0022] The following description and drawings are provided for the purpose of explanation, not limitation of the present disclosure. Rather, they provide a basis for one of ordinary skill in the art to understand all modifications, equivalents, and alternatives that fall within the scope of the claims.

[0023] Figure 1 1 is a block diagram of an exemplary integrated circuit device 100 having a plurality of analog circuit blocks 1-5. Although the specific purpose and arrangement of the plurality of analog circuit blocks 1-5 are not relevant to the present disclosure, suitable examples of integrated circuit devices would include power modules (e.g., voltage and current regulators, voltage converters, AC-DC converters, gate drivers, LED drivers, ground fault circuit interrupter (GFCI) controllers, voltage references, battery managers), signal conditioners (e.g., amplifiers, filters, redrivers, analog-to-digital converters), sensors (e.g., inductive sensors, capacitive sensors, photodetectors, temperature sensors, accelerometers, ultrasonic sensors), motor controllers, and interfaces (e.g., Ethernet controllers, wired and wireless transceivers, optocouplers, automotive bus controllers). Suitable examples of analog circuit blocks 1-5 include voltage references, current sources, oscillators, mixers, analog filters, amplifiers, analog-to-digital converters, digital-to-analog converters, amplifiers, switches, integrated sensors (including MEMS), etc., which are collectively arranged to achieve the desired functionality of the integrated circuit device 100. The integrated circuit device may also include digital circuits, which may be tested using existing techniques.

[0024] Each of the plurality of analog circuit blocks 1-5 is coupled between the first power rail VCC and the intermediate node 102 to draw current for its operation. When closed, the bypass switch 104 couples the intermediate power node 102 to the second power rail GND to complete the power circuit of each of the plurality of analog circuit blocks 1-5. When the bypass switch 104 is open, the current reaches the second power rail via the current sensor 106. Therefore, the bypass switch 104 enables the current sensor 106 when it is open, and disables or bypasses the current sensor 106 when it is closed.

[0025] Each of the multiple analog circuit blocks 1-5 can be placed in a default state via the control bus 108. The default state can be, for example, a disabled state, which can be achieved by interrupting the connection of the block to the intermediate node 102 or otherwise preventing the block from drawing any current from any power rail. Alternatively, the default state can be a state in which all analog signal inputs are maintained at a ground (GND) voltage. Alternatively, the default state can be a state in which all analog signal inputs are maintained at a supply voltage (VCC) or any other arbitrary reference voltage. Alternatively, the default state can be customized for a single block. In any case, the default state can be different for different analog circuit blocks in the multiple analog circuit blocks 1-5.

[0026] Each of the plurality of analog circuit blocks 1-5 may be placed in one or more different operating modes. An operating mode is a mode in which the block is active and can draw current from any of the power rails. Some blocks (such as a bandgap voltage reference) may have only one operating mode. Others (such as amplifiers) may have multiple operating modes, such as a first operating mode with an input close to a supply voltage and a second operating mode with an input close to a ground voltage. As a rule of thumb, those blocks that apply an analog input signal to a transistor gate or base may employ at least two operating modes, one of which applies a signal voltage sufficient to place the transistor in a conducting state and the other applies a signal voltage sufficient to place the transistor in a non-conducting state.

[0027] Additional operating modes may be employed to test different input signal combinations and / or to test intermediate input signal voltages as well.For example, a differential amplifier may be tested with positive and negative differential input signals at each of high and low common mode voltages.

[0028] The exemplary integrated circuit device 100 includes a built-in self-test (BIST) circuit, which includes a memory 110, a test input / output (test I / O) interface 112, and a BIST sequencer 114. The control bus 108 may carry signals from the memory 110, which are represented as selected test vectors from a test pattern stored via the test I / O interface 112. The test I / O interface 112 may support any standard communication and test protocols, including scan chains or other serial buses, such as inter-integrated circuit (I2C), management data input / output (MDIO), joint test group (JTAG), and test access port (TAP), which enables external automatic test equipment (ATE) to provide test patterns, initiate test processes, and receive stored test results. The built-in self-test sequencer 114 steps through the test patterns in the memory 110, applying one test vector at a time as a signal on the bus 108, and obtains corresponding measurements of static current or operating current from the current sensor 106. The current measurement (e.g., a digital measurement of the current) is stored in the memory 110 to form a test signature for the device. When the test is complete, the ATE can read the test signature via the test I / O bus.

[0029] The plurality of analog circuit blocks 1-5 may be tested one at a time in a sequence specified by the test mode. When a given one of the plurality of analog circuit blocks 1-5 is tested, the remaining analog circuit blocks may be disabled or placed in a default state. For each of the plurality of analog circuit blocks 1-5, the test mode specifies a corresponding sequence of one or more operating modes, and the memory 110 captures digital measurements of current for each operating mode. The digital measurements are maintained in an order corresponding to the sequence of operating modes within the block sequence, and the digital measurements collectively form a test signature for the device.

[0030] Due to the previously mentioned process variations, some variation in the operating characteristics of different integrated circuit devices is expected. However, for certain components and block types, a high degree of consistency is expected. For example, voltage references are designed to be consistent between different devices, and comparators that rely on voltage references for comparing thresholds are expected to exhibit corresponding consistency. The resistance of integrated circuit resistors typically exhibits a high degree of consistency, at least between integrated circuit devices manufactured on the same semiconductor wafer batch. Therefore, current sensors designed to employ such components can achieve accurate and consistent current measurements between integrated circuit devices from a given batch (e.g., devices patterned on a given wafer). A design that provides a consistent and minimal voltage drop across the current sensor over a wide current range can further minimize any nonlinear or other sources of inaccurate current measurements.

[0031] Testing can be performed after the integrated circuit devices have been packaged, or it can be performed before the wafer is singulated. For packaged integrated circuit devices, ATE relies on the pins or other contacts of the package, including those used to test I / O. For unsingulated devices, ATE may employ probes connected to the integrated circuit device contacts on the surface of the wafer.

[0032] The exemplary integrated circuit device 100 employs low-side current sensing, ie, the current sensor 106 is coupled between the intermediate node 102 and the lower voltage power rail GND. Figure 2 An alternative integrated circuit device 200 employing high-side current sensing is shown, i.e., the current sensor 106 is coupled between the intermediate node 102 and the higher voltage power rail VCC. Figure 1 , wherein the plurality of analog circuit blocks 1-5 are powered by current from an upper voltage power rail VCC to an intermediate node 102, Figure 2 The multiple analog circuit blocks 1-5 in are powered by the current between the intermediate node 102 and the lower voltage power rail GND.

[0033] Figure 3 1 is a schematic diagram of an exemplary current sensor 106 that can be used for high-side or low-side current sensing. In the illustrated implementation, the measured current is from a higher voltage input node IN to a lower voltage output node OUT. The current sensor 106 includes a group of resistors R1-RN, which are combined with an array of switches S1-SM to provide a configurable resistance. In order to simplify the description, the illustrated implementation has resistors R1-RN arranged in series between the input node IN and the output node OUT, thereby forming a ladder of intermediate nodes, each of which can be coupled to the output node OUT to avoid one or more of the resistors. If the resistors have equal values, this arrangement enables the resistor group to provide N-1 equally spaced resistance values. The resistor group can adopt an alternative resistor arrangement, such as placing some or all of the resistors that may have different resistance values ​​in a selectable parallel combination. Such an alternative arrangement can significantly reduce the number of components, and therefore reduce area requirements.

[0034] The array of switches S1-SM is set by a switch control 302 (e.g., a controller) which begins to systematically change the switch settings based on the output of a comparator 304 in response to an initiation signal (INIT). According to Ohm's law, the effective resistance of the resistor group converts the current into a voltage drop V=IR. The comparator 304 compares the voltage drop across the resistor group with a predetermined reference voltage Vref, and enables its output when the voltage drop exceeds the reference voltage, and disables its output when the voltage drop falls below the reference voltage. The voltage drop V is the product of the current I and the resistance R of the resistor group determined by the selected switch configuration. In at least some specific implementations, the switch control 302 performs a binary search, first determining whether the switch configuration that provides half-value maximum resistance produces a voltage drop above or below a fixed reference voltage Vref. Based on the comparator output, the switch control 302 sets or clears the first bit of the digital current measurement (DCM) and sets the switch to increase or decrease the effective resistance by one-quarter of the maximum value. Likewise, based on the comparator output, switch control 302 sets or clears the second bit of DCM and sets the switch to raise or lower the effective resistance by one eighth of the maximum value. This process of iteratively adjusting the resistor bank based on the comparator output is repeated until switch control 302 has determined all bits of DCM, at which point the voltage drop across the resistor bank is as close as possible to the reference voltage Vref. The time required to obtain a current measurement for a given operating mode may be on the order of a few microseconds.

[0035] As previously mentioned, the reference voltage Vref can be kept relatively small, but large enough to permit the use of a relatively low complexity comparator design. In designs employing a switch input configuration that implements offset measurement and compensation, a reference voltage of about 100 mV would be suitable. Any suitable offset compensation or auto-zeroing technique may be used. It should be noted that to ensure that the current measurement represents normal operating conditions, the supply voltage may be increased to compensate for the voltage drop across the resistor bank, for example, a 3 volt nominal supply voltage may be increased to 3.1 volts during the test process.

[0036] Figure 44 is a flow chart of an exemplary test method that can be implemented by the integrated circuit device 100, 200. After the test pattern has been imported into the built-in self-test circuit memory 110, the method is initiated by the ATE to specify the sequence of analog circuit blocks to be tested and the sequence of operating modes to be applied to each analog circuit block. It starts in box 402, where the sequencer 114 causes the control bus 108 to select the first of the multiple analog circuit blocks 1-5 and disable the remaining analog circuit blocks. In box 408, the sequencer then causes the control bus 108 to place the selected analog circuit block in a first operating mode. In box 410, the sequencer initiates a measurement performed by the current sensor 106 and causes the memory 110 to capture or otherwise store the result. In box 412, the sequencer determines whether there are more operating modes for the currently selected block, and if so, the sequencer configures the selected block to the next operating mode in box 414 before returning to box 410. Otherwise, in box 416, the sequencer determines whether there are more analog circuit blocks, and if so, the sequencer selects the next analog circuit block in box 418 and disables the remaining analog circuit blocks before returning to box 408. Once each analog circuit block has been configured for each operating mode in the corresponding sequence, the sequencer signals the completion of the test in box 420. This signaling can be done using register tags, or one of the test I / O signal pins can be switched. In box 422, the current measurement of each operating mode of each analog circuit block is derived as an integrated circuit device signature. The built-in self-test circuit transmits the device signature via a serial test bus. In this way, the built-in self-test circuit iterates the sequence of operating modes of the specified sequence of analog circuit blocks according to the test mode. This completes the processing of the integrated circuit device, but the processing continues, and the ATE evaluates the current measurement, passing the integrated circuit devices with signatures that are consistent with each other or with the expected device signature, and not passing the integrated circuit devices with inconsistent signatures.

[0037] Figure 5An illustrative external tester 502 coupled to a plurality of devices under test 504, 506, 508, 510 is shown. For ease of illustration, the figure shows only four devices under test. In practice, the external tester (here labeled as automatic test equipment ATE) 502 can be connected to as many devices as its hardware will support. The external tester 502 can provide a test mode to each of the plurality of devices 504-510 simultaneously, start the built-in self-test circuit, and once the test is completed, retrieve the device signature from each of the plurality of devices 504-510. In this way, the ATE 502 can obtain the expected current measurement of each operating mode of each analog circuit block, and can compare the measurement with its corresponding expected value. If the measurement deviates beyond a predetermined threshold (the predetermined threshold can be expressed as a percentage or an absolute value), the ATE 502 can determine that the integrated circuit device is faulty.

[0038] Examples of suitable predetermined thresholds include 1%, 2%, 5%, 10%, 10nA, 20nA, 50nA, 100nA, 250nA, 0.5μA, 1μA, and the threshold may be different for different operating modes. The ATE may further compare measurements between devices of a given batch and may determine whether any of the current measurements deviate from the average or median measurement by more than a predetermined threshold, e.g., whether the maximum absolute difference between the actual measurement and the expected or average corresponding measurement in the device signature falls below a predetermined threshold. The predetermined threshold for batch testing may be different from the predetermined threshold for expected measurements, and likewise, it may vary for different operating modes. If none of the actual measurements of a given integrated circuit device deviate by more than a predetermined threshold, the ATE may determine that the measurements are consistent and may declare that the integrated circuit device has passed the verification test. There are indications that the process will detect more than 99% of manufacturing faults, requires a minimum surface area of ​​the die, and with built-in current sensors, the process may be performed quickly, i.e., in a fraction of the time of comparable tests by other means.

[0039] In summary, an exemplary built-in self-test circuit design and verification method for an integrated circuit device has been described. A disclosed integrated circuit device includes: an analog circuit block configured to be powered by a current from a first power rail and an intermediate node; a current sensor configured to provide a digital measurement of the current; a built-in self-test circuit configured to set the analog circuit block into a sequence of operating modes and coupled to the current sensor to capture a corresponding one of the digital measurements for each operating mode.

[0040] An illustrative method for testing a plurality of integrated circuit devices from a given manufacturing lot includes, for each of the plurality of integrated circuit devices: powering an analog circuit block with current from a first power rail; iterating a sequence of operating modes for the analog circuit block; for each operating mode in the sequence, storing a corresponding digital measurement of the current; transmitting a device signature including the stored digital measurement to an external tester; and failing the integrated circuit device if the device signature is inconsistent with device signatures of other integrated circuit devices in the plurality of integrated circuit devices.

[0041] Another disclosed integrated circuit device includes: a plurality of analog circuit blocks, each analog circuit block coupled between a first power rail and an intermediate node; a current sensor coupled between the intermediate power node and a second power rail, the current sensor configured to provide a digital measurement of a current between the intermediate power node and the second power rail; and a sequencer configured to iterate over the plurality of analog circuit blocks, enabling the analog circuit blocks one at a time according to a test mode, the test mode further specifying a sequence of operating modes of the enabled analog circuit blocks, and the sequencer further configured to capture a corresponding digital measurement for each operating mode of each analog circuit block.

[0042] Each of the foregoing devices, designs, and methods may be used alone or in combination, and may include one or more of the following features in any suitable combination: 1. A current sensor having a resistor bank coupling the intermediate node to the second power rail and configured to convert the current into a voltage drop. 2. A comparator configured to compare the voltage drop to a fixed reference voltage. 3. A controller configured to determine a digital measurement by iteratively adjusting the resistor bank based on an output of the comparator. 4. The analog circuit block is one of a plurality of analog circuit blocks, each having a corresponding sequence of operating modes to be set by a built-in self-test circuit, each of the plurality of analog circuit blocks being configured to be powered by a current from the first power rail to the intermediate node. 5. The built-in self-test circuit is configured to capture a digital measurement of a given analog circuit block of the plurality of analog circuit blocks while disabling other analog circuit blocks of the plurality of analog circuit blocks. 6. The sequence of operating modes is specified by a test mode imported into the built-in self-test circuit. 7. The built-in self-test circuit is configured to derive a device signature including the captured digital measurement. 8. The built-in self-test circuit includes a memory configured to store the test pattern and the captured digital measurements. 9. The built-in self-test circuit includes a sequencer configured to set each operating mode in a sequence of operating modes of the analog circuit block and store a corresponding one of the digital measurements in the memory. 10. The manufacturing lot corresponds to devices patterned on a given wafer. 11. The transmitting includes communicating the device signature to an external tester via a serial test bus. 12. If the maximum absolute difference between corresponding digital measurements of different integrated circuit devices is below a predetermined threshold, it is determined that the device signatures are inconsistent. 13. A controller configured to adjust the resistor bank as needed for the voltage drop to converge to a fixed reference voltage. 14. A bypass switch for the resistor bank, the bypass switch configured to disable the current sensor when closed. 15. A memory; and a built-in self-test interface coupled to the memory to store the test pattern and derive a device signature including the digital measurements for each operating mode of each analog circuit block.

Claims

1. An integrated circuit device, characterized in that: The integrated circuit device comprises: an analog circuit block configured to be powered by a current between the first power rail and the intermediate node; a current sensor configured to provide a digital measurement of the current; and A built-in self-test circuit is configured to set the analog circuit block to an operating mode in a sequence of operating modes and is coupled to the current sensor to capture a corresponding one of the digital measurements for each operating mode in the sequence.

2. The integrated circuit device according to claim 1, characterized in that The current sensor comprises: a resistor bank coupling the intermediate node to a second power rail and configured to convert the current into a voltage drop; a comparator configured to provide an output indicating whether the voltage drop exceeds a fixed reference voltage; and A controller is configured to iteratively adjust the resistor bank based on the output of the comparator to provide the digital measurement of current.

3. The integrated circuit device according to any one of claims 1 to 2, characterized in that: The analog circuit block is one of a plurality of analog circuit blocks, each analog circuit block having a corresponding sequence of operating modes to be set by the built-in self-test circuit, each of the plurality of analog circuit blocks being configured to be powered by a current from the first power rail to the intermediate node.

4. The integrated circuit device according to claim 3, characterized in that The built-in self-test circuit is configured to capture the digital measurement of a given one of the plurality of analog circuit blocks while disabling all other one of the plurality of analog circuit blocks.

5. The integrated circuit device according to any one of claims 1 to 2, characterized in that: The sequence of operating modes is specified by a test pattern input to the built-in self-test circuit, The built-in self-test circuit is configured to output a device signature including the digital measurement, The built-in self-test circuit includes a memory configured to store the test pattern and the digital measurement, and The built-in self-test circuit includes a sequencer configured to iterate the sequence of operating modes of the analog circuit block and store the corresponding one of the digital measurements in the memory.

6. A built-in self-test method, characterized in that Testing a plurality of integrated circuit devices from a given manufacturing lot, for each integrated circuit device in the plurality of integrated circuit devices, the testing comprising: powering analog circuit blocks using current from the first power rail; iterating a sequence of operation modes of the analog circuit block; for each operating mode in the sequence, storing a digital measurement of the current corresponding to the operating mode; transmitting a device signature including the stored digital measurements to an external tester; and If the device signature is inconsistent with device signatures of other integrated circuit devices in the plurality of integrated circuit devices, the integrated circuit device is disabled.

7. The built-in self-test method according to claim 6, characterized in that: The given manufacturing lot includes the plurality of integrated circuit devices patterned on a given wafer.

8. The built-in self-test method according to any one of claims 6 to 7, further characterized in that: The built-in self-test method obtains the digital measurement by the following steps: comparing a reference voltage to a voltage drop across a resistor bank coupling the intermediate node to a second power rail; as well as The resistor bank is iteratively adjusted based on the comparison.

9. The built-in self-test method according to any one of claims 6 to 7, characterized in that: The analog circuit block is one of a plurality of analog circuit blocks in the integrated circuit device, and The method also includes importing a test pattern that specifies a corresponding sequence of operating modes for each analog circuit block of the plurality of analog circuit blocks.

10. The built-in self-test method according to claim 9, characterized in that: The method includes disabling the other analog circuit blocks of the plurality of analog circuit blocks during the iterating of the sequence of operating modes of the analog circuit blocks.

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