Chip testing method and chip testing system

Abstract

The invention provides a chip testing method, a chip testing system, a chip testing machine and a computer readable storage medium, and the chip testing method comprises the steps: combining a quality assurance test with a finished product test, i.e., carrying out the finished product test of chips to be tested one by one in a finished product test mode, and counting the chips passing the finished product test, and when the count value passing the finished product test meets the set value corresponding to the sampling frequency required by the quality assurance test, converting the finished product test mode into a quality assurance test mode, and sampling the tested chip passing the finished product test in the previous finished product test mode so as to carry out the quality assurance test. Compared with the prior art, the chip testing method provided by the invention combines finished product testing and quality assurance testing into a whole, the quality assurance testing is carried out in an automatic mode, the production line does not need to additionally carry out the quality assurance testing process again after the finished product testing is completed, and the testing efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a chip testing method, a chip testing system, a chip testing machine, and a computer-readable storage medium that combine finished product testing and quality assurance testing. Background Art

[0002] With the rapid development of the semiconductor industry, modern IC chips tend to be highly integrated and miniaturized, and the design, production and manufacturing are becoming increasingly complicated. Errors in any link can easily lead to product failure. After the IC chip completes the processing and manufacturing process, in order to verify the normal and complete functions of the IC, it needs to be tested and sorted to eliminate defective products. Using good chip testing methods and testing systems is one of the keys to improving chip quality.

[0003] In the semiconductor industry, chips generally need to undergo wafer probe testing (CP) and final testing (FT) before entering the market. Wafer probe testing is a part of important performance testing after the wafer is taped out. Final testing is also called finished product testing, which tests the chip performance and functional quality after the wafer is packaged, and screens out chips with abnormal functions or performance that does not meet the design standards.

[0004] Among them, in the finished product testing process, normal finished product testing requires a random test after completing a complete batch of tests. The random test can also be called quality assurance testing (Quality Assurance; QA). The procedure of the quality assurance test is different from that of the finished product test. The role of the quality assurance test is to use a more relaxed procedure than the finished product test, and to conduct random inspections on qualified products that have passed the finished product test. The logic of the quality assurance test is to use a relaxed test procedure to test qualified products in strict finished product testing. If the test fails, then there is a high probability that there is a loophole in the finished product testing plan. The cause needs to be found out as soon as possible and the loophole needs to be repaired. This is an integral part of the finished product testing quality system.

[0005] In the actual operation of the relevant testing technology, the finished product test is carried out first. After the finished product test is completed, the qualified products that have passed the finished product test are sampled and subjected to quality assurance testing. The qualified products that have passed the quality assurance test need to be put back into the mass production batch. In this way, the relevant testing procedures are quite inconvenient and time-consuming, affecting the overall testing efficiency, and also increasing the risk of mixing. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the related art, the purpose of the present disclosure is to provide a chip testing method, a chip testing system, a chip testing machine, and a computer-readable storage medium to solve various problems in the related art.

[0007] A first aspect of the present disclosure provides a chip testing method, comprising:

[0008] Entering the finished product test mode, performing finished product tests on each chip to be tested one by one; during the finished product test process, when any chip to be tested passes the finished product test, a cumulative count is performed; and

[0009] According to the preset sampling frequency, when the count value that passes the finished product test reaches the set value, the current finished product test mode is converted to the quality assurance test mode, and samples are taken from the tested chips that passed the finished product test in the previous finished product test mode for quality assurance testing.

[0010] In certain examples of the first aspect, the chip testing method includes the step of pre-setting a sampling frequency related to a quality assurance test, and the step of setting the sampling frequency includes: determining the total number of chips in a corresponding batch based on work order information; determining the sampling quantity for performing quality assurance tests in the batch based on the quality specifications of the chips; and calculating the sampling frequency for performing quality assurance tests based on the total number of chips in the batch and the sampling quantity for performing quality assurance tests.

[0011] In certain examples of the first aspect, after the quality assurance test is completed, the current quality assurance test mode is converted to the finished product test mode, and the finished product test is continued to be performed on each chip to be tested one by one until the count value reaches the set value again, and the finished product test mode is converted to the quality assurance test mode, and samples are taken from the tested chips that passed the finished product test in the previous finished product test mode for quality assurance testing.

[0012] In some examples of the first aspect, the count starts when entering the production test mode; the count is cleared when the production test mode is switched to the quality assurance test mode or after the quality assurance test is completed.

[0013] In some examples of the first aspect, sampling from the tested chips that passed the finished product test in the previous finished product test mode for quality assurance testing includes: randomly selecting at least one chip from the tested chips that passed the finished product test in the previous finished product test mode for quality assurance testing.

[0014] In some examples of the first aspect, sampling the tested chips that have passed the finished product test in the previous finished product test mode for quality assurance testing includes: sampling the chip whose count value in the finished product test mode reaches a set value for quality assurance testing.

[0015] In certain examples of the first aspect, in the finished product test mode, chips that pass the finished product test are classified according to their electrical functions, and chips that fail the finished product test are classified as failures according to their electrical functions; in the quality assurance test mode, chips that fail the quality assurance test are stored separately.

[0016] In some examples of the first aspect, the chip testing method further includes separately storing data of finished product testing in the finished product testing mode and data of quality assurance testing in the quality assurance testing mode.

[0017] A second aspect of the present disclosure provides a chip testing system, comprising: a control module, a test conversion module, a finished product testing module, and a quality assurance testing module;

[0018] The control module is used to execute test cases according to the operation instructions, and control the finished product test module and the quality assurance test module to perform corresponding test operations;

[0019] The finished product test module is used to perform finished product tests on each chip to be tested one by one in the finished product test mode; during the finished product test process, when any chip to be tested passes the finished product test, a cumulative count is performed;

[0020] The quality assurance test module is used to sample the tested chips that have passed the finished product test in the previous finished product test mode for quality assurance testing in the quality assurance test mode;

[0021] The test conversion module is controlled by the control module and is used to execute the conversion between the finished product test mode and the quality assurance test mode; wherein, according to the preset sampling frequency, when the count value passing the finished product test reaches the set value, the current finished product test mode is converted to the quality assurance test mode.

[0022] In some examples of the second aspect, the test conversion module is used to convert a current quality assurance test mode to a finished product test mode after the quality assurance test module completes the quality assurance test.

[0023] The third aspect of the present disclosure provides a chip testing system, including: a chip testing machine and a sorting machine communicatively connected to the chip testing machine; the chip testing machine is configured with a testing program, and the chip testing machine controls the sorting machine to grab the chip to be tested according to the testing program and executes the chip testing method described above on the chip to be tested.

[0024] A fourth aspect of the present disclosure provides a chip testing machine, comprising: a processor; a memory storing a test program; wherein the test program executes the chip testing method as described above when executed by the processor.

[0025] A fifth aspect of the present disclosure provides a computer-readable storage medium storing a test program, which executes the chip testing method as described above when the test program is executed.

[0026] As described above, the present disclosure provides a chip testing method, a chip testing system, a chip testing machine, and a computer-readable storage medium, wherein the chip testing method combines quality assurance testing with finished product testing, that is, in the finished product testing mode, each chip to be tested is subjected to finished product testing one by one, and the chips that pass the finished product testing are counted, until the count value that passes the finished product testing meets the set value corresponding to the sampling frequency required by the quality assurance testing, the finished product testing mode is converted to the quality assurance testing mode, and samples are taken from the tested chips that have passed the finished product testing in the previous finished product testing mode to perform quality assurance testing. Compared with the related art, the chip testing method provided by the present disclosure combines finished product testing and quality assurance testing into one, performs quality assurance testing in an automated manner, and does not require the production line to perform the quality assurance testing process again after completing the finished product testing, thereby improving testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a structural block diagram of a chip testing system provided by the present disclosure in one embodiment.

[0028] Figure 2 Display as Figure 1 A schematic diagram of the structure of a chip tester in one embodiment.

[0029] Figure 3 Shown is a schematic flow chart of a chip testing method provided by the present disclosure in one embodiment.

[0030] Figure 4 Shown is a flowchart of a chip testing method provided by the present disclosure in a specific example.

[0031] Figure 5 Shown is a functional block diagram of a chip testing system in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the information disclosed by the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in the present disclosure can also be modified or changed in various ways according to different viewpoints and application modules without departing from the spirit of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0033] The following is a detailed description of the embodiments of the present disclosure with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0034] In the representations of the present disclosure, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or a group of embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present disclosure and the features of different embodiments or examples, unless they are mutually contradictory.

[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of the present disclosure, "a group" means two or more, unless otherwise clearly and specifically defined.

[0036] In order to clearly describe the present disclosure, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0037] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0038] Although the terms first, second, etc. are used to represent various elements in this article in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate that there are the described features, steps, operations, elements, modules, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or a group of other features, steps, operations, elements, modules, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0039] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present disclosure. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0040] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with relevant technical literature and the message of the present disclosure, and shall not be overly interpreted as ideal or very formal meanings unless defined.

[0041] In the actual operation of the relevant chip testing technology, the final test (FT) is carried out first. After the final test is completed, the qualified products that have passed the final test are sampled and subjected to quality assurance test (QA). The qualified products that have passed the quality assurance test need to be put back into the mass production batch. In this way, the relevant testing procedures are quite inconvenient, with a low degree of automation, and are time-consuming, which affects the overall testing efficiency and also increases the risk of material mixing.

[0042] In view of this, a chip testing method, a chip testing system, a chip testing machine, and a computer-readable storage medium are provided in the embodiments of the present disclosure, which can realize the integrated operation of finished product testing and quality assurance testing. In the process of finished product testing, according to the sampling frequency of the quality assurance test, the chips that pass the finished product test are sampled in time for quality assurance testing, and the finished product test and the quality assurance test are combined into one. The quality assurance test is performed in an automated manner, and the production line does not need to re-perform the quality assurance test process after completing the finished product test, thereby improving the testing efficiency.

[0043] The present disclosure provides a chip testing method embodiment which can be executed in a chip testing machine, a similar computing device, or a chip testing system including a chip testing machine or a similar computing device.

[0044] See also Figure 1 , which is a structural block diagram of a chip testing system provided by the present disclosure in one embodiment. Figure 1 As shown, the chip testing system includes a chip testing machine 11 and a sorting machine 13 .

[0045] The sorting machine 13 is used to grab the chips to be tested from the material box and place them on the corresponding test bench, and, according to the sorting instructions of the chip tester 11, grab the chips that have completed the test and transfer them to the corresponding storage tray. In some optional embodiments, after the sorting machine 13 grabs the chips to be tested from the material box and places them on the corresponding test bench, it will send a test start instruction to the chip tester 11, so that the chip tester 11 can test the chips to be tested according to the received test start instruction. In some optional embodiments, after the sorting machine 13 grabs the chips to be tested from the material box and places them on the corresponding test bench, it will send a chip placement completion signal to the chip tester 11, so that the chip tester 11 can test the chips to be tested according to the received chip placement completion signal.

[0046] The chip tester 11 is used to send a test signal to the chip to be tested after receiving a test start instruction from the sorter, obtain a test result according to a feedback signal, and generate and send a sorting instruction to the sorter 13 according to the test result.

[0047] The chip tester 11 establishes a communication connection with the sorter 13. In some optional embodiments, the chip tester 11 may be provided with a first communication port, and the sorter 13 may be provided with a second communication port, and the chip tester 11 establishes a communication connection with the sorter 13 through the first communication port and the second communication port.

[0048] Exemplarily, the chip tester 11 and the sorter 13 establish a communication connection through a sorting signal line, so that the chip tester 11 can send a sorting instruction to the sorter 13 through the sorting signal line. Of course, the sorter 13 can send a test start instruction to the chip tester 11 through the sorting signal line.

[0049] Exemplarily, the chip tester 11 and the sorter 13 establish a communication connection through wireless communication, so that the chip tester 11 can send a sorting instruction to the sorter 13 through wireless communication, and of course, the sorter 13 can send a test start instruction to the chip tester 11 through wireless communication. The wireless communication protocol includes: for example, one or more of Near Field Communication (NFC) technology, infrared (IR) technology, mobile communication technology (for example, GSM, WCDMA, LTE, NR, etc.), Bluetooth, etc.

[0050] The chip tester 11 establishes a connection with the chip to be tested. In some optional embodiments, the chip tester 11 can be electrically connected to the chip to be tested through a test cable. Exemplarily, the chip to be tested can be placed on a test bench 15, and the number of the test benches 15 can be one or more. Correspondingly, the chip tester 11 can be provided with one or more test ports, which are electrically connected to at least one test bench 15 through the test cable. In this way, the chip tester 11 and the chip on at least one test bench 15 can transmit test signals and test results through the test cable.

[0051] Through the chip testing system in the above embodiment, an integrated chip test combining finished product testing and quality assurance testing can be performed on the chip to be tested, thereby improving the testing efficiency.

[0052] The finished product test may also be called the final test (FT), which is to test the chip performance and functional quality after the wafer packaging is completed, and screen out chips with abnormal functions or performance that does not meet the design standards.

[0053] The quality assurance test (QA) is a random test of the chips that have passed the finished product test after a full batch of normal finished product tests are completed. Generally, the quality assurance test is a test that is more relaxed than the finished product test.

[0054] See also Figure 2 , displayed as Figure 1 A schematic diagram of the structure of a chip tester in one embodiment.

[0055] The chip tester 11 includes a processor 111 and a memory 113. The processor 111 and the memory 113 can communicate with each other through a bus 112. A test program can be stored in the memory 113. The processor 111 executes each step of the integrated chip test combined with the finished product test and the quality assurance test by running the test program in the memory 113.

[0056] The bus 112 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, although only one thick line is used in the figure, it does not mean that there is only one bus or one type of bus.

[0057] In some embodiments, the processor 111 may be implemented as a central processing unit (CPU), a microcontroller unit (MCU), a system on chip (SoC), or a field programmable gate array (FPGA). The memory 113 may include a volatile memory for temporary storage of data when running a program, such as a random access memory (RAM). The memory 113 may also include a non-volatile memory for data storage, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid-state disk (SSD).

[0058] In some embodiments, the chip tester 11 may also include a communicator or a communication port. The communicator or communication port is used to communicate with the outside. In a specific example, the communicator or communication port may include one or a group of wired and / or wireless communication circuit modules. For example, the wired communication circuit module may include one or more of a wired network card, a USB module, a serial interface module, etc. The wireless communication protocols followed by the wireless communication module include: for example, one or more of NFC technology, infrared (IR) technology, global system for mobile communications (GSM), code division multiple access (CDMA), wideband code division multiple access (WCDMA), long term evolution (LTE), new air interface (NR), Bluetooth (BT), global navigation satellite system (GNSS), etc.

[0059] Based on the chip testing system and the chip testing machine in the chip testing system in the above-mentioned embodiments, the present disclosure further provides a chip testing method, in which both a finished product testing process and a quality assurance testing process are included, so that quality assurance testing can be performed in an automated manner during the finished product testing process.

[0060] See also Figure 3 , which is a schematic diagram showing a flow chart of a chip testing method provided by the present disclosure in one embodiment.

[0061] like Figure 3 As shown, the chip testing method may include the following steps:

[0062] Step S301, entering the finished product test mode, and performing finished product tests on each chip to be tested one by one.

[0063] In this embodiment, the quality assurance test is to perform a random test on the chips that have passed the finished product test after the normal finished product test completes a complete batch of tests. That is, for a certain set batch, the quality assurance test is performed after the finished product test of the batch of chips is completed. Therefore, when the test program is started, the default is to enter the finished product test mode, and the finished product test is performed one by one on each of the chips to be tested in a set number of batches.

[0064] In the present invention, the chip testing method further comprises the step of presetting a sampling frequency associated with a quality assurance test.

[0065] In some optional embodiments, the step of setting a sampling frequency associated with quality assurance testing includes:

[0066] Step 1-1, determine the total number of chips in the corresponding batch according to the work order information. In view of the fact that the quality assurance test is a random test of the chips that have passed the finished product test after the normal finished product test completes a full batch of tests, the chips in the corresponding batch mentioned here refer to the chips that have passed the finished product test, that is, determining the total number of chips in the corresponding batch is to determine the total number of chips that have passed the finished product test in the corresponding batch.

[0067] Step 1-2, determining the sampling quantity for performing quality assurance test in the batch according to the quality specification of the chip.

[0068] Exemplarily, step 1-2 determines the sampling quantity and is performed according to the sampling standard. The sampling standard refers to a set of criteria for selecting samples from a population according to certain rules and methods when performing quality control and statistical analysis. For example, the recipient of a batch of products or materials usually refers to the AQL (Acceptable Quality Level) to formulate a sampling plan. The AQL sampling standard is a definition of the product quality acceptance level and determines the criteria for determining qualified and unqualified products.

[0069] Step 1-3, according to the total number of chips in the batch and the sampling quantity for performing quality assurance testing, calculate the sampling frequency for performing quality assurance testing. Exemplarily, the sampling frequency is the quotient of the sampling quantity for performing quality assurance testing in the batch and the total number of chips for performing finished product testing in the batch, that is, sampling frequency = sampling quantity / total number of batches.

[0070] Exemplarily, if the total number of chips in the batch that perform finished product testing is 10,000, and the sampling quantity requirement in the AQL sampling standard is 500, then the sampling frequency for performing the quality assurance test is 500 / 1000=1 / 20, that is, one chip is sampled from twenty chips that pass the finished product test for quality assurance testing. Exemplarily, if the total number of chips in the batch that perform finished product testing is 10,000, and the sampling quantity requirement in the AQL sampling standard is 450, then the sampling frequency for performing the quality assurance test is 450 / 10000=9 / 200=1 / 22.2, so that one chip can be sampled from twenty-three chips that pass the finished product test for quality assurance testing.

[0071] In actual applications, in some optional embodiments, the set sampling frequency associated with the quality assurance test is written into a dedicated file for the test program to read. Alternatively, in some optional embodiments, the set sampling frequency associated with the quality assurance test is directly written into the test program.

[0072] As can be seen from the above, sampling can be performed according to the calculated sampling frequency for performing quality assurance testing to perform quality assurance testing. For the convenience of actual operation, the sampling frequency for performing quality assurance testing is simplified to 1 / N, where N is the quotient of sampling quantity / total batch quantity rounded up, so as to ensure that the actual sampling is greater than the theoretical value. In this way, in operation, after each chip that passes the finished product test reaches N, 1 chip is sampled from the N chips that pass the finished product test for quality assurance testing. Therefore, when performing finished product testing, it is necessary to count the chips that pass the finished product test. In step S301, when entering the finished product test mode, the count is zero and starts counting. During the finished product test process, the chips that pass the finished product test are counted, that is, when any chip to be tested passes the finished product test, the count is accumulated.

[0073] For each chip, when performing finished product testing, generally, the sorting machine receives the sorting instruction of the chip tester, grabs the chip to be tested from the material box, transfers it and places it on the corresponding test bench, so that after the chip to be tested is placed on the test bench, it can be electrically connected to the chip tester through the test cable, and then the sorting machine sends a test start instruction or a signal that the chip has been placed to the chip tester. According to the received test start instruction or the signal that the chip has been placed, the chip tester sends a test signal to the chip to be tested through the test cable to perform finished product testing. Subsequently, the chip tester receives the test result corresponding to the chip to be tested through the test cable, and determines whether the chip to be tested has passed the finished product test according to the test result and the test specification of the finished product test. If it is determined that the chip to be tested has passed the finished product test, the count value is incremented by 1, and at the same time, a sorting signal is sent to the sorting machine to enable the sorting machine to transfer the chip to the corresponding classification box of normal products (or good products) according to its electrical function; if it is determined that the chip to be tested has not passed the finished product test, the count value remains unchanged, and a sorting signal is sent to the sorting machine to enable the sorting machine to transfer the chip to the corresponding failure classification box of abnormal products (or defective products) according to its electrical function.

[0074] Step S303, according to the preset sampling frequency, when the count value of finished product test reaches the set value, the current finished product test mode is converted to the quality assurance test mode, and samples are taken from the tested chips that have passed the finished product test in the previous finished product test mode for quality assurance testing.

[0075] In step S301, in the finished product test mode, each chip to be tested is subjected to a finished product test one by one in sequence. If the current chip passes the finished product test, a cumulative count is performed, the count value is accumulated by 1, and it is determined whether the accumulated count value reaches the set value corresponding to the sampling frequency. If the count value does not reach the set value corresponding to the sampling frequency, the next chip to be tested is subjected to a finished product test; if the current chip does not pass the finished product test, the count value remains unchanged, and the next chip to be tested is subjected to a finished product test. In this way, until the count value that passes the finished product test reaches the set value corresponding to the sampling frequency, the current finished product test mode is converted to a quality assurance test mode, and samples are taken from the tested chips that have passed the finished product test in the previous finished product test mode for quality assurance testing.

[0076] The quality assurance test is a more relaxed test than the finished product test, and its purpose is to use a relaxed test procedure to test qualified products in strict finished product testing to check whether there are any loopholes in the finished product testing plan.

[0077] When the production test mode is switched to the quality assurance test mode, samples are taken from the tested chips that have passed the production test in the previous production test mode for quality assurance testing.

[0078] In some optional embodiments, sampling from the tested chips that passed the finished product test in the previous finished product test mode for quality assurance testing includes: randomly selecting at least one chip from the tested chips that passed the finished product test in the previous finished product test mode for quality assurance testing.

[0079] Exemplarily, in actual operation, during the finished product test, if the current chip passes the finished product test, an accumulated count is performed, the count value is accumulated by 1, and it is determined whether the accumulated count value reaches the set value corresponding to the sampling frequency. If the count value reaches the set value corresponding to the sampling frequency, a sorting signal is sent to the sorting machine to enable the sorting machine to transfer the chip to the corresponding classification box of normal products (or good products) according to its electrical function; the finished product test mode is converted to a quality assurance test mode, and a sorting signal is sent to the sorting machine to enable the sorting machine to randomly select a chip from the corresponding classification box of normal products (or good products) and transfer it to the corresponding test bench, so that the randomly selected chip can be placed on the test bench and electrically connected to the chip tester through the test cable, and then the sorting machine sends a test start instruction or a chip placement completion signal to the chip tester, and the chip tester sends a test signal to the randomly selected chip through the test cable according to the received test start instruction or chip placement completion signal to perform a quality assurance test.

[0080] In some optional embodiments, sampling from the tested chips that have passed the finished product test in the previous finished product test mode for quality assurance testing includes: sampling the chip whose count value in the finished product test mode reaches the set value for quality assurance testing.

[0081] For example, in actual operation, during the finished product test, if the current chip passes the finished product test, an accumulated count is performed, the count value is accumulated by 1, and it is determined whether the accumulated count value reaches the set value corresponding to the sampling frequency. If the count value reaches the set value corresponding to the sampling frequency, the finished product test mode is converted to a quality assurance test mode, and the chip tester sends a test signal to the current chip through the test cable for quality assurance testing.

[0082] The chip whose count value in the finished product test mode reaches the set value is directly sampled for quality assurance testing. There is no need to operate a sorting machine. The chip testing machine only needs to convert the finished product test mode into the quality assurance test mode and send a test signal for quality assurance testing to the current chip. Compared with other testing methods, the testing efficiency can be improved.

[0083] In step S303, in the quality assurance test mode, the chips that have passed the finished product test are sampled and then subjected to quality assurance testing. If the chip passes the quality assurance test, the chip is transferred to a corresponding classification box of normal products (or good products) according to its electrical function; if the chip fails the quality assurance test, the chip is stored separately, for example, in a dedicated quality assurance test failure classification box.

[0084] In the chip testing method disclosed in the present invention, after the quality assurance test is completed, the current quality assurance test mode is converted to the finished product test mode, and the finished product test is continued to be performed on each chip to be tested one by one until the count value reaches the set value again, and the finished product test mode is converted to the quality assurance test mode, and samples are taken from the tested chips that have passed the finished product test in the previous finished product test mode for quality assurance testing.

[0085] When the finished product test mode is switched to the quality assurance test mode or after the quality assurance test is completed, the count is reset.

[0086] In this way, through the above steps, the finished product test and the quality assurance test can be combined to complete the chip test. The quality assurance test is performed in an automated manner, and the production line does not need to perform the quality assurance test process again after the finished product test is completed, thereby improving the test efficiency. The data obtained by performing the quality assurance test in the quality assurance test mode can be used to check whether there are any loopholes in the finished product test plan.

[0087] In addition, the chip testing method disclosed in the present invention also includes separately storing data of finished product testing in the finished product testing mode and data of quality assurance testing in the quality assurance testing mode.

[0088] See also Figure 4 , which is a flow chart of a chip testing method provided by the present disclosure in a specific example.

[0089] Step S401, enter the finished product test mode and start counting.

[0090] Step S403: Select a chip to be tested and perform a finished product test on the chip to be tested.

[0091] Step S405: determine whether the chip to be tested has passed the finished product test according to the test result.

[0092] Step S407: If it is determined that the chip to be tested has not passed the finished product test, the count value remains unchanged, and the chip is transferred to the corresponding failure classification box of abnormal products according to its electrical function.

[0093] Step S409: If it is determined that the chip to be tested has passed the finished product test, the count value is incremented by 1.

[0094] Step S411, determining whether the count value reaches a set value corresponding to the sampling frequency.

[0095] In step S413, if the count value does not reach the set value corresponding to the sampling frequency, the chip is transferred to the corresponding classification box of normal products according to its electrical function, and the process returns to step S403 to continue the finished product test on the next chip to be tested.

[0096] Step S415, if the count value reaches the set value corresponding to the sampling frequency, the finished product test mode is converted to the quality assurance test mode; and the quality assurance test is performed on the chip that currently reaches the set value.

[0097] Step S417: determine whether the chip has passed the quality assurance test based on the test results.

[0098] If the chip passes the quality assurance test, it will be transferred to the corresponding classification box of normal products according to its electrical function.

[0099] Step S419: If the chip fails the quality assurance test, the chip is stored in a dedicated quality assurance test failure classification box.

[0100] The present disclosure also provides a chip testing system corresponding to the chip testing method.

[0101] See also Figure 5 , which is a functional block diagram of a chip testing system disclosed in one embodiment.

[0102] like Figure 5 As shown, the chip testing system includes: a control module 51 , a test conversion module 53 , a finished product testing module 55 , and a quality assurance testing module 57 .

[0103] The control module 51 is used to execute test cases according to the operation instructions, and control the finished product test module 55 and the quality assurance test module 57 to perform corresponding test operations. Specifically, the control module 51 is used to control the finished product test module 55 to perform finished product testing, and the control module 51 is used to control the quality assurance test module 57 to perform quality assurance testing.

[0104] The finished product test module 55 is used to perform finished product tests on each chip to be tested one by one in the finished product test mode; during the finished product test process, when any chip to be tested passes the finished product test, a cumulative count is performed.

[0105] The quality assurance test module 57 is used to sample the tested chips that have passed the final product test in the final product test mode for quality assurance test in the quality assurance test mode.

[0106] The test conversion module 53 is controlled by the control module and is used to execute the conversion between the finished product test mode and the quality assurance test mode; wherein, according to the preset sampling frequency, when the count value passing the finished product test reaches the set value, the current finished product test mode is converted to the quality assurance test mode; after the quality assurance test module completes the quality assurance test, the current quality assurance test mode is converted to the finished product test mode.

[0107] It should be noted that the chip test system disclosed in the above embodiment and the chip test method disclosed in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs the operation has been described in detail in the method embodiment and will not be repeated here. In practical applications, the chip test system disclosed in the above embodiment can allocate the above functions to different functional modules as needed, that is, divide the internal structure of the system into different functional modules to complete all or part of the functions described above, and this is not limited here.

[0108] In an embodiment of the present disclosure, a computer-readable storage medium may be provided, storing a computer program or instructions, which, when executed, implements the method flow or functions in any of the previous embodiments.

[0109] That is, the method steps in the above embodiments are implemented as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or are implemented as computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded via a network and to be stored in a local recording medium, so that the method represented herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA).

[0110] In the embodiments of the present disclosure, a computer program product may be provided, one or more computer programs or instructions, which, when executed, fully or partially execute the process or function in the embodiments of the present disclosure. The computer program product includes one or more computer programs or instructions.

[0111] The computer program or instructions may be stored in a readable storage medium or transmitted from one readable storage medium to another readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired or wireless means. The readable storage medium may be any available medium that can be accessed or a data storage device such as a server, data center, etc. that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it may also be an optical medium, such as a digital video disk; it may also be a semiconductor medium, such as a solid state drive. The computer readable storage medium may be a volatile or non-volatile storage medium, or may include both volatile and non-volatile types of storage media.

[0112] The present disclosure provides a chip testing method, a chip testing system, a chip testing machine, and a computer-readable storage medium. The chip testing method combines quality assurance testing with finished product testing, that is, in the finished product testing mode, each chip to be tested is subjected to finished product testing one by one, and the chips that pass the finished product testing are counted until the count value that passes the finished product testing meets the set value corresponding to the sampling frequency required by the quality assurance testing, and then the finished product testing mode is converted to the quality assurance testing mode, and samples are taken from the tested chips that have passed the finished product testing in the previous finished product testing mode to perform quality assurance testing. Compared with the related art, the chip testing method provided by the present disclosure combines finished product testing and quality assurance testing in one, performs quality assurance testing in an automated manner, and does not require the production line to perform the quality assurance testing process again after completing the finished product testing, thereby improving testing efficiency.

[0113] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the protection scope of the present disclosure.

Claims

1. A chip testing method, characterized in that: The steps include: Enter the finished product test mode and perform finished product tests on each chip to be tested one by one; during the finished product test process, when any chip to be tested passes the finished product test, the count is accumulated; as well as According to the preset sampling frequency, when the count value that passes the finished product test reaches the set value, the current finished product test mode is converted to the quality assurance test mode, and samples are taken from the tested chips that passed the finished product test in the previous finished product test mode for quality assurance testing.

2. The chip testing method according to claim 1, characterized in that: The method comprises the steps of presetting a sampling frequency associated with a quality assurance test, wherein the step of presetting the sampling frequency comprises: According to the work order information, determine the total number of chips in the corresponding batch; Determining a sampling amount of the batch for performing quality assurance testing based on the quality specifications of the chip; and The sampling frequency for performing the quality assurance test is calculated based on the total number of chips in the batch and the sampling amount for performing the quality assurance test.

3. The chip testing method according to claim 1, characterized in that: After completing the quality assurance test, the current quality assurance test mode is converted to the finished product test mode, and the finished product test is continued on each chip to be tested one by one until the count value reaches the set value again, and the finished product test mode is converted to the quality assurance test mode, and samples are taken from the tested chips that passed the finished product test in the previous finished product test mode for quality assurance testing.

4. The chip testing method according to claim 1 or 3, characterized in that: The count starts when entering the finished product test mode; the count is reset to zero when the finished product test mode is switched to the quality assurance test mode or after the quality assurance test is completed.

5. The chip testing method according to claim 1, characterized in that: The sampling from the tested chips that passed the finished product test in the previous finished product test mode for quality assurance test includes: randomly selecting at least one chip from the tested chips that passed the finished product test in the previous finished product test mode for quality assurance test.

6. The chip testing method according to claim 1, characterized in that: The sampling of the tested chips that have passed the finished product test in the previous finished product test mode for quality assurance test includes: taking the chip whose count value in the finished product test mode reaches the set value as a sample for quality assurance test.

7. The chip testing method according to claim 1, characterized in that: In the finished product test mode, the chips that pass the finished product test are classified according to their electrical functions, and the chips that fail the finished product test are classified as failures according to their electrical functions; in the quality assurance test mode, the chips that fail the quality assurance test are stored separately.

8. The chip testing method according to claim 1, characterized in that: The method also includes separating and storing data of finished product testing in the finished product testing mode and data of quality assurance testing in the quality assurance testing mode.

9. A chip testing system, characterized in that: include: control module, test conversion module, finished product test module, and quality assurance test module; The control module is used to execute test cases according to the operation instructions, and control the finished product test module and the quality assurance test module to perform corresponding test operations; The finished product test module is used to perform finished product tests on each chip to be tested one by one in the finished product test mode; during the finished product test process, when any chip to be tested passes the finished product test, a cumulative count is performed; The quality assurance test module is used to sample the tested chips that have passed the finished product test in the previous finished product test mode for quality assurance testing in the quality assurance test mode; The test conversion module is controlled by the control module and is used to execute the conversion between the finished product test mode and the quality assurance test mode; wherein, according to the preset sampling frequency, when the count value passing the finished product test reaches the set value, the current finished product test mode is converted to the quality assurance test mode.

10. The chip testing system according to claim 9, characterized in that: The test conversion module is used to convert the current quality assurance test mode into a finished product test mode after the quality assurance test module completes the quality assurance test.

11. A chip testing system, characterized in that: include: A chip tester and a sorter communicatively connected to the chip tester; the chip tester is configured with a test program, and the chip tester controls the sorter according to the test program to grab the chip to be tested and execute the chip testing method as described in any one of claims 1 to 8 on the chip to be tested.

12. A chip testing machine, characterized in that: include: processor; A memory storing a test program; Wherein, when the test program is executed by the processor, the chip testing method as described in any one of claims 1 to 8 is executed.

13. A computer-readable storage medium, characterized in that: A test program is stored, and when the test program is executed, the chip testing method according to any one of claims 1 to 8 is executed.

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