A Reconfigurable GNSS Signal Processing System

Abstract

The present invention relates to the field of satellite receiver technology, and specifically discloses a reconfigurable GNSS signal processing system, the system comprising: a preprocessing filter, a correlator channel, a DFT unit and a processor, the processor is respectively connected to the preprocessing filter, the correlator channel and the DFT unit, the preprocessing filter is connected to the correlator channel, the correlator channel is connected to the DFT unit, and the preprocessing filter, the correlator channel and the DFT unit are all composed of an array consisting of a complex accumulator operator, a digital waveform generator and a pseudo-random code generator. The preprocessing filter, the correlator channel and the DFT unit of the present application are all composed of an array consisting of a complex accumulator operator, a digital waveform generator and a pseudo-random code generator, and the array can be freely configured according to different functional requirements, which greatly reduces the complexity of the chip, improves the utilization rate of logic resources, and reduces the chip area and power consumption.

Description

Background Art

[0002] After more than 40 years of development, satellite navigation has been widely used in various fields of social life. Satellite navigation can improve the accuracy of time and space information. It has become the time and space benchmark for the Internet of Everything and Intelligence of Everything. It also puts forward higher requirements on satellite navigation receivers. Satellite navigation receivers are mainly used to process GNSS signals (Global Navigation Satellite System, wireless signals transmitted by the GNSS global navigation satellite system).

[0003] However, the existing processing of GNSS signals requires integrating different computing units on a chip, which increases the chip area and power consumption. Summary of the invention

[0004] In order to overcome the problem of increasing the chip area and power consumption by integrating different operation units on a chip in the existing GNSS signal processing, the present invention provides a reconfigurable GNSS signal processing system.

[0005] In order to solve the above technical problems, the present invention provides a reconfigurable GNSS signal processing system, including: a preprocessing filter, a correlator channel, a DFT unit and a processor, the processor is respectively connected to the preprocessing filter, the correlator channel and the DFT unit, the preprocessing filter is connected to the correlator channel, the correlator channel is connected to the DFT unit, and the preprocessing filter, the correlator channel and the DFT unit are all composed of an array consisting of a complex accumulator operator, a digital waveform generator and a pseudo-random code generator.

[0006] The beneficial effects of the present invention are as follows: the preprocessing filter, correlator channel and DFT unit of the present application are all composed of an array consisting of a complex accumulator operator, a digital waveform generator and a pseudo-random code generator, and the array can be freely configured according to different functional requirements, which greatly reduces the complexity of the chip, improves the utilization rate of logic resources, and reduces the chip area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0008] Figure 1 A schematic diagram of the structure of a reconfigurable GNSS signal processing system according to an embodiment of the present invention;

[0009] Figure 2 It is a structural schematic diagram of the complex accumulator operator of the present invention;

[0010] Figure 3 It is a structural schematic diagram of a digital waveform generator of the present invention;

[0011] Figure 4 is a schematic diagram of the structure of a feedback shift register;

[0012] Figure 5 It is a structural schematic diagram of a shift sampling pulse generator;

[0013] Figure 6 It is a structural diagram of the preprocessing filter;

[0014] Figure 7 is a structural diagram of a correlator channel;

[0015] Figure 8 Schematic diagram of the structure of the DFT unit. DETAILED DESCRIPTION

[0016] The following examples are provided to further explain and supplement the present invention and do not constitute any limitation to the present invention.

[0017] A reconfigurable GNSS signal processing system according to an embodiment of the present invention is described below with reference to the accompanying drawings.

[0018] like Figure 1 As shown, the present invention provides a reconfigurable GNSS signal processing system, including: a preprocessing filter, a correlator channel, a DFT unit and a processor (which may be a CPU in this embodiment), the processor is respectively connected to the preprocessing filter, the correlator channel and the DFT unit, the preprocessing filter is connected to the correlator channel, the correlator channel is connected to the DFT unit, and the preprocessing filter, the correlator channel and the DFT unit are all composed of an array consisting of a complex accumulator operator, a digital waveform generator and a pseudo-random code generator.

[0019] In this embodiment, the preprocessing filter, correlator channel and DFT unit of the present application are all composed of an array consisting of a complex accumulator operator, a digital waveform generator and a pseudo-random code generator. The array can be freely configured according to different functional requirements, which greatly reduces the complexity of the chip, improves the utilization of logic resources, and reduces the chip area and power consumption.

[0020] like Figure 2 As shown, the complex accumulator operator MAC (Multiply And Accumulate) includes 7 ports, namely A port, B port, C port, Cin port, AccMode port, MulMode port, ShiftBits port, and its output result is Result and a Cout.

[0021] The complex accumulator operator can achieve different functions through different module configurations, as shown in Table 1 below:

[0022] Table 1 Complex accumulator operator configuration table

[0023]

[0024] Among them, the Cin port controls whether the Reverse module performs a reverse operation on the input signal B. When the Cin port is 0, it does not reverse, B'=B. When the Cin port is 1, the signal B is reversed to obtain -B, that is, the signal B'=-B.

[0025] The latch is used to control whether the Cin port needs to be latched. When the latch is at a high level, the signal of the Cin port is stored in the register, and Cout is the output of the register.

[0026] The ShiftBits port is used to perform a shift operation on the complex accumulator operator output to obtain the final output Result.

[0027] like Figure 3 As shown, the digital waveform generator (Digital Wave Generator) consists of an accumulator and a lookup table. Different waveforms can be generated according to different lookup tables.

[0028] The waveform period in the digital waveform generator is controlled by inputting a frequency control word, and the real part and the imaginary part of the waveform are output by the digital waveform generator.

[0029] In addition, the fluctuation phase = the original fluctuation phase + the frequency control word;

[0030] Take the high w bits (the wth bit) of the wave phase as the index value of the lookup table, and address the lookup table through the index value to obtain the real and imaginary parts of the output waveform:

[0031] Real = LUT_R[Index],Imag = LUT_I[Index]

[0032] Among them, Real represents the real part, LUT_R represents the lookup table R, and LUT_I represents the lookup table I.

[0033] The pseudo random code generator PRNG (Pseudo Random Noise Generator) consists of two feedback shift registers and a shift sampling pulse generator. The bit mask is used to control the target bit of the feedback shift register to participate in the XOR operation. The formula is as follows:

[0034]

[0035] Among them, X represents the output result of the pseudo-random code generator, Indicates the i-th bit of the feedback shift register, Represents the i-th bit of the bit mask, i=0, 1,...n, n represents the length of the feedback shift register.

[0036] like Figure 4 As shown in the figure, the two feedback shift registers have both serial and parallel modes, which are controlled by the Mode signal. When mode=0, it works in parallel mode, and the outputs of the two feedback shift registers are XORed as the output, that is, PRNCode=Code A signal^Code B signal, Code A signal represents the signal output by feedback shift register A, and Code B signal represents the signal output by feedback shift register B; when mode=1, it works in serial mode, at this time, the two feedback shift registers are cascaded into a longer feedback shift register, and the output of feedback shift register B is used as the output of PRNG, that is, PRNCode=CodeB signal.

[0037] like Figure 5 As shown, the shift sampling pulse generator includes CodeFreq and CodeNCO, CodeFreq and CodeNCO are used to generate a code sampling pulse period, wherein the bit width of CodeNco and CodeFreq is typically 32 bits.

[0038]

[0039] When CodeNco overflows during the accumulation process, a sampling pulse is generated. The sampling pulse is used to sample the pseudo-random code.

[0040] SubCnt is incremented by 1 each time a sampling pulse is generated, and is cleared when the accumulated value reaches the preset value. At the same time, when a sampling pulse is generated, CodeShift is used to control the feedback shift register to shift.

[0041] In this embodiment, by combining the above three basic operators (an array consisting of a complex accumulator operator, a digital waveform generator and a pseudo-random code generator), operations such as filtering, downsampling, carrier stripping and correlation operations, as well as DFT and other operations on GNSS signals can be implemented, thereby realizing signal capture and tracking, thereby completing the processing of baseband signals.

[0042] Optionally, the preprocessing filter is composed of a first digital waveform generator and a plurality of first complex accumulator operators.

[0043] In this embodiment, a first digital waveform generator and a plurality of first complex accumulator operators constitute a preprocessing filter, which performs down-conversion and low-pass filtering on the digital intermediate frequency signal to achieve filtering processing on the GNSS signal.

[0044] Optionally, in the preprocessing filter, the first digital waveform generator is connected to the first first complex accumulator operator, the first first complex accumulator operator is configured in multiplication mode, and the first digital waveform generator is configured as a complex sine wave; the second to last first complex accumulator operators are all configured in multiplication-addition mode.

[0045] like Figure 6 As shown, multiple first complex accumulator operators are represented by MAC 0-MAC n-1 respectively. It can be seen that MAC0+digital waveform generator constitutes a digital down converter DDC (Digital Down Converter), and MAC 1-MAC n-1 constitute a low-pass filter.

[0046] Optionally, each first complex accumulator operator is configured with 7 ports, wherein:

[0047] The first port of the first complex accumulator operator is connected to the GNSS signal;

[0048] The second port of the first complex accumulator operator is connected to the output of the first digital waveform generator;

[0049] The first ports of the second to the last first complex accumulator operators are respectively connected to the output of the first first complex accumulator operator;

[0050] In the second to last second complex accumulator operator, the output of the previous first complex accumulator operator is cascaded to the third port of the next first complex accumulator operator;

[0051] Configure the second port of the second to last first complex accumulator operator as a filter coefficient.

[0052] In this embodiment, the structure of the preprocessing filter is as follows: Figure 6 As shown, the details are as follows:

[0053] a: Configure MAC 0 to multiplication mode and the digital waveform generator to complex sine wave;

[0054] b: Port A (the first port) of MAC 0 is connected to the input intermediate frequency signal, and port B (the second port) of MC 0 is connected to the output of the digital waveform generator;

[0055] c: Configure MA 1~MAC n-1 to multiply-add mode;

[0056] d: Input A (first port) of MAC 1~MAC n-1 is connected to the output of MAC0;

[0057] e: Cascade the output of MAC x (the previous complex accumulator operator) and C (the third port) of MAC x+1 (the next complex accumulator operator);

[0058] f: Input port B (the second port) of MAC 1~MAC n-1 is the filter coefficient.

[0059] Optionally, the correlator channel is composed of a second digital waveform generator, a pseudo-random code generator and a plurality of second complex accumulator operators.

[0060] In this embodiment, a correlator channel is composed of a second digital waveform generator, a pseudo-random code generator and a plurality of second complex accumulator operators, which strip the carrier and pseudo-random code of the GNSS signal to obtain a correlation value.

[0061] Optionally, in the correlator channel, the second digital waveform generator is connected to the first second complex accumulator operator, the first second complex accumulator operator is configured in multiplication mode, the second digital waveform generator is configured as a complex sine wave, and the second to last second complex accumulator operators are configured in multiplication-accumulation mode.

[0062] like Figure 7 As shown, multiple second complex accumulator operators are represented by MAC 0-MAC n-1 respectively. It can be seen that MAC0+digital waveform generator constitutes a digital down converter DDC (Digital Down Converter), and each of the remaining second complex accumulator operators is a correlator channel.

[0063] Optionally, each second complex accumulator operator is configured with 7 ports, wherein:

[0064] The first port of the first second complex accumulator operator is connected to the GNSS signal;

[0065] The second port of the first second complex accumulator operator is connected to the output of the second digital waveform generator;

[0066] The second ports of the second to the last second complex accumulator operators are respectively connected to the output of the first second complex accumulator operator, and the first ports are connected to a preset constant value;

[0067] Connecting the output of the pseudo-random code generator to the third port of the second second complex accumulator operator, and linking the pulse generated by the pseudo-random code generator to the latch of the second to last second complex accumulator operator;

[0068] In the second to last second complex accumulator operator, the output of the register of the previous second complex accumulator operator is cascaded to the fourth port of the next second complex accumulator operator;

[0069] At the end of the pseudo-random code generator cycle, the output value of the second to last second complex accumulator operator is latched to obtain the correlation value of different phases with the same number of second complex accumulators with an integration time of one code period, and the second to last second complex accumulator operator is cleared at the same time.

[0070] In this embodiment, the structure of the correlator channel is as follows: Figure 7 As shown, the details are as follows:

[0071] a: Configure MAC 0 to multiplication mode and configure the digital waveform generator to complex sine wave;

[0072] b: Port A (the first port) of MAC 0 is connected to the input intermediate frequency signal, and port B (the second port) of MC 0 is connected to the output of the digital waveform generator;

[0073] c: Configure MA 1~MAC n-1 to multiply-accumulate mode;

[0074] d: Port B (the second port) of MAC 1~MAC n-1 is connected to the output of MAC 0, and port A (the first port) is connected to the constant value 1;

[0075] e: Configure a PRNG, connect the PRNCode (PRNG output) of the PRNG to the Cin (third port) of MAC 1, and the SmaplePulse (pulse) of the PRNG to the Latch (latch) of MAC1~MAC n-1;

[0076] f: Cascade the Cout (register output) of MAC x to the Cin (fourth port) of MAC x+1;

[0077] g: At the end of the PRNG cycle, latch the output values ​​of MAC 1 to MAC n-1 to obtain n-1 (the same number as the number of complex accumulators) correlation values ​​with different phases with an integration time of one code period, and clear MAC 1 to MAC n-1 at the same time.

[0078] Optionally, the DFT unit is composed of a third digital waveform generator and a plurality of third complex accumulator operators.

[0079] In this embodiment, a third digital waveform generator and a plurality of third complex accumulator operators constitute a DFT unit to complete the carrier Doppler search.

[0080] Optionally, in the DFT unit, the third digital waveform generator is configured as a complex sine wave, multiple third complex accumulator operators are all configured as a multiplication-accumulation mode, and the third digital waveform generator is connected to the last third complex accumulator operator.

[0081] In this embodiment, the structure of the DFT unit is as follows: Figure 8 As shown, a plurality of third complex accumulator operators are represented by MAC 0-MAC n-1, respectively, as follows:

[0082] a: Configure the digital waveform generator to a complex sine wave;

[0083] b: Configure MA 1~MAC n-1 to multiply-accumulate mode;

[0084] d: The correlator values ​​of multiple correlator channels are processed in sequence to obtain integrals of different frequencies, thereby completing the frequency search of the signal.

[0085] Optionally, there are multiple correlator channels, and the multiple correlator channels constitute a correlator channel group.

[0086] In this embodiment, a configured correlator channel is replicated into CH-N copies to form a correlator channel group, and the correlator values ​​of the CH-N correlator channels are processed in turn to obtain integrals of different frequencies, thereby completing the frequency search of the signal.

[0087] Those skilled in the art know that the present invention can be implemented as a system, method or computer program product. Therefore, the present disclosure can be specifically implemented in the following forms, namely: it can be complete hardware, it can be complete software (including firmware, resident software, microcode, etc.), or it can be a combination of hardware and software, generally referred to as "circuit", "module" or "system" herein. In addition, in some embodiments, the present invention can also be implemented in the form of a computer program product in one or more computer-readable media, and the computer-readable medium contains computer-readable program code. Computer-readable storage media can be, for example, but not limited to - electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above.

[0088] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0089] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A reconfigurable GNSS signal processing system, characterized in that: include: A preprocessing filter, a correlator channel, a DFT unit and a processor, wherein the processor is connected to the preprocessing filter, the correlator channel and the DFT unit respectively, the preprocessing filter is connected to the correlator channel, the correlator channel is connected to the DFT unit, the preprocessing filter is composed of a first digital waveform generator and a plurality of first complex accumulator operators, the correlator channel is composed of a second digital waveform generator, a pseudo-random code generator and a plurality of second complex accumulator operators, and the DFT unit is composed of a third digital waveform generator and a plurality of third complex accumulator operators.

2. The system according to claim 1, characterized in that In the preprocessing filter, the first digital waveform generator is connected to the first first complex accumulator operator, the first first complex accumulator operator is configured in multiplication mode, and the first digital waveform generator is configured as a complex sine wave; the second to the last first complex accumulator operators are all configured in multiplication-addition mode.

3. The system according to claim 2, characterized in that Each of the first complex accumulator operators is configured with 7 ports, where: A first port of the first complex accumulator operator is connected to a GNSS signal; A second port of the first complex accumulator operator is connected to the output of the first digital waveform generator; The first ports of the second to the last first complex accumulator operators are respectively connected to the output of the first first complex accumulator operator; In the second to last second complex accumulator operator, the output of the previous first complex accumulator operator is cascaded to the third port of the next first complex accumulator operator; Configure the second port of the second to last first complex accumulator operator as a filter coefficient.

4. The system according to claim 1, characterized in that In the correlator channel, the second digital waveform generator is connected to the first of the second complex accumulator operators, the first of the second complex accumulator operators is configured in multiplication mode, the second digital waveform generator is configured as a complex sine wave, and the second to last second complex accumulator operators are configured in multiplication-accumulation mode.

5. The system according to claim 4, characterized in that Each of the second complex accumulator operators is configured with 7 ports, where: A first port of the first second complex accumulator operator is connected to the GNSS signal; A second port of the first of the second complex accumulator operators is connected to the output of the second digital waveform generator; The second ports of the second to the last second complex accumulator operators are respectively connected to the output of the first second complex accumulator operator, and the first ports are connected to a preset constant value; Connecting the output of the pseudo-random code generator to the third port of the second second complex accumulator operator, and linking the pulse generated by the pseudo-random code generator to the latch of the second to last second complex accumulator operator; In the second to last second complex accumulator operator, the output of the register of the previous second complex accumulator operator is cascaded to the fourth port of the next second complex accumulator operator; At the end of the pseudo-random code generator cycle, the output value of the second to last second complex accumulator operator is latched to obtain the correlation value of different phases with the same number of second complex accumulators with an integration time of one code period, and the second to last second complex accumulator operator is cleared at the same time.

6. The system according to claim 1, characterized in that In the DFT unit, the third digital waveform generator is configured as a complex sine wave, multiple third complex accumulator operators are configured as a multiplication-accumulation mode, and the third digital waveform generator is connected to the last third complex accumulator operator.

7. The system according to any one of claims 1 to 6, characterized in that: There are multiple correlator channels, and the multiple correlator channels form a correlator channel group.

Images