A differential reference voltage buffer used in ADC and its working method

Abstract

The present invention discloses a differential reference voltage buffer for use in an ADC and a working method thereof. In the differential reference voltage buffer, the stability of the bandgap reference Bandgap and the negative feedback loop formed by the error amplifier AMP1, the error amplifier AMP2, and the error amplifier AMP3 work together to ensure the stability of the output voltage under different PVT conditions, thereby reducing the output voltage error offset caused by PVT changes. Through precise resistor voltage division and the clamping effect of the error amplifier, high-precision positive and negative reference input voltages can be provided, thereby achieving high-precision analog-to-digital conversion. When the CDAC switch is switched, the present invention can shield the ringing phenomenon introduced by the bonding inductance, thereby ensuring the stable output of the reference voltage. The differential design and optimized circuit layout reduce the reference voltage crosstalk between sub-ADCs of different channels, thereby improving the reliability of the system and the performance of the ADC.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a differential reference voltage buffer used in an ADC and a working method thereof. Background Art

[0002] Analog signal processing and conversion are essential in modern electronic systems. With the advancement of technology, analog-to-digital converters (ADCs) have become the bridge between the analog and digital worlds, quantizing natural analog signals into digital signals for computer processing and transmission. As a core component in ADC systems, the reference voltage buffer's performance directly impacts the accuracy and speed of analog-to-digital conversion.

[0003] The primary function of a reference voltage buffer is to provide a stable reference voltage for the ADC, ensuring accurate conversion. Traditional reference voltage buffers typically employ an operational amplifier plus a source follower structure, using a negative feedback loop to limit the output node voltage to the input reference voltage. While this structure provides a stable output, its performance in high-speed, high-precision signal processing systems is limited by the operational amplifier's response speed and the source follower's drive capability.

[0004] To improve output voltage stability and keep it close to the supply voltage, some designs add a level shifter, such as a charge pump, between the op amp and the source follower. A charge pump achieves level shifting by continuously charging and discharging a capacitor. However, this design introduces high-frequency ripple in the source follower, degrading the reference voltage buffer's performance.

[0005] With the advancement of information technology, the demand for high-speed, high-precision ADCs is growing. The application of these converters in communications systems, mobile terminals, and other fields places higher demands on reference voltage buffers. Traditional reference voltage buffers, due to their high power consumption, slow response speed, and limited accuracy, have gradually become a bottleneck restricting further improvement in analog-to-digital converter system performance.

[0006] In summary, traditional voltage reference buffers are no longer able to meet the performance requirements of high-speed, high-precision ADCs. They suffer from shortcomings in response speed, stability, power consumption, and noise suppression, particularly when processing high-speed, high-current transients. Therefore, research and development of new voltage reference buffers to improve performance, reduce power consumption, and enhance interference immunity has become a key issue in electronic design. These new buffers must maintain high accuracy while offering faster response times and improved noise suppression to meet the demands of high-performance ADCs in modern electronic systems. Summary of the Invention

[0007] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a differential reference voltage buffer for use in an ADC.

[0008] To achieve the above objectives, the technical solutions provided by the present invention are:

[0009] A differential reference voltage buffer used in an ADC includes a differential reference voltage generating module, a differential reference voltage buffer module, and a differential reference voltage driving module;

[0010] The differential reference voltage buffer module is connected between the differential reference voltage generating module and the differential reference voltage driving module;

[0011] The differential reference voltage generation module includes a bandgap reference Bandgap, an error amplifier AMP1, an NMOS source follower MN8, and polysilicon resistors R1 and R2;

[0012] Among them, the positive input terminal of the error amplifier AMP1 is connected to the output terminal of the bandgap reference Bandgap, and the input reference voltage Vref_in is generated by the bandgap reference Bandgap; the negative input terminal of the error amplifier AMP1 is connected to the source of the NMOS source follower MN8, one end of the polysilicon resistor R1 and the differential reference voltage buffer module to form a positive reference input voltage Vrefp_in; the output terminal of the error amplifier AMP1 is connected to the gate of the NMOS source follower MN8 to generate a bias voltage Vb6; the drain of the NMOS source follower MN8 is connected to the power supply VDD; the other end of the polysilicon resistor R1 and one end of the polysilicon resistor R2 are connected to the differential reference voltage buffer module to generate a negative reference input voltage Vrefn_in, and the other end of the polysilicon resistor R2 is grounded.

[0013] Furthermore, the differential reference voltage buffer module includes an error amplifier AMP2, an error amplifier AMP3, an NMOS source follower MN1, an NMOS source follower MN2, an NMOS current mirror MN3, and an NMOS current mirror MN7;

[0014] in,

[0015] The positive input terminal of the error amplifier AMP2 is connected to the negative input terminal of the error amplifier AMP1, the source of MN8, and one end of R1; the negative input terminal of the error amplifier AMP2 is connected to the source of the NMOS source follower MN1 and the drain of the NMOS source follower MN2, and outputs a positive reference buffer voltage Vrefp_buf; the output terminal of the error amplifier AMP2 is connected to the gate of the NMOS source follower MN1 and the differential reference voltage driver module to generate a bias voltage Vb1;

[0016] The positive input terminal of the error amplifier AMP3 is connected to the polysilicon resistor R1 and the polysilicon resistor R2, and the negative input terminal of the error amplifier AMP3 is connected to the source of the NMOS source follower MN2 and the drain of the NMOS source follower MN3 to form a negative reference buffer voltage Vrefn_buf; the output terminal of the error amplifier AMP3 is connected to the gate of the NMOS source follower MN2 and the differential reference voltage driver module to generate a bias voltage Vb2;

[0017] The gate of the NMOS current mirror MN3 and the gate and drain of the NMOS current mirror MN7 are connected to the differential reference voltage driving module to form a stable current source to generate a bias voltage Vb3;

[0018] The drain of the NMOS source follower MN1 is connected to VDD, and the source of the NMOS current mirror MN3 and the source of the NMOS current mirror MN7 are both grounded.

[0019] Furthermore, the differential reference voltage driving module includes a polysilicon resistor R3, a polysilicon resistor R4, a filter capacitor C1, an NMOS source follower MN4, an NMOS source follower MN5 and an NMOS current mirror MN6;

[0020] One end of the polysilicon resistor R3 is connected to the output end of AMP2, and the other end of the polysilicon resistor R3 is connected to the upper plate of the filter capacitor C1 and the gate of the NMOS source follower MN4 to generate a bias voltage Vb4;

[0021] One end of the polysilicon resistor R4 is connected to the output end of the error amplifier AMP3, and the other end of the polysilicon resistor R4 is connected to the lower plate of the filter capacitor C1 and the gate of the NMOS source follower MN5 to generate a bias voltage Vb5;

[0022] The source of the NMOS source follower MN4 is connected to the drain of the NMOS source follower MN5, and outputs a positive reference output voltage Vrefp_out;

[0023] The source of the NMOS source follower MN5 is connected to the drain of the NMOS current mirror MN6, and outputs a negative reference output voltage Vrefn_out;

[0024] The drain of the NMOS source follower MN4 is connected to VDD, and the source of the NMOS current mirror MN6 is grounded.

[0025] Furthermore, the present invention also provides a working method of the differential reference voltage buffer applied to the ADC, comprising:

[0026] First, the differential reference voltage generation module converts the stable voltage Vref_in generated by the bandgap reference Bandgap into a positive reference input voltage Vrefp_in and a negative reference input voltage Vrefn_in. These two voltages serve as the input references for the differential reference voltage buffer module. During this process, the error amplifier AMP1 and the NMOS source follower MN8 form a negative feedback loop to ensure that the voltage of Vrefp_in is equal to Vref_in. The proportional relationship between polysilicon resistors R1 and R2 allows Vrefp_in and Vrefn_in to be accurately determined. At the same time, by increasing the gain of the error amplifier AMP1, the gain error of the output voltage Vrefp_in is reduced.

[0027] Subsequently, the positive reference input voltage Vrefp_in and the negative reference input voltage Vrefn_in are input to the differential reference voltage buffer module. Through two independent negative feedback loops, the module outputs stable bias gate voltages Vb1 and Vb2 via error amplifiers AMP2 and AMP3. Vrefp_buf and Vrefn_buf generated at the sources of MN1 and MN2 are equal to Vrefp_in and Vrefn_in, respectively. By increasing the gains of error amplifiers AMP2 and AMP3, the gain error of the output voltages Vrefp_buf and Vrefn_buf is reduced. NMOS current mirrors MN7, MN3, and MN6 work together to generate the required branch current by adjusting the size ratio between the input current Idc and the NMOS current mirrors MN7, MN3, and MN6, thereby improving the response speed and response bandwidth.

[0028] Finally, Vrefp_buf and Vrefn_buf are input into the differential reference voltage driver module, which reduces high-frequency noise and ripple through an equivalent low-pass filter network consisting of polysilicon resistor R3, filter capacitor C1, and polysilicon resistor R4. NMOS source follower MN4 and NMOS source follower MN5 then output a positive reference output voltage Vrefp_out and a negative reference output voltage Vrefn_out for use by the ADC.

[0029] Compared with the existing technology, the principles and advantages of this technical solution are as follows:

[0030] 1. In the differential reference voltage generation module, the stable reference voltage Vref_in generated by the bandgap reference Bandgap is used as the input. The negative feedback loop formed by the error amplifier AMP1 and the NMOS source follower MN8 can accurately control the positive reference input voltage Vrefp_in and the negative reference input voltage Vrefn_in. The polysilicon resistors R1 and R2 ensure their accuracy through the voltage divider ratio relationship. At the same time, the high gain of the error amplifier AMP1 helps to reduce the gain error of the output voltage.

[0031] 2. In the differential reference voltage buffer module, error amplifiers AMP2 and AMP3 output stable bias gate voltages Vb1 and Vb2 through two independent negative feedback loops. Vrefp_buf and Vrefn_buf generated at the sources of NMOS source followers MN1 and MN2 are equal to Vrefp_in and Vrefn_in, respectively. Increasing the gain of error amplifiers AMP2 and AMP3 further reduces the gain error of output voltages Vrefp_buf and Vrefn_buf. NMOS current mirrors MN7, MN3, and MN6 work together to generate the required branch currents by adjusting the size ratio between input current Idc and NMOS current mirrors MN7, MN3, and MN6, thereby improving response speed and response bandwidth.

[0032] 3. In the differential reference voltage driver module, NMOS source followers MN4 and MN5 provide fast voltage tracking, enabling the reference voltage to quickly establish, meeting the ADC's response speed requirements for the reference voltage buffer. The low-pass filter network significantly reduces high-frequency noise and ripple, improving the reference voltage signal quality.

[0033] 4. In the differential reference voltage driver module, an equivalent low-pass filter network consisting of polysilicon resistor R3, filter capacitor C1, and polysilicon resistor R4 reduces high-frequency noise and ripple. The open-loop structure formed by NMOS source followers MN4 and MN5 and load capacitor CDAC significantly improves the settling speed of Vrefp_out and Vrefn_out compared to traditional closed-loop structures. Using NMOS current mirror MN6 as a load exhibits better PVT characteristics and faster response than a resistive load.

[0034] 5. The stability of the bandgap reference Bandgap and the negative feedback loop composed of error amplifiers AMP1, AMP2, and AMP3 work together to ensure the stability of the output voltage under different PVT conditions and reduce the output voltage error offset caused by PVT changes.

[0035] 6. Through precise resistor voltage division and the clamping effect of the error amplifier, it can provide high-precision positive and negative reference input voltages, thereby achieving high-precision analog-to-digital conversion.

[0036] 7. When the CDAC switch is switched, this technical solution can shield the ringing phenomenon introduced by the bonding inductance, ensuring the stable output of the reference voltage.

[0037] 8. Differential design and optimized circuit layout reduce reference voltage crosstalk between sub-ADCs of different channels, improving system reliability and ADC performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the services required for use in the embodiments or the prior art descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A module circuit diagram of a differential reference voltage buffer used in an ADC according to the present invention;

[0040] Figure 2 FIG. 1 is a circuit diagram of an open-loop structure composed of an NMOS source follower MN4, an NMOS source follower MN5 and a load capacitor CDAC;

[0041] Figure 3 Schematic diagram of the recovery of the output voltages VREFP22 and VREFN22 of the differential reference voltage buffer when the upper plate voltages VDACP1 and VDACN1 of the differential CDAC are compared and switched in actual ADC operation. DETAILED DESCRIPTION

[0042] The present invention will be further described below in conjunction with specific embodiments:

[0043] like Figure 1 As shown, the differential reference voltage buffer used in the ADC described in this embodiment includes a differential reference voltage generating module 401, a differential reference voltage buffer module 402 and a differential reference voltage driving module 403;

[0044] The differential reference voltage buffer module 402 is connected between the differential reference voltage generating module 401 and the differential reference voltage driving module 403; the differential reference voltage generating module 401 includes a bandgap reference Bandgap, an error amplifier AMP1, an NMOS source follower MN8, and polysilicon resistors R1 and R2;

[0045] Among them, the positive input terminal of the error amplifier AMP1 is connected to the output terminal of the bandgap reference Bandgap, and the input reference voltage Vref_in is generated by the bandgap reference Bandgap; the negative input terminal of the error amplifier AMP1 is connected to the source of the NMOS source follower MN8, one end of the polysilicon resistor R1 and the differential reference voltage buffer module 402 to form a positive reference input voltage Vrefp_in; the output terminal of the error amplifier AMP1 is connected to the gate of the NMOS source follower MN8 to generate a bias voltage Vb6; the drain of the NMOS source follower MN8 is connected to the power supply VDD; the other end of the polysilicon resistor R1 and one end of the polysilicon resistor R2 are connected to the differential reference voltage buffer module 402 to generate a negative reference input voltage Vrefn_in, and the other end of the polysilicon resistor R2 is grounded.

[0046] The differential reference voltage buffer module 402 includes an error amplifier AMP2, an error amplifier AMP3, an NMOS source follower MN1, an NMOS source follower MN2, an NMOS current mirror MN3, and an NMOS current mirror MN7;

[0047] The positive input of the error amplifier AMP2 is connected to the negative input of the error amplifier AMP1, the source of MN8, and one end of R1; the negative input of the error amplifier AMP2 is connected to the source of the NMOS source follower MN1 and the drain of the NMOS source follower MN2, and outputs a positive reference buffer voltage Vrefp_buf; the output of the error amplifier AMP2 is connected to the gate of the NMOS source follower MN1 and the differential reference voltage driver module 403 to generate a bias voltage Vb1;

[0048] The positive input terminal of the error amplifier AMP3 is connected to the polysilicon resistor R1 and the polysilicon resistor R2, and the negative input terminal of the error amplifier AMP3 is connected to the source of the NMOS source follower MN2 and the drain of the NMOS source follower MN3 to form a negative reference buffer voltage Vrefn_buf; the output terminal of the error amplifier AMP3 is connected to the gate of the NMOS source follower MN2 and the differential reference voltage driver module 403 to generate a bias voltage Vb2;

[0049] The gate of the NMOS current mirror MN3 and the gate and drain of MN7 are connected to the differential reference voltage driving module 403 to form a stable current source to generate a bias voltage Vb3;

[0050] The drain of the NMOS source follower MN1 is connected to VDD, and the source of the NMOS current mirror MN3 and the source of the NMOS current mirror MN7 are both grounded.

[0051] The differential reference voltage driving module 403 includes a polysilicon resistor R3, a polysilicon resistor R4, a filter capacitor C1, an NMOS source follower MN4, an NMOS source follower MN5 and an NMOS current mirror MN6;

[0052] One end of the polysilicon resistor R3 is connected to the output end of AMP2, and the other end of the polysilicon resistor R3 is connected to the upper plate of the filter capacitor C1 and the gate of the NMOS source follower MN4 to generate a bias voltage Vb4;

[0053] One end of the polysilicon resistor R4 is connected to the output end of the error amplifier AMP3, and the other end of the polysilicon resistor R4 is connected to the lower plate of the filter capacitor C1 and the gate of the NMOS source follower MN5 to generate a bias voltage Vb5;

[0054] The source of the NMOS source follower MN4 is connected to the drain of the NMOS source follower MN5, and outputs a positive reference output voltage Vrefp_out;

[0055] The source of the NMOS source follower MN5 is connected to the drain of the NMOS current mirror MN6, and outputs a negative reference output voltage Vrefn_out;

[0056] The drain of the NMOS source follower MN4 is connected to VDD, and the source of the NMOS current mirror MN6 is grounded.

[0057] In this embodiment, the working principle of the differential reference voltage buffer used in the ADC is as follows:

[0058] First, the differential reference voltage generation module 401 converts the stable voltage Vref_in generated by the bandgap reference Bandgap into a positive reference input voltage Vrefp_in and a negative reference input voltage Vrefn_in. These two voltages serve as input references for the differential reference voltage buffer module 402. During this process, the error amplifier AMP1 and the NMOS source follower MN8 form a negative feedback loop to ensure that the voltage of Vrefp_in is equal to Vref_in. The proportional relationship between the polysilicon resistors R1 and R2 allows Vrefp_in and Vrefn_in to be accurately determined. At the same time, the gain error of the output voltage Vrefp_in is reduced by increasing the gain of the error amplifier AMP1.

[0059] Subsequently, the positive reference input voltage Vrefp_in and the negative reference input voltage Vrefn_in are input to the differential reference voltage buffer module 402. Through two independent negative feedback loops, the module outputs stable bias gate voltages Vb1 and Vb2 via error amplifiers AMP2 and AMP3. Vrefp_buf and Vrefn_buf generated at the sources of MN1 and MN2 are equal to Vrefp_in and Vrefn_in, respectively. By increasing the gains of error amplifiers AMP2 and AMP3, the gain error of the output voltages Vrefp_buf and Vrefn_buf is reduced. NMOS current mirrors MN7, MN3, and MN6 work together to generate the required branch current by adjusting the size ratio between the input current Idc and the NMOS current mirrors MN7, MN3, and MN6, thereby improving the response speed and response bandwidth.

[0060] Finally, Vrefp_buf and Vrefn_buf are input into the differential reference voltage driver module 403, which reduces high-frequency noise and ripple through an equivalent low-pass filter network consisting of a polysilicon resistor R3, a filter capacitor C1, and a polysilicon resistor R4; the NMOS source follower MN4 and the NMOS source follower MN5 then output a positive reference output voltage Vrefp_out and a negative reference output voltage Vrefn_out for use by the ADC.

[0061] In this embodiment,

[0062] In the differential reference voltage generation module 401, a stable reference voltage Vref_in generated by a bandgap reference Bandgap is used as an input. The positive reference input voltage Vrefp_in and the negative reference input voltage Vrefn_in can be precisely controlled through a negative feedback loop formed by the error amplifier AMP1 and the NMOS source follower MN8. The polysilicon resistors R1 and R2 ensure their accuracy through a voltage divider ratio relationship. At the same time, the high gain of the error amplifier AMP1 helps to reduce the gain error of the output voltage.

[0063] In the differential reference voltage buffer module 402, error amplifiers AMP2 and AMP3 output stable bias gate voltages Vb1 and Vb2 through two independent negative feedback loops. Vrefp_buf and Vrefn_buf generated at the sources of NMOS source followers MN1 and MN2 are equal to Vrefp_in and Vrefn_in, respectively. By increasing the gain of error amplifiers AMP2 and AMP3, the gain error of the output voltages Vrefp_buf and Vrefn_buf can be further reduced. NMOS current mirrors MN7, MN3, and MN6 work together to generate the desired branch current by adjusting the size ratio between the input current Idc and the NMOS current mirrors MN7, MN3, and MN6, thereby improving the response speed and response bandwidth.

[0064] In the differential reference voltage driving module 403,

[0065] NMOS source followers MN4 and MN5 provide fast voltage following capability, enabling the reference voltage to settle quickly, meeting the ADC's response speed requirements for the reference voltage buffer. The low-pass filter network significantly reduces high-frequency noise and ripple, improving the reference voltage's signal quality.

[0066] The equivalent low-pass filter network composed of polysilicon resistor R3, filter capacitor C1, and polysilicon resistor R4 is used to reduce high-frequency noise and ripple. Figure 2 As shown in Figure 1, the open-loop structure formed by NMOS source followers MN4 and MN5 and load capacitor CDAC significantly improves the settling speed of Vrefp_out and Vrefn_out compared to the traditional closed-loop structure. Using NMOS current mirror MN6 as the load exhibits better PVT characteristics and faster response speed than a resistive load.

[0067] The stability of the bandgap reference Bandgap and the negative feedback loop formed by the error amplifiers AMP1, AMP2, and AMP3 work together to ensure the stability of the output voltage under different PVT conditions and reduce the output voltage error offset caused by PVT changes.

[0068] Through precise resistor voltage division and the clamping effect of the error amplifier, high-precision positive and negative reference input voltages can be provided, thereby achieving high-precision analog-to-digital conversion.

[0069] When the CDAC switch is switched, this technical solution can shield the ringing phenomenon introduced by the bonding inductance, thereby ensuring the stable output of the reference voltage.

[0070] Differential design and optimized circuit layout reduce reference voltage crosstalk between sub-ADCs of different channels, improving system reliability and ADC performance.

[0071] The differential reference voltage buffer described in this embodiment is applied to an ADC, such as Figure 3 As shown, the CDAC is always established before the CDAC switch is switched, and the error is kept within 1 / 2 LSB. Furthermore, the present invention can shield the ringing phenomenon introduced by the bonding inductance during each CDAC switch switching, as well as the crosstalk of the reference voltage between the sub-ADCs of different channels, thereby ensuring the stability of the reference voltage and the performance of the ADC.

[0072] The embodiments described above are only preferred embodiments of the present invention and are not intended to limit the scope of implementation of the present invention. Therefore, any changes made based on the shape and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A differential reference voltage buffer used in an ADC, characterized in that: It includes a differential reference voltage generating module, a differential reference voltage buffer module and a differential reference voltage driving module; The differential reference voltage buffer module is connected between the differential reference voltage generating module and the differential reference voltage driving module; The differential reference voltage generation module includes a bandgap reference Bandgap, an error amplifier AMP1, an NMOS source follower MN8, and polysilicon resistors R1 and R2; The positive input of the error amplifier AMP1 is connected to the output of the bandgap reference Bandgap, which generates an input reference voltage Vref_in. The negative input of the error amplifier AMP1 is connected to the source of the NMOS source follower MN8, one end of the polysilicon resistor R1, and a differential reference voltage buffer module to form a positive reference input voltage Vrefp_in. The output of the error amplifier AMP1 is connected to the gate of the NMOS source follower MN8 to generate a bias voltage Vb6. The drain of the NMOS source follower MN8 is connected to the power supply VDD. The other end of the polysilicon resistor R1 and one end of the polysilicon resistor R2 are connected to the differential reference voltage buffer module to generate a negative reference input voltage Vrefn_in. The other end of the polysilicon resistor R2 is grounded. The differential reference voltage buffer module includes an error amplifier AMP2, an error amplifier AMP3, an NMOS source follower MN1, an NMOS source follower MN2, an NMOS current mirror MN3 and an NMOS current mirror MN7; The differential reference voltage driving module includes a polysilicon resistor R3, a polysilicon resistor R4, a filter capacitor C1, an NMOS source follower MN4, an NMOS source follower MN5 and an NMOS current mirror MN6; One end of the polysilicon resistor R3 is connected to the output end of AMP2, and the other end of the polysilicon resistor R3 is connected to the upper plate of the filter capacitor C1 and the gate of the NMOS source follower MN4 to generate a bias voltage Vb4; One end of the polysilicon resistor R4 is connected to the output end of the error amplifier AMP3, and the other end of the polysilicon resistor R4 is connected to the lower plate of the filter capacitor C1 and the gate of the NMOS source follower MN5 to generate a bias voltage Vb5; The source of the NMOS source follower MN4 is connected to the drain of the NMOS source follower MN5, and outputs a positive reference output voltage Vrefp_out; The source of the NMOS source follower MN5 is connected to the drain of the NMOS current mirror MN6, and outputs a negative reference output voltage Vrefn_out; The drain of the NMOS source follower MN4 is connected to VDD, and the source of the NMOS current mirror MN6 is grounded.

2. A differential reference voltage buffer for use in an ADC according to claim 1, characterized in that: The positive input terminal of the error amplifier AMP2 is connected to the negative input terminal of the error amplifier AMP1, the source of MN8, and one end of R1; the negative input terminal of the error amplifier AMP2 is connected to the source of the NMOS source follower MN1 and the drain of the NMOS source follower MN2, and outputs a positive reference buffer voltage Vrefp_buf; the output terminal of the error amplifier AMP2 is connected to the gate of the NMOS source follower MN1 and the differential reference voltage driver module to generate a bias voltage Vb1; the positive input terminal of the error amplifier AMP3 is connected to the polysilicon resistor R1 and the polysilicon resistor R2, and the negative input terminal of the error amplifier AMP3 is connected to the source of the NMOS source follower MN2 and the drain of the NMOS source follower MN3 to form a negative reference buffer voltage Vrefn_buf; the output terminal of the error amplifier AMP3 is connected to the gate of the NMOS source follower MN2 and the differential reference voltage driver module to generate a bias voltage Vb2; The gate of the NMOS current mirror MN3 and the gate and drain of MN7 are connected to the differential reference voltage driver module to form a stable current source to generate a bias voltage Vb3; The drain of the NMOS source follower MN1 is connected to VDD, and the source of the NMOS current mirror MN3 and the source of the NMOS current mirror MN7 are both grounded.

3. A method for operating a differential reference voltage buffer used in an ADC according to claim 2, characterized in that: include: First, the differential reference voltage generation module converts the stable voltage Vref_in generated by the bandgap reference Bandgap into a positive reference input voltage Vrefp_in and a negative reference input voltage Vrefn_in. These two voltages serve as the input references of the differential reference voltage buffer module. During this process, the error amplifier AMP1 and the NMOS source follower MN8 form a negative feedback loop to ensure that the voltage of Vrefp_in is equal to Vref_in. The proportional relationship between the polysilicon resistors R1 and R2 accurately obtains Vrefp_in and Vrefn_in. At the same time, by increasing the gain of the error amplifier AMP1, the gain error of the output voltage Vrefp_in is reduced. Subsequently, the positive reference input voltage Vrefp_in and the negative reference input voltage Vrefn_in are input to the differential reference voltage buffer module. Through two independent negative feedback loops, the error amplifiers AMP2 and AMP3 output stable bias gate voltages Vb1 and Vb2. The Vref generated at the source of MN1 and MN2 Vrefp_buf and Vrefn_buf are equal to Vrefp_in and Vrefn_in, respectively. By increasing the gains of error amplifiers AMP2 and AMP3, the gain errors of output voltages Vrefp_buf and Vrefn_buf are reduced. NMOS current mirrors MN7, MN3, and MN6 work together to generate the required branch current by adjusting the size ratio between the input current Idc and the NMOS current mirrors MN7, MN3, and MN6, thereby improving the response speed and response bandwidth. Finally, Vrefp_buf and Vrefn_buf are input to the differential reference voltage driver module, which reduces high-frequency noise and ripple through an equivalent low-pass filter network composed of polysilicon resistor R3, filter capacitor C1, and polysilicon resistor R4. NMOS source follower MN4 and NMOS source follower MN5 then output a positive reference output voltage Vrefp_out and a negative reference output voltage Vrefn_out for use by the ADC.

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