A filter shaping circuit, low voltage dropout regulator and power management unit applied to enable port

Abstract

The present invention provides a filtering and shaping circuit, a low-voltage dropout regulator, and a power management unit for an enable port, relating to the technical field of integrated circuit design. The circuit comprises: an output end of a first inverter connected to an input end of a NOR gate, a gate of a second NMOS transistor, and an input end of a NAND gate via the second inverter; a gate of the first NMOS transistor connected to the output end of the NOR gate, and a drain connected to a power supply voltage via a gate voltage regulation circuit; a drain of the second NMOS transistor connected to the drain of a first PMOS transistor, and a source and gate of the first PMOS transistor respectively connected to the power supply voltage and the gate voltage regulation circuit; two ends of a charge-discharge device respectively connected to the power supply voltage and the drain of the first PMOS transistor; a gate of the second PMOS transistor connected to the drain of the first PMOS transistor, and a drain connected to the drains of a third NMOS transistor and a fourth NMOS transistor respectively, and connected to the gate of the third NMOS transistor via a third inverter; and an output end of the third inverter respectively connected to the input end of the NOR gate and the input end of the NAND gate. The beneficial effect is that glitch signals are effectively filtered.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a filtering and shaping circuit, a low voltage dropout regulator, and a power management unit applied to an enable port. Background Art

[0002] In highly integrated modern electronic systems, enable ports serve as key interfaces connecting control signals to functional circuits. Their stability and reliability are crucial to the proper operation of the entire system. Enable signals are transmitted through these ports to activate or disable specific circuit modules, such as power management units, data converters, and communication interfaces.

[0003] However, with increasing system complexity and volatile operating environments, the enable signal on the enable port faces increasing interference and challenges. This interference can originate from other circuit modules within the system or from the external environment. Internal interference can include power supply noise, digital circuit noise, and analog circuit interference. These interferences can couple to the enable port through power lines, ground lines, or signal lines, causing instability in the enable signal. External interference can include electromagnetic interference (EMI), electrostatic discharge (ESD), and external power supply instability. These interferences can enter the electronic system through antenna effects, direct conduction, or coupling, further affecting the accuracy of the enable signal.

[0004] The impact of enable port fluctuations on downstream circuits cannot be ignored. On the one hand, fluctuating enable signals can cause circuit modules to mistrigger or experience unstable operation, impacting the performance and stability of the entire system. On the other hand, long-term fluctuations can accelerate the aging of circuit components and shorten the life of the device. Therefore, reducing enable port fluctuations and improving the stability and reliability of the enable signal have become urgent challenges. Summary of the Invention

[0005] In view of the problems existing in the prior art, the present invention provides a filtering and shaping circuit applied to an enabling port, comprising:

[0006] A first inverter, wherein an input terminal of the first inverter is connected to an external enable signal, an output terminal of the first inverter is connected to an input terminal of a NOR gate, and is connected to an input terminal of a NAND gate through a second inverter;

[0007] a first NMOS transistor, wherein the gate of the first NMOS transistor is connected to the output end of the NOR gate, the drain is connected to the power supply voltage through the gate voltage regulation circuit, and the source is grounded;

[0008] a second NMOS transistor, wherein the gate of the second NMOS transistor is connected to the output end of the first inverter, the source is grounded, the drain is connected to the drain of the first PMOS transistor, and the source and gate of the first PMOS transistor are respectively connected to the power supply voltage and the gate voltage regulation circuit;

[0009] a charge-discharge device, one end of which is connected to the power supply voltage, and the other end of which is connected to the drain of the first PMOS tube;

[0010] a second PMOS transistor, wherein the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor, the source is connected to the power supply voltage, the drain is respectively connected to the drains of the third NMOS transistor and the fourth NMOS transistor, the sources of the third NMOS transistor and the fourth NMOS transistor are grounded, the gate of the fourth NMOS transistor is connected to the gate voltage regulation circuit, and the drain of the second PMOS transistor is further connected to the gate of the third NMOS transistor via a third inverter;

[0011] The output end of the third inverter is connected to the input end of the NOR gate and the input end of the NAND gate respectively, and the output end of the NAND gate is connected to the enable port.

[0012] Preferably, the gate voltage regulation circuit includes:

[0013] a third PMOS transistor, wherein a source of the third PMOS transistor is connected to the power supply voltage, a drain of the third PMOS transistor is connected to the drain of the first NMOS transistor via a first resistor, and the drain of the third PMOS transistor is also connected to the gate of the first PMOS transistor;

[0014] a fourth PMOS transistor, wherein a source of the fourth PMOS transistor is connected to the power supply voltage, and a gate thereof is respectively connected to the gate and drain of the third PMOS transistor, and is connected to the gate of the first PMOS transistor;

[0015] a fifth NMOS transistor, wherein the source of the fifth NMOS transistor is grounded, the gate and the drain are short-circuited, and the drain of the fifth NMOS transistor is also connected to the drain of the fourth PMOS transistor.

[0016] Preferably, it further comprises a fifth PMOS transistor, wherein the source of the fifth PMOS transistor is connected to the power supply voltage, and the drain is connected to the drain of the second NMOS transistor;

[0017] The output end of the third inverter is connected to the gate of the fifth PMOS transistor through a fourth inverter.

[0018] Preferably, the charging and discharging device is a capacitor.

[0019] Preferably, the charging and discharging device is a sixth PMOS tube, the source and drain of the sixth PMOS tube are short-circuited and connected to the power supply voltage, and the gate of the sixth PMOS tube is connected to the drain of the second NMOS tube.

[0020] Preferably, the enable port is valid when at a high level, and invalid when at a low level or when left floating.

[0021] The present invention also provides a low voltage dropout regulator, wherein an enable port of the low voltage dropout regulator is connected to the above-mentioned filtering and shaping circuit.

[0022] The present invention also provides a power management unit, comprising the above-mentioned low voltage dropout regulator.

[0023] The above technical solution has the following advantages or beneficial effects: when the external enable signal changes from a low level to a high level, a certain signal delay can be generated by charging the charge-discharge device, thereby achieving a delayed flip of the signal output to the enable port, thereby effectively filtering the glitch signal and reducing functional errors. At the same time, it has the advantages of simple structure, small chip area and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A circuit diagram of a filter and shaping circuit applied to an enable port in a preferred embodiment of the present invention;

[0025] Figure 2 A circuit diagram of a filter and shaping circuit applied to an enable port in a preferred embodiment of the present invention;

[0026] Figure 3 FIG1 is a schematic diagram for verifying the filtering and shaping results of the filtering and shaping circuit in a preferred embodiment of the present invention;

[0027] Figure 4 FIG. 1 is a circuit diagram of a low voltage dropout regulator in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0029] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a filtering and shaping circuit applied to an enabling port is provided, such as Figure 1 and Figure 2 Shown, including:

[0030] A first inverter INV1, wherein the input end of the first inverter INV1 is connected to the external enable signal EN_L, the output end of the first inverter INV1 is connected to the input end of the NOR gate NOR, and is connected to the input end of the NAND gate NAND through the second inverter INV2;

[0031] A first NMOS transistor NM1, wherein the gate of the first NMOS transistor NM1 is connected to the output end of the NOR gate NOR, the drain is connected to the power supply voltage VDD through the gate voltage regulation circuit 100, and the source is grounded;

[0032] a second NMOS transistor NM2 , wherein the gate of the second NMOS transistor NM2 is connected to the output terminal of the first inverter INV1 , the source is grounded, and the drain is connected to the drain of the first PMOS transistor PM1 . The source and gate of the first PMOS transistor PM1 are connected to the power supply voltage VDD and the gate voltage regulation circuit 100 , respectively;

[0033] A charge-discharge device 200 , one end of which is connected to the power supply voltage VDD, and the other end of which is connected to the drain of the first PMOS transistor PM1 ;

[0034] a second PMOS transistor PM2, wherein the gate of the second PMOS transistor PM2 is connected to the drain of the first PMOS transistor PM1, the source is connected to the power supply voltage VDD, the drain is connected to the drains of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 respectively, the sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are grounded, the gate of the fourth NMOS transistor NM4 is connected to the gate voltage regulation circuit 100, and the drain of the second PMOS transistor PM2 is further connected to the gate of the third NMOS transistor NM3 via the third inverter INV3;

[0035] The output end of the third inverter INV3 is connected to the input end of the NOR gate NOR and the input end of the NAND gate NAND respectively, and the output end of the NAND gate NAND is connected to the enable port.

[0036] Specifically, in this embodiment, when the circuit is operating normally, the external enable signal EN_L is at a low level. After passing through the first inverter INV1, the output signal A is at a high level. Output signal A is connected to the gate of the second NMOS transistor NM2, turning on the second NMOS transistor NM2. Since the source of the second NMOS transistor NM2 is grounded and the drain is connected to the gate of the second PMOS transistor PM2, a low level is connected to the gate of the second PMOS transistor PM2, turning on the second PMOS transistor PM2. Since the source of the second PMOS transistor PM2 is connected to the power supply voltage, the output signal D of the second PMOS transistor PM2 is at a high level. After passing through the third inverter INV3, the output signal C is at a low level. Consequently, both inputs of the NAND gate NAND are at a low level, and the output signal EN_H at the output of the NAND gate is at a high level.

[0037] When the external enable signal EN_L transitions from a low level to a high level, the output signal A transitions from a high level to a low level, while the output signal C remains low. At this point, both inputs of the NOR gate are low, and the output signal B is high, turning on the first NMOS transistor NM1. Because the output signal A is low, it is connected to the gate of the second NMOS transistor NM2, turning off the second NMOS transistor NM2. Because the source of the first NMOS transistor NM1 is grounded, the gate of the first PMOS transistor PM1 is connected to a low level, enabling charging of the charge-discharge device 200. This generates a certain signal delay, delaying the gate voltage of the second PMOS transistor PM2 from reaching a high level, thus delaying its shutdown. This delays the transition of the output signal D, and thus the transition of the output signal C, ultimately resulting in a delayed transition of the output signal EN_H to a low level. This effectively filters glitches and provides a certain degree of anti-disturbance capability. Furthermore, the overall circuit, implemented using logic gates and MOS transistors, has the advantages of a simple structure, a small chip area, and low power consumption.

[0038] like Figure 3 As shown, the upper part of the figure is the external enable signal, which can be seen to contain two glitches. The filtering and shaping circuit based on the present invention can obtain the signal waveform of the lower part of the figure and filter the two glitches.

[0039] In a preferred embodiment of the present invention, the gate voltage regulation circuit 100 includes:

[0040] a third PMOS transistor PM3 , wherein the source of the third PMOS transistor PM3 is connected to the power supply voltage VDD, the drain of the third PMOS transistor PM3 is connected to the drain of the first NMOS transistor NM1 via the first resistor R1 , and the drain of the third PMOS transistor PM3 is also connected to the gate of the first PMOS transistor PM1 ;

[0041] a fourth PMOS transistor PM4 , wherein a source of the fourth PMOS transistor PM4 is connected to the power supply voltage VDD, and a gate thereof is respectively connected to the gate and drain of the third PMOS transistor PM3 , and is connected to the gate of the first PMOS transistor PM1 ;

[0042] The fifth NMOS transistor NM5 has a source connected to the ground, a gate and a drain short-circuited, and a drain connected to the drain of the fourth PMOS transistor PM4.

[0043] Specifically, in this embodiment, the gate voltage regulating circuit 100 is used to provide corresponding gate voltages for the first PMOS transistor PM1 and the fourth NMOS transistor NM4 .

[0044] In a preferred embodiment of the present invention, a fifth PMOS transistor PM5 is further included, wherein the source of the fifth PMOS transistor PM5 is connected to the power supply voltage, and the drain is connected to the drain of the second NMOS transistor NM2;

[0045] The output end of the third inverter INV3 is connected to the gate of the fifth PMOS transistor PM5 through the fourth inverter INV4.

[0046] Specifically, in this embodiment, by providing a fifth PMOS tube, when the output signal C jumps to a high level, a low level acts on the gate of the fifth PMOS tube to turn it on, thereby ensuring that the second PMOS tube is completely turned off, further saving power consumption.

[0047] In a preferred embodiment of the present invention, the charge-discharge device 200 is a capacitor.

[0048] In a preferred embodiment of the present invention, the charge-discharge device 200 is a sixth PMOS transistor, the source and drain of the sixth PMOS transistor are short-circuited and connected to the power supply voltage VDD, and the gate of the sixth PMOS transistor is connected to the drain of the second NMOS transistor NM2.

[0049] In a preferred embodiment of the present invention, the enable port is valid when it is at a high level, and is invalid when it is at a low level or when it is suspended.

[0050] The present invention also provides a low voltage difference regulator, such as Figure 4 As shown, the enable port of the low voltage dropout regulator is connected to the above-mentioned filter shaping circuit. Among them, the enable port EN is connected to the output end of the NAND gate NAND of the filter shaping circuit, V IN is the input voltage of the low dropout regulator, C IN is the input capacitance of the low dropout regulator, V OUT is the output voltage of the low dropout regulator, C OUT is the output capacitor of the low dropout regulator.

[0051] The present invention also provides a power management unit, comprising the above-mentioned low voltage dropout regulator.

[0052] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A filter shaping circuit applied to an enable port, characterized in that: include: A first inverter, wherein an input terminal of the first inverter is connected to an external enable signal, an output terminal of the first inverter is connected to an input terminal of a NOR gate, and is connected to an input terminal of a NAND gate through a second inverter; a first NMOS transistor, wherein the gate of the first NMOS transistor is connected to the output end of the NOR gate, the drain is connected to the power supply voltage through the gate voltage regulation circuit, and the source is grounded; a second NMOS transistor, wherein the gate of the second NMOS transistor is connected to the output end of the first inverter, the source is grounded, the drain is connected to the drain of the first PMOS transistor, and the source and gate of the first PMOS transistor are respectively connected to the power supply voltage and the gate voltage regulation circuit; a charge-discharge device, one end of which is connected to the power supply voltage, and the other end of which is connected to the drain of the first PMOS tube; a second PMOS transistor, wherein the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor, the source is connected to the power supply voltage, the drain is respectively connected to the drains of the third NMOS transistor and the fourth NMOS transistor, the sources of the third NMOS transistor and the fourth NMOS transistor are grounded, the gate of the fourth NMOS transistor is connected to the gate voltage regulation circuit, and the drain of the second PMOS transistor is further connected to the gate of the third NMOS transistor via a third inverter; The output end of the third inverter is connected to the input end of the NOR gate and the input end of the NAND gate respectively, and the output end of the NAND gate is connected to the enable port.

2. The filter shaping circuit according to claim 1, characterized in that: The gate voltage regulation circuit comprises: a third PMOS transistor, wherein a source of the third PMOS transistor is connected to the power supply voltage, a drain of the third PMOS transistor is connected to the drain of the first NMOS transistor via a first resistor, and the drain of the third PMOS transistor is also connected to the gate of the first PMOS transistor; a fourth PMOS transistor, wherein a source of the fourth PMOS transistor is connected to the power supply voltage, and a gate thereof is respectively connected to the gate and drain of the third PMOS transistor, and is connected to the gate of the first PMOS transistor; a fifth NMOS transistor, wherein the source of the fifth NMOS transistor is grounded, the gate and the drain are short-circuited, and the drain of the fifth NMOS transistor is also connected to the drain of the fourth PMOS transistor.

3. The filter shaping circuit according to claim 1, characterized in that: It also includes a fifth PMOS transistor, wherein the source of the fifth PMOS transistor is connected to the power supply voltage, and the drain is connected to the drain of the second NMOS transistor; The output end of the third inverter is connected to the gate of the fifth PMOS transistor through a fourth inverter.

4. The filter shaping circuit according to claim 1, characterized in that: The charging and discharging device is a capacitor.

5. The filter shaping circuit according to claim 1, characterized in that: The charging and discharging device is a sixth PMOS tube, the source and drain of the sixth PMOS tube are short-circuited and connected to the power supply voltage, and the gate of the sixth PMOS tube is connected to the drain of the second NMOS tube.

6. The filter shaping circuit according to claim 1, characterized in that: The enable port is valid when it is at a high level, and invalid when it is at a low level or when it is suspended.

7. A low voltage dropout regulator, characterized in that: The enable port of the low-dropout voltage regulator is connected to the filtering and shaping circuit according to any one of claims 1 to 6.

8. A power management unit, characterized in that: Including the low voltage dropout regulator according to claim 7.

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