Touch display panel and touch display device

Abstract

The invention provides a touch display panel and a touch display device. The touch display panel includes: a substrate; the first electrode layer is located on one side of the substrate and comprises a plurality of first signal lines extending in the first direction and a plurality of electrode parts connected to the first signal lines; the touch layer and the first electrode layer are located on the same side of the substrate, and the touch layer comprises a plurality of touch electrodes which are mutually spaced; the first insulating layer is positioned between the first electrode layer and the touch layer and is provided with a plurality of first via holes; at least part of the electrode parts in the plurality of electrode parts are conducted with the touch electrodes through the first via holes; the pixel electrodes and the first electrode layer are located on the same side of the substrate; wherein the orthographic projection of the electrode part on the substrate is only located at the orthographic projection of the gap of part of adjacent pixel electrodes on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a touch display panel and a touch display device. Background Art

[0002] Liquid Crystal Display (LCD) is the most widely used flat panel display at present, and has gradually become a display with high-resolution color screen used in various electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, desktop computers or laptop computers.

[0003] With the development and progress of liquid crystal display technology, people have put forward higher requirements for LCD display quality, appearance design, human-machine interface, etc. Touch technology has become a hot spot in technology development due to its convenient operation and high integration. Touch technology has developed rapidly in recent years, and many touch panels have been put into mass production. For existing touch panels, according to the different settings of the touch sensor, it can be divided into touch sensors covered on the liquid crystal box (On Cell), touch sensors embedded in the liquid crystal box (In Cell), and touch sensors external to the display panel (Out Cell). Among them, In-Cell touch panel refers to a method of embedding the touch function into the liquid crystal pixel, which not only further reduces the thickness of the whole machine, but also can be made together with LCD, without additional production processes, and does not affect its visibility in bright environments such as outdoors. Therefore, research on In-Cell touch panels is becoming more and more popular. Summary of the invention

[0004] The present disclosure provides a touch display panel and a touch display device. The touch display panel includes:

[0005] substrate;

[0006] A first electrode layer, located at one side of the substrate, comprises: a plurality of first signal lines extending along a first direction, and a plurality of electrode portions connected to the plurality of first signal lines;

[0007] A touch layer, located on the same side of the substrate as the first electrode layer, comprising a plurality of touch electrodes spaced apart from each other;

[0008] A first insulating layer is located between the first electrode layer and the touch control layer, and has a plurality of first via holes; at least some of the plurality of electrode portions are electrically connected to the touch control electrodes through the first via holes;

[0009] a plurality of pixel electrodes, located on the same side of the substrate as the first electrode layer;

[0010] The orthographic projection of the electrode portion on the substrate is only located at the orthographic projection of a portion of the gaps between adjacent pixel electrodes on the substrate.

[0011] In a possible implementation manner, all of the electrode portions are electrically connected to the touch electrode through the first via hole.

[0012] In a possible implementation manner, the minimum distance between at least some of the adjacent two electrode portions in the first direction and their orthographic projections on the substrate is greater than the length of the orthographic projection of the pixel electrode on the substrate along the first direction.

[0013] In a possible implementation, the minimum distance between at least some of the adjacent two electrode portions in the second direction and their projections on the substrate is greater than the length of the pixel electrode's projection on the substrate along the second direction, and the second direction is perpendicular to the first direction.

[0014] In a possible implementation, the touch layer includes: a plurality of touch electrode groups extending along the first direction and arranged along the second direction;

[0015] The plurality of electrode portions include: a plurality of electrode portion groups extending along the first direction and arranged along the second direction, the orthographic projection of the touch electrode group on the substrate at least partially overlapping with the orthographic projection of the electrode portion group on the substrate;

[0016] At least one electrode portion group among the plurality of electrode portion groups comprises: a plurality of sub-electrode portion groups arranged along the first direction, the sub-electrode portion group comprising at least one electrode portion; an orthographic projection of the touch electrode on the substrate overlaps at least part of an orthographic projection of the sub-electrode portion group on the substrate;

[0017] The sub-electrode sections in the same electrode section group are distributed in a staggered manner.

[0018] In a possible implementation manner, each electrode portion in the same sub-electrode portion group is located at a gap between two adjacent columns of pixel electrodes.

[0019] In a possible implementation manner, each of the electrode portions in the same sub-electrode portion group is electrically connected to the same first signal line.

[0020] In a possible implementation manner, each of the electrode portions located in the same touch electrode region is located in a gap between two adjacent columns of pixel electrodes.

[0021] In a possible implementation manner, the electrode portions located in the same touch electrode region are all electrically connected to the same first signal line.

[0022] In a possible implementation manner, a distance between two adjacent sub-electrode groups in the second direction is substantially equal to a width of the touch electrode in the second direction.

[0023] In a possible implementation, in the second direction, intervals between at least two adjacent sub-electrode groups are substantially equal.

[0024] In a possible implementation manner, the electrode portion includes: a first type of electrode portion;

[0025] The touch display panel further comprises: an array substrate and an opposite substrate arranged opposite to each other; the opposite substrate is provided with a first spacer on a side facing the array substrate; the first spacer comprises a first surface opposite to the array substrate;

[0026] The orthographic projection of at least part of the first-type electrode portion on the substrate has an overlapping area with the orthographic projection of the first surface on the substrate.

[0027] In a possible implementation manner, an orthographic projection of the first via hole on the substrate does not overlap with an orthographic projection of the first surface on the substrate.

[0028] In a possible implementation manner, the electrode portion further includes: a second type of electrode portion; an orthographic projection of the second type of electrode portion on the substrate and an orthographic projection of the first surface on the substrate do not overlap each other.

[0029] In a possible implementation, the electrode portion includes a first type of electrode portion and a second type of electrode portion, and a length of the first type of electrode portion in the second direction is greater than a length of the second type of electrode portion in the second direction.

[0030] In a possible implementation, the touch display panel further includes: a plurality of gate lines extending along a second direction; at least one gate line among the plurality of gate lines includes: a plurality of first sub-gate line portions sequentially distributed along the second direction; adjacent first sub-gate line portions are disconnected;

[0031] The touch display panel further comprises: a transfer portion located at a side of the electrode portion away from the first signal line; an orthographic projection of the transfer portion on the substrate and an orthographic projection of the first sub-gate line portion on the substrate have an overlapping area;

[0032] The touch display panel further includes: a second insulating layer located between the first electrode layer and the gate line, the second insulating layer having a second via hole; and the transfer portion is electrically connected to the first sub-gate line portion through the second via hole.

[0033] In a possible implementation manner, the gate line further includes: a connection end connected to an end of the first sub-gate line portion; a width of the connection end in the first direction is greater than a width of the first sub-gate line portion in the first direction;

[0034] One end of the transition portion is connected to the connecting end of a first sub-gate line portion through a second via hole, and the other end of the transition portion is connected to the connecting end of another first sub-gate line portion through another second via hole, so that adjacent first sub-gate line portions are connected through the transition portion.

[0035] In a possible implementation manner, the gate line further includes: a second sub-gate line portion connected to the first sub-gate line portion;

[0036] The width of the second sub-gate line portion in the first direction is greater than the width of the first sub-gate line portion in the first direction; the width of the second sub-gate line portion in the first direction is substantially equal to the width of the connecting end in the first direction.

[0037] In a possible implementation manner, an orthographic projection of the second sub-gate line portion on the substrate does not overlap with an orthographic projection of the electrode portion on the substrate.

[0038] In a possible implementation manner, the touch display panel further includes: a first electrode of a transistor; the electrode portion includes a second type of electrode portion;

[0039] At least partially between adjacent first signal lines, the transition portion is located between the orthographic projection of the first electrode of the transistor on the substrate and the orthographic projection of the second-type electrode portion on the substrate.

[0040] In a possible implementation manner, a length of the second type of electrode portion in the second direction is smaller than a length of the first electrode of the transistor in the second direction.

[0041] In a possible implementation manner, a length of the first electrode of the transistor in the second direction is smaller than a length of the transition portion in the first direction.

[0042] In a possible implementation, the electrode portion includes a first type of electrode portion, and a length of the first type of electrode portion in the second direction is greater than a length of the first electrode of the transistor in the second direction and less than a length of the switching portion in the second direction.

[0043] In a possible implementation, the touch display panel further includes: a plurality of data lines extending along the first direction, a first electrode of a transistor electrically connected to the pixel electrode;

[0044] A first signal line and a data line form a signal routing group. In the same signal routing group, the electrode portion is electrically connected to a side of the first signal line away from the data line, and the first electrode of the transistor is located on a side of the data line away from the first signal line.

[0045] In a possible implementation manner, an orthographic projection of an extension line of an outer edge of the electrode portion parallel to the second direction on the substrate overlaps with an orthographic projection of the first electrode of the transistor on the substrate.

[0046] In a possible implementation manner, the first signal line and the data line are located in the same layer.

[0047] In a possible implementation manner, the touch layer is located between the layer where the data lines are located and the first electrode layer;

[0048] The touch electrode comprises: a third via hole; the pixel electrode passes through the third via hole and is connected to the first electrode of the transistor.

[0049] In a possible implementation, the touch electrode further includes a first slit extending along the first direction, and an orthographic projection of the first slit on the substrate overlaps at least part of an orthographic projection of the first signal line on the substrate.

[0050] The embodiment of the present disclosure further provides a touch display device, which includes the touch display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1A One of the schematic diagrams of stacking of some film layers provided in an embodiment of the present disclosure;

[0052] Figure 1B The second schematic diagram of stacking of some film layers provided in the embodiment of the present disclosure;

[0053] Figure 1C The third schematic diagram of stacking of some film layers provided in the embodiment of the present disclosure;

[0054] Figure 1D The fourth schematic diagram of stacking of some film layers provided in the embodiment of the present disclosure;

[0055] Figure 1E The fifth schematic diagram of stacking of some film layers provided in the embodiment of the present disclosure;

[0056] Figure 2A This is one of the top view schematic diagrams of a touch display panel provided in an embodiment of the present disclosure;

[0057] Figure 2B for Figure 2A A schematic diagram of stacking of other film layers except the pixel electrode layer;

[0058] Figure 2C for Figure 2A Schematic diagram of a single film layer of the middle light-shielding layer;

[0059] Figure 2D for Figure 2A Schematic diagram of a single film layer of the active layer;

[0060] Figure 2E for Figure 2A Schematic diagram of a single film layer in the middle grid line layer;

[0061] Figure 2F for Figure 2A Schematic diagram of a single film layer of the middle interlayer dielectric layer;

[0062] Figure 2G for Figure 2A Schematic diagram of a single film layer of the data line layer;

[0063] Figure 2H for Figure 2A Schematic diagram of a single film layer in the middle flat layer;

[0064] Fig.2I for Figure 2A Schematic diagram of a single film layer of the touch electrode layer;

[0065] Figure 2J for Figure 2A Schematic diagram of a single film of the middle passivation layer;

[0066] Figure 2K for Figure 2A Schematic diagram of a single film layer of the pixel electrode layer;

[0067] Figure 2L for Figure 2A Schematic diagram of the cross section along the dotted line EF;

[0068] Figure 3 A schematic top view of a touch display panel under a microscope provided in an embodiment of the present disclosure;

[0069] Figure 4 A schematic diagram of a touch display panel provided in an embodiment of the present disclosure;

[0070] Figure 5A A schematic diagram of a top view structure of a touch display panel;

[0071] Figure 5B for Figure 5A An enlarged schematic diagram at the lower left corner;

[0072] Figure 6 A schematic diagram showing a comparison of reflectivity of different types of array substrates;

[0073] Figure 7 Schematic diagram of the reflectivity comparison table of different types of array substrates. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0075] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0076] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0077] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances are expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0078] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0079] For the Touch In Cell structure, the touch function is realized by the touch pad (TPM Pad) made of the data line layer, and the TPM Pad exists in each group of pixels, but a large part of it is used as a floating (Dummy) and has no practical effect. For the Dummy TPM Pad, it will directly lead to the following two problems: on the one hand, it will cause display afterimages. Specifically, in terms of the reflectivity of the array substrate, the Dummy TPM Pad will cause the reflectivity of the array substrate to increase by about 1%, and then during the photolithography patterning process, it will cause overexposure, affecting the underlying alignment film layer, resulting in uneven alignment film pattern, and further causing afterimage problems when the display is produced; on the other hand, the TPM Pad will cause the space (Space) with adjacent wiring to become smaller, and the risk of metal residue (Remain) caused by particles (Particle) falling between adjacent wirings will increase accordingly, resulting in adjacent signal lines being connected, reducing product yield.

[0080] In view of this, see Figure 1A-1E , Figure 2A-2K , Figure 3 As shown, Figure 1A This is one of the schematic diagrams of stacking of some film layers provided in an embodiment of the present disclosure, Figure 1B The second schematic diagram of the stacking of some film layers provided in the embodiment of the present disclosure, Figure 1C The third schematic diagram of the stacking of some film layers provided in the embodiment of the present disclosure, Figure 1D The fourth schematic diagram of the stacking of some film layers provided in the embodiment of the present disclosure is as follows: Figure 1E The fifth schematic diagram of the stacking of some film layers provided in the embodiment of the present disclosure, Figure 2A This is one of the top view schematic diagrams of a touch display panel provided in an embodiment of the present disclosure, Figure 2B for Figure 2A Schematic diagram of the stacking of other film layers except the pixel electrode layer, Figure 2C for Figure 2A Schematic diagram of a single film layer in the middle light-shielding layer. Figure 2D for Figure 2A Schematic diagram of a single film layer of the active layer, Figure 2E for Figure 2A Schematic diagram of a single film layer in the middle grid line layer. Figure 2F for Figure 2A Schematic diagram of a single film layer of the middle interlayer dielectric layer, Figure 2G for Figure 2A Schematic diagram of a single film layer of the data line layer. Figure 2H for Figure 2A Schematic diagram of a single film layer in the flat layer. Fig.2I for Figure 2A Schematic diagram of a single film layer of the touch electrode layer. Figure 2J for Figure 2A Schematic diagram of a single film of the passivation layer. Figure 2K for Figure 2A Schematic diagram of a single film layer of a pixel electrode layer in FIG. 1 , an embodiment of the present disclosure provides a touch display panel, which includes:

[0081] substrate;

[0082] The first electrode layer 2 is located on one side of the substrate, and includes: a plurality of first signal lines 21 extending along a first direction X, and a plurality of electrode portions 22 connected to the plurality of first signal lines 21, namely a touch pad (TPM Pad);

[0083] The touch layer 3 is located on the same side of the substrate as the first electrode layer 2 and includes a plurality of touch electrodes 30 spaced apart from each other;

[0084] The first insulating layer is located on the same side of the substrate as the first electrode layer 2 and between the first electrode layer 2 and the touch layer 3, and has a plurality of first via holes K1; at least some of the plurality of electrode portions 22 are electrically connected to the touch electrodes 30 through the first via holes K1;

[0085] A plurality of pixel electrodes 5 are located on the same side of the substrate as the first electrode layer 2;

[0086] The orthographic projection of the electrode portion 22 on the substrate is only located at the orthographic projection of the gap between some adjacent pixel electrodes 5 on the substrate. Specifically, the gap between adjacent pixel electrodes 5 may be the gap between two adjacent pixel electrodes 5 in the first direction X. Specifically, the orthographic projection of the electrode portion 22 on the substrate may also overlap with the part of the orthographic projection of the pixel electrode 5 on the substrate.

[0087] In the embodiment of the present disclosure, the electrode portion 22 is projected on the substrate only at the gap between some adjacent pixel electrodes 5 on the substrate. Compared with the conventional structure, the electrode portion 22 is arranged next to each pixel electrode 5. The electrode portion 22 of the embodiment of the present disclosure is only located next to some pixel electrodes 5, which can improve the problem that too many electrode portions 22 will lead to too high reflectivity of the array substrate, affecting the exposure of the alignment film, causing uneven patterning of the alignment film layer, and further leading to the problem of afterimage during display. It can also improve the problem that too many electrode portions 22 will lead to a smaller space between the first signal line 21 and the data line 22, and particulate matter will fall between the first signal line 21 and the data line 22. The metal residue caused by the metal residue will cause the first signal line 21 and the data line 22 to be connected, resulting in low product yield. Moreover, the cost of the touch display panel will not be increased. That is, the embodiment of the present disclosure can improve the afterimage performance of the touch display panel without increasing the cost, and at the same time reduce the defective rate of the touch display panel.

[0088] It should be noted that Figure 2B In order to clearly illustrate the relationship between the various film layers of the touch panel, the pixel electrode 5 is not shown, and the embodiment of the present disclosure is not limited to this. In a specific implementation, the touch display panel can be provided with a pixel electrode 5, such as Figure 2A shown.

[0089] In a possible implementation, the touch layer 3 is also multiplexed as a common electrode layer, and signals are loaded in time division to realize touch and display functions. For example, in the first period, a common signal is loaded to the touch layer 3, so that the touch layer 3 is used as a common electrode layer to realize the display function; in the second period, a touch signal is loaded to the touch layer, so that the touch layer 3 is used as a touch layer to realize the touch monitoring function.

[0090] In a possible implementation, all electrode portions 22 are connected to the touch electrode 30 through the first via K1. That is, in the disclosed embodiment, the remaining electrode portions 22 are all effective electrode portions 22 connected to the touch electrode 30, and there is no floating electrode portion 22 that is not loaded with an electrical signal, thereby minimizing the adverse effects of the floating electrode portion 22 that is not loaded with an electrical signal on the touch display panel.

[0091] In a possible implementation, part of the electrode portions 22 are connected to the touch electrodes 30 through the first via holes K1. That is, in the embodiment of the present disclosure, there may also be a small number of floating electrode portions 22 that are not loaded with electrical signals.

[0092] In a possible implementation manner, the minimum distance between at least two adjacent electrode portions 22 in the first direction X and the orthographic projection of the substrate is greater than the length of the orthographic projection of the pixel electrode 5 on the substrate along the first direction X. Specifically, for example, Figure 3 As shown, along the first direction X, two adjacent electrode portions 22 ( Figure 3The position shown in the box is the position where the electrode portion 22 is located) and the minimum distance b1 of the positive projection of the substrate is greater than the length b2 of the positive projection of a pixel electrode 5 on the substrate in the same direction; that is, for example, in the column direction of the first direction X, an electrode portion 22 can be arranged at least every other pixel electrode 5.

[0093] Specifically, the minimum distance between all two adjacent electrode portions 22 on the substrate's positive projection in the first direction X may be greater than the length of the pixel electrode 5 on the substrate's positive projection along the first direction X, that is, the minimum distance between any two adjacent electrode portions 22 on the substrate's positive projection may be greater than the length of the pixel electrode 5 on the substrate's positive projection along the first direction X.

[0094] In a possible implementation, the minimum distance between at least two adjacent electrode portions 22 along the second direction Y and the orthographic projections on the substrate is greater than the length of the orthographic projection of the pixel electrode 5 on the substrate 2 along the second direction Y, and the second direction Y is perpendicular to the first direction X. That is, Figure 3 As shown, in the row direction along the second direction Y, an electrode portion 22 may be provided at least every other pixel electrode 5 .

[0095] Specifically, the minimum distance between all two adjacent electrode portions 22 along the second direction Y and the orthogonal projections on the substrate may be greater than the length of the orthogonal projection of the pixel electrode 5 on the substrate 2 along the second direction Y. In other words, the minimum distance between any two adjacent electrode portions 22 along the second direction Y and the orthogonal projections on the substrate may be greater than the length of the orthogonal projection of the pixel electrode 5 on the substrate 2 along the second direction Y.

[0096] In a possible implementation, along at least one of the first direction X and the second direction Y, the minimum distance between two adjacent electrode portions 22 projected on the substrate is greater than the width of at least two pixel electrodes 5 projected on the substrate in the same direction. Figure 3 As shown, in the first direction X, one electrode portion 22 may be provided at least every two pixel electrodes 5 ; for another example, in the second direction Y, one electrode portion 22 may be provided at least every two pixel electrodes 5 .

[0097] In a specific implementation, since the orthographic projection area of ​​the touch electrode 30 on the substrate is larger than the orthographic projection area of ​​the pixel electrode 5 on the substrate, the area where one touch electrode 30 is located can cover multiple pixel electrodes 5, and the electrode portion 22 is arranged around the pixel electrode 5, and the area where one touch electrode 30 is located can also be covered with multiple electrode portions 22. Specifically, in a possible implementation, see Figure 4As shown, the touch layer 3 includes: a plurality of touch electrode groups C extending along the first direction X and arranged along the second direction Y; the plurality of electrode portions 22 include: a plurality of electrode portion groups D extending along the first direction X and arranged along the second direction Y, the orthographic projection of the touch electrode group C on the substrate at least partially overlaps with the orthographic projection of the electrode portion group D on the substrate; specifically, the orthographic projection of the touch electrode group C on the substrate may cover the orthographic projection of the electrode portion group D on the substrate, specifically, the touch electrode group C corresponds to the electrode portion group D one by one, and the plurality of electrode portions 22 in the area covered by the touch electrode group C may be regarded as the electrode portion group D;

[0098] At least one electrode portion group D among the multiple electrode portion groups D includes: a plurality of sub-electrode portion groups D0 arranged along the first direction X, the sub-electrode portion group D0 including at least one electrode portion 22; the orthographic projection of the touch electrode 30 on the substrate at least partially overlaps with the orthographic projection of the sub-electrode portion group D0 on the substrate; specifically, the orthographic projection of the touch electrode 30 on the substrate covers the orthographic projection of the sub-electrode portion group D0 on the substrate; specifically, the touch electrode 30 corresponds to the sub-electrode portion group D0 one-to-one, and the multiple electrode portions 22 in the area covered by the touch electrode 30 can be used as the sub-electrode portion group D0; the sub-electrode portion groups D0 in the same electrode portion group D are staggered. In the embodiment of the present disclosure, while removing redundant electrode portions 22 to improve the afterimage of the touch display panel and increase the defective rate, different touch electrodes 30 are electrically connected to different first signal lines 21, so that the first signal lines 21 can provide signals to different touch electrodes 30, and / or transmit the signals detected by the touch electrodes 30 to the first signal lines 21, and then transmit them to the control chip IC by the first signal lines 21.

[0099] Specifically, for the staggered distribution of each sub-electrode portion group D0 in the same electrode portion group D, the side edge extension lines of the electrode portions 22 in different electrode portion groups D (for example, Figure 4 The right edge extension lines of the electrode portions 22 in different electrode portion groups D do not overlap. Specifically, Figure 4As shown, for the first column of touch electrodes 30 from the left, the first touch electrode 30 from top to bottom can correspond to retaining the electrode portion 22 around the second column of pixel electrodes 5, so as to be electrically connected to the first signal line 21 through the electrode portion 22 around the second column of pixel electrodes 5, and then connected to the IC, and the remaining electrode portions in the area where the touch electrode 30 is located are removed; for the second touch electrode 30 from top to bottom, the electrode portion 22 around the fourth column of pixel electrodes 5 can be correspondingly retained, so as to be electrically connected to the first signal line 21 through the electrode portion 22 around the fourth column of pixel electrodes 5, and then connected to the IC, and the remaining electrode portions in the area where the touch electrode 30 is located are removed; for the third touch electrode 30 from top to bottom, the electrode portion 22 around the sixth column of pixel electrodes 5 can be correspondingly retained, so as to be electrically connected to the first signal line 21 through the electrode portion 22 around the sixth column of pixel electrodes 5, and then connected to the IC, and the remaining electrode portions in the area where the touch electrode 30 is located are removed; that is, each touch The electrodes 30 all select the electrode portion 22 next to a column of pixel electrodes 5 for connection with the control chip IC, and the rest are removed, and each touch electrode 30 is independently connected to each other without affecting each other; of course, the above is only an example of a connection method between the touch electrode 30 and the electrode portion 22, and the embodiment of the present disclosure is not limited to this, and other distribution methods can also be used, such as the first touch electrode 30 from top to bottom corresponds to the electrode portion 22 retained around the second column of pixel electrodes 5, the second touch electrode 30 from top to bottom corresponds to the electrode portion 22 retained around the third column of pixel electrodes 5, and the third touch electrode 30 from top to bottom corresponds to the electrode portion 22 retained around the fourth column of pixel electrodes 5; for a column of touch electrodes 30, the electrode portions 5 around different columns of pixel electrodes 5 are selected from top to bottom in equal intervals to be connected to the touch electrode 30, which can make the electrode portion 22 and the first signal line layout 21 more concise and beautiful and match the design of the conventional control chip IC.

[0100] Specifically, for example, combining Figure 5A and Figure 5B As shown, Figure 5A 1 is a schematic diagram of a top view of a conductive electrode portion of a touch display panel and a first via hole of a touch electrode. Figure 5B for Figure 5A The corresponding enlarged schematic diagram in the lower left corner, Figure 5AThe figure shows 3 rows and 5 columns of touch electrodes 30, each of which covers a plurality of pixel electrodes 5. Specifically, for a column of touch electrodes 30, the hole groups opened in different touch electrodes 30 can be sequentially offset. For example, for the first column of touch electrodes 30 on the left, the second hole group K12 opened corresponding to the second touch electrode 30 from top to bottom can be offset to the right relative to the first hole group K11 opened corresponding to the first touch electrode 30 from top to bottom; the third hole group K13 opened corresponding to the third touch electrode 30 from top to bottom can be offset to the right relative to the second hole group K12 opened corresponding to the second touch electrode 30 from top to bottom..., and the holes are offset in sequence to realize the electrical connection between different touch electrodes 30 in the same column and the corresponding electrode parts 22. Specifically, the first hole group K11, the second hole group K12, and the third hole group K13 can all include a plurality of first via holes K1, and each first via hole K1 exposes an electrode part 22.

[0101] It should be noted that Figure 4 The touch display panel has 3 rows and 4 columns of touch electrodes 30, and each touch electrode 30 has 3 rows and 6 columns of pixel electrodes 5 as an example for schematic description. Specifically, the touch display panel may include more rows and columns of touch electrodes 30, and each touch electrode 30 may have more rows and columns of pixel electrodes 5 in the area where the touch electrode 30 is located. The embodiments of the present disclosure are not limited thereto. Similarly, Figure 4 The outer contour of the pixel electrode 5 is a rectangle for schematic illustration. In specific implementation, the pixel electrode 5 may also be in other shapes and may also include slits. The embodiment of the present disclosure is not limited thereto. Figure 5B In order to clearly illustrate the distribution of the third control group K13, only a plurality of first via holes K1 are shown without showing other film layer structures, but the embodiment of the present disclosure is not limited thereto.

[0102] In a possible implementation manner, the area covered by one touch electrode 30 may only include the electrode portions 22 in the sub-electrode portion group D0 , and the electrode portions 22 in the area outside the sub-electrode portion group D0 may not be provided.

[0103] In one possible implementation, see Figure 4 As shown, each electrode portion 22 in the same sub-electrode portion group D0 is located in the same column. Specifically, each electrode portion 22 in the same sub-electrode portion group D0 is located in the gap between two adjacent columns of pixel electrodes 5. Specifically, for example, Figure 4 In the figure, the first sub-electrode portion group D0 on the left side from top to bottom is located at the gap between the first column of pixel electrodes 5 and the second column of pixel electrodes 5 .

[0104] In one possible implementation, see Figure 4As shown in FIG. 1 , different sub-electrode sections D0 of the same electrode section group D are located at the gaps between pixel electrodes 5 of different columns. Figure 4 In the figure, the first sub-electrode portion group D0 from top to bottom on the left side is located at the gap between the first column of pixel electrodes 5 and the second column of pixel electrodes 5; for another example, the second sub-electrode portion group D0 from top to bottom on the left side is located at the gap between the third column of pixel electrodes 5 and the fourth column of pixel electrodes 5.

[0105] In one possible implementation, see Figure 4 As shown, each electrode portion 22 in the same sub-electrode portion group D0 is electrically connected to the same first signal line 21 .

[0106] In one possible implementation, see Figure 4 As shown, each electrode portion 22 located in the same touch electrode 30 region is located in the same column direction. Specifically, each electrode portion 22 located in the same touch electrode 30 region is located in the gap between two adjacent columns of pixel electrodes 5. Specifically, for example, Figure 4 In the figure, the first sub-electrode portion group D0 from the left in the area where the first row of touch electrodes 30 is located is located in the gap between the first column of pixel electrodes 5 and the second column of pixel electrodes 5 .

[0107] In one possible implementation, see Figure 4 As shown, each electrode portion 22 located in the same area where the touch electrode 30 is located is electrically connected to the same first signal line 21. The area covered by the touch electrode 30 may not include an electrode portion 22 that is not electrically connected to the first signal line 21.

[0108] In one possible implementation, see Figure 4 As shown, the spacing e1 between two adjacent sub-electrode groups D0 in the second direction Y is substantially equal to the width e2 of the touch electrode 30 in the second direction Y. That is, for the second column of touch electrodes 20 from the left, the electrode portion 22 selected to be connected to the first signal line 21 can correspond to the position of the electrode portion 22 selected to be connected to the first signal line 21 for the first column of touch electrodes 20 from the left, that is, the first touch electrode 20 from the top to the bottom of the first column of touch electrodes 20 from the left is connected to the first signal line 21 through the electrode portion 22 around the second column of pixel electrodes 5, and for the first touch electrode 20 from the top to the bottom of the second column of touch electrodes 20 from the left, the electrode portion 22 around the second column of pixel electrodes 5 in the area covered by the touch electrode 20 can also be selected to be connected to the corresponding first signal line 21, so that it has the advantages of being regular, simple and beautiful and matching the conventional control chip IC.

[0109] Specifically, Figure 4As shown, the distance e1 between two adjacent sub-electrode groups D0 may be the side of two adjacent electrode portions 22 in the same row electrically connected to the first signal line 21 (for example, Figure 2G The distance between the right side where the first signal line 21 of the middle electrode part 22 is connected.

[0110] Specifically, for the touch electrodes 30 in the same row, no other electrode portions 22 may be provided between two sub-electrode portion groups D0 in the corresponding coverage areas of the adjacent touch electrodes 30. Figure 4 As shown, in the area covered by the first row of touch electrodes 30 , there is no other electrode portion 22 between the first sub-electrode portion group D0 from the left and the second sub-electrode portion group D0 from the left.

[0111] In one possible implementation, see Figure 4 As shown, in the second direction Y, the spacing e1 between at least two adjacent sub-electrode portion groups D0 is substantially equal. For example, in the area covered by the first row of touch electrodes 30, the distance between the second sub-electrode portion group D0 and the third sub-electrode portion group D0 is substantially equal to the distance between the third sub-electrode portion group D0 and the fourth sub-electrode portion group D0. Specifically, in the direction perpendicular to the first direction X, the spacing e1 between any adjacent sub-electrode portion groups D0 may be substantially equal.

[0112] In one possible implementation, see Figure 2A As shown, the electrode portion 22 includes: a first type of electrode portion 221; the touch display panel also includes: an array substrate and an opposing substrate arranged oppositely; the opposing substrate is provided with a first spacer PS1 on the side facing the array substrate, and the first spacer PS1 includes a first surface opposite to the array substrate (specifically, the first spacer PS1 may have a top surface and a bottom surface, wherein the bottom surface may be in contact with the opposing substrate, the top surface may be opposite to the array substrate, and the first surface may specifically be the top surface of the first spacer PS); the orthographic projection of at least part of the first type of electrode portion 221 on the substrate has an overlapping area with the orthographic projection of the first surface on the substrate. In another possible embodiment, the orthographic projection of part of the first type of electrode portion 221 on the substrate may not have an overlapping area with the orthographic projection of the first surface on the substrate, such as Figure 2A shown.

[0113] It should be noted that Figure 2A The first spacer PS1 shown in FIG. 1 may be an orthographic projection of a first surface of the first spacer PS1 on the array substrate.

[0114] In one possible implementation, see Figure 1BAs shown, the orthographic projection of the first via hole K1 on the substrate does not overlap with the orthographic projection of the first surface on the substrate 1. In the disclosed embodiment, the orthographic projection of the first via hole K1 on the substrate does not overlap with the orthographic projection of the first surface on the substrate 1, which can prevent the first spacer PS1 from being disposed in the area where the first via hole K1 is located, which will affect the conduction effect between the electrode portion 22 and the touch electrode 30, and when the first spacer PS1 is in the area where the first via hole K1 is located, the contact surface is uneven, it is easy to move, and it cannot play a stable support effect.

[0115] In one possible implementation, combining Figure 2A As shown, the opposing substrate may also be provided with a second spacer PS2; specifically, the height of the first spacer PS1 in a direction perpendicular to the substrate 1 may be greater than the height of the second spacer PS2 in a direction perpendicular to the substrate 1, that is, the first spacer PS1 may be a main spacer, and the second spacer PS2 may be a secondary spacer. In a specific implementation, the first surface of the first spacer PS1 may be in contact with the array substrate, and the second spacer PS2 may not be in contact with the array substrate; in the disclosed embodiment, for the column where the first spacer PS1 is located, the length of the electrode portion 22 retained in the column in the second direction Y may be made longer (as a first type of electrode portion 221), and for the column where the first spacer PS is not provided, the electrode portion 22 may be made shorter (as a second type of electrode portion 222), so as to avoid that when the first spacer PS1 is placed at the position of the electrode portion 22 of the column, due to the contact of the first spacer PS1 with the array substrate, if the first spacer PS1 is in contact with the first via K1, it will affect the support effect.

[0116] In a specific implementation, a second spacer PS2 may also be provided for the column where the first spacer PS is located. Since the second spacer PS2 may contact the array substrate only when the display panel is pressed, and may be in a non-contact state with the array substrate when not pressed, the orthographic projection of the second spacer PS2 on the substrate 1 may overlap with the orthographic projection of the first via hole K1, or may not overlap with the orthographic projection of the first via hole K1.

[0117] In one possible implementation, see Figure 1B As shown, the electrode portion 22 further includes: a second type electrode portion 222; the orthographic projection of the second type electrode portion 222 on the substrate and the orthographic projection of the first surface on the substrate do not overlap each other.

[0118] In one possible implementation, combining Figure 1B and Figure 2GAs shown, the electrode portion 22 includes: a first type of electrode portion 221 and a second type of electrode portion 222; the length a1 of the first type of electrode portion 221 in the second direction Y is greater than the length a2 of the second type of electrode portion 222 in the second direction Y. In the disclosed embodiment, for the electrode portion 22 in the column where the first spacer PS1 is located, the length of the electrode portion 22 in the first direction X can be made longer, as the first type of electrode portion 221; and for the electrode portion 22 in the column where the first spacer PS1 is not located, the length of the electrode portion 22 can be made shorter, as the second type of electrode portion 222; the adverse effects of the electrode portion 22 on the touch display panel can be minimized.

[0119] In one possible implementation, combining Figure 1C , Figure 2E and 2F As shown, the touch display panel further includes: a plurality of gate lines 6 extending along the second direction Y; at least one gate line 6 among the plurality of gate lines 6 includes: a plurality of first sub-gate line portions 61 sequentially distributed along the second direction Y; adjacent first sub-gate line portions 61 are disconnected; the touch display panel further includes: a transfer portion 23 located on the side of the electrode portion 22 away from the first signal line 21; the orthographic projection of the transfer portion 23 on the substrate has an overlapping area with the orthographic projection of the first sub-gate line portion 61 on the substrate; the touch display panel further includes: a second insulating layer 71 located between the first electrode layer 2 and the gate line 6, the second insulating layer 71 having a second via K2; the transfer portion 23 is electrically connected to the first sub-gate line portion 61 through the second via K2. In the disclosed embodiment, the gate line 6 is divided into a plurality of first sub-gate line portions 61 that are disconnected from each other, which can avoid the problem that static electricity is easily generated when the gate line 6 is too long, causing the gate line 6 to be easily burned.

[0120] In one possible implementation, combining Figure 1C , Figure 2E and 2FAs shown, the gate line 6 also includes: a connecting end 62 connected to the end of the first sub-gate line portion 61; a width d3 of the connecting end 62 in the first direction X is greater than a width d1 of the first sub-gate line portion 61 in the first direction X; one end of the transition portion 23 is connected to the connecting end 62 of a first sub-gate line portion 61 through a second via hole K2, and the other end of the transition portion 23 is connected to the connecting end 62 of another first sub-gate line portion 61 through another second via hole K2, so that adjacent first sub-gate line portions 61 are connected through the transition portion 23. In the embodiment of the present disclosure, when the electrode portion 22 is only provided around a part of the pixel electrode 5, there can be more wiring space, and the position of the adapter portion 23 can be flexibly set as needed. Specifically, in order to avoid the problem that the gate line 6 is long and prone to static electricity, the adapter portion 23 is provided to perform a jumper design through the layer where the data line 25 is located. When the adapter portion 23 is located between the first pole 24 of the transistor and the electrode portion 22, the space (Space) between the first pole 24 of the transistor, the electrode portion 22 and the intermediate adapter portion 23 will become smaller, and the size of the electrode portion 22 will be compressed accordingly. At this time, the distance (Margin) between the outer edge of the first via K1 and the outer edge of the electrode portion 22 becomes smaller, and the risk of metal residue (Remain) / broken wire (Open) increases accordingly. In addition, the first via K1 will also be closer to the overlapping position of the layer where the gate line 6 and the data line 25 are located, increasing the risk of the spacer falling off the first via K1, resulting in poor display. Specifically, for example, in a 200PPI product, the Space between the first electrode 24 of the transistor and the strip-shaped transition portion 23 is 3μm, which is the lower limit of the current design rules. When the PPI increases, if it is still necessary to ensure that it is above 3μm, the Space needs to compress the size of the transition portion 23; the overlap margin between the first via K1 and the electrode portion 22 is correspondingly reduced, increasing the problem of hole exposure / overlap offset, resulting in dark spots / flickering (Crack) or poor display of the first via K1 due to the spacer falling off; further, in the disclosed embodiment, when the electrode portion 22 is only provided around a portion of the pixel electrode 5, the wiring distribution space of the transition portion 23 is larger, the wiring is more flexible, and can be actually adjusted according to the different designs of different models of touch display panels, and the overall yield risk is greatly reduced.

[0121] In one possible implementation, combining Figure 2E As shown, the gate line 6 also includes: a second sub-gate line portion 63 connected to the first sub-gate line portion 61; the width d2 of the second sub-gate line portion 63 in the first direction X is greater than the width d1 of the first sub-gate line portion 61 in the first direction X; the width d2 of the second sub-gate line portion 63 in the first direction X is substantially equal to the width d3 of the connecting end 62 in the first direction X. In the disclosed embodiment, the gate line 6 also includes the second sub-gate line portion 63 with a wider line width, which can reduce the resistance of the gate line 6 and improve the problem that the gate line 6 has a large line resistance that affects signal transmission.

[0122] In one possible implementation, combining Figure 2E As shown, the width d1 of the first sub-gate line portion 61 in the first direction X may be 1 μm to 10 μm; in a possible embodiment, the width d1 of the first sub-gate line portion 61 in the first direction X may be 2 μm to 8 μm; in a possible embodiment, the width d1 of the first sub-gate line portion 61 in the first direction X may be 2 μm, 3 μm, 3.5 μm, 4 μm, 5 μm, 6 μm, 7 μm, or 8 μm.

[0123] In one possible implementation, combining Figure 2E As shown, the width d2 of the second sub-gate line portion 63 in the first direction X may be substantially equal to the width d3 of the connection end 62 in the first direction X.

[0124] In one possible implementation, combining Figure 2E As shown, the width d3 of the connecting end 62 in the first direction X may be 1 μm to 10 μm; in a possible embodiment, the width d3 of the connecting end 62 in the first direction X may be 3 μm to 8 μm; in a possible embodiment, the width d3 of the connecting end 62 in the first direction X may be 3 μm, 4 μm, 5 μm, 5.9 μm, 6 μm, 7 μm, or 8 μm.

[0125] In one possible implementation, combining Figure 1C As shown, the orthographic projection of the second sub-gate line portion 63 on the substrate does not overlap with the orthographic projection of the electrode portion 22 (including the first type electrode portion 21 and the second type electrode portion 22) on the substrate. In this way, it is avoided that the second sub-gate line portion 63 and the electrode portion 22 generate a large overlapping capacitance, which affects the signal transmission of the gate line 6.

[0126] In one possible implementation, combining Figure 2G As shown, the touch display panel also includes: a first electrode 24 of a transistor; the electrode portion 22 includes a second type of electrode portion 222; and between at least part of adjacent first signal lines 21, the adapter portion 23 is located between the orthographic projection of the first electrode 24 of the transistor on the substrate and the orthographic projection of the second type of electrode portion 222 on the substrate.

[0127] In one possible implementation, see Figure 2GAs shown, the electrode portion 22 includes a first type electrode portion 221; the length a2 of the second type electrode portion 222 in the second direction Y is less than the length a3 of the first electrode 24 of the transistor in the second direction Y. In a possible implementation, the length a2 of the second type electrode portion 222 in the second direction Y may also be substantially equal to the length a3 of the first electrode 24 of the transistor in the second direction Y. In a possible implementation, the length a2 of the second type electrode portion 222 in the second direction Y may also be greater than the length a3 of the first electrode 24 of the transistor in the second direction Y.

[0128] In one possible implementation, see Figure 2G As shown, the length a3 of the transistor first electrode 24 in the second direction Y is less than the length a4 of the transition portion 23 in the first direction X. In a possible implementation, the length a3 of the transistor first electrode 24 in the second direction Y may also be greater than the length a4 of the transition portion 23 in the first direction X. In a possible implementation, the length a3 of the transistor first electrode 24 in the second direction Y may also be equal to the length a4 of the transition portion 23 in the first direction X.

[0129] In one possible implementation, see Figure 2G As shown, the length a1 of the first type electrode portion 221 in the second direction Y is greater than the length a3 of the first electrode 24 of the transistor in the second direction Y, and less than the length a4 of the adapter 23 in the second direction Y. In a possible implementation, the length a1 of the first type electrode portion 221 in the second direction Y may also be greater than or equal to the length a3 of the first electrode 24 of the transistor in the second direction Y. In a possible implementation, the length a1 of the first type electrode portion 221 in the second direction Y may also be greater than or equal to the length a4 of the adapter 23 in the second direction Y.

[0130] In one possible implementation, see Figure 2G As shown, the length a1 of the first type of electrode portion 221 in the second direction Y may be 10 μm to 20 μm; in a possible embodiment, the length a1 of the first type of electrode portion 221 in the second direction Y may be 12 μm to 18 μm; in a possible embodiment, the length a1 of the first type of electrode portion 221 in the second direction Y may be 12 μm, 14 μm, 14.9 μm, 15 μm, 16 μm, 17 μm, or 18 μm.

[0131] In one possible implementation, see Figure 2GAs shown, the length a2 of the second type of electrode portion 222 in the second direction Y may be 1 μm to 10 μm; in a possible embodiment, the length a2 of the second type of electrode portion 222 in the second direction Y may be 5 μm to 8 μm; in a possible embodiment, the length a2 of the second type of electrode portion 222 in the second direction Y may be 5 μm, 6 μm, 6.1 μm, 6.5 μm, 7 μm, or 8 μm.

[0132] In one possible implementation, see Figure 2G As shown, the length a3 of the first electrode 24 of the transistor in the second direction Y may be 5 μm to 15 μm; in a possible embodiment, the length a3 of the first electrode 24 of the transistor in the second direction Y may be 8 μm to 13 μm; in a possible embodiment, the length a3 of the first electrode 24 of the transistor in the second direction Y may be 8 μm, 9 μm, 10 μm, 10.5 μm, 11 μm, or 12 μm.

[0133] In one possible implementation, see Figure 2G As shown, the length a4 of the transition portion 23 in the second direction Y may be 15 μm to 25 μm; in a possible embodiment, the length a4 of the transition portion 23 in the second direction Y may be 18 μm to 23 μm; in a possible embodiment, the length a4 of the transition portion 23 in the second direction Y may be 18 μm, 19 μm, 19.5 μm, 20 μm, 21 μm, 22 μm, or 23 μm.

[0134] In one possible implementation, see Figure 2G As shown, the length a5 of the first type electrode portion 221 in the first direction X may be substantially equal to the length a6 of the second type electrode portion 222 in the first direction X; in a possible implementation manner, see Figure 2G As shown, the length a6 of the second type electrode portion 222 in the first direction X may be substantially equal to the length a7 of the first electrode 24 of the transistor in the first direction X; in a possible implementation manner, see Figure 2G As shown, the length a6 of the second-type electrode portion 222 in the first direction X may be greater than the length a8 of the transition portion 23 in the first direction X.

[0135] In one possible implementation, see Figure 2G As shown, the length a8 of the transition portion 23 in the first direction X may be 5 μm to 15 μm; in a possible embodiment, the length a8 of the transition portion 23 in the first direction X may be 6 μm to 10 μm; in a possible embodiment, the length a8 of the transition portion 23 in the first direction X may be 6 μm, 7 μm, 7.2 μm, 7.5 μm, 8 μm, 9 μm, or 10 μm.

[0136] In one possible implementation, see Figure 2G As shown, the length a1 of the first type electrode portion 221 in the second direction Y may be greater than the length of the first via hole K1 in the second direction Y; in a possible implementation manner, see Figure 2G As shown, the length a2 of the second-type electrode portion 222 in the second direction Y may be greater than the length of the first via hole K1 in the second direction Y.

[0137] In a possible embodiment, the distance between the centers of adjacent pixel electrodes 5 in the first direction X may be 5 μm to 15 μm; in a possible embodiment, the distance between the centers of adjacent pixel electrodes 5 in the first direction X may be 5 μm, 6 μm, 7 μm, 8 μm, 8.5 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm or 15 μm.

[0138] In a possible embodiment, the distance between the centers of adjacent pixel electrodes 5 in the second direction Y may be 5 μm to 15 μm; in a possible embodiment, the distance between the centers of adjacent pixel electrodes 5 in the second direction Y may be 5 μm, 6 μm, 7 μm, 8 μm, 8.5 μm, 9 μm, 9.8 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm or 15 μm.

[0139] In a possible implementation manner, the distance between the centers of adjacent pixel electrodes 5 in the second direction Y may be greater than the distance between the centers of adjacent pixel electrodes 5 in the first direction X.

[0140] In a possible embodiment, the sum of the length a1 of the first type of electrode portion 221 in the second direction Y and the length a3 of the first electrode 24 of the transistor in the second direction Y may be less than one third of the length of the pixel unit in the second direction Y; in a possible embodiment, the sum of the length a2 of the second type of electrode portion 222 in the second direction Y, the length a3 of the first electrode 24 of the transistor in the second direction Y, and the length a4 of the adapter portion 23 in the second direction Y may be less than one third of the length of the pixel unit in the second direction Y; specifically, the pixel unit may include three sub-pixels of red, green, and blue.

[0141] In a possible embodiment, the length of the pixel unit in the second direction Y may be 30 μm to 200 μm; in a possible embodiment, the length of the pixel unit in the second direction Y may be 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 165 μm, 167.1 μm, 170 μm, 180 μm, 190 μm or 200 μm.

[0142] In one possible implementation, see Figure 2G As shown, the touch display panel also includes: a plurality of data lines 25 extending along a first direction Y, and a transistor first electrode 24 electrically connected to the pixel electrode 5; a first signal line 21 and a data line 25 form a signal wiring group 200, in which the electrode portion 22 is electrically connected to a side of the first signal line 21 away from the data line 25, and the transistor first electrode 24 is located on a side of the data line 25 away from the first signal line 21.

[0143] For details, see Figure 2G As shown, the area of ​​the data line 25 between two adjacent gate lines 6 may include: a first data portion 251 arranged along the first direction X, and a second data line portion 252, the extension lines of the first data portion 251 and the second data portion 252 do not overlap, specifically, the first angle α1 formed by the first data line portion 251 and the second data portion 252 may be an obtuse angle; specifically, the area of ​​the first signal line 21 between two adjacent gate lines 6 may include a first signal portion 211 and a second signal portion 212 sequentially distributed in the first direction X, the extension lines of the first signal portion 211 and the second signal portion 212 do not overlap, specifically, the second angle α2 formed by the first signal portion 211 and the second signal portion 212 may be an obtuse angle. Specifically, the first data portion 251 may be parallel to the first signal portion 211, the second data portion 252 may be parallel to the second signal portion 212, and the first angle α1 and the second angle α2 may be equal.

[0144] In one possible implementation, see Figure 2G As shown, the orthographic projection of the outer edge extension line L of the electrode portion 22 parallel to the second direction Y on the substrate overlaps with the orthographic projection of the transistor first electrode 24 on the substrate. That is, the electrode portion 22 and the transistor first electrode 24 can be arranged in substantially the same row upward.

[0145] In one possible implementation, see Figure 2G As shown, the first signal line 21 and the data line 25 are located in the same layer. In this way, the first signal line 21 can be formed while the data line 25 is formed, so as to simplify the manufacturing process of the touch display panel.

[0146] In a possible implementation manner, the touch layer 3 is located between the first electrode layer 2 and the layer where the pixel electrode 5 is located; see Fig.2I As shown, the touch electrode 30 includes: a third via hole K3; the pixel electrode 5 passes through the third via hole K3 and is connected to the first electrode 24 of the transistor.

[0147] In one possible implementation, combining Figure 1D and Fig.2I As shown, the touch electrode 30 further includes a first slit S1 extending along the first direction X, and the orthographic projection of the first slit S1 on the substrate at least partially overlaps with the orthographic projection of the first signal line 21 on the substrate. Fig.2I As shown, the first slit S1 may include a first sub-slit S11 and a second sub-slit S12 arranged along the first direction X. Specifically, the extension lines of the first sub-slit S11 and the second sub-slit S12 may not overlap. Specifically, the third angle α3 formed by the first sub-slit S11 and the second sub-slit S12 may be an obtuse angle. Specifically, the third angle α3 may be substantially equal to the first angle α1.

[0148] In one possible implementation, see Figure 2K As shown, the pixel electrode 5 may have a plurality of second slits S2; the second slit S2 may include: a third sub-slit portion S21 and a fourth sub-slit portion S22 sequentially distributed along the first direction X, wherein the extension lines of the third sub-slit portion S21 and the fourth sub-slit portion S22 may not overlap, and specifically, the fourth angle α4 formed by the two may be an obtuse angle, and specifically, the fourth angle α4 may be substantially equal to the first angle α1. Specifically, the first slit S1 may be similar in shape to the second slit S2.

[0149] In a possible implementation, the first insulating layer 4 may be a flat layer. The first electrode layer 2 may be the layer where the data line 25 is located; the first electrode layer 2 may be located on the side of the gate line 6 away from the substrate; the touch layer 3 may be located on the side of the first electrode layer 2 away from the substrate, and the pixel electrode layer 5 may be located on the side of the touch layer 3 away from the substrate; an active layer 9 may be provided between the substrate and the layer where the gate line 6 is located; a light shielding layer 8 may be provided between the substrate and the active layer 9, and a second insulating layer 71 may be provided between the gate line 6 and the layer where the data line 25 is located; a passivation layer 72 may be provided between the touch layer 3 and the layer where the pixel electrode 5 is located, that is, in combination with Figure 2A-2L As shown, Figure 2L for Figure 2AIn the cross-sectional schematic diagram along the dotted line EF in the middle, the touch display panel can be sequentially provided with: a buffer layer 73, a shading layer 8 (including a plurality of shading patterns 80), an active layer 9 (including a plurality of active patterns 90), a gate insulating layer 74, a gate line 6, a second insulating layer 71 (which can be an interlayer dielectric layer), a first electrode layer 2 (a layer where the data line 25, the electrode portion 22, and the first electrode 24 of the transistor are located), a first insulating layer 4 (which can also be a flat layer), a touch layer 3, and a passivation layer 72.

[0150] In one possible implementation, combining Figure 2L As shown, the display panel may further include: an eighth via hole K8 penetrating the second insulating layer 71 and the gate insulating layer 74 , and the first electrode 24 of the transistor contacts the active pattern 90 through the eighth via hole K8 .

[0151] In one possible implementation, combining Figure 2H as well as Figure 2L As shown, the first insulating layer 4 may further have a plurality of seventh via holes K7 , so that the pixel electrode 5 passes through the third via hole K3 , the fourth via hole K4 , and the seventh via hole K7 , and is connected to the first electrode 24 of the transistor.

[0152] In one possible implementation, combining Figure 2L As shown, the orthographic projection of the seventh via hole K7 on the substrate 1 may have an overlapping area with the orthographic projection of the eighth via hole K8 on the substrate 1; in a possible implementation manner, the orthographic projection of the seventh via hole K7 on the substrate 1 may also have no overlapping area with the orthographic projection of the eighth via hole K8 on the substrate 1; in a possible implementation manner, combined with Figure 2L As shown, the orthographic projection of the third via hole K3 on the substrate 1 may have an overlapping area with the orthographic projection of the eighth via hole K8 on the substrate 1; in a possible implementation manner, the orthographic projection of the third via hole K3 on the substrate 1 may also have no overlapping area with the orthographic projection of the eighth via hole K8 on the substrate 1; in a possible implementation manner, combined with Figure 2L As shown, the orthographic projection of the fourth via K4 on the substrate 1 may have an overlapping area with the orthographic projection of the eighth via K8 on the substrate 1; in a possible implementation, the orthographic projection of the fourth via K4 on the substrate 1 may also have no overlapping area with the orthographic projection of the eighth via K8 on the substrate 1.

[0153] In one possible implementation, combining Figure 2LAs shown, the slope angle β1 formed by the first insulating layer 4 at the seventh via hole K7 may be in the range of 30° to 80°; in a possible embodiment, the slope angle β1 formed by the first insulating layer 4 at the seventh via hole K7 may be in the range of 40° to 70°; in a possible embodiment, the slope angle β1 formed by the first insulating layer 4 at the seventh via hole K7 may be in the range of 50° to 65°; in a possible embodiment, the slope angle β1 formed by the first insulating layer 4 at the seventh via hole K7 may be in the range of 50°, 51°, 52°, 53°, 54°, 55°, 56°, 57°, 58°, 59°, 60°, 61°, 62°, 63°, 64°, or 65°.

[0154] In one possible implementation, combining Figure 2L As shown, the slope angle β2 formed by the passivation layer 72 at the fourth via hole K4 may range from 80° to 110°; in a possible embodiment, the slope angle β2 formed by the passivation layer 72 at the fourth via hole K4 may range from 85° to 100°; in a possible embodiment, the slope angle β2 formed by the passivation layer 72 at the fourth via hole K4 may range from 85°, 86°, 87°, 88°, 89°, 90°, 91°, 92°, 93°, 94°, or 95°.

[0155] Specifically, the second insulating layer 71 may be an interlayer dielectric layer. Figure 2F As shown, the second insulating layer 71 may further include: a fifth via hole K5, and a sixth via hole K6); the active layer 9 may include a plurality of active patterns 90, the active pattern 90 may include a source region 91, and a drain region 92, the source region 91 may be connected to the data line 25 through the fifth via hole K5, and the drain region 92 may be connected to the first electrode 24 of the transistor through the sixth via hole K6 (as shown in FIG. Figure 1E The light shielding layer 8 may have a plurality of light shielding patterns 80, and the light shielding patterns 80 may shield at least part of the active pattern 90 of the transistor to prevent the influence of external light on the active pattern. The passivation layer 72 may include a plurality of fourth via holes K4, so that the pixel electrode 5 passes through the third via hole K3 and the fourth via hole K4 and is connected to the first electrode 24 of the transistor.

[0156] For details, see Figure 6 and Figure 7 As shown, the reflectivity of array substrates with similar PPI and different structures is tested, including the number of data lines and the presence or absence of Dummy TPM Pad; Figure 6They include: 0Dual Source structure array substrate 0DS, 1Dual Source structure array substrate 1DS, 3Dual Source structure array substrate 3DS, 3Dual Source structure array substrate 3DSD with Dummy TPM Pad removed, Figure 7 Including: 0Dual Source structure array substrate 0DS, 1Dual Source structure array substrate 1DS, 3Dual Source structure array substrate 3DS, 3DualSource removed Dummy TPM Pad structure array substrate 3DSD reflectivity values ​​at different exposure wavelengths, and reflectivity average (Ave), according to Figure 6 and Figure 7 As shown, it can be clearly seen that, under similar PPI, the more electrode parts 22 (TPM Pad) there are (that is, the number of electrode parts 22 of 0DualSource structure array substrate 0DS is less than the number of electrode parts 22 of 1Dual Source structure array substrate 1DS is less than the number of electrode parts 22 of 3Dual Source structure array substrate 3DS, and the number of electrode parts 22 of 3Dual Source structure array substrate 3DSD without Dummy TPM Pad is less than 3Dual Source structure array substrate 3DS), the higher the reflectivity is, and the reflectivity can be reduced by about 1% by removing the Dummy Pad.

[0157] In specific implementation, the dummy TPM pads are removed by periodic arrangement to the greatest extent possible, which can improve the problem of false detection during automatic optical inspection (AOI) of the array substrate. Specifically, the dummy pads can be removed by periodic arrangement to the greatest extent possible in the following manner:

[0158] 1. Get the distributed TPM Pad;

[0159] 2. In order to improve the efficiency of drawing and editing AOI detection methods (recipes), Dummy TPMPad can be removed periodically;

[0160] 3. Find the position of the electrode part (TPM Pad) according to the touch electrode, find the minimum period of the electrode part (TPM Pad) distribution by column / row, and then arrange the array horizontally according to the minimum period;

[0161] 4. For the vertically staggered arrangement of the touch display panel models, find the minimum period by column;

[0162] 5. According to the overall distribution evaluation, after the minimum longitudinal period is removed, it can ensure that the dummy pad is removed to the maximum extent without affecting the drawing and detection efficiency;

[0163] In summary, for periodic removal of Dummy Pad or manual maximum removal, the choice should be based on the actual situation of the model, comprehensive Dummy Pad removal rate, AOI inspection, drawing cost, and improvement effect.

[0164] Based on the same inventive concept, the embodiment of the present disclosure further provides a touch display device, including the touch display panel provided by the embodiment of the present disclosure. The implementation of the touch display device can refer to the embodiment of the touch display panel, and the repeated parts will not be repeated.

[0165] In specific implementation, in the embodiments of the present disclosure, the touch display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be described in detail here, nor should they be used as a limitation to the present disclosure.

[0166] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0167] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A touch display panel, wherein: include: substrate; A first electrode layer, located at one side of the substrate, comprises: a plurality of first signal lines extending along a first direction, and a plurality of electrode portions connected to the plurality of first signal lines; A touch layer, located on the same side of the substrate as the first electrode layer, comprising a plurality of touch electrodes spaced apart from each other; A first insulating layer is located between the first electrode layer and the touch control layer, and has a plurality of first via holes; at least some of the plurality of electrode portions are electrically connected to the touch control electrodes through the first via holes; a plurality of pixel electrodes, located on the same side of the substrate as the first electrode layer; The orthographic projection of the electrode portion on the substrate is only located at the orthographic projection of a portion of the gaps between adjacent pixel electrodes on the substrate.

2. The touch display panel according to claim 1, wherein: All the electrode parts are electrically connected to the touch electrode through the first via hole.

3. The touch display panel according to claim 2, wherein: The minimum distance between at least two adjacent electrode portions in the first direction and their orthographic projections on the substrate is greater than the length of the orthographic projection of the pixel electrode on the substrate along the first direction.

4. The touch display panel according to any one of claims 1 to 3, wherein: The minimum distance between at least two adjacent electrode portions in the second direction and their orthographic projections on the substrate is greater than the length of the orthographic projection of the pixel electrode on the substrate along the second direction, and the second direction is perpendicular to the first direction.

5. The touch display panel according to claim 4, wherein: The touch layer includes: a plurality of touch electrode groups extending along the first direction and arranged along the second direction; The plurality of electrode portions include: a plurality of electrode portion groups extending along the first direction and arranged along the second direction, the orthographic projection of the touch electrode group on the substrate at least partially overlapping with the orthographic projection of the electrode portion group on the substrate; At least one electrode portion group among the plurality of electrode portion groups comprises: a plurality of sub-electrode portion groups arranged along the first direction, the sub-electrode portion group comprising at least one electrode portion; an orthographic projection of the touch electrode on the substrate overlaps at least part of an orthographic projection of the sub-electrode portion group on the substrate; The sub-electrode sections in the same electrode section group are distributed in a staggered manner.

6. The touch display panel according to claim 5, wherein: Each of the electrode portions in the same sub-electrode portion group is located at a gap between two adjacent columns of pixel electrodes.

7. The touch display panel according to claim 5, wherein: Each of the electrode portions in the same sub-electrode portion group is electrically connected to the same first signal line.

8. The touch display panel according to claim 5, wherein: Each of the electrode portions located in the same area where the touch electrode is located is located in a gap between two adjacent columns of pixel electrodes.

9. The touch display panel according to claim 5, wherein: The electrode portions located in the same touch electrode region are all electrically connected to the same first signal line.

10. The touch display panel according to claim 5, wherein: The distance between two adjacent sub-electrode groups in the second direction is substantially equal to the width of the touch electrode in the second direction.

11. The touch display panel according to claim 5, wherein: In the second direction, intervals between at least two adjacent sub-electrode groups are substantially equal.

12. The touch display panel according to claim 4, wherein: The electrode portion includes: a first type of electrode portion; The touch display panel comprises: an array substrate and an opposite substrate arranged opposite to each other; the opposite substrate is provided with a first spacer on a side facing the array substrate; the first spacer comprises a first surface opposite to the array substrate; The orthographic projection of at least part of the first-type electrode portion on the substrate has an overlapping area with the orthographic projection of the first surface on the substrate.

13. The touch display panel according to claim 12, wherein: The orthographic projection of the first via hole on the substrate does not overlap with the orthographic projection of the first surface on the substrate.

14. The touch display panel according to claim 12, wherein: The electrode portion further includes: a second type of electrode portion; an orthographic projection of the second type of electrode portion on the substrate and an orthographic projection of the first surface on the substrate do not overlap each other.

15. The touch display panel according to claim 4, wherein: The electrode portion includes a first type of electrode portion and a second type of electrode portion, and a length of the first type of electrode portion in the second direction is greater than a length of the second type of electrode portion in the second direction.

16. The touch display panel according to claim 1, wherein: The touch display panel further comprises: a plurality of gate lines extending along a second direction; at least one gate line among the plurality of gate lines comprises: a plurality of first sub-gate line portions sequentially distributed along the second direction; adjacent first sub-gate line portions are disconnected; The touch display panel further comprises: a transfer portion located at a side of the electrode portion away from the first signal line; an orthographic projection of the transfer portion on the substrate and an orthographic projection of the first sub-gate line portion on the substrate have an overlapping area; The touch display panel further includes: a second insulating layer located between the first electrode layer and the gate line, the second insulating layer having a second via hole; and the transfer portion is electrically connected to the first sub-gate line portion through the second via hole.

17. The touch display panel according to claim 16, wherein: The gate line further comprises: a connection end connected to an end of the first sub-gate line portion; a width of the connection end in the first direction is greater than a width of the first sub-gate line portion in the first direction; One end of the transition portion is connected to the connecting end of a first sub-gate line portion through a second via hole, and the other end of the transition portion is connected to the connecting end of another first sub-gate line portion through another second via hole, so that adjacent first sub-gate line portions are connected through the transition portion.

18. The touch display panel according to claim 17, wherein: The gate line further comprises: a second sub-gate line portion connected to the first sub-gate line portion; The width of the second sub-gate line portion in the first direction is greater than the width of the first sub-gate line portion in the first direction; the width of the second sub-gate line portion in the first direction is substantially equal to the width of the connecting end in the first direction.

19. The touch display panel according to claim 18, wherein: An orthographic projection of the second sub-gate line portion on the substrate does not overlap with an orthographic projection of the electrode portion on the substrate.

20. The touch display panel according to claim 4, wherein: The touch display panel further includes: a first electrode of a transistor; the electrode portion includes a second type of electrode portion; At least partially between adjacent first signal lines, the transition portion is located between the orthographic projection of the first electrode of the transistor on the substrate and the orthographic projection of the second-type electrode portion on the substrate.

21. The touch display panel according to claim 20, wherein: A length of the second-type electrode portion in the second direction is smaller than a length of the first electrode of the transistor in the second direction.

22. The touch display panel according to claim 20, wherein: The length of the first electrode of the transistor in the second direction is smaller than the length of the switching portion in the first direction.

23. The touch display panel according to claim 20, wherein: The electrode portion includes a first type of electrode portion, and a length of the first type of electrode portion in the second direction is greater than a length of the first electrode of the transistor in the second direction and less than a length of the switching portion in the second direction.

24. The touch display panel according to claim 1, wherein: The touch display panel further includes: a plurality of data lines extending along the first direction, and a first electrode of a transistor electrically connected to the pixel electrode; A first signal line and a data line form a signal routing group. In the same signal routing group, the electrode portion is electrically connected to a side of the first signal line away from the data line, and the first electrode of the transistor is located on a side of the data line away from the first signal line.

25. The touch display panel according to claim 24, wherein: An orthographic projection of an extension line of an outer edge of the electrode portion parallel to the second direction on the substrate overlaps with an orthographic projection of the first electrode of the transistor on the substrate.

26. The touch display panel according to claim 24, wherein: The first signal line and the data line are located in the same layer.

27. The touch display panel according to claim 24, wherein: The touch control layer is located between the first electrode layer and the layer where the pixel electrodes are located; The touch electrode comprises: a third via hole; the pixel electrode passes through the third via hole and is connected to the first electrode of the transistor.

28. The touch display panel according to claim 27, wherein: The touch electrode further includes a first slit extending along the first direction, wherein an orthographic projection of the first slit on the substrate overlaps at least a portion of an orthographic projection of the first signal line on the substrate.

29. A touch display device, wherein: Comprising a touch display panel as described in any one of claims 1-28.

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