Storage system and operating method thereof
By combining DRAM and NAND flash memory in the storage system and optimizing the data movement method, the NAND flash memory latency problem is solved, and efficient data reading and writing is achieved.
Patent Information
- Application Number
- CN202311298992.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-15
- Filing Date
- 2023-10-09
- Publication Date
- 2025-03-18
AI Technical Summary
The slow reading and writing speed of NAND flash memory leads to latency problems. It is difficult for the prior art to effectively increase the bandwidth of NAND flash memory to improve latency.
By introducing a small amount of DRAM into the storage system and systematically changing the way data is moved, the data is divided into two parts, partly writing to DRAM with short delay and partly writing to NAND flash memory with long delay, the data read and write speed is optimized.
It effectively reduces the latency problems caused by NAND flash memory, improves the read and write efficiency of the overall storage system, and makes its performance close to that of DRAM.
Smart Images
Figure CN119645292A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a storage system and an operating method thereof. Background Art
[0002] Currently, NAND flash memory and DRAM (dynamic random access memory) are common memory types.
[0003] NAND flash memory has become popular for several reasons. (1) High-density storage: NAND flash memory can store a large amount of data in a relatively small physical space, which makes it ideal for smartphones, tablets, and solid-state drives (SSDs). (2) Non-volatility: NAND flash memory is non-volatile, which means that it retains stored data when the power is turned off. This is different from DRAM, which loses its stored data when there is no power. (3) Durability: NAND flash memory is more durable and more able to withstand vibration and shock than traditional hard disk drives (HDDs). (4) Low power consumption: NAND flash memory consumes relatively low power when operating, which makes it particularly suitable for mobile devices such as smartphones and laptops. (5) Good read speed: Although NAND's write and read speeds are not very fast, they are still sufficient for many applications. (6) Price: With the advancement of manufacturing technology and the effect of economies of scale, the price of NAND flash memory has dropped significantly, making it an economical choice for many consumer electronic products. (7) Technological progress: In recent years, the development of multi-level storage technology (such as 3D NAND) has further improved the storage density and performance of NAND flash memory.
[0004] In summary, NAND flash memory combines multiple advantages, making it the mainstream storage solution in the current electronics market.
[0005] DRAM (dynamic random access memory) is also a common computer memory technology that has the following benefits: (1) High-speed performance: DRAM has very fast read and write speeds, especially compared to NAND flash and other storage technologies. (2) Simple architecture: The cell structure of DRAM is relatively simple, which makes it easier to achieve high density during manufacturing. (3) Gradually decreasing costs: Due to DRAM's simple structure and high-volume manufacturing, DRAM's manufacturing costs are gradually decreasing. (4) Scalability: As semiconductor technology advances, DRAM's density and performance are also constantly improving, allowing it to continue to meet the growing performance requirements. (5) Low power mode: Many modern DRAM technologies (such as LPDDR SDRAM (low power Double Data Rate Synchronous Dynamic Random Access Memory) for mobile devices) provide low power modes, which helps extend battery life. (6) Widespread support: DRAM technology has been around for a long time, so it is widely supported in both hardware and software.
[0006] Take NAND flash memory for example. Even the most advanced models on the market today still have slower read and write speeds than DRAM. Specifically, NAND's latency is a few tens of micro-seconds, while DRAM only takes a few tens of nano-seconds. The latency difference is mainly due to the storage operation method, not the speed of data transmission. Therefore, even if the number of NAND I / Os is increased, the bandwidth cannot be effectively increased to improve this latency.
[0007] Therefore, the present invention proposes a system design that effectively reduces the delay problem caused by NAND flash memory by adding a small amount of DRAM and systematically changing the movement of data. Summary of the invention
[0008] According to one aspect of the present invention, a method for operating a storage system is provided, the storage system comprising a memory control circuit, a first type memory and a second type memory, a first read delay of the first type memory being shorter than a second read delay of the second type memory, the method comprising: when a first data is written into the storage system, the memory control circuit divides the first data into a first part and a second part; the first part of the first data is written into the first type memory by the memory control circuit; and the second part of the first data is written into the second type memory by the memory control circuit. A data amount of the first part of the first data is related to a read delay difference and a data transfer rate of the second type memory, the read delay difference being related to the first read delay of the first type memory and the second read delay of the second type memory.
[0009] According to another aspect of the present invention, a storage system is provided, comprising: a memory control circuit; a first type memory coupled to the memory control circuit; and a second type memory coupled to the memory control circuit. A first read delay of the first type memory is shorter than a second read delay of the second type memory. When a first data is written into the storage system, the memory control circuit divides the first data into a first part and a second part. The memory control circuit writes the first part of the first data to the first type memory. The memory control circuit writes the second part of the first data to the second type memory. An amount of data of the first part of the first data is related to a read delay difference and a data transfer rate of the second type memory, and the read delay difference is related to the first read delay of the first type memory and the second read delay of the second type memory.
[0010] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 A functional block diagram of a storage system according to an embodiment of the present invention is shown.
[0012] Figure 2 A schematic diagram showing reading of a first type memory and a second type memory according to an embodiment of the present invention is shown.
[0013] Figure 3 A schematic diagram showing a write operation of a storage system according to an embodiment of the present invention is shown.
[0014] Figure 4 A schematic diagram showing a reading operation of a storage system according to an embodiment of the present invention is shown.
[0015] Description of Reference Numerals
[0016] 50: Processing circuit
[0017] 100: Storage System
[0018] 110: Memory control circuit
[0019] 120: Type 1 memory
[0020] 130: Second type of memory DETAILED DESCRIPTION
[0021] The technical terms of this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition of this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.
[0022] In one embodiment of the present invention, input data is written to at least two types of memories with different delay times. When the input data is written to the storage system, the input data will be divided into two parts. In the write operation, the first part of the input data will be written to the first type of memory with a shorter delay (for example, but not limited to DRAM), and the second part of the input data will be written in parallel to the second type of memory with a longer delay (for example, but not limited to NAND flash memory). Therefore, in general, for the write operation, the overall write delay of the storage system will be very close to the first type of memory with a shorter write delay. For the read operation, the data will be read from the first type of memory and the second type of memory in parallel, and recombined by the memory control circuit to obtain the complete data. Therefore, in general, for the read operation, the overall read delay of the storage system will be very close to the first type of memory with a shorter read delay.
[0023] That is, in one embodiment of the present invention, two memories with different delays are used to optimize the data read and write speed. One embodiment of the present invention maximizes the data read and write efficiency by using two memories with different delays at the same time, thereby providing an efficient and competitive solution.
[0024] Figure 1 A functional block diagram of a storage system according to an embodiment of the present invention is shown. Figure 1As shown, a storage system 100 according to an embodiment of the present invention includes: a memory control circuit 110, a first type memory 120, and a second type memory 130. The memory control circuit 110 is coupled to the first type memory 120 and the second type memory 130. The memory control circuit 110 is further coupled to a processing circuit 50 (for example but not limited to a central processing unit CPU).
[0025] The memory control circuit 110 includes a plurality of hardware control circuits to control the first type memory 120 and the second type memory 130 .
[0026] The first type memory 120 includes a plurality of hardware circuits to store data. In one possible example, the first type memory 120 is, for example but not limited to, a DRAM, which has a shorter read / write delay and a faster read / write speed.
[0027] The second type memory 130 includes a plurality of hardware circuits to store data. In one possible example, the second type memory 130 is, for example but not limited to, a NAND flash memory, which has a longer read / write delay and a slower read / write speed than the first type memory 120 .
[0028] Of course, the present invention is not limited thereto, and according to the spirit of the present invention, the storage system of other possible embodiments of the present invention may include three or more different types of memories, and the delay times of the three or more different types of memories are different from each other. This is also within the spirit of the present invention.
[0029] Figure 2 A schematic diagram showing the reading of the first type memory 120 and the second type memory 130 according to an embodiment of the present invention is shown. Figure 2 In the example, the first read latency Latency_1 of the first type memory 120 is shorter than the second read latency Latency_2 of the second type memory 130. The read latency gap Latency_Gap represents the difference between the first read latency Latency_1 of the first type memory 120 and the second read latency Latency_2 of the second type memory 130 (Latency_Gap=Latency_2-Latency_1).
[0030] Memory read latency refers to the time between when the memory receives a request to read data from the memory and when the memory starts to transmit data. The lower the read latency, the faster the system responds. Low-latency memories are more expensive (higher cost per bit) and have lower density, while high-latency memories reduce the computing performance of the entire system. Therefore, an embodiment of the present invention proposes a hybrid memory composed of two types of memories, which has short latency and high memory density without significantly increasing costs. That is, an embodiment of the present invention seeks a solution that finds a balance between performance, capacity, and cost.
[0031] Figure 3 A schematic diagram of a write operation of a storage system according to an embodiment of the present invention is shown. For a write process of a hybrid memory combining a first type memory 120 with short latency and a second type memory 130 with long latency and high storage density, the write data (transmitted from the processing circuit 50 to the memory control circuit 110) is divided into two parts by the memory control circuit 110: a first part data segment_1 and a second part data segment_2. The first part datasegment_1 of the write data is written to the faster first type memory 120 to obtain short latency performance. The second part datasegment_2 of the write data is written to the high density but long latency second type memory 130.
[0032] The data volume of the first portion of the written data data segment_1 is related to the read latency difference Latency_Gap and the data transfer rate Data Transfer_Rate_2 of the second type memory 130. For example but not limited thereto, the data volume of the first portion of the written data data segment_1 can be expressed as follows: data segment_1 = Latency_Gap × Data_Transfer_Rate_2. The data volume of the first portion of the written data data segment_1 is the product of the read latency difference Latency_Gap and the data transfer rate Data_Transfer_Rate_2 of the second type memory.
[0033] For example, the first read latency Latency_1 of the first type memory 120 and the second read latency Latency_2 of the second type memory 130 are 20ns and 20μs respectively, and the data transfer rate Data_Transfer_Rate_2 of the second type memory 130 is 3.2GB / s, and the amount of data of the first part data segment_1 written data is: datasegment_1=Latency_Gap×Data_Transfer_Rate_2=(20us-20ns)×3.2GB / s≈20×10 -6 ×6.4×10 9 ≈64KB. That is, when writing data, the input data will be divided into two parts by the memory control circuit 110: the first part data segment_1 (data volume is about 64KB) and the second part data segment_2 (the rest). 64KB of data will be written into the faster first type memory 120, while the rest of the data will be written into the high-density but long-delay second type memory 130.
[0034] In addition, in an embodiment of the present case, even if the data transmission rates of the first type memory 120 and the second type memory 130 are different, it will not greatly affect the effect to be achieved in the embodiment of the present case.
[0035] That is, in one embodiment of the present case, since the storage system 100 is a hybrid memory system including a first type memory 120 with short delay and a second type memory 130 with long delay and high storage density, one embodiment of the present case provides a data writing strategy, which is designed to ensure that the advantages of high-speed reading and writing and large capacity are obtained at the same time.
[0036] Figure 4 A schematic diagram of a read operation of a storage system according to an embodiment of the present invention is shown. During reading, the memory control circuit 110 receives a read instruction and a read address from the processing circuit 50. In response, the memory control circuit 110 reads the first part of the data, data segment_1, from the first type memory 120 and the second part of the data, data segment_2, from the second type memory 130. The memory control circuit 110 combines the read data (read data = data segment_1 + data segment_2) and transmits it back to the processing circuit 50.
[0037] During a read operation, the first type memory 120 and the second type memory 130 may be read simultaneously.
[0038] Since the read latency of the first type memory 120 is shorter, after the first read latency Latency_1 of the first type memory 120, the first part of the data, data segment_1, is first transmitted back from the first type memory 120 to the memory control circuit 110. Then, the second part of the data, data segment_2, is transmitted back from the second type memory 130 to the memory control circuit 110.
[0039] For the reading process of the storage system 100 (hybrid memory system), when data needs to be read, the memory control circuit 110 needs to read out the first part data_segement_1 and the second part data_segement_2. Since the two parts of data are stored in two different memories (the first type memory 120 with short delay and the second type memory 130 with long delay and high storage density), the reading operation will be performed synchronously in the two memories.
[0040] Since the first type memory 120 has a shorter delay, the first part data_segement_1 stored in the first type memory 120 can be read out faster than the second part data_segement_2 stored in the second type memory 130 with a longer delay and higher storage density. Therefore, when the memory control circuit 110 starts to output data to the processing circuit 50, the first part data_segement_1 is output first, followed by the second part data_segement_2. Such a read strategy ensures that data can be read out continuously at the fastest speed.
[0041] Since the two memories have different write and read delays, the memory with a slower read and write speed will dominate the final read and write delay of the traditional storage system (with a hybrid memory). However, in the present embodiment, through the above-mentioned read and write strategy, data can be read out continuously at the fastest speed; and for the read operation, the overall read delay of the storage system 100 will be very close to the first type of memory 120 with a shorter read delay.
[0042] In practice, in one embodiment of the present invention, the first type memory 120 and the second type memory 130 can be integrated into the same memory card or the same dual in-line memory module (DIMM). The memory card or the DIMM includes an internal memory control circuit (internal control) that can execute Figure 1 The operation and function of the memory control circuit 110. In other words, Figure 1 The memory control circuit 110 is located in the memory card or the DIMM.
[0043] Alternatively, in another embodiment of the present invention, the first type memory 120 and the second type memory 130 can be integrated into the same memory card or the same dual in-line memory module, but Figure 1 The functions and operations of the memory control circuit 110 can be performed by the host's processing circuit (such as a CPU, etc.) (external control). In other words, Figure 1 The memory control circuit 110 is located outside the memory card or the DIMM.
[0044] Alternatively, in one embodiment of the present case, the first type memory 120 and the second type memory 130 are respectively located in two independent memory cards or two independent DIMMs, and the two independent memory cards or the two independent DIMMs both include an internal memory control circuit (internal control) that can execute Figure 1 The operation and function of the memory control circuit 110. In other words, Figure 1 The memory control circuit 110 is located in the two independent memory cards or the two independent DIMMs.
[0045] Alternatively, in another embodiment of the present invention, the first type memory 120 and the second type memory 130 are respectively located in two independent memory cards or two independent DIMMs, but Figure 1 The functions and operations of the memory control circuit 110 can be performed by the host's processing circuit (such as a CPU, etc.) (external control). In other words, Figure 1 The memory control circuit 110 is located outside the two independent memory cards or the two independent DIMMs.
[0046] An embodiment of the present case is not limited to a specific memory type and can be applied to a variety of different memories and storage technologies, including SRAM (static random access memory), DRAM (dynamic random access memory), NAND flash memory, NOR flash memory, hard disk drives, ROM (read-only memory), RRAM (resistive random access memory), MRAM (magnetoresistive random access memory) and FeRAM (ferroelectric random access memory), etc.
[0047] In addition, in other possible embodiments of the present invention, the data volume of the first part data_segment_1 can also be obtained by using different relationship formulas between the read latency difference (Latency_Gap) and the data transfer rate (Data_Transfer_Rate_2), which is also within the spirit of the present invention, as long as the transmission efficiency can be maximized. The data volume of the first part data_segment_1 can also be adjusted according to different system design requirements or considerations.
[0048] An embodiment of the present invention discloses a new memory technology or system that combines two memories with different characteristics to achieve optimal performance and cost-effectiveness. As is known, in memory technology, memories with short delays, such as DRAM, provide fast data access, but their manufacturing cost is high and their storage density is low. On the contrary, memories with long delays, such as NAND flash memory, although providing greater storage density and lower cost, have slower access speeds. An embodiment of the present invention proposes a new method that combines these two types of memories to achieve the advantages of short delay, high density and low cost. A hybrid memory system of an embodiment of the present invention includes a fast and high-cost first type of memory (such as DRAM) and a slow, high-storage-density, low-cost second type of memory (such as NAND flash memory). In order to make these two memories work together, an embodiment of the present invention also discloses a memory control circuit (having multiple hardware control circuits) to manage data access and transmission. In a read operation, when the slow, high-storage-density, low-cost second type of memory (such as NAND flash memory) is still preparing for data transmission (i.e., within the delay time Lantency_2), the fast and high-cost first type of memory (such as DRAM) may be ready to transmit data to the memory control circuit. The read / write strategy of an embodiment of the present invention ensures that even if a second type of memory (such as NAND flash memory) with a slow speed, high storage density and low cost is used, the storage system of an embodiment of the present invention can still quickly access or transmit data. Therefore, the overall latency of the storage system of an embodiment of the present invention is similar to the overall latency of using only a first type of memory (such as DRAM) with a fast and high cost.
[0049] In summary, the hybrid storage system of an embodiment of the present invention combines the advantages of short-latency memory and high-density memory, and uses a specific memory control circuit and data transfer / combination strategy to achieve optimal performance.
[0050] An embodiment of the present invention is applicable to working memory, computational memory or storage memory. Moreover, an embodiment of the present invention can be applied to both non-volatile memory and volatile memory.
[0051] Although the present invention may describe many specific details, these should not be understood as limiting the scope of the claimed invention, but should be regarded as a description of the characteristics of a particular embodiment. In the description of the present invention, certain characteristics described in the context of a single embodiment may also be implemented in a single embodiment in combination. Conversely, the various characteristics described in the context of a single embodiment may also be implemented in multiple embodiments alone or in any appropriate sub-combination. In addition, although the characteristics may initially be described as working in certain combinations, or even initially described as such a combination, in some cases, one or more characteristics may be deleted from the combination, and the described combination may be for a sub-combination or a variation of a sub-combination. Similarly, although the operations are depicted in the diagram as being performed in a particular order, this should not be understood as requiring that the operations must be performed in the particular order or sequence shown, or that all depicted operations must be performed to achieve the desired result.
[0052] Although the above embodiments of the present invention only disclose some examples and implementations, according to the disclosed content, the examples and implementations and other implementations may be changed, modified and enhanced.
[0053] In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached claims.
Claims
1. A method for operating a storage system, characterized in that: The storage system includes a memory control circuit, a first type memory, and a second type memory. A first read latency of the first type memory is shorter than a second read latency of the second type memory. The operating method includes: When first data is written into the storage system, the memory control circuit divides the first data into a first part and a second part; The first portion of the first data is written into the first type memory by the memory control circuit; and The second part of the first data is written into the second type memory by the memory control circuit, in, A data size of the first portion of the first data is related to a read delay difference and a data transfer rate of the second type memory. The read delay difference is related to the first read delay of the first type memory and the second read delay of the second type memory.
2. The method for operating a storage system according to claim 1, wherein: The read latency difference is a difference between the first read latency of the first type of memory and the second read latency of the second type of memory.
3. The method for operating a storage system according to claim 1, wherein: The first portion of the first data is a product of the read latency difference and the data transfer rate of the second type memory.
4. The method for operating a storage system according to claim 1, wherein: When the first data is read from the storage system, The memory control circuit reads the first portion of the first data from the first type memory and the second portion of the first data from the second type memory in parallel; as well as The memory control circuit combines the first part of the first data and the second part of the first data into the first data, and returns the first data.
5. A storage system, characterized in that: include: a memory control circuit; a first type memory coupled to the memory control circuit; as well as a second type memory coupled to the memory control circuit, in, A first read latency of the first type memory is shorter than a second read latency of the second type memory, When first data is written into the storage system, the memory control circuit divides the first data into a first part and a second part. The memory control circuit writes the first portion of the first data to the first type memory, The memory control circuit writes the second portion of the first data to the second type memory, A data size of the first portion of the first data is related to a read delay difference and a data transfer rate of the second type memory. The read delay difference is related to the first read delay of the first type memory and the second read delay of the second type memory.
6. The storage system according to claim 5, characterized in that The read latency difference is a difference between the first read latency of the first type of memory and the second read latency of the second type of memory.
7. The storage system according to claim 5, characterized in that The data size of the first portion of the first data is a product of the read delay difference and the data transfer rate of the second type memory.
8. The storage system according to claim 5, characterized in that For a read operation, the memory control circuit reads the first portion of the first data and the second portion of the first data from the first type memory and the second type memory in parallel; as well as The memory control circuit combines the first portion of the first data and the second portion of the first data into the first data.
9. The storage system according to claim 5, characterized in that The first type of memory and the second type of memory are integrated into the same memory card or the same dual in-line memory module; as well as The memory control circuit is located in the memory card or the dual inline memory module, or the memory control circuit is located outside the memory card or the dual inline memory module.
10. The storage system according to claim 5, characterized in that The first type of memory and the second type of memory are respectively located in two independent memory cards or two independent dual in-line memory modules; and The memory control circuit is located in the two independent memory cards or the two independent dual in-line memory modules, or the memory control circuit is located outside the two independent memory cards or the two independent dual in-line memory modules.