Method, device and equipment for optimizing SSD (Solid State Disk) write-in buffer area and medium

Abstract

The invention relates to a method, a device, equipment and a medium for optimizing an SSD (Solid State Disk) write buffer area, and the method comprises the following steps: acquiring a newly written operation request to obtain written data; judging whether the new write-in is host write-in or not; if so, writing the write-in data into a data preparation area; judging whether the data volume in the data preparation area reaches a concurrent write-in threshold value or not; if yes, concurrence data is formed, the concurrence data prepared in the data preparation area is transferred into the data programming area, and the concurrence data is transmitted to a specified Page of each DIE specified WL; whether loading of the Page data corresponding to the WL is completed or not is judged; and if the loading is completed, initiating a programming command of the WL corresponding to each DIE until the data programming is completed. According to the invention, the key data can be processed in time, the delay of data processing is reduced, the idle or excessive allocation of resources is avoided, and the optimal configuration of the resources is realized.

Description

Technical Field

[0001] The present invention relates to the field of SSD writing technology, and in particular to a method, device, equipment and medium for optimizing an SSD writing buffer. Background Art

[0002] As an innovator of data storage technology, SSD (solid-state drive) has been widely used in many fields such as personal computers (PCs), data centers, and embedded systems, with its excellent read and write speed, low latency, and high reliability, and has gradually replaced traditional HDD hard disks to become the mainstream of the market. Especially in the PC market, SSD not only significantly improves the efficiency of daily operations such as system startup and application loading, but also brings users a smoother user experience.

[0003] With the continuous upgrading of interface technologies such as SATA, PCIe, and NVMe, the transmission rate of SSD has achieved a qualitative leap, and the performance ceiling continues to rise. However, in the consumer-grade SSD market, cost control has become a key factor restricting its further popularization. How to effectively reduce costs while ensuring product performance has become an important challenge facing SSD manufacturers.

[0004] In the composition structure of SSD, the main control chip (SOC) plays a core role, responsible for data processing, scheduling and transmission, and its cost accounts for a significant proportion. As an important component of SOC, the size of Memory not only directly affects the cost of SOC, but also directly affects the write performance of SSD. Specifically, during the writing process of SSD, a larger buffer (ie Memory) can temporarily store data from the host. After accumulating to a certain amount (such as 1MB), the main control chip will optimize this data and initiate concurrent write operations of NAND flash memory in batches, thereby making full use of NAND's parallel processing capabilities to obtain higher bandwidth and write speed.

[0005] However, in the pursuit of low-cost consumer-grade SSDs, budget constraints often make it impossible to configure a large enough memory as a write buffer, which results in the inability to fully guarantee the write concurrency of the NAND flash memory, which in turn affects the overall performance of the SSD, such as reduced write speed and increased latency. Therefore, how to effectively utilize the limited write buffer memory and ensure the concurrent write performance of the NAND flash memory through innovative design and technical optimization within a limited cost budget has become the key for SSD manufacturers to improve product competitiveness and meet market demand. Summary of the invention

[0006] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method, device, equipment and medium for optimizing an SSD write buffer.

[0007] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0008] In a first aspect, this embodiment provides a method for optimizing an SSD write buffer, comprising the following steps:

[0009] Get the newly written operation request to obtain the written data;

[0010] Determine whether the new write is a host write;

[0011] If the new write is a host write, the write data is written to the data preparation area;

[0012] Determine whether the amount of data in the data preparation area reaches the concurrent write threshold;

[0013] If the amount of data reaches the threshold of concurrent writing, concurrent data is formed, the concurrent data prepared in the data preparation area is transferred to the data programming area, and the concurrent data is transferred to the specified Page of the WL specified by each DIE;

[0014] Determine whether the Page data of the corresponding WL has been loaded;

[0015] If the Page data of the corresponding WL is loaded, the programming command of each DIE corresponding to the WL is initiated until the data programming is completed;

[0016] Among them, DIE is a module that can be operated independently and concurrently; WL is a module that can be programmed and written independently; Page is a reading module.

[0017] A further technical solution is: before the step of obtaining a new write operation request to obtain write data, it also includes: initializing a write buffer to obtain a data preparation area and a data programming area.

[0018] A further technical solution is: before the step of judging whether the Page data corresponding to the WL has been loaded, it also includes: releasing the data in the data programming area to obtain an empty data programming area.

[0019] Its further technical solution is: after the step of determining whether the new write is a host write, it also includes: if the new write is not a host write, reading the write data and allocating it to the write buffer.

[0020] In a second aspect, the present embodiment provides a device for optimizing an SSD write buffer, comprising: an acquisition unit, a first judgment unit, a writing unit, a second judgment unit, a formation transfer unit, a third judgment unit, and a programming unit;

[0021] The acquisition unit is used to acquire a new write operation request to obtain write data;

[0022] The first determination unit is used to determine whether the new write is a host write;

[0023] The writing unit is used to write the write data into the data preparation area if the new write is a host write;

[0024] The second judgment unit is used to judge whether the amount of data in the data preparation area reaches a threshold value for concurrent writing;

[0025] The formation transfer transmission unit is used to form concurrent data if the data volume reaches the concurrent write threshold, transfer the concurrent data prepared in the data preparation area to the data programming area, and transmit the concurrent data to the specified Page of the WL specified by each DIE;

[0026] The third judgment unit is used to judge whether the Page data corresponding to the WL has been loaded;

[0027] The programming processing unit is used to initiate programming commands for the WLs corresponding to the DIEs if the Page data corresponding to the WLs are all loaded, until the data programming is completed;

[0028] Among them, DIE is a module that can be operated independently and concurrently; WL is a module that can be programmed and written independently; Page is a reading module.

[0029] A further technical solution is: the device also includes: an initialization unit, which is used to initialize the write buffer area to obtain a data preparation area and a data programming area.

[0030] A further technical solution is: the device also includes: a releasing unit, which is used to release the data in the data programming area to obtain an empty data programming area.

[0031] A further technical solution is as follows: the device further comprises: a read allocation unit, which is used to read the write data and allocate it to the write buffer if the new write is not a host write.

[0032] In a third aspect, this embodiment provides a computer device, which includes a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the method for optimizing the SSD write buffer as described above is implemented.

[0033] In a fourth aspect, the present embodiment provides a storage medium storing a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method for optimizing the SSD write buffer as described above can be implemented.

[0034] The beneficial effects of the present invention compared with the prior art are as follows: by identifying and giving priority to host write operations, it is possible to ensure that key data is processed in a timely manner, reduce data processing delays, and thus improve overall write efficiency; in addition, the data is first written to the data preparation area, and when the amount of data accumulates to the threshold of concurrent writes, concurrent data is formed for subsequent processing. This mechanism effectively utilizes the concurrent processing capabilities of the storage device, avoids idleness or over-allocation of resources, and achieves optimal resource configuration; in addition, by switching NAND operations at the Page level, it is possible to use only the buffer size required for Page-level concurrency without sacrificing write performance, significantly reducing the dependence and demand on write buffer resources, which is crucial to improving the cost-effectiveness and scalability of SSDs.

[0035] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0037] Figure 1 This is a typical schematic diagram of the NAND structure inside an SSD;

[0038] Figure 2 A schematic diagram of a typical SSD writing scenario in the prior art;

[0039] Figure 3 A schematic diagram of a flow chart of a method for optimizing an SSD write buffer area provided by an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of an application scenario of the method for optimizing SSD write buffer provided by an embodiment of the present invention;

[0041] Figure 5 A schematic block diagram of a device for optimizing an SSD write buffer area provided by an embodiment of the present invention;

[0042] Figure 6 A schematic block diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0045] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0046] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0047] See also Figure 1 The typical SSD internal NAND composition diagram shown includes the following modules:

[0048] DIE, modules / units that can operate independently and concurrently;

[0049] Block, an independently erasable module / unit, after the data in each physical location is written, the entire Block must be erased before the next write;

[0050] WL (Wordline), a module / unit that can be programmed independently, contains multiple Pages. Taking QLC as an example: a WL generally contains 4 Pages;

[0051] Page, read module / unit, usually 16KB.

[0052] See also Figure 2 The following is a schematic diagram of a typical SSD write scenario in the prior art; for ease of explanation, 16 DIEs and QLC NAND (each WL has 4 Pages) are used for explanation:

[0053] A large write buffer needs to be kept inside the SSD, such as 2MB;

[0054] The write buffer is divided into two areas:

[0055] Area 1: used to receive data written by the host;

[0056] Area 2: Data is ready to be written to each page of the specified WL of 16 DIEs;

[0057] In this configuration, sufficient data (such as area 2, 1MB) must be gathered to initiate NAND parallel writing. During the NAND writing process, data written by the host must also be received in parallel, so a buffer in area 1 is also required.

[0058] After the NAND write and the new host data reception are completed, area 1 and area 2 are exchanged to perform the next WL write and host data reception respectively.

[0059] As can be seen above, in order to achieve concurrent NAND writes and host writes, two groups of write buffers are required; and in order to write each DIE of NAND to WL in parallel, each group requires 1MB (16DIE*16KB*4) of data. This memory overhead is very large and difficult to implement in consumer SSDs. If the memory size is reduced, the concurrency of NAND writes must be reduced or the host write and NAND write must be serialized, which will greatly reduce performance.

[0060] See also Figure 3 to Figure 4 In the specific embodiment shown, the present invention discloses a method for optimizing an SSD write buffer, comprising the following steps:

[0061] S1, obtain a new write operation request to obtain write data;

[0062] Specifically, during the writing process of the SSD, a mechanism is first required to monitor and capture new write operation requests from the host or other data sources. This is usually implemented through the SSD's main control chip (SOC), which serves as the brain of the SSD and is responsible for processing all instructions related to data reading and writing. In specific implementation, the main control chip will be configured with one or more input / output (I / O) interfaces to receive write operation requests from the outside (such as SATA, PCIe or NVMe controllers on PC motherboards). These requests usually contain the data to be written, the target address (i.e., the logical block address or LBA on which the data should be stored), and other possible metadata (such as data verification information). When the main control chip receives a new write operation request, it will first parse the request to extract the data to be written. This step may involve transferring the data in the request from the external interface buffer to a temporary storage area inside the SSD (such as DRAM cache) for subsequent processing.

[0063] More specifically, by real-time monitoring and capturing new write operation requests, the SSD can quickly respond to the host's data writing needs, reduce data waiting time, and improve the overall response speed of the system. In addition, after receiving the write request, the main control chip immediately parses and extracts the data. This step ensures the integrity and accuracy of the data and avoids write failures caused by data transmission errors or losses. In addition, temporarily storing the received data in a temporary storage area inside the SSD (such as DRAM cache) can make full use of the fast storage resources inside the SSD, facilitate subsequent data processing (such as data compression, encryption, verification, etc.), and reduce frequent access to external interfaces, reducing power consumption and latency. In addition, this implementation allows the SSD to process write requests from different sources and types, such as direct I / O requests from the operating system, write commands from the file system, or data storage requests from applications, thereby improving the flexibility and compatibility of the SSD.

[0064] S2, determine whether the new write is a host write;

[0065] Specifically, in the SSD write process, determining whether the newly written data comes from the host is a key step, which usually involves identifying and analyzing the source of the write operation request. In specific implementation, the SSD's main control chip (SOC) will receive write operation requests from different sources. These requests may include direct I / O requests from the host, management commands from the SSD's internal firmware or operating system, or data processing requests from other internal components (such as data compression / decompression modules, encryption / decryption modules). In order to determine whether the newly written data comes from the host, the main control chip can adopt one or a combination of the following strategies:

[0066] Request source identification: When receiving a write request, the main control chip can check whether the request contains a specific source identification. For example, a request from the host may contain a specific identifier or tag that is recognized as "host write" inside the SSD.

[0067] Request type analysis: The main control chip can also analyze the type and content of the request to determine whether it comes from the host. For example, a request from the host usually contains a clear data block address (LBA) and the amount of data to be written, while an internal command or data processing request may not contain this information, or contain different parameters and formats.

[0068] Interface protocol identification: SSDs may communicate with external devices through different interfaces (such as SATA, PCIe, NVMe, etc.). The main control chip can identify which interface the request is received through and determine the source of the request based on the interface protocol. For example, some interface protocols may be specifically used for communication between the host and the SSD.

[0069] Internal state management: The SSD's main control chip may maintain an internal state table to track current active requests and their sources. When a new request arrives, the main control chip can query the state table to determine the source of the request.

[0070] More specifically, by determining whether the new write is from the host, the SSD can prioritize the host's write request to ensure timely storage of critical data and system response speed. In addition, based on the source of the request, the SSD can dynamically adjust its resource allocation, such as cache size, processing priority, etc., to optimize performance and efficiency. In addition, identifying and distinguishing requests from the host and other internal requests helps the SSD implement more sophisticated access control and security policies to prevent unauthorized access and data leakage. In addition, this implementation allows the SSD to be compatible with different types of external devices and interface protocols, improving the flexibility and versatility of the SSD.

[0071] S3, if the new write is a host write, write the write data to the data preparation area;

[0072] Specifically, in the SSD writing process, when it is determined that the newly written data does come from the host, the next step is to write the data to a specific area, called the "data preparation area". This step is a key link to ensure that the data can be stored in the SSD in an orderly and efficient manner. In specific implementation, the SSD's main control chip (SOC) will perform the following operations:

[0073] Data reception and parsing: First, the main control chip receives the write data from the host and parses it, which includes extracting the data content, the target address (that is, at which logical block address or LBA the data should be stored), and possible metadata (such as data verification information).

[0074] Data preparation area allocation: Then, the main control chip will find a suitable space in the data preparation area inside the SSD to store this data. The data preparation area is usually one or more reserved areas for temporarily storing data to be written. They may be located in the DRAM cache of the SSD or directly in a specific location on the NAND flash chip.

[0075] Data writing: Once a suitable space is found, the main control chip will write the parsed data into the data preparation area. This step may involve pre-processing operations such as data formatting, encryption, and verification to ensure data integrity and security.

[0076] Status update: After writing is completed, the main control chip will update the status table or metadata inside the SSD to record the data stored in the data preparation area and its related information (such as target address, data size, etc.).

[0077] More specifically, by temporarily storing data in the data preparation area, the SSD can buffer and queue write requests, thereby optimizing the write process and reducing performance degradation caused by frequent small data writes. In addition, the data preparation area acts as an intermediate buffer to ensure the orderliness and integrity of the data before it is written to the NAND flash memory, which helps to reduce the generation of data fragmentation and improve subsequent reading speed and efficiency. In addition, through reasonable design and management of the data preparation area, the SSD can more effectively utilize its internal resources (such as DRAM cache, NAND flash memory chips, etc.), thereby improving overall performance and durability. In addition, this implementation allows the SSD to dynamically adjust the size and location of the data preparation area according to the size and frequency of the host write request to adapt to different application scenarios and needs.

[0078] S4, determining whether the amount of data in the data preparation area reaches the concurrent write threshold; if the amount of data does not reach the concurrent write threshold, returning to execute step S3;

[0079] Specifically, in the SSD writing process, after the data is temporarily stored in the data preparation area, the next important step is to determine whether the amount of data in the area has reached a preset concurrent write threshold. This step is crucial for optimizing write performance, reducing write latency, and improving the overall efficiency of the SSD. In specific implementation, the SSD's main control chip (SOC) will perform the following operations:

[0080] Data volume monitoring: The main control chip will continuously monitor the amount of data in the data preparation area. This can be achieved by maintaining a counter or status table, which will record the amount of data stored in the data preparation area in real time.

[0081] Threshold setting: During the initialization or configuration process of the SSD, a concurrent write threshold is preset. This threshold is usually determined based on the SSD hardware configuration (such as the capacity and speed of the NAND flash chip), performance requirements, and application scenarios.

[0082] Threshold judgment: Whenever new data is written to the data preparation area, the main control chip will check whether the current data volume has reached the preset concurrent write threshold. This can be achieved by comparing the current data volume with the threshold.

[0083] Decision and execution: If the judgment result is "yes", that is, the data volume has reached the threshold of concurrent writing, then the main control chip will trigger a series of subsequent operations, such as organizing the data in the data preparation area into concurrent data blocks, scheduling the write operation of the NAND flash memory chip, etc. If the judgment result is "no", it will continue to wait for new data to be written or perform other processing.

[0084] More specifically, by determining whether the amount of data in the data preparation area reaches the threshold for concurrent writing, the SSD can more effectively utilize the write bandwidth of the NAND flash memory chip, reduce write latency, and improve write efficiency. In addition, this implementation allows the SSD to dynamically adjust the write strategy according to the amount of data in the data preparation area, thereby optimizing resource utilization and avoiding unnecessary write operations and data movement. In addition, through concurrent writing, the SSD can reduce conflicts and waiting times between different write operations, and improve the overall throughput and response speed of the system. In addition, a reasonable concurrent write strategy helps reduce the write pressure inside the SSD, reduce the risk of write errors and data corruption, and thus enhance the stability and reliability of the system.

[0085] S5, if the data volume reaches the threshold of concurrent writing, concurrent data is formed, the concurrent data prepared in the data preparation area is transferred to the data programming area, and the concurrent data is transferred to the specified Page of the WL specified by each DIE;

[0086] Specifically, when the accumulated data volume reaches the preset concurrent write threshold, the system identifies and confirms that concurrent data has been formed. The threshold can be flexibly set according to the hardware configuration, performance parameters and actual application scenarios of the SSD. The data preparation area is responsible for storing the data to be written. When the data volume reaches the threshold, the data in this area is marked as concurrent data and is ready for subsequent write operations. In addition, the concurrent data is transferred from the data preparation area to the data programming area, which is a buffer inside the SSD for temporarily storing data to be written to the NAND flash memory. In the data programming area, the data will undergo a series of processing and verification to ensure the accuracy and integrity of the data. The data in the data programming area is further distributed to each DIE inside the SSD. The distribution process is carried out according to the concurrent access strategy inside the SSD to ensure that the data can be efficiently written to each DIE. For each DIE, the system determines a specific WL and Page as the write target. The selection of WL and Page is based on the address mapping table inside the SSD (managed by the FTL) and the current write strategy and status. The data is written to the target WL and Page in the specified order and format.

[0087] More specifically, through concurrent writing, the parallel processing capabilities within the SSD can be fully utilized to improve the efficiency of data writing. Compared with the traditional serial writing method, concurrent writing can significantly reduce the writing time and improve the overall performance of the system. In addition, the concurrent writing strategy can flexibly adjust the resource allocation within the SSD according to the actual amount of data and writing requirements, which helps to avoid resource waste and bottlenecks and ensure that the SSD can operate in the best state. In addition, in the data programming area and writing process, the system will check and verify the data multiple times to ensure the accuracy and integrity of the data, which helps to reduce the risk of data errors and loss and improve the reliability and security of data.

[0088] S6, determine whether the Page data corresponding to the WL has been loaded; if the Page data corresponding to the WL has not been loaded, return to execute step S2;

[0089] Specifically, in the SSD writing process, especially when performing concurrent writing, determining whether the page data of the corresponding WL has been loaded is a key step. This step ensures that the data can be written to the NAND flash chip accurately and efficiently, avoiding the risk of data loss or writing errors. In specific implementation, the SSD's main control chip (SOC) will perform the following operations:

[0090] Loading status tracking: The main control chip maintains a loading status table or status register to track the loading status of each WL Page data. When data starts to be loaded into a WL Page, the main control chip updates the corresponding status mark in the status table, indicating that the data of the Page is being loaded.

[0091] Loading completion check: When it is necessary to determine whether the Page data of the corresponding WL has been loaded, the main control chip will traverse the status table or status register to check the loading status of all Pages under the WL. If the status of all Pages is marked as "loaded", the judgment result is "yes"; if the status of any Page is still "loading" or "not loaded", the judgment result is "no".

[0092] Timeout processing: In order to avoid deadlock or long waiting during data loading, the main control chip can also set a timeout period. If the Page data of the corresponding WL is not fully loaded within the timeout period, the main control chip will trigger the timeout processing mechanism, such as interrupting the current loading operation, reporting an error prompt, etc.

[0093] Subsequent operations: Based on the judgment result, the main control chip will perform the corresponding subsequent operations. If the judgment result is "yes", you can continue to write data; if the judgment result is "no", you may need to wait for the data to be loaded, or perform other error handling processes.

[0094] More specifically, by judging whether the Page data of the corresponding WL has been loaded, it can be ensured that the data is ready before being written to the NAND flash memory chip, avoiding the risk of data loss or write errors. In addition, this implementation makes the SSD write process more orderly and efficient, avoiding write delays or interruptions caused by incomplete data loading. In addition, by real-time monitoring and checking the data loading status, potential loading problems can be discovered and handled in a timely manner, thereby enhancing the stability and reliability of the SSD system. In addition, this technical feature enables the SSD to better support high-performance write operations, such as concurrent writes, large data block writes, etc., improving the overall performance and throughput of the system.

[0095] S7, if the Page data corresponding to the WL is loaded, the programming command of each DIE corresponding to the WL is initiated until the data programming is completed;

[0096] Specifically, in the SSD write process, when the page data of the corresponding WL is loaded, the next key step is to initiate the programming command of each DIE corresponding to the WL to actually write the data into the NAND flash chip. This step is the core link to ensure that the data can be accurately and permanently stored inside the SSD. In the specific implementation, the SSD main control chip (SOC) will perform the following operations:

[0097] Programming command preparation: The main control chip will prepare the corresponding programming command based on the current amount of data to be written, the target address (i.e., at which logical block address or LBA the data should be stored), and the specifications and configuration of the NAND flash chip. The programming command usually includes the identification of the target DIE, the number of the target WL, the page address to be written, and the actual data content.

[0098] Command issuance and status monitoring: When it is confirmed that the Page data of the corresponding WL has been loaded, the main control chip will issue the programming command to the target DIE through the internal bus or interface. At the same time, the main control chip will start the status monitoring mechanism to track the execution status of the programming command in real time, including the progress of data writing and whether errors occur.

[0099] Programming completion confirmation: During the execution of the programming command, the main control chip will continuously check the response status of the NAND flash chip to confirm whether the data has been successfully written to the Page of the target WL. If an error or abnormality occurs during the data programming process, the main control chip will immediately trigger the error handling mechanism, such as retrying writing, error prompts, etc. If the data programming is successfully completed, the main control chip will update the internal status table or metadata to record the storage location and status of the data.

[0100] Subsequent operations: After data programming is completed, the main control chip will perform corresponding subsequent operations, such as clearing the data preparation area and data programming area, releasing related resources, etc. At the same time, the main control chip will also decide whether to continue to receive new write requests or enter low power mode based on the current write demand and SSD performance status.

[0101] More specifically, by ensuring that the Page data of the corresponding WL is loaded before initiating the programming command, the risk of errors or anomalies in the data writing process can be greatly reduced, and the writing accuracy can be improved. In addition, this implementation enables the SSD to more efficiently utilize the write bandwidth and parallel processing capabilities of the NAND flash memory chip, thereby optimizing write performance and reducing write latency. In addition, by real-time monitoring of the execution status of programming commands and timely handling of errors or anomalies, the stability and reliability of the SSD system can be enhanced, avoiding the risk of data loss or damage. In addition, this technical feature enables the SSD to better support high-performance applications, such as real-time databases, big data analysis, etc., which usually require large amounts of data to be written quickly and accurately.

[0102] In one embodiment, before the step of obtaining a new write operation request to obtain write data, the step further includes: initializing a write buffer to obtain a data preparation area and a data programming area.

[0103] Specifically, in the SSD write process, before obtaining and processing a new write operation request, there is a key preparatory step of initializing the write buffer. The purpose of this step is to prepare the necessary storage space for the upcoming write operation and ensure that the data writing process can proceed smoothly. Specifically, initializing the write buffer includes dividing two key areas: the data preparation area and the data programming area.

[0104] Write buffer initialization: When the SSD system starts or receives the initialization signal for the write operation, the main control chip (SOC) will first perform the initialization operation of the write buffer. The initialization process includes allocating the necessary physical storage space for the write buffer and setting the corresponding access rights and control parameters.

[0105] Data preparation area division: In the write buffer, the main control chip will divide a special data preparation area. This area is used to temporarily store the data to be written received from the host until the data is ready and a programming command can be issued for writing. The size of the data preparation area can be flexibly configured according to the capacity, performance requirements and actual application scenarios of the SSD.

[0106] Data programming area division: In addition to the data preparation area, the main control chip will also divide a data programming area in the write buffer. This area is used to further organize and process the data after the data preparation is completed, so that the data can be programmed to the correct location according to the specifications and writing requirements of the NAND flash chip. The data programming area can also be customized according to the characteristics and requirements of the SSD to ensure the efficiency and accuracy of the writing process.

[0107] Area status monitoring: After initialization is completed, the main control chip will continue to monitor the status of the data preparation area and the data programming area, including data loading progress, storage space usage, etc. This helps to ensure that when a new write operation request is received, both areas are in an available state, so that the write request can be processed and responded to in a timely manner.

[0108] More specifically, by initializing the write buffer and dividing it into a data preparation area and a data programming area, the SSD can manage storage space more effectively, reduce waiting time and data movement overhead during the write process, and thus improve write efficiency. In addition, this implementation enables the SSD to utilize internal resources more flexibly, and dynamically adjust the size and configuration of the data preparation area and the data programming area according to actual write requirements and performance goals, thereby optimizing resource utilization. In addition, by initializing and continuously monitoring the status of the write buffer, the SSD can promptly detect and handle potential write problems, such as insufficient storage space, data loading errors, etc., thereby enhancing the stability and reliability of the system. In addition, initializing the write buffer and preparing the necessary data preparation area and data programming area for write operations enables the SSD to better support high-performance write operations, such as concurrent writes, large data block writes, etc.

[0109] In one embodiment, before the step of determining whether all Page data corresponding to the WL has been loaded, the step further includes: releasing the data in the data programming area to obtain an empty data programming area.

[0110] Specifically, during the operation of the storage device, especially before data is written, in order to ensure that the data can be accurately stored in the specified storage unit, it is usually necessary to check and prepare the data programming area (i.e., the area for actually storing data). According to an embodiment of the present invention, this preparation process includes the following steps:

[0111] Identify the Page status of the current WL: First, the system uses internal control logic to identify whether the WL and its corresponding Page that need to be operated are in an idle or writable state. This step is a necessary check before data writing to avoid data overwriting or writing conflicts.

[0112] Release data in the data programming area: Once it is confirmed that the page of the target WL is writable, the system will perform a data release operation. This step is achieved by clearing or erasing the original data in the data programming area to ensure that the data programming area is in an "empty" state. The release operation may include logical erasure (only marking the data as invalid) or physical erasure (actually removing the data from the storage medium), depending on the type of memory (such as NANDFlash, DRAM, etc.) and design requirements.

[0113] Verify the data programming area status: After the release operation is completed, the system will check again whether the data programming area has been cleared to ensure that there is no residual data affecting subsequent writing. This step can be achieved through read verification (reading the data programming area and checking whether it is all 0 or a specific mark value) or other status detection mechanisms.

[0114] Prepare the data programming area: After confirming that the data programming area has been cleared and prepared, the system can load the data to be written into the area and prepare for subsequent programming (writing) operations.

[0115] More specifically, by pre-releasing and preparing the data programming area, write failures and retries caused by data conflicts or overwriting during the data writing process are avoided, thereby improving the overall data writing efficiency. In addition, releasing the data programming area ensures that new data will not be interfered with by old data, which helps to maintain the integrity and accuracy of the stored data. In addition, through a clear data release and preparation process, the system can manage storage resources more effectively, including reducing unnecessary waste of storage space and optimizing storage performance. In addition, in complex storage systems, this technical feature also helps to achieve parallel processing between different WLs or Pages, further improving the overall throughput and response speed of the storage device.

[0116] In one embodiment, after the step of determining whether the new write is a host write, the process further includes: S8, if the new write is not a host write, reading the write data and allocating it to a write buffer.

[0117] Specifically, if the judgment result shows that the new write is not initiated by the host, the system will instead execute a specific processing flow for non-host writes. This step is the key to the technical features of the present invention. Next, the system will read the data to be written, which may come from the internal cache, other storage units, or a processing module within the system. Once the data is read, the system will allocate it to one or more write buffers. The write buffer is a memory area specifically used to temporarily store data to be written. It allows the system to process or optimize the data before preparing to write it to the final storage medium. After the data is allocated to the write buffer, the system may sort, compress, encrypt, or perform other forms of pre-processing as needed to improve write efficiency or data security.

[0118] More specifically, by distinguishing between host writes and non-host writes and taking corresponding processing steps, the system can manage data write operations more effectively and reduce unnecessary processing steps and resource waste. In addition, reading and allocating data written by non-hosts to the write buffer allows the system to pre-process and optimize the data before writing it to the final storage medium, thereby improving write efficiency. In addition, this technical feature enables the storage system to handle write requests from different sources, enhancing the flexibility and scalability of the system. In addition, pre-processing (such as encryption) of data in the write buffer can enhance data security, especially when processing sensitive or critical data. In addition, by temporarily storing data written by non-hosts in the write buffer, the system can more efficiently schedule and process write requests from the host, thereby reducing the overall load of the system.

[0119] In one embodiment, after the step of reading the write data and allocating it to the write buffer, it also includes: determining whether the amount of data in the write buffer reaches the threshold of concurrent writing; if the amount of data in the write buffer reaches the threshold of concurrent writing, jumping to execute step S5; if the amount of data in the write buffer does not reach the threshold of concurrent writing, returning to execute step S8.

[0120] See also Figure 4 The schematic diagram of the application scenario of the method for optimizing the SSD write buffer shown in the figure is illustrated with 16 DIEs and QLC NAND (each WL has 4 Pages) for ease of explanation:

[0121] Divide the write buffer into two groups according to the Page concurrency, each group size is 256KB (16*16KB);

[0122] Area 1, data preparation area, is used to receive data written by the host or read data from NAND;

[0123] Area 2, data programming area, is used to write the pages of the specified WL of each DIE in parallel;

[0124] Host write scheduling module: writes the data sent by the host write command into the buffer of the current area 1 as required;

[0125] SSD write scheduling module: schedules data preparation and NAND data writing;

[0126] NAND read scheduling module: reads the source data to be moved as required and writes it into the buffer of current area 1;

[0127] NAND write scheduling module: transfers data to the pages of the WL specified by each DIE as required.

[0128] Among them, the SSD write scheduling module organizes the preparation of the data to be written, and after the data with full Page concurrency is gathered, the data transmission of Page 0 of WL is initiated; after the data transmission of Page 0 is completed, the corresponding buffer is released, and the data transmission of Page 1 is initiated with the new data to be written, and the next set of data to be written is prepared at the same time; and so on, until the 4 Page data of WL are all transmitted, the programming command is issued at this time; and at this time, the buffers used are all in an idle state, and they can all enter area 1 to prepare the data to be programmed later. In this process, only 2 groups of buffers with Page concurrency are used for data preparation and write ping-pong operations. Under the premise of meeting the concurrent performance requirements, the memory demand is reduced to 1 / 4 of that of traditional SSDs.

[0129] The present invention can ensure that key data is processed in a timely manner by identifying and giving priority to host write operations, reducing data processing delays and thus improving overall write efficiency. In addition, the data is first written to the data preparation area, and when the amount of data accumulates to the threshold of concurrent write, concurrent data is formed for subsequent processing. This mechanism effectively utilizes the concurrent processing capability of the storage device, avoids idleness or over-allocation of resources, and achieves optimal resource configuration. In addition, by switching NAND operations at the Page level, only the buffer size required for the concurrency of the Page level can be used without sacrificing write performance, significantly reducing dependence on write buffer resources. and needs, which is crucial to improving the cost-effectiveness and scalability of SSDs; in addition, the concurrent data in the data preparation area is transferred to the data programming area and accurately transmitted to the specified Page of each DIE specified WL. This process fully utilizes the concurrent operation characteristics of the SSD internal hardware (such as DIE, WL), significantly enhances the concurrent processing capability of data writing, and further shortens the writing time; in addition, after confirming that all the Page data of the corresponding WL has been loaded, the programming command is initiated to ensure the integrity and consistency of the data during the programming process, reduce programming errors caused by incomplete data loading, and improve the accuracy and reliability of SSD data writing.

[0130] See also Figure 5 As shown, the present invention also discloses a device for optimizing SSD write buffer, comprising: an acquisition unit 10, a first judgment unit 20, a writing unit 30, a second judgment unit 40, a transfer unit 50, a third judgment unit 60 and a programming unit 70;

[0131] The acquisition unit 10 is used to acquire a new write operation request to obtain write data;

[0132] The first determination unit 20 is used to determine whether the new write is a host write;

[0133] The writing unit 30 is used to write the write data into the data preparation area if the new write is a host write;

[0134] The second judgment unit 40 is used to judge whether the amount of data in the data preparation area reaches a threshold for concurrent writing;

[0135] The formation transfer transmission unit 50 is used to form concurrent data if the data volume reaches the concurrent write threshold, transfer the concurrent data prepared in the data preparation area to the data programming area, and transmit the concurrent data to the specified Page of each DIE specified WL;

[0136] The third judgment unit 60 is used to judge whether the Page data corresponding to the WL has been loaded;

[0137] The programming processing unit 70 is used to initiate programming commands for the WLs corresponding to the DIEs if the Page data corresponding to the WLs are loaded, until the data programming is completed;

[0138] Among them, DIE is a module that can be operated independently and concurrently; WL is a module that can be programmed and written independently; Page is a reading module.

[0139] In one embodiment, the device further comprises: an initialization unit, configured to initialize the write buffer area to obtain a data preparation area and a data programming area.

[0140] In one embodiment, the device further comprises: a releasing unit, configured to release the data in the data programming area to obtain an empty data programming area.

[0141] In one embodiment, the apparatus further comprises: a read allocation unit 80, configured to read the write data and allocate it to the write buffer if the new write is not a host write.

[0142] In one embodiment, the device also includes: a fourth judgment unit, used to judge whether the amount of data in the write buffer reaches the threshold of concurrent writing; if the amount of data in the write buffer reaches the threshold of concurrent writing, then jump execution to form concurrent data, transfer the concurrent data prepared in the data preparation area to the data programming area, and transfer the concurrent data to the specified Page of each DIE specified WL; if the amount of data in the write buffer does not reach the threshold of concurrent writing, then execute reading of write data and allocate it to the write buffer.

[0143] It should be noted that technicians in the relevant field can clearly understand that the specific implementation process of the above-mentioned device and each unit for optimizing the SSD write buffer can refer to the corresponding description in the aforementioned method embodiment, and for the convenience and brevity of description, it will not be repeated here.

[0144] The above-mentioned device for optimizing the SSD write buffer can be implemented in the form of a computer program. The computer program can be used in the following manner: Figure 6 Runs on the computer device shown.

[0145] See also Figure 6 , Figure 6 is a schematic block diagram of a computer device provided in an embodiment of the present application; the computer device 500 may be a terminal or a server, wherein the terminal may be an electronic device with communication functions such as a smart phone, a tablet computer, a laptop computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of multiple servers.

[0146] See also Figure 6 The computer device 500 includes a processor 502 , a memory and a network interface 505 connected via a system bus 501 , wherein the memory may include a non-volatile storage medium 503 and an internal memory 504 .

[0147] The non-volatile storage medium 503 can store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions, and when the program instructions are executed, the processor 502 can execute a method for optimizing an SSD write buffer.

[0148] The processor 502 is used to provide computing and control capabilities to support the operation of the entire computer device 500 .

[0149] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a method for optimizing the SSD write buffer.

[0150] The network interface 505 is used to communicate with other devices over the network. Figure 6 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 500 to which the solution of the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0151] The processor 502 is used to run the computer program 5032 stored in the memory to implement the following steps:

[0152] Get a new write operation request to get the write data; determine whether the new write is a host write; if the new write is a host write, write the write data to the data preparation area; determine whether the amount of data in the data preparation area reaches the threshold of concurrent write; if the amount of data reaches the threshold of concurrent write, form concurrent data, transfer the prepared concurrent data in the data preparation area to the data programming area, and transfer the concurrent data to the specified Page of the WL specified by each DIE; determine whether the Page data of the corresponding WL are all loaded; if the Page data of the corresponding WL are all loaded, initiate the programming command of each DIE corresponding to the WL until the data programming is completed; among them, DIE is a module that can be independently operated concurrently; WL is a module that can be independently programmed and written; Page is a reading module.

[0153] It should be understood that in the embodiment of the present application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0154] It can be understood by those skilled in the art that all or part of the processes in the method for implementing the above embodiment can be completed by instructing the relevant hardware through a computer program. The computer program includes program instructions, and the computer program can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiment of the above method.

[0155] Therefore, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the above-mentioned method for optimizing the SSD write buffer can be implemented. The storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the above-mentioned method can be implemented. The program instructions include the following steps:

[0156] Get a new write operation request to get the write data; determine whether the new write is a host write; if the new write is a host write, write the write data to the data preparation area; determine whether the amount of data in the data preparation area reaches the threshold of concurrent write; if the amount of data reaches the threshold of concurrent write, form concurrent data, transfer the prepared concurrent data in the data preparation area to the data programming area, and transfer the concurrent data to the specified Page of the WL specified by each DIE; determine whether the Page data of the corresponding WL are all loaded; if the Page data of the corresponding WL are all loaded, initiate the programming command of each DIE corresponding to the WL until the data programming is completed; among them, DIE is a module that can be independently operated concurrently; WL is a module that can be independently programmed and written; Page is a reading module.

[0157] The storage medium may be a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk, etc., which are computer-readable storage media that can store program codes.

[0158] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0159] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of each unit is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or skipped.

[0160] The steps in the method of the embodiment of the present invention can be adjusted in order, combined and deleted according to actual needs. The units in the device of the embodiment of the present invention can be combined, divided and deleted according to actual needs. In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0161] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, terminal, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention.

[0162] The above embodiments are preferred implementation schemes of the present invention. In addition, the present invention may also be implemented in other ways. Any obvious replacement without departing from the concept of the present technical solution is within the protection scope of the present invention.

Claims

1. A method for optimizing SSD write buffer, characterized in that: The following steps are involved: Get the newly written operation request to obtain the written data; Determine whether the new write is a host write; If the new write is a host write, the write data is written to the data preparation area; Determine whether the amount of data in the data preparation area reaches the concurrent write threshold; If the amount of data reaches the threshold of concurrent writing, concurrent data is formed, the concurrent data prepared in the data preparation area is transferred to the data programming area, and the concurrent data is transferred to the specified Page of the WL specified by each DIE; Determine whether the Page data of the corresponding WL has been loaded; If the Page data of the corresponding WL is loaded, the programming command of each DIE corresponding to the WL is initiated until the data programming is completed; Among them, DIE is a module that can be operated independently and concurrently; WL is a module that can be programmed and written independently; Page is a reading module.

2. The method for optimizing SSD write buffer according to claim 1, characterized in that: Before the step of obtaining a new write operation request to obtain write data, the method further includes: initializing a write buffer to obtain a data preparation area and a data programming area.

3. The method for optimizing SSD write buffer according to claim 1, characterized in that: Before the step of judging whether all the Page data corresponding to the WL have been loaded, the method further includes: releasing the data in the data programming area to obtain an empty data programming area.

4. The method for optimizing SSD write buffer according to claim 1, characterized in that: After the step of determining whether the new write is a host write, the method further includes: if the new write is not a host write, reading the write data and allocating it to the write buffer.

5. A device for optimizing SSD write buffer, characterized in that: include: An acquisition unit, a first judgment unit, a writing unit, a second judgment unit, a formation transfer unit, a third judgment unit and a programming unit; The acquisition unit is used to acquire a new write operation request to obtain write data; The first determination unit is used to determine whether the new write is a host write; The writing unit is used to write the write data into the data preparation area if the new write is a host write; The second judgment unit is used to judge whether the amount of data in the data preparation area reaches a threshold value for concurrent writing; The formation transfer transmission unit is used to form concurrent data if the data volume reaches the concurrent write threshold, transfer the concurrent data prepared in the data preparation area to the data programming area, and transmit the concurrent data to the specified Page of the WL specified by each DIE; The third judgment unit is used to judge whether the Page data corresponding to the WL has been loaded; The programming processing unit is used to initiate programming commands for the WLs corresponding to the DIEs if the Page data corresponding to the WLs are all loaded, until the data programming is completed; Among them, DIE is a module that can be operated independently and concurrently; WL is a module that can be programmed and written independently; Page is a reading module.

6. The device for optimizing SSD write buffer according to claim 5, characterized in that: The device further comprises: an initialization unit, which is used for initializing the write buffer area to obtain a data preparation area and a data programming area.

7. The device for optimizing SSD write buffer according to claim 5, characterized in that: The device further comprises: a releasing unit, which is used for releasing the data in the data programming area to obtain an empty data programming area.

8. The device for optimizing SSD write buffer according to claim 5, characterized in that: The device further comprises: a read allocation unit, configured to read the write data and allocate the read data to the write buffer if the new write is not a host write.

9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the method for optimizing the SSD write buffer according to any one of claims 1 to 4 when executing the computer program.

10. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method for optimizing an SSD write buffer according to any one of claims 1 to 4 is implemented.

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