In-memory multiply-accumulate computation apparatus and method based on sram

Abstract

The application discloses an in-memory multiplication and accumulation computing device and method based on SRAM, and the device comprises a first SRAM bit cell, a second SRAM bit cell, a first transmission gate circuit and a second transmission gate circuit, wherein the first transmission gate circuit comprises a first NMOS tube, a first PMOS tube and a first input port; the second transmission gate circuit comprises a second NMOS tube, a second PMOS tube and a second input port; a third MOS tube and a fourth MOS tube are arranged between the BLL bit line and the first and second transmission gate circuits; a fifth MOS tube and a sixth MOS tube are arranged between the BLR bit line and the first and second transmission gate circuits; a NAND gate is arranged between the BLR bit line and the carry output port, or the input end of the NAND gate is connected with the output end of the NAND gate and the BLL bit line. By adopting the technical scheme, the multiplication and accumulation results of two groups of inputs and weights can be directly outputted, the first-stage half-adder circuit in the multiplication unit and the addition tree is not needed, the use of transistors is saved, the area and power consumption of the addition tree are reduced, and the energy efficiency of the overall CIM macro is improved.

Description

Technical Field

[0001] The present invention relates to the field of digital storage and calculation technology, and in particular to an SRAM-based in-memory multiplication and accumulation calculation device and method. Background Art

[0002] Traditional computer architecture is based on the von Neumann architecture, which separates computation and storage. However, with the rapid development of artificial intelligence (AI), neural networks have gained widespread application in many fields. Neural networks require massive computational complexity, and traditional von Neumann architectures require frequent data transfers between memory and processors. This results in the majority of energy being consumed in data transfer, leaving only a minimal portion of the energy actually used for computation, severely impacting overall energy efficiency. Furthermore, the significant disparity in the development speed of processors and memory has created a "memory wall" and "power wall" effect, known as the von Neumann bottleneck.

[0003] Against this backdrop, the integrated storage and computing architecture came into being. This architecture integrates storage units and computing units, effectively reducing data transmission, significantly improving energy efficiency and data throughput, and thus breaking through the von Neumann bottleneck. The integrated storage and computing architecture can be further divided into analog storage and computing and digital storage and computing. In the analog storage and computing architecture, information is stored in the form of continuous voltage or current and is directly used to perform computing tasks. This architecture is susceptible to factors such as PVT (process, temperature, voltage), and accuracy is relatively difficult to guarantee. The digital storage and computing architecture is based on traditional digital logic circuit design and uses digital signals (i.e., discrete states of 0 and 1) for calculations. It is not easily affected by external interference and has higher accuracy.

[0004] However, existing digital computing architectures also have their own challenges. They require adder trees to perform accumulation operations. The power consumption of the adder tree is a major component of the power consumption of the CIM (Computing in Memory) macro. A large number of accumulation operations often results in high area and power consumption, which in turn reduces the energy efficiency of the CIM macro. In an adder tree circuit, the area and power consumption of the first-stage adders typically dominate the entire adder tree circuit. This is because the first-stage adders are the largest in number and handle the initial parallel accumulation of all input data. The area and power consumption of the first-stage adders typically account for over 50% of the entire adder tree circuit, or even more. The first stage processes the largest number of inputs, resulting in a peak number of adder units at this level. As the number of layers increases, the number of required adders decreases. In terms of power consumption, the first-stage adders typically account for 50-60% of the total adder tree power consumption. This is because the initial parallel addition operation requires a large number of adder units to be activated simultaneously, resulting in high power consumption. Although power consumption decreases gradually with the increase of the number of layers and the number of required adders decreases, the energy efficiency of the CIM macro is difficult to effectively reduce due to the problems existing in the first-layer adders.

[0005] Furthermore, traditional SRAM in-memory computing units typically perform AND or XOR operations on external inputs and weights stored in the SRAM unit to achieve multiplication, resulting in single-bit data. Most neural networks utilize matrix operations during training and inference, which generate numerous multiplication-accumulation calculations. Multiplying multiple inputs by multiple weights produces multiple single-bit multiplication results. Multiple multiplication results with the same weight need to be accumulated, and these accumulations are typically performed directly using adder tree circuits. Summary of the Invention

[0006] Purpose of the invention: The present invention provides an SRAM-based in-memory multiplication and accumulation computing device and method, aiming to solve the technical problems in the prior art of the high area and power consumption of the adder tree in the digital storage and computing architecture, and the need for an independent multiplication unit to perform multiplication calculations.

[0007] Technical solution: The present invention provides an in-memory multiplication and accumulation computing device based on SRAM, comprising: a BLL bit line, a BLR bit line, a first SRAM bit cell, a second SRAM bit cell, a first transmission gate circuit, a second transmission gate circuit, a carry output port, and a sum output port, wherein: the first transmission gate circuit comprises a first NMOS transistor, a first PMOS transistor, and a first input port, the source of the first NMOS transistor is connected to the source of the first PMOS transistor, and the connection point of the two sources serves as the first input port, and the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor. The gate of the first NMOS transistor is connected to the Q node of the first SRAM bit unit, and the gate of the first PMOS transistor is connected to the QB node of the first SRAM bit unit; the second transmission gate circuit includes a second NMOS transistor, a second PMOS transistor and a second input port, the source of the second NMOS transistor is connected to the source of the second PMOS transistor, and the connection point of the two sources serves as the second input port, the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the second NMOS transistor is connected to the Q node of the second SRAM bit unit, and the gate of the second PMOS transistor is connected to the Q node of the second SRAM bit unit. A QB node of the unit; a third MOS transistor is provided between the BLL bit line and the first transmission gate circuit, the gate of the third MOS transistor is connected to the drain of the first NMOS transistor, and the other two electrodes of the third MOS transistor are connected to the BLL bit line and the ground respectively; a fourth MOS transistor is provided between the BLL bit line and the second transmission gate circuit, the gate of the fourth MOS transistor is connected to the drain of the second NMOS transistor, and the other two electrodes of the fourth MOS transistor are connected to the BLL bit line and the ground respectively; a fifth MOS transistor is provided between the BLR bit line and the first transmission gate circuit, and the BLR bit line is connected to the second transmission gate circuit A sixth MOS transistor is provided between the two paths; the gate of the fifth MOS transistor is connected to the drain of the first PMOS transistor, and the other two electrodes of the fifth MOS transistor are respectively connected to the BLR bit line and the sixth MOS transistor; the gate of the sixth MOS transistor is connected to the drain of the second PMOS transistor, and the other two electrodes of the sixth MOS transistor are respectively connected to the fifth MOS transistor and the ground; a NOT gate is provided between the BLR bit line and the carry output port, and the output end of the NOT gate is connected to the carry output port; a NOR gate is provided between the output end of the NOT gate and the sum output port, and the input end of the NOR gate is respectively connected to the output end of the NOT gate and the BLL bit line.

[0008] Specifically, both the first SRAM bit cell and the second SRAM bit cell are 6T SRAM bit cells.

[0009] Specifically, the 6T SRAM bit cell includes a first inverter and a second inverter, wherein the Q node is the output of the first inverter, and the QB node is the output of the second inverter; the voltage levels of the Q node and the QB node are opposite.

[0010] Specifically, a precharge circuit is also included, which includes a MOS tube arranged between the BLL bit line and the BLR bit line. The gate of the MOS tube is used to receive a precharge signal, and the other two electrodes of the MOS tube are respectively connected to the BLL bit line and the BLR bit line.

[0011] Specifically, a pre-charging circuit is further included, which includes a first pre-charging MOS transistor corresponding to the BLL bit line and a second pre-charging MOS transistor corresponding to the BLR bit line, wherein the gate of the first pre-charging MOS transistor is used to receive a pre-charging signal, and the other two electrodes of the first pre-charging MOS transistor are respectively connected to the BLL bit line and the power supply; the gate of the second pre-charging MOS transistor is used to receive a pre-charging signal, and the other two electrodes of the second pre-charging MOS transistor are respectively connected to the BLR bit line and the power supply.

[0012] Specifically, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are all NMOS transistors. The source of the third MOS transistor is grounded, and the drain of the third MOS transistor is connected to the BLL bit line; the source of the fourth MOS transistor is grounded, and the drain of the fourth MOS transistor is connected to the BLL bit line; the drain of the fifth MOS transistor is connected to the BLR bit line; the source of the sixth MOS transistor is grounded, and the drain of the sixth MOS transistor is connected to the source of the fifth MOS transistor.

[0013] The present invention also provides an SRAM-based in-memory multiplication and accumulation calculation method, which uses the SRAM-based in-memory multiplication and accumulation calculation device provided by the present invention, including: charging the BLL bit line and the BLR bit line to a high level; inputting a signal combination including a first input signal and a second input signal, wherein the first input port of the first transmission gate circuit receives the first input signal, and the second input port of the second transmission gate circuit receives the second input signal; determining the weight corresponding to the signal combination according to the written weight data, the first SRAM bit unit controls the level of the Q node based on the weight, and the second SRAM bit unit controls the level of the Q node based on the weight; obtaining the carry signal output by the carry output port and the sum signal output by the sum output port.

[0014] Specifically, the weight corresponding to the signal combination is determined according to the written weight data, which includes: performing a write operation on the SRAM array in the storage mode, and writing the weight data into the corresponding SRAM array.

[0015] Specifically, when the Q node of the first SRAM bit cell is at a high level and the first input signal is at a high level, the third MOS transistor is turned on, and the BLL bit line is discharged to a low level to the ground through the third MOS transistor; when the Q node of the second SRAM bit cell is at a high level and the second input signal is at a high level, the fourth MOS transistor is turned on, and the BLL bit line is discharged to a low level to the ground through the fourth MOS transistor.

[0016] Specifically, when the Q node of the first SRAM bit cell is at a high level, the Q node of the second SRAM bit cell is at a high level, and the first input signal and the second input signal are both at a high level, the BLL bit line discharges to a low level to the ground, and the BLR bit line discharges to a low level to the ground through the fifth MOS transistor and the sixth MOS transistor.

[0017] Beneficial effects: Compared with the existing technology, the present invention has the following significant advantages: it can directly output the multiplication and accumulation results of two sets of inputs and weights, without the need for a multiplication unit and the first-stage half-adder circuit in the addition tree, which greatly saves the use of transistors, helps to reduce the area and power consumption of the addition tree, and improves the energy efficiency of the overall CIM macro. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the structure of the SRAM-based in-memory multiplication and accumulation computing device provided by the present invention. DETAILED DESCRIPTION

[0019] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0020] See Figure 1 , which is a structural diagram of the SRAM-based in-memory multiplication and accumulation computing device provided by the present invention.

[0021] The present invention provides an in-memory multiplication and accumulation computing device based on SRAM, comprising: a BLL bit line, a BLR bit line, a first SRAM bit unit, a second SRAM bit unit, a first transmission gate circuit, a second transmission gate circuit, a carry output port (Cout) and a sum output port (Sum), wherein: the first transmission gate circuit comprises a first NMOS transistor (N1), a first PMOS transistor (P1) and a first input port (IN1), the source of the first NMOS transistor is connected to the source of the first PMOS transistor, the connection point of the two sources serves as the first input port, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor (serving as a transmission port), and the sum output port (Sum) is connected to the drain of the first PMOS transistor. The gate of the first NMOS transistor is connected to the Q node (Q1) of the first SRAM bit unit, and the gate of the first PMOS transistor is connected to the QB node (Q1B) of the first SRAM bit unit; the second transmission gate circuit includes a second NMOS transistor (N2), a second PMOS transistor (P2) and a second input port (IN2), the source of the second NMOS transistor is connected to the source of the second PMOS transistor, and the connection point of the two sources serves as the second input port, the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor (serving as a transmission gate), and the gate of the second NMOS transistor is connected to the Q node (Q 2), the gate of the second PMOS transistor is connected to the QB node (Q2B) of the second SRAM bit unit; a third MOS transistor (N3) is provided between the BLL bit line and the first transmission gate circuit, the gate of the third MOS transistor is connected to the drain of the first NMOS transistor, and the other two electrodes of the third MOS transistor are respectively connected to the BLL bit line and the ground; a fourth MOS transistor (N4) is provided between the BLL bit line and the second transmission gate circuit, the gate of the fourth MOS transistor is connected to the drain of the second NMOS transistor, and the other two electrodes of the fourth MOS transistor are respectively connected to the BLL bit line and the ground; a fifth MOS transistor ( N5), a sixth MOS transistor (N6) is provided between the BLR bit line and the second transmission gate circuit; the gate of the fifth MOS transistor is connected to the drain of the first PMOS transistor, and the other two electrodes of the fifth MOS transistor are respectively connected to the BLR bit line and the sixth MOS transistor; the gate of the sixth MOS transistor is connected to the drain of the second PMOS transistor, and the other two electrodes of the sixth MOS transistor are respectively connected to the fifth MOS transistor and the ground; a NOT gate is provided between the BLR bit line and the carry output port, and the output end of the NOT gate is connected to the carry output port; a NOR gate is provided between the output end of the NOT gate and the sum output port, and the input end of the NOR gate is respectively connected to the output end of the NOT gate and the BLL bit line.

[0022] In the embodiment of the present invention, both the first SRAM bit cell and the second SRAM bit cell are 6T SRAM bit cells.

[0023] In an embodiment of the present invention, the 6T SRAM bit cell includes a first inverter, a second inverter, and two transfer transistors (MOS transistors), wherein the Q node is the output of the first inverter and is connected to the input of the second inverter (the gate connection point of the two MOS transistors) and the transfer transistor (the MOS transistor close to the BL bit line); the QB node is the output of the second inverter and is connected to the input of the first inverter (the gate connection point of the two MOS transistors) and the transfer transistor (the MOS transistor close to the BLB bit line); the voltage levels of the Q node and the QB node are opposite.

[0024] In practice, 6T SRAM (Static Random Access Memory) is a commonly used static random access memory (SRAM) with a storage cell consisting of six transistors. Due to its high speed, low power consumption, and high reliability, 6T SRAM is widely used in caches, register files, and other scenarios requiring fast data access. A 6T SRAM storage cell consists of two cross-coupled inverters, forming a bistable trigger. Each inverter consists of two transistors (MOS tubes), plus two transfer transistors (MOS tubes), so the entire 6TSRAM storage cell consists of six transistors.

[0025] In a specific implementation, the gates of the two MOS transistors serving as transfer transistors in a 6T SRAM are connected to the same word line (WL). When the word line is activated, the transfer transistors are turned on, and data signals can be read or written from the bit line (BL) and the bit line bar (BLB).

[0026] like Figure 1 The detailed structure of the 6T SRAM shown in Figure 1 shows that in a 6T SRAM, the Q and QB nodes are two important nodes, representing the two complementary logic states stored in the memory cell. The states of these two nodes determine whether the data stored in the memory cell is a "0" (low level) or a "1" (high level).

[0027] In an embodiment of the present invention, a pre-charging circuit is further included, which includes a first pre-charging MOS transistor corresponding to the BLL bit line and a second pre-charging MOS transistor corresponding to the BLR bit line, wherein the gate of the first pre-charging MOS transistor is used to receive a pre-charging signal (Pre-Charge), and the other two electrodes of the first pre-charging MOS transistor are respectively connected to the BLL bit line and the power supply (VDD); the gate of the second pre-charging MOS transistor is used to receive the pre-charging signal (Pre-Charge), and the other two electrodes of the second pre-charging MOS transistor are respectively connected to the BLR bit line and the power supply (VDD).

[0028] In a specific implementation, the four MOS transistors N3 to N6 can be either NMOS transistors or PMOS transistors, and their connection method meets the requirements of the application scenario of the present invention, that is, they can ensure that the BLL bit line and the BLR bit line are connected to the ground and discharge toward the ground. In an embodiment of the present invention, a specific implementation is provided in which the four MOS transistors N3 to N6 are NMOS transistors.

[0029] In the embodiment of the present invention, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are all NMOS transistors. The source of the third MOS transistor is grounded, and the drain of the third MOS transistor is connected to the BLL bit line. The source of the fourth MOS transistor is grounded, and the drain of the fourth MOS transistor is connected to the BLL bit line. The drain of the fifth MOS transistor is connected to the BLR bit line. The source of the sixth MOS transistor is grounded, and the drain of the sixth MOS transistor is connected to the source of the fifth MOS transistor.

[0030] In an embodiment of the present invention, the pre-charge circuit further includes a MOS transistor arranged between the BLL bit line and the BLR bit line, the gate of the MOS transistor is used to receive a pre-charge signal (Pre-Charge), and the other two electrodes of the MOS transistor are respectively connected to the BLL bit line and the BLR bit line.

[0031] In a specific implementation, a MOS transistor is provided between the BLL bit line and the BLR bit line to balance the voltage and ensure that the initial voltages on the two bit lines are consistent.

[0032] In an embodiment of the present invention, an SRAM-based in-memory multiplication and accumulation calculation method is provided, and an SRAM-based in-memory multiplication and accumulation calculation device provided by the present invention is applied.

[0033] In the SRAM-based in-memory multiplication and accumulation calculation method provided by the present invention, a write operation can be first performed on the SRAM array (the first SRAM bit unit and the second SRAM bit unit) in the storage mode to write the weight data into the corresponding SRAM array.

[0034] In the embodiment of the present invention, the Pre-Charge signal of the pre-charging circuit controls the corresponding first pre-charging MOS transistor and the second pre-charging MOS transistor, so that the bit lines BLL and BLR are pre-charged to the high level VDD.

[0035] In the embodiment of the present invention, the input includes a signal combination of a first input signal and a second input signal, wherein a first input port (IN1) of a first transmission gate circuit receives the first input signal, and a second input port (IN2) of a second transmission gate circuit receives the second input signal. In the description, IN1 refers to the first input signal, and IN2 refers to the second input signal.

[0036] In the embodiment of the present application, the weight corresponding to the signal combination is determined according to the written weight data, the first SRAM bit cell controls the high or low level of the Q node (Q1) based on the weight, and the second SRAM bit cell controls the high or low level of the Q node (Q2) based on the weight.

[0037] In the specific implementation, the written weight data can realize the mathematical logic operation of IN1*Q1 and IN2*Q2. That is, according to the weight data, the level signal multiplication signal corresponding to the first input signal in the signal combination (represented by the high or low level of the Q1 node of the first SRAM bit cell) and the level signal multiplication signal corresponding to the second input signal (represented by the high or low level of the Q2 node of the second SRAM bit cell) are determined, and the level of the QB node is opposite to the level of the Q node.

[0038] In the specific implementation, when Q1 and Q2 are both low, the first transmission gate circuit and the second transmission gate circuit are not conductive (N1, N2, P1 and P2 are not conductive), and the gates of N3, N4, N5 and N6 are not applied with voltage, so the voltage of the bit line BLL and the bit line BLR always remains VDD regardless of the input value.

[0039] In the embodiment of the present application, the Q1 node of the first SRAM bit cell is high (the Q2 node of the second SRAM bit cell is low), the first transmission gate circuit is conductive, and when the first input signal is high, the third MOS tube (N3) and the fifth MOS tube (N5) are conductive, the BLL bit line is discharged to low through the third MOS tube, and since the fourth MOS tube (N4) and the sixth MOS tube (N6) are not conductive and the fifth MOS tube and the sixth MOS tube are connected in series, the bit line BLR cannot form a path to ground and still remains VDD.

[0040] Similarly, when the Q2 node of the second SRAM bit cell is high (the Q1 node of the first SRAM bit cell is low), the second transmission gate circuit is conductive, and when the second input signal is high, the fourth MOS tube (N4) and the sixth MOS tube (N6) are conductive, the BLL bit line is discharged to low through the fourth MOS tube, the third MOS tube (N3) and the fifth MOS tube (N5) are not conductive, the bit line BLR cannot form a path to ground and still remains VDD.

[0041] In the embodiment of the present application, the Q1 node of the first SRAM bit cell is high, the Q2 node of the second SRAM bit cell is high, the first transmission gate circuit and the second transmission gate circuit are conductive, and when the first input signal IN1 and the second input signal IN2 are both high, N3 to N6 are all conductive, the BLL bit line is discharged to low through N3 and N4, and the BLR bit line is discharged to low through N5 and N6.

[0042] In the embodiment of the present invention, a carry signal (of a signal combination) outputted by a carry output port and a sum signal (of a signal combination) outputted by a sum output port are obtained.

[0043] In a specific implementation, based on the above, the Boolean logic expressions of the BLL bit line and the BLR bit line can be obtained as follows:

[0044]

[0045] In a specific implementation, a single horizontal bar on a letter symbol or a formula indicates that the letter symbol or the formula is negated.

[0046] In a specific implementation, since the bit line BLR outputs the carry output signal Cout through the NOT gate, and the bit line BLL and the carry output signal Cout output the sum output signal through the NOR gate, the Boolean logic expression of the sum output signal Sum and the carry output signal Cout can be obtained (for convenience of explanation, A is used to represent IN1×Q1, and B is used to represent IN2×Q2):

[0047]

[0048] The truth table of the half adder is shown in Table 1. The logical expression of the half adder is:

[0049] Cout=AB.

[0050] Table 1:

[0051]

[0052] The in-memory multiplication-accumulation computing device and corresponding calculation method provided by the present invention utilize a computing device connected in a specific manner to accumulate the result of multiplying a first input signal by its corresponding weight and the result of multiplying a second input signal by its corresponding weight, generating a summed output signal and a carry output signal. This calculation directly outputs the multiplication-accumulation result of the two sets of inputs and weights, eliminating the need for a multiplication unit and the first-stage half-adder circuit in the adder tree. Compared to previous designs, which required two AND gates and one half-adder for a total of 26 transistors to perform the multiplication-accumulation operation on two sets of inputs and weights, the in-memory multiplication-accumulation computing device proposed by the present invention only requires 14 transistors to achieve the same function, significantly saving transistors and helping to reduce the area and power consumption of the adder tree, thereby improving the energy efficiency of the entire CIM macro.

Claims

1. An in-memory multiplication and accumulation computing device based on SRAM, characterized in that: include: BLL bit line, BLR bit line, first SRAM bit cell, second SRAM bit cell, first transmission gate circuit, second transmission gate circuit, carry output port and sum output port, wherein: The first transmission gate circuit includes a first NMOS transistor, a first PMOS transistor and a first input port, the source of the first NMOS transistor is connected to the source of the first PMOS transistor, the connection point of the two sources serves as the first input port, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the gate of the first NMOS transistor is connected to the Q node of the first SRAM bit cell, and the gate of the first PMOS transistor is connected to the QB node of the first SRAM bit cell; The second transmission gate circuit includes a second NMOS transistor, a second PMOS transistor, and a second input port, the source of the second NMOS transistor is connected to the source of the second PMOS transistor, the connection point of the two sources serves as the second input port, the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the second NMOS transistor is connected to the Q node of the second SRAM bit cell, and the gate of the second PMOS transistor is connected to the QB node of the second SRAM bit cell; A third MOS transistor is provided between the BLL bit line and the first transmission gate circuit, the gate of the third MOS transistor is connected to the drain of the first NMOS transistor, and the other two electrodes of the third MOS transistor are connected to the BLL bit line and the ground respectively; a fourth MOS transistor is provided between the BLL bit line and the second transmission gate circuit, the gate of the fourth MOS transistor is connected to the drain of the second NMOS transistor, and the other two electrodes of the fourth MOS transistor are connected to the BLL bit line and the ground respectively; A fifth MOS transistor is provided between the BLR bit line and the first transmission gate circuit, and a sixth MOS transistor is provided between the BLR bit line and the second transmission gate circuit; the gate of the fifth MOS transistor is connected to the drain of the first PMOS transistor, and the other two electrodes of the fifth MOS transistor are connected to the BLR bit line and the sixth MOS transistor respectively; the gate of the sixth MOS transistor is connected to the drain of the second PMOS transistor, and the other two electrodes of the sixth MOS transistor are connected to the fifth MOS transistor and ground respectively; A NOT gate is provided between the BLR bit line and the carry output port, and the NOT gate output end is connected to the carry output port; a NOR gate is provided between the output end of the NOT gate and the sum output port, and the NOR gate input end is connected to the NOT gate output end and the BLL bit line respectively.

2. The SRAM-based in-memory multiplication and accumulation computing device according to claim 1, characterized in that: The first SRAM bit cell and the second SRAM bit cell are both 6T SRAM bit cells.

3. The SRAM-based in-memory multiplication and accumulation computing device according to claim 2, characterized in that: The 6T SRAM bit cell includes a first inverter and a second inverter, wherein the Q node is the output of the first inverter, and the QB node is the output of the second inverter; the voltage levels of the Q node and the QB node are opposite.

4. The SRAM-based in-memory multiplication and accumulation computing device according to claim 1, characterized in that: It also includes a precharge circuit, which includes a MOS tube arranged between the BLL bit line and the BLR bit line. The gate of the MOS tube is used to receive a precharge signal, and the other two electrodes of the MOS tube are respectively connected to the BLL bit line and the BLR bit line.

5. The SRAM-based in-memory multiplication and accumulation computing device according to claim 1, characterized in that: The system also includes a pre-charging circuit, which includes a first pre-charging MOS transistor corresponding to the BLL bit line and a second pre-charging MOS transistor corresponding to the BLR bit line. The gate of the first pre-charging MOS transistor is used to receive a pre-charging signal, and the other two electrodes of the first pre-charging MOS transistor are respectively connected to the BLL bit line and the power supply; the gate of the second pre-charging MOS transistor is used to receive a pre-charging signal, and the other two electrodes of the second pre-charging MOS transistor are respectively connected to the BLR bit line and the power supply.

6. The SRAM-based in-memory multiplication and accumulation computing device according to claim 1, characterized in that: The third MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor are all NMOS transistors. The source of the third MOS transistor is grounded, and the drain of the third MOS transistor is connected to the BLL bit line; the source of the fourth MOS transistor is grounded, and the drain of the fourth MOS transistor is connected to the BLL bit line; the drain of the fifth MOS transistor is connected to the BLR bit line; the source of the sixth MOS transistor is grounded, and the drain of the sixth MOS transistor is connected to the source of the fifth MOS transistor.

7. A method for multiplication and accumulation calculation in memory based on SRAM, characterized in that: The SRAM-based in-memory multiplication and accumulation computing device according to any one of claims 1 to 6 is applied, comprising: Charge the BLL bit line and the BLR bit line to a high level; The input includes a signal combination of a first input signal and a second input signal, wherein the first input port of the first transmission gate circuit receives the first input signal, and the second input port of the second transmission gate circuit receives the second input signal; Determine the weight corresponding to the signal combination according to the written weight data, the first SRAM bit unit controls the level of the Q node based on the weight, and the second SRAM bit unit controls the level of the Q node based on the weight; Obtain the carry signal output by the carry output port and the sum signal output by the sum output port.

8. The SRAM-based in-memory multiplication and accumulation calculation method according to claim 7, wherein: The step of determining the weight corresponding to the signal combination according to the written weight data includes: Perform a write operation on the SRAM array in storage mode to write the weight data into the corresponding SRAM array.

9. The SRAM-based in-memory multiplication and accumulation calculation method according to claim 7, wherein: The first SRAM bit cell controls the level of the Q node based on the weight, and the second SRAM bit cell controls the level of the Q node based on the weight, including: When the Q node of the first SRAM bit cell is at a high level and the first input signal is at a high level, the third MOS transistor is turned on, and the BLL bit line is discharged to a low level to the ground through the third MOS transistor; when the Q node of the second SRAM bit cell is at a high level and the second input signal is at a high level, the fourth MOS transistor is turned on, and the BLL bit line is discharged to a low level to the ground through the fourth MOS transistor.

10. The SRAM-based in-memory multiplication and accumulation calculation method according to claim 7, wherein: The first SRAM bit cell controls the level of the Q node based on the weight, and the second SRAM bit cell controls the level of the Q node based on the weight, including: When the Q node of the first SRAM bit cell is at a high level, the Q node of the second SRAM bit cell is at a high level, and the first input signal and the second input signal are both at a high level, the BLL bit line is discharged to a low level to the ground, and the BLR bit line is discharged to a low level to the ground through the fifth MOS transistor and the sixth MOS transistor.

Images