Incremental compiling method and device, equipment, storage medium and product

Abstract

The invention discloses an incremental compiling method and device, equipment, a storage medium and a product. The method can be applied to the field of financial science and technology and comprises the steps that newly-added code blocks in the engineering project development process are obtained; performing incremental compiling on the newly added code block to obtain a compiled bit stream code; performing cross coding on the compiled bit stream code to obtain a target bit stream code; and storing the target bit stream code so as to post-process the target bit stream code. According to the technical scheme, the bit stream processing rate after incremental compiling is improved, so that the code design implementation time in the engineering development process is shortened, and the engineering project development efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of financial technology, and in particular to an incremental compilation method, device, equipment, storage medium and product. Background Art

[0002] Incremental compilation means compiling only the modified parts of the completed engineering code design and regenerating the bitstream for the modified parts, thereby accelerating the design code implementation process, shortening the time for design re-implementation and improving code design and development efficiency.

[0003] Existing incremental compilation technologies include incremental compilation based on Go language and Maven incremental compilation, etc. However, the processing efficiency of existing incremental compilation bitstream is not high. Due to the low efficiency of bitstream processing, the efficiency of post-processing implementation process of subsequent code design is low. Summary of the invention

[0004] The present invention provides an incremental compilation method, apparatus, device, storage medium and product to improve the bit stream processing rate after incremental compilation, thereby shortening the code design implementation time in the engineering development process, and further improving the efficiency of engineering project development.

[0005] According to one aspect of the present invention, there is provided an incremental compilation method, the method comprising:

[0006] Get the newly added code blocks during the project development process;

[0007] Incrementally compiling the newly added code block to obtain a compiled bit stream code;

[0008] Cross-coding the compiled bit stream code to obtain a target bit stream code;

[0009] The target bit stream code is stored to post-process the target bit stream code.

[0010] According to another aspect of the present invention, there is provided an incremental compilation device, the device comprising:

[0011] The code block acquisition module is used to obtain the newly added code blocks in the process of project development;

[0012] An incremental compilation module, used for incrementally compiling the newly added code block to obtain a compiled bit stream code;

[0013] A cross-coding module, used for cross-coding the compiled bit stream code to obtain a target bit stream code;

[0014] The storage module is used to store the target bit stream code so as to perform post-processing on the target bit stream code.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] at least one processor; and

[0017] a memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the incremental compilation method described in any embodiment of the present invention.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the incremental compilation method described in any embodiment of the present invention when executed.

[0020] According to another aspect of the present invention, a computer program product is provided. The computer program product includes a computer program. When the computer program is executed by a processor, the incremental compilation method is implemented.

[0021] The technical solution of the embodiment of the present invention obtains compiled bitstream codes by incrementally compiling the acquired newly added code blocks, cross-encoding the compiled bitstream codes to obtain target bitstream codes, and storing the target bitstream codes for subsequent processing. By performing secondary cross-compilation on the incrementally compiled bitstream codes, the bitstream output rate is accelerated, the time consumption of the overall compilation process is reduced, and the bitstream code processing rate is increased, thereby shortening the implementation time of other post-processing designs in the subsequent engineering development process, thereby improving the development efficiency of the engineering project.

[0022] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 is a flowchart of an incremental compilation method provided according to Embodiment 1 of the present invention;

[0025] Figure 2is a flowchart of an incremental compilation method provided according to Embodiment 2 of the present invention;

[0026] Figure 3A is a schematic diagram of the structure of a combined cross encoder provided according to Embodiment 3 of the present invention;

[0027] Figure 3B is a schematic diagram of the structure of another combined cross encoder provided according to Embodiment 3 of the present invention;

[0028] Figure 4 is a schematic diagram of the structure of an incremental compilation device provided according to a fourth embodiment of the present invention;

[0029] Figure 5 It is a structural schematic diagram of an electronic device for implementing the incremental compilation method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] Embodiment 1

[0033] Figure 1 This is a flowchart of an incremental compilation method provided in the first embodiment of the present invention. This embodiment is applicable to the case of compiling incremental code in the process of engineering project code design. The method can be executed by an incremental compilation device. The incremental compilation device can be implemented in the form of hardware and / or software. The incremental compilation device can be configured in an electronic device. Figure 1 As shown, the method includes:

[0034] S110. Acquire newly added code blocks during the development of the engineering project.

[0035] S120 , incrementally compile the newly added code block to obtain a compiled bit stream code.

[0036] S130 , cross-encoding the compiled bit stream code to obtain a target bit stream code.

[0037] S140: Store the target bit stream code to perform post-processing on the target bit stream code.

[0038] Among them, the newly added code blocks are the codes that are updated or modified during the development, operation and maintenance or design process of the engineering project.

[0039] The compiled bitstream code may be a bit sequence obtained after compiling the newly added code block. For example, the newly added code block may be compiled using an existing incremental compilation method, such as incremental compilation based on the Go language, to obtain the compiled bitstream code obtained by the initial compilation.

[0040] It should be noted that the storage format of the compiled bit stream code obtained by incremental compilation in the computer is a 4-bit hexadecimal code sequence.

[0041] The compiled bit stream code obtained by the initial encoding is re-encoded, i.e., cross-encoded, to obtain the target bit stream code. The target bit stream code obtained by cross-compilation is a 12-bit code sequence. The cross-coding method can be obtained by cross-coding based on a pre-trained coding network model, or by calculating based on a cross-coding algorithm that can convert a hexadecimal 4-bit code sequence into a 12-bit code sequence.

[0042] The target bitstream code after cross-coding is stored for subsequent design implementation. It can be understood that after the cross-compilation of the compiled bitstream code obtained by the initial coding is completed, the obtained target bitstream code is thrown back to the main design thread, and the storage format is changed from the initial format to the 12-bit coding sequence format stored in the project, instead of the initial hexadecimal digital coding format to store the compiled bitstream code. Taking 1 second of calculation time as an example, assuming that the compiled bitstream code is 0x1010, its corresponding stored coding sequence is 1010, which is 4 bits. Assuming that 4 bits are input to the cross-coding algorithm in 1 second, that is, the input bitstream rate is 4 bits / s, after cross-coding, the bit rate of the output target bitstream code obtained in 1 second is also 12 bits / s, thereby improving the bitstream speed and accelerating the subsequent process of incremental compilation.

[0043] The technical solution of the embodiment of the present invention obtains compiled bitstream codes by incrementally compiling the acquired newly added code blocks, cross-encoding the compiled bitstream codes to obtain target bitstream codes, and storing the target bitstream codes for subsequent processing. By performing secondary cross-compilation on the incrementally compiled bitstream codes, the bitstream output rate is accelerated, the time consumption of the overall compilation process is reduced, and the bitstream code processing rate is increased, thereby shortening the implementation time of other post-processing designs in the subsequent engineering development process, thereby improving the development efficiency of the engineering project.

[0044] Embodiment 2

[0045] Figure 2 This is a flow chart of an incremental compilation method provided in Embodiment 2 of the present invention. This embodiment is optimized and improved on the basis of the above technical solutions.

[0046] Furthermore, the step of "cross-encoding the compiled bitstream code to obtain the target bitstream code" is refined into "determining the code block capacity of the newly added code block; and cross-compiling the compiled bitstream code according to the code block capacity to obtain the target bitstream code." to improve the cross-compilation method of the compiled bitstream code.

[0047] It should be noted that for the parts not described in detail in the embodiments of the present invention, reference can be made to the descriptions of other embodiments. Figure 2 As shown, the method comprises the following specific steps:

[0048] S210. Acquire a newly added code block during the development of the engineering project.

[0049] S220: incrementally compile the newly added code block to obtain a compiled bit stream code.

[0050] S230: Determine the code block capacity of the newly added code block.

[0051] S240 . Cross-compile the compiled bitstream code according to the code block capacity to obtain a target bitstream code.

[0052] S250: Store the target bit stream code to perform post-processing on the target bit stream code.

[0053] By determining the code block capacity of the newly added code block and cross-compiling the compiled bitstream code according to the code block capacity to obtain the target bitstream code, dynamic compilation of the compiled bitstream code is achieved and the cross-compilation flexibility is improved, thereby improving the compilation efficiency of cross-compilation while ensuring the subsequent processing efficiency of the bitstream code.

[0054] The code block capacity is used to represent the size of the code block or the size of the memory occupied by the code block; the larger the memory occupied by the code block, the larger the code block capacity, and the smaller the memory occupied by the code block, the smaller the code block capacity.

[0055] In the process of cross-compiling the compiled bitstream code, the code block capacity is considered, and based on different code block capacities, different resources required for cross-compiling are configured to cross-compile the compiled bitstream code.

[0056] In an optional embodiment, the compiled bitstream code is cross-compiled according to the code block capacity to obtain the target bitstream code, including: determining the number of registers and the number of adders required for cross-compilation according to the code block capacity; generating target registers of the corresponding number of registers and generating target adders of the corresponding number of adders; cross-compiling the compiled bitstream code based on the target registers and the target adders to obtain the target bitstream code.

[0057] Optionally, the number of registers and adders required for cross-compilation is determined based on the code block capacity, including: if the code block capacity is greater than a preset capacity threshold, the number of registers and the number of adders are set to four respectively; or, if the code block capacity is not greater than the preset capacity threshold, the number of registers and the number of adders are set to three respectively.

[0058] The capacity threshold can be pre-set by relevant technical personnel based on actual experience or experimental values, or dynamically configured based on design requirements in the development process of different engineering projects. For example, the capacity threshold can be set to 1M.

[0059] Optionally, determining the number of registers and adders required for cross-compilation according to the code block capacity may also include: determining the number of registers and adders according to the capacity interval to which the code block capacity belongs.

[0060] Specifically, the capacity intervals are pre-set, for example, the capacity interval A1 may include (a1, a2], the capacity interval A2 may include (a2, a3], the capacity interval A3 may include (a3, a4], the capacity interval A4 may include (a4, a5], and the capacity interval A5 may include (a5, a6]. In addition, the numbers of registers and adders corresponding to different capacity intervals are pre-configured. For example, the number of registers and adders corresponding to the capacity interval A1 is set to m1, the number of registers and adders corresponding to the capacity interval A2 is set to m2, the number of registers and adders corresponding to the capacity interval A3 is set to m3, the number of registers and adders corresponding to the capacity interval A4 is set to m4, and the number of registers and adders corresponding to the capacity interval A5 is set to m5. Determine the capacity interval to which the code capacity belongs, and determine the number of registers and adders corresponding to the corresponding capacity interval.

[0061] The technical solution of the above-mentioned embodiment determines whether the code block capacity is greater than a preset capacity threshold. If so, the number of registers and the number of adders are set to four. If not, the number of registers and the number of adders are set to three respectively, thereby realizing accurate configuration of the number of registers and adders, comprehensively considering the code block capacity characteristics, and using the capacity threshold as the configuration division point, thereby improving the flexibility of the configuration number of registers and adders.

[0062] Generate target registers corresponding to the number of registers and generate target adders corresponding to the number of adders. For example, if the number of registers and the number of adders are five, five target registers and five target adders are generated respectively.

[0063] The compiled bitstream code is cross-compiled based on the target registers and the target adders to obtain the target bitstream code. Exemplarily, each target register and the target adder are combined, and there may be multiple combinations of different numbers of target registers and target adders.

[0064] In an optional embodiment, the compiled bitstream code is cross-compiled based on the target registers and the target adders to obtain the target bitstream code, including: determining the connection relationship between each target register and each target adder, and combining each target register and the target adder based on the connection relationship to obtain a combined cross compiler; inputting the compiled bitstream code into the combined cross compiler in sequence according to the bit order to obtain the target bitstream code output by the combined cross compiler.

[0065] It should be noted that each target register has an initial value, and the initial value is usually set to 0.

[0066] Among them, the connection relationship between each target register and each target adder can be pre-configured according to actual needs, and the configuration rule is to ensure that the result of the adder output is a 12-bit encoding sequence. Exemplarily, if there are three target registers and three target adders, the other three target registers are b1, b2 and b3, and the three target adders are n1, n2 and n3, respectively. The corresponding connection relationship can be that the input of target adder n1 is the output of target register b1; the input of target adder n2 is the output of target register b1 and target register b3; the input of target adder n3 is the output of target register b1, target register b1 and target register b3.

[0067] Based on the connection relationship between the target registers and the target adders, the target registers and the target adders are combined to obtain a combined cross compiler for cross compilation calculation. The compiled bit stream code is sequentially input into the combined cross compiler in bit order to obtain the target bit stream code output by the cross compiler.

[0068] The above technical scheme determines the connection relationship between each target register and each target adder, and based on the connection relationship, combines each target register and the target adder to obtain a combined cross-compiler, and inputs the compiled bit stream code into the combined cross-compiler in bit order to obtain the target bit stream code output by the combined cross-compiler, thereby realizing cross-compilation of the target bit stream code. During the compilation process, based on the combination of registers and adders with different numbers, it is ensured that the number of bits of the output bit stream code meets the requirements, and the selection of different combinations improves the flexibility of the cross-coding process.

[0069] It can be understood that the compiled bitstream code obtained by the initial compilation is a four-bit hexadecimal bit sequence, and the bit sequence number of the target bitstream code obtained by the secondary cross-compilation is larger than the compiled bitstream code, and is related to the code block capacity of the newly added code block. Specifically, when the code capacity is small, the number of target registers and target adders required is small, and the bit sequence number of the output target bitstream code is small, but larger than the compiled bitstream code. When the code capacity is large, the number of target registers and target adders required is large, and the bit sequence number of the output target bitstream code is large. For example, when the number of target adders and target registers is 3 respectively, the number of bits of the output target bitstream code is 12 bits; when the number of target adders and target registers is 4 respectively, the number of bits of the output target bitstream code is 16 bits.

[0070] The target bit stream code obtained after the secondary cross compilation has a different bit sequence number due to the influence of the code block capacity, but is still larger than the bit sequence number of the encoded bit stream code, thereby ensuring the bit stream output rate after cross compilation.

[0071] The technical solution of the above-mentioned embodiment determines the number of registers and adders required for cross-compilation according to the code block capacity, generates target registers of the corresponding number of registers and generates target adders of the corresponding number of adders, cross-compiles the compiled bitstream code based on the target registers and target adders to obtain the target bitstream code, and during cross-compilation, generates or creates registers and adders by clarifying the number of registers and adders, thereby avoiding resource redundancy and resource loss, ensuring the rationality of memory usage of resources such as registers and adders, and avoiding resource waste and resource occupation.

[0072] Embodiment 3

[0073] This embodiment provides a preferred example based on the above embodiment. The steps of the preferred embodiment are as follows:

[0074] S31. Assume that there is a newly added code block A. The encoded bit stream code obtained after incremental compilation is Bn. The storage format of Bn in the computer memory is a hexadecimal encoding sequence of 0x1010, that is, a digital code.

[0075] S32a, if the size of the newly added code block does not exceed 1M, three registers and three adders can be selected for combination. The combined cross encoder can be found in Figure 3A shown.

[0076] Among them, b1, b2 and b3 represent registers, c1, c2 and c3 represent adders. The initial value stored in each of the three registers is 0, and the three adders have their own input and output. If the encoded bit stream code Bn is 0x1010, the encoding process is as follows:

[0077] The first input number is 1. At this time, 1 enters register b1, then b1=1, and the original initial value 0 of b1 is pushed out and pushed to the four lines A, B, C, and G, that is, A=0, B=0, C=0, and G=0. At this time, the 0 on the G line enters register b2, then b2=0, and the initial value 0 of b2 is pushed out and pushed to the two lines D and H, that is, D=0, H=0. Similarly, the initial value 0 on the H line enters register b3, then b3=0, then the initial value 0 of b3 is pushed out and pushed to the two lines E and F, that is, E=0, F=0. At this time, the adder c1 outputs c1=A=0. The adder c2 outputs c2=B⊕E=0⊕0=0. The adder c3 outputs c3=C⊕D⊕F=0⊕0⊕0=0, so the output this time is c1c2c3=000. At this time, registers b1, b2, and b3 change from their initial values ​​000 to 100, and are used in the calculation for the next round of digital input.

[0078] The second input number is 0. At this time, 0 enters register b1, then b1=0, and the value 1 of b1 in the previous round is pushed out and pushed to the four lines A, B, C, and G, that is, A=1, B=1, C=1, and G=1. At this time, the 1 on the G line enters register b2, then b2=1, and the value 0 of b2 in the previous round is pushed out and pushed to the two lines D and H, that is, D=0, H=0. Similarly, the value 0 on the H line enters register b3, then b3=0, then the value 0 of b3 in the previous round is pushed out and pushed to the two lines E and F, that is, E=0, F=0. At this time, the adder c1 outputs c1=A=1. The adder c2 outputs c2=B⊕E=1⊕0=1. The adder c3 outputs c3=C⊕D⊕F=1⊕0⊕0=1, so the output this time is c1c2c3=111. At this time, registers b1, b2, and b3 change from 100 after the previous round to 010, and are used for calculation when the next round of digital input occurs.

[0079] The third input number is 1. At this time, 1 enters register b1, then b1=1, and the value 0 of b1 in the previous round is pushed out and pushed to the four lines A, B, C, and G, that is, A=0, B=0, C=0, and G=0. At this time, the 0 on the G line enters register b2, then b2=0, and the value 1 of b2 in the previous round is pushed out and pushed to the two lines D and H, that is, D=1, H=1. Similarly, the value 1 on the H line enters register b3, then b3=1, and the value 0 of b3 in the previous round is pushed out and pushed to the two lines E and F, that is, E=0, F=0. At this time, the adder c1 outputs c1=A=0, and the adder c2 outputs c2=B⊕E=0⊕0=0. The adder c3 outputs c3=C⊕D⊕F=0⊕1⊕0=1. Therefore, the output this time is c1c2c3=001. At this time, register b1b2b3 changes from 010 after the previous round to 101, and is used for calculation when the next round of digital input occurs.

[0080] The fourth input number is 0. At this time, 0 enters register b1, then b1=0, and the value 1 of b1 in the previous round is pushed out and placed on the four lines A, B, C, and G, that is, A=1, B=1, C=1, and G=1. At this time, the 1 on line G enters register b2, then b2=1, and the value 0 of b2 in the previous round is pushed out and placed on the two lines D and H, that is, D=0, H=0. Similarly, the value 1 on line H enters register b3, then b3=1, and the value 1 of b3 in the previous round is pushed out and placed on the two lines E and F, that is, E=0, F=0. At this time, adder c1 outputs c1=A=1, and adder c2 outputs c2=B⊕E=1⊕1=0. Adder c3 outputs c3=C⊕D⊕F=1⊕0⊕1=0. Therefore, the output this time is c1c2c3=100. At this time, register b1b2b3 changes from 001 after the previous round to 010 now.

[0081] The target bit stream code Cn obtained by the above conversion process is 000 111 001 100, that is, 12 bits.

[0082] S32b, if the size of the newly added code block exceeds 1M, four registers and four adders can be selected for combination. The larger the code block size, the higher the bit stream required for processing. In order to achieve the purpose of reducing time consumption, it is necessary to select a more complex combination of registers and adders to make the cross-coding output bit stream rate faster. The combined cross-coding encoder can be seen in Figure 3B shown.

[0083] Among them, b1, b2, b3 and b4 represent registers, c1, c2, c3 and c4 represent adders, the initial value stored in each of the four registers is 0, and the four adders have their own input and output terminals. If the encoded bit stream code Bn is 0x1010, the encoding process is as follows:

[0084] The first input number is 1. At this time, 1 enters register b1, then b1=1, and the original initial value 0 of b1 is pushed out and pushed to the five lines A, B, C, D, and K, that is, A=0, B=0, C=0, D=0, and K=0. At this time, the 0 on the K line enters register b2, then b2=0, and the initial value 0 of b2 is pushed out and pushed to the three lines E, F, and L, that is, E=0, F=0, and L=0. Similarly, the initial value 0 on the L line enters register b3, then b3=0, and the initial value 0 of b3 is pushed out and pushed to the three lines G, H, and M, that is, G=0, H=0, and M=0. Similarly, the 0 on the M line enters register b4, then b4=0, and the initial value 0 of b4 is pushed out and pushed to the two lines I and J, that is, I=0, J=0. At this time, the adder c1 outputs c1=A=0. Adder c2 outputs c2=B⊕E=0⊕0=0. Adder c3 outputs c3=C⊕G⊕I=0⊕0⊕0=0, and adder c4 outputs c4=D⊕F⊕H⊕J=0⊕0⊕0⊕0=0. Therefore, the output this time is c1c2c3c4=0000. At this time, registers b1, b2, b3, and b4 change from the initial value 0000 to 1000, and are used for calculation in the next round of digital input.

[0085] The second input number is 0. At this time, 0 enters register b1, then b1=0, and the value 1 of b1 in the previous round is pushed out and pushed to the five lines A, B, C, D, and K, that is, A=1, B=1, C=1, D=1, and K=1. At this time, the 1 on the K line enters register b2, then b2=1, and the value 0 of b2 in the previous round is pushed out and pushed to the three lines E, F, and L, that is, E=0, F=0, and L=0. Similarly, the value 0 on the L line enters register b3, then b3=0, and at the same time, the value 0 of b3 in the previous round is pushed out and pushed to the three lines G, H, and M, that is, G=0, H=0, and M=0. Similarly, the 0 on the M line enters register b4, then b4=0, and at the same time, the value 0 of b4 in the previous round is pushed out and pushed to the two lines I and J, then I=0, J=0. At this time, the adder c1 outputs c1=A=1. Adder c2 outputs c2=B⊕E=1⊕0=1. Adder c3 outputs c3=C⊕G⊕I=1⊕0⊕0=1, and adder c4 outputs c4=D⊕F⊕H⊕J=1⊕0⊕0⊕0=1. Therefore, the output this time is c1c2c3c4=1111. At this time, registers b1, b2, b3, and b4 change from the previous round value 1000 to 0100, and are used for calculation in the next round of digital input.

[0086] The third input number is 1. At this time, 1 enters register b1, then b1=1, and the value 0 of b1 in the previous round is pushed out and pushed to the five lines A, B, C, D, and K, that is, A=0, B=0, C=0, D=0, and K=0. At this time, the 0 on the K line enters register b2, then b2=0, and the value 1 of b2 in the previous round is pushed out and pushed to the three lines E, F, and L, that is, E=1, F=1, and L=1. Similarly, the value 1 on the L line enters register b3, then b3=1, and at the same time, the value 0 of b3 in the previous round is pushed out and pushed to the three lines G, H, and M, that is, G=0, H=0, and M=0. Similarly, the 0 on the M line enters register b4, then b4=0, and at the same time, the value 0 of b4 in the previous round is pushed out and pushed to the two lines I and J, then I=0, J=0. At this time, the adder c1 outputs c1=A=0. Adder c2 outputs c2=B⊕E=0⊕1=1. Adder c3 outputs c3=C⊕G⊕I=0⊕0⊕0=0, and adder c4 outputs c4=D⊕F⊕H⊕J=0⊕1⊕0⊕0=1. Therefore, the output this time is c1c2c3c4=0101. At this time, registers b1, b2, b3, and b4 change from the previous round value 0100 to 1010, and are used for calculation in the next round of digital input.

[0087] The fourth input number is 0. At this time, 0 enters register b1, then b1=0, and the value 1 of b1 in the previous round is pushed out and pushed to the five lines A, B, C, D, and K, that is, A=1, B=1, C=1, D=1, and K=1. At this time, the 1 on the K line enters register b2, then b2=1, and the value 0 of b2 in the previous round is pushed out and pushed to the three lines E, F, and L, that is, E=0, F=0, and L=0. Similarly, the value 0 on the L line enters register b3, then b3=0, and at the same time, the value 1 of b3 in the previous round is pushed out and pushed to the three lines G, H, and M, that is, G=1, H=1, and M=1. Similarly, the 1 on the M line enters register b4, then b4=1, and at the same time, the value 0 of b4 in the previous round is pushed out and pushed to the two lines I and J, then I=0, J=0. At this time, the adder c1 outputs c1=A=1. Adder c2 outputs c2=B⊕E=1⊕0=1. Adder c3 outputs c3=C⊕G⊕I=1⊕1⊕0=1, and adder c4 outputs c4=D⊕F⊕H⊕J=1⊕0⊕1⊕0=1. Therefore, the output this time is c1c2c3c4=1111. At this time, registers b1, b2, b3, and b4 change from the previous round value 1010 to 0101.

[0088] The target bit stream code Cn obtained by the above conversion process is 0000 1111 0101 1111, that is, 16 bits.

[0089] After the above process, the cross-coding of the above Bn is completed, and the result target bit stream code Cn is thrown back to the main thread, and the storage format is changed to the cross-coding result Cn such coding format stored in the project, rather than the original hexadecimal digital coding format Bn storage. And calculated in 1 second, the Bn sequence 1010 in the above example is 4 bits, assuming that 4 bits are input to the cross-coding in 1 second, that is, the input bit stream rate is 4bit / s. After cross-coding, the bit rate of the output result Cn in the same 1 second is 12bit / s or 16bit / s, which increases the bit stream rate, thereby speeding up the subsequent process of incremental compilation.

[0090] Optionally, the above cross-coding algorithm can be encapsulated as an SDK (Software Development Kit), which can be encapsulated as a source code package file with the suffix .framework, exposing the entrance of the cross method to the outside, and adding the SDK to the code project file, that is, embedding it in the project, and the cross-coding method can be directly called through the code to complete the cross-coding.

[0091] Embodiment 4

[0092] Figure 4 The structure diagram of an incremental compilation device provided by the fourth embodiment of the present invention. The incremental compilation device provided by the embodiment of the present invention can be applied to the case of compiling incremental code in the process of engineering project code design. The incremental compilation device can be implemented in the form of hardware and / or software, such as Figure 4 As shown, the device specifically includes: a code block acquisition module 401, an incremental compilation module 402, a cross-coding module 403 and a storage module 404. Among them,

[0093] The code block acquisition module 401 is used to acquire the newly added code blocks in the process of engineering project development;

[0094] An incremental compilation module 402 is used to perform incremental compilation on the newly added code block to obtain a compiled bit stream code;

[0095] A cross-coding module 403, configured to perform cross-coding on the compiled bit stream code to obtain a target bit stream code;

[0096] The storage module 404 is used to store the target bit stream code so as to perform post-processing on the target bit stream code.

[0097] The technical solution of the embodiment of the present invention obtains compiled bitstream codes by incrementally compiling the acquired newly added code blocks, cross-encoding the compiled bitstream codes to obtain target bitstream codes, and storing the target bitstream codes for subsequent processing. By performing secondary cross-compilation on the incrementally compiled bitstream codes, the bitstream output rate is accelerated, the time consumption of the overall compilation process is reduced, and the bitstream code processing rate is increased, thereby shortening the implementation time of other post-processing designs in the subsequent engineering development process, thereby improving the development efficiency of the engineering project.

[0098] Optionally, the cross-coding module 403 includes:

[0099] A capacity determination unit, used to determine the code block capacity of the newly added code block;

[0100] The cross-compilation unit is used to cross-compile the compiled bit stream code according to the code block capacity to obtain a target bit stream code.

[0101] Optional, cross-compilation unit, including:

[0102] A quantity determination subunit, used to determine the number of registers and adders required for cross-compilation according to the code block capacity;

[0103] A generating subunit, configured to generate target registers of a corresponding number of registers and target adders of a corresponding number of adders;

[0104] The cross-compiling subunit is used to cross-compile the compiled bit stream code based on the target register and the target adder to obtain a target bit stream code.

[0105] Optional, quantity determination subunit, specifically used for:

[0106] If the code block capacity is greater than a preset capacity threshold, the number of registers and the number of adders are set to four respectively; or,

[0107] If the code block capacity is not greater than a preset capacity threshold, the number of registers and the number of adders are respectively set to three.

[0108] Optional, cross-compilation subunit, specifically for:

[0109] Determine a connection relationship between each of the target registers and each of the target adders, and based on the connection relationship, combine each of the target registers and the target adders to obtain a combined cross compiler;

[0110] The compiled bit stream code is sequentially input into the combined cross compiler in bit order to obtain the target bit stream code output by the combined cross compiler.

[0111] Optionally, the compiled bit stream code is a four-bit hexadecimal bit sequence; the bit number of the bit sequence of the target bit stream code is greater than that of the compiled bit stream code and is related to the code block capacity of the newly added code block.

[0112] The incremental compilation device provided in the embodiment of the present invention can execute the incremental compilation method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0113] Embodiment 5

[0114] Figure 5 A schematic diagram of an electronic device 50 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0115] like Figure 5 As shown, the electronic device 50 includes at least one processor 51, and a memory connected to the at least one processor 51 in communication, such as a read-only memory (ROM) 52, a random access memory (RAM) 53, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 51 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 52 or the computer program loaded from the storage unit 58 to the random access memory (RAM) 53. In the RAM 53, various programs and data required for the operation of the electronic device 50 can also be stored. The processor 51, the ROM 52, and the RAM 53 are connected to each other via a bus 54. An input / output (I / O) interface 55 is also connected to the bus 54.

[0116] A number of components in the electronic device 50 are connected to the I / O interface 55, including: an input unit 56, such as a keyboard, a mouse, etc.; an output unit 57, such as various types of displays, speakers, etc.; a storage unit 58, such as a disk, an optical disk, etc.; and a communication unit 59, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 59 allows the electronic device 50 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0117] The processor 51 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 51 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 51 executes the various methods and processes described above, such as the incremental compilation method.

[0118] In some embodiments, the incremental compilation method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 58. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 50 via the ROM 52 and / or the communication unit 59. When the computer program is loaded into the RAM 53 and executed by the processor 51, one or more steps of the incremental compilation method described above may be performed. Alternatively, in other embodiments, the processor 51 may be configured to perform the incremental compilation method in any other suitable manner (e.g., by means of firmware).

[0119] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0120] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0121] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0122] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0123] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0124] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0125] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0126] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An incremental compilation method, characterized in that: include: Get the newly added code blocks during the project development process; Incrementally compiling the newly added code block to obtain a compiled bit stream code; Cross-coding the compiled bit stream code to obtain a target bit stream code; The target bit stream code is stored to post-process the target bit stream code.

2. The method according to claim 1, characterized in that The cross-coding the compiled bit stream code to obtain a target bit stream code includes: Determine the code block capacity of the newly added code block; The compiled bit stream code is cross-compiled according to the code block capacity to obtain a target bit stream code.

3. The method according to claim 2, characterized in that The cross-compiling the compiled bitstream code according to the code block capacity to obtain the target bitstream code includes: Determining the number of registers and adders required for cross-compilation according to the code block capacity; generating a target register corresponding to the number of registers and generating a target adder corresponding to the number of adders; The compiled bit stream code is cross-compiled based on the target register and the target adder to obtain a target bit stream code.

4. The method according to claim 3, characterized in that Determining the number of registers and adders required for cross-compilation according to the code block capacity includes: If the code block capacity is greater than a preset capacity threshold, the number of registers and the number of adders are set to four respectively; or, If the code block capacity is not greater than a preset capacity threshold, the number of registers and the number of adders are respectively set to three.

5. The method according to claim 3, characterized in that: The cross-compiling the compiled bit stream code based on the target register and the target adder to obtain the target bit stream code includes: Determine a connection relationship between each of the target registers and each of the target adders, and based on the connection relationship, combine each of the target registers and the target adders to obtain a combined cross compiler; The compiled bit stream code is sequentially input into the combined cross compiler in bit order to obtain the target bit stream code output by the combined cross compiler.

6. The method according to any one of claims 1 to 5, characterized in that: The compiled bit stream code is a four-bit hexadecimal bit sequence; the bit sequence of the target bit stream code has a larger number of bits than the compiled bit stream code and is related to the code block capacity of the newly added code block.

7. An incremental compilation device, characterized in that: include: The code block acquisition module is used to obtain the newly added code blocks in the process of project development; An incremental compilation module, used for incrementally compiling the newly added code block to obtain a compiled bit stream code; A cross-coding module, used for cross-coding the compiled bit stream code to obtain a target bit stream code; The storage module is used to store the target bit stream code so as to perform post-processing on the target bit stream code.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the service resource scheduling method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the service resource scheduling method according to any one of claims 1 to 6 when executed.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the computer program implements the service resource scheduling method according to any one of claims 1 to 6.

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