An online upgrading method of a multi-core microcontroller startup boot program

Abstract

The application discloses an online upgrading method of a multi-core microcontroller starting guide program, and the PC pointer is pointed to the RAM before erasing and writing the FLASH, and the B core is put to sleep and waits for the instruction; when the A core has an upgrading request, the B core receives the IPC interrupt request, the PC pointer jumps to the storage area of the interrupt vector table, the corresponding IPC interrupt service function address is searched, the corresponding upgrading service processing is executed, the PC pointer jumps back to the RAM after the execution is completed, the PC pointer is prevented from pointing to the invalid address, and thus the B core is prevented from abnormally stopping and the starting guide program upgrading operation is successfully completed.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an online upgrading method for a multi-core microcontroller boot program. Background Art

[0002] Some MCUs (Micro Controller Units) are internally divided into two cores: one core dedicated to running the bootloader (B-core), and the other core dedicated to running the application (A-core). Generally speaking, the FLASH (flash memory) operation interface of this type of MCU is stored in the B-core, and the A-core erases and writes the FLASH of the B-core through IPC (Inter-processor Communication). When the A-core needs to perform an online upgrade of the B-core's bootloader, the bootloader code area (the area in the FLASH that stores the program code) of the B-core must be erased first. At this time, because the PC pointer of the B-core points to the bootloader code area, the address pointed to by the PC pointer of the B-core after erasing the bootloader code area is invalid, causing the B-core to freeze abnormally and be unable to continue operation.

[0003] Therefore, how to avoid the stuck situation caused by the current upgrade operation is a technical problem that needs to be solved urgently. Summary of the Invention

[0004] In order to address the deficiencies of the prior art, the present invention provides an online upgrade method for a boot program of a multi-core microcontroller. Before erasing the FLASH, the PC pointer (program counter) is pointed to the RAM (Random Access Memory), and the B core is put into sleep mode to wait for instructions. When the A core has an upgrade request, the B core receives an IPC interrupt request, and the PC pointer jumps to the storage area of ​​the interrupt vector table (IVT). The corresponding IPC interrupt service function address is searched, and the corresponding upgrade service processing is executed. After the execution is completed, the PC pointer jumps back to the RAM, thereby preventing the PC pointer from pointing to an invalid address, thereby avoiding abnormal freezing of the B core and successfully completing the boot program upgrade operation.

[0005] The embodiments of the present invention provide the following solutions:

[0006] An embodiment of the present invention provides an online upgrade method for a multi-core microcontroller boot program, the method comprising:

[0007] S1. When the device is powered on, the PC pointer of the B core in the MCU, which is used to run the bootloader, jumps to point to RAM. A loop is injected, and the B core enters a sleep state and waits for new instructions to generate an interrupt. At this time, the PC pointer of the B core is in RAM.

[0008] S2. When the A core in the MCU that is used to run the application program has an upgrade request, it sends an inter-core communication interrupt processing request to erase the FLASH to the inter-core communication hardware controller;

[0009] S3, the inter-core communication hardware controller generates an inter-core communication interrupt processing request;

[0010] S4. Core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in RAM to find the corresponding inter-core communication interrupt processing service function address;

[0011] S5. The PC pointer of core B jumps to the ROM storing the inter-core communication interrupt service function according to the address of the inter-core communication interrupt service function, and executes the corresponding inter-core communication interrupt processing service, that is, the FLASH is erased. At this time, the bootloader code area of ​​core B is erased.

[0012] S6: The PC pointer of core B returns to RAM, and core B enters sleep state and waits for new instructions to generate interrupts;

[0013] S7. Core A sends an inter-core communication interrupt processing request for programming FLASH to the inter-core communication hardware controller;

[0014] S8, the inter-core communication hardware controller generates an inter-core communication interrupt processing request;

[0015] S9, core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in RAM to find the corresponding inter-core communication interrupt processing service function address;

[0016] S10. The PC pointer of core B jumps to the ROM (Read Only Memory) storing the inter-core communication interrupt service function address according to the inter-core communication interrupt service function address, and executes the corresponding inter-core communication interrupt processing service, that is, performs FLASH programming processing, and completes the programming operation of the new version of the bootloader code;

[0017] S11. The PC pointer of core B returns to RAM, and core B enters sleep state and waits for new instructions to generate interrupts.

[0018] In an optional embodiment, when the device is powered on in step S1, the PC pointer of the B core in the MCU for running the boot program immediately jumps from pointing to the FLASH area to pointing to the RAM.

[0019] In an optional embodiment, the inter-core communication interrupt processing service function address described in step S4 is filled into the interrupt vector table when the B core is started and initialized.

[0020] In an optional embodiment, the inter-core communication interrupt processing service function address described in step S9 is filled into the interrupt vector table when the B core is started and initialized.

[0021] The beneficial effects of the present invention based on its technical solution are:

[0022] (1) The present invention provides an online upgrade method for a multi-core microcontroller bootloader, which moves the main loop sleep function of the B core to the RAM area. In this way, after the B core erases the bootloader code area, the PC pointer pointing to an abnormality error will not occur, thereby solving the problem of being unable to upgrade online.

[0023] (2) The present invention provides an online upgrade method for a bootloader of a multi-core microcontroller. It only requires improving the processing sequence of the two cores of the multi-core processor, without having to modify the hardware interface of the product to be upgraded. It also eliminates the need to physically connect the burner to the SWD (Serial Debug Interface Protocol) interface or the step of disassembling the device, thereby enabling batch and remote online upgrades. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 Schematic diagram of hardware connection of an embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of PC pointer jump according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field fall within the scope of protection of the embodiments of the present invention.

[0028] The present invention provides an online bootloader upgrade method for multi-core microcontrollers. This method is applicable to multi-core microcontrollers, such as in-vehicle terminals, personal computers, and industrial computers, where all bootloaders and application programs are stored separately on two cores and the Flash operation interface is stored in the bootloader core. This method is applicable to all products that use this type of multi-core microcontroller and require a bootloader upgrade.

[0029] This embodiment is described by taking a TBOX (Telematics BOX, a vehicle-mounted communication terminal) as an example.

[0030] Reference Figure 1 , the hardware connection preparations before upgrading are as follows:

[0031] Step 1: The cloud server and TBOX are connected via a wireless network, and the upgrade firmware package is also sent from the cloud server to the MPU of TBOX;

[0032] Step 2: The TBOX's internal MPU (Micro Processor Unit) and MCU are connected via a serial data interface, and the upgraded firmware package is transmitted from the MPU to the MCU.

[0033] Step 3: The application core (core A) and the boot core (core B) inside the MCU are connected through the internal IPC component, and the application core will complete the program flashing of the boot core.

[0034] Reference Figure 2 The upgrade process includes:

[0035] S1. When the device is powered on, the PC pointer of the B core in the MCU, which is used to run the bootloader, immediately jumps from pointing to the FLASH area to pointing to the RAM, as shown in the process ① in the figure.

[0036] A loop is injected into RAM, and core B goes into sleep state and waits for a new instruction to generate an interrupt. At this time, the PC pointer of core B is in RAM.

[0037] S2. When the A core in the MCU for running the application program has an upgrade request, an inter-core communication interrupt processing request for erasing the FLASH is sent to the inter-core communication hardware controller.

[0038] S3. The inter-core communication hardware controller generates an inter-core communication interrupt processing request (IPC interrupt), as shown in the process ② in the figure.

[0039] S4. Core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in RAM to find the corresponding inter-core communication interrupt processing service function address, as shown in the process ③ in the figure.

[0040] The inter-core communication interrupt processing service function address is filled into the interrupt vector table when the B core is started and initialized.

[0041] S5. The PC pointer of core B jumps to the ROM storing the inter-core communication interrupt service function address and executes the corresponding inter-core communication interrupt service, i.e., performing the FLASH erase process, as shown in step 4 in the figure. At this time, the bootloader code area of ​​core B is erased.

[0042] S6. The PC pointer of core B returns to RAM, and core B enters sleep state and waits for new instructions to generate interrupts, as shown in the process ⑤ in the figure.

[0043] S7. Core A sends an inter-core communication interrupt processing request for programming FLASH to the inter-core communication hardware controller.

[0044] S8. The inter-core communication hardware controller generates an inter-core communication interrupt processing request.

[0045] S9. Core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in RAM to find the corresponding inter-core communication interrupt processing service function address.

[0046] The inter-core communication interrupt processing service function address is filled into the interrupt vector table when the B core is started and initialized.

[0047] S10. The PC pointer of core B jumps to the ROM (Read Only Memory) storing the inter-core communication interrupt service function address according to the inter-core communication interrupt service function address, and executes the corresponding inter-core communication interrupt processing service, that is, performs FLASH programming processing, and completes the programming operation of the new version of the bootloader code;

[0048] S11. The PC pointer of core B returns to RAM, and core B enters sleep state and waits for new instructions to generate interrupts.

[0049] Those skilled in the art will appreciate that embodiments of the present application can be devised for a variety of applications. It is intended that the present application be limited only by the scope of the appended claims, and it is intended that various modifications and alterations made by those skilled in the art be considered as within the scope of the present application. The embodiments of the present application will be described with reference to the attached drawings, wherein:

[0050] The present application is described in reference to the drawings using a flowchart illustration and / or a block diagram of the method, apparatus (modules) and computer program product according to embodiments of the present application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0051] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0052] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0053] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such modifications and variations as fall within the true scope of the present application.

[0054] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A method for online upgrading of a bootloader of a multi-core microcontroller, characterized in that: The method comprises: S1. When the device is powered on, the PC pointer of the B core in the MCU, which is used to run the bootloader, jumps to point to RAM. A loop is injected, and the B core enters a sleep state and waits for a new instruction to generate an interrupt. At this time, the PC pointer of the B core is in RAM. S2. When the A core in the MCU that is used to run the application program has an upgrade request, it sends an inter-core communication interrupt processing request to erase the FLASH to the inter-core communication hardware controller; S3, the inter-core communication hardware controller generates an inter-core communication interrupt processing request; S4. Core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in RAM to find the corresponding inter-core communication interrupt processing service function address; S5. The PC pointer of core B jumps to the ROM storing the inter-core communication interrupt service function according to the address of the inter-core communication interrupt service function, and executes the corresponding inter-core communication interrupt processing service, that is, the FLASH is erased. At this time, the bootloader code area of ​​core B is erased. S6: The PC pointer of core B returns to RAM, and core B enters sleep state and waits for new instructions to generate interrupts; S7. Core A sends an inter-core communication interrupt processing request for programming FLASH to the inter-core communication hardware controller; S8, the inter-core communication hardware controller generates an inter-core communication interrupt processing request; S9, core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in RAM to find the corresponding inter-core communication interrupt processing service function address; S10. The PC pointer of core B jumps to the ROM storing the inter-core communication interrupt service according to the inter-core communication interrupt service function address, and executes the corresponding inter-core communication interrupt processing service, that is, performs FLASH programming processing to complete the programming operation of the new version of the bootloader code; S11. The PC pointer of core B returns to RAM, and core B enters sleep state and waits for new instructions to generate interrupts.

2. The online upgrade method for a multi-core microcontroller boot program according to claim 1, characterized in that: When the device is powered on in step S1, the PC pointer of the B core in the MCU, which is used to run the boot program, immediately jumps from pointing to the FLASH area to pointing to the RAM.

3. The online upgrade method for a multi-core microcontroller boot program according to claim 1, characterized in that: The inter-core communication interrupt processing service function address described in step S4 is filled into the interrupt vector table when the B core is started and initialized.

4. The online upgrade method for a multi-core microcontroller boot program according to claim 1, characterized in that: The inter-core communication interrupt processing service function address described in step S9 is filled into the interrupt vector table when the B core is started and initialized.

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