Microcontrollers and their operation methods

Abstract

This invention discloses a microcontroller and its operation method. The microcontroller includes a processor, an instruction memory, and an instruction fetch circuit. The instruction fetch circuit includes a cache, a decoder, a branch predictor, and an address arbitrator. The cache receives the current instruction address I from the processor. The decoder retrieves the instruction corresponding to the next instruction address I+1 from the cache, decodes it, and determines whether it is a branch instruction. When the instruction corresponding to instruction address I+1 is a branch instruction and a jump occurs, the branch predictor determines the target instruction address J. The target instruction address J is arbitrated by the address arbitrator and then sent to the instruction memory. The instruction fetch circuit reads the instructions corresponding to the target instruction address J to the instruction address J+P from the instruction memory and stores them in the cache. If the processor requests access to any instruction address from the target instruction address J to the instruction address J+P, the processor reads the instruction corresponding to the requested instruction address from the cache, improving the processor's instruction fetch speed.

Description

Technical Field

[0001] This invention relates generally to the field of integrated circuits, and more particularly, to a microcontroller and a method of operating the microcontroller. Background Technology

[0002] Microcontrollers (MCUs) are widely used in industrial control, electric vehicles, and consumer electronics. A microcontroller typically consists of a processor and an instruction memory. The instruction memory is non-volatile memory. The processor executes programs, and the program's instructions are stored in the instruction memory. The processor retrieves instructions by accessing the instruction memory. Therefore, the speed at which the processor executes a program is affected by the speed at which instructions are read from the non-volatile memory. For example, if a processor operates at a frequency above 72MHz, but a single read operation from flash memory (non-volatile memory) takes 25–40 ns, the processor's performance cannot be fully utilized. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a microcontroller and a microcontroller control method to improve the instruction fetching speed of the processor.

[0004] According to one aspect of an embodiment of the present invention, a microcontroller is provided. The microcontroller includes a processor, an instruction memory, and an instruction fetch circuit. The processor is configured to issue instruction addresses. The instruction memory stores a plurality of instructions. The instruction fetch circuit includes a cache, a decoder, a branch predictor, and an address arbitrator. The cache of the instruction fetch circuit receives a request from the processor to access the current instruction address I, where I is an integer. If the cache stores an instruction corresponding to the next instruction address I+1 of the current instruction address I, the decoder retrieves the instruction corresponding to instruction address I+1 from the cache, decodes the instruction corresponding to instruction address I+1, and determines whether the instruction corresponding to instruction address I+1 is a branch instruction. When the instruction corresponding to instruction address I+1 is a branch instruction and the branch instruction jumps, the branch predictor determines a target instruction address J, where J is an integer, and the instruction corresponding to instruction address J is not in the cache. The target instruction address J is sent to the instruction memory after arbitration by the address arbitrator. When the instruction address received by the instruction memory is the target instruction address J, the instruction fetching circuit reads the instructions corresponding to the target instruction address J to the instruction address J+P from the instruction memory and stores them in the cache. If the processor requests to access any instruction address among the target instruction address J to the instruction address J+P, the processor reads the instruction corresponding to the requested instruction address from the cache, where P is a positive integer greater than or equal to 1 and P is less than the maximum number of instructions that can be stored in the cache.

[0005] In some embodiments, the instruction fetch circuit further includes a multiplexer. If the cache contains the instruction corresponding to instruction address I, the instruction corresponding to instruction address I is provided to the processor via the multiplexer. If the cache does not contain the instruction corresponding to instruction address I, the instruction address I and the target instruction address J are arbitrated by the address arbitrator. First, the instruction address I is sent to the instruction memory. Instructions corresponding to instruction addresses I to I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from I to I+P, the instruction corresponding to the requested instruction address is read from the cache. Then, the target instruction address J is sent to the instruction memory. Instructions corresponding to target instruction addresses J to J+P are read from the instruction memory and stored in the cache. If the processor requests access to any instruction address from J to J+P, the processor reads the instruction corresponding to the requested instruction address from the cache.

[0006] In some embodiments, if the cache contains the instruction corresponding to instruction address I, the instruction corresponding to instruction address I is provided to the processor via the multiplexer. If the cache does not contain the instruction corresponding to instruction address I or the instruction corresponding to instruction address I+P+1, the instruction address I, the instruction address I+P+1, and the target instruction address J are arbitrated by the address arbitrator. First, the instruction address I is sent to the instruction memory. Then, the instructions corresponding to instruction addresses I to I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from I to I+P, it reads the instruction corresponding to the requested instruction address from the cache, then sends the instruction address I+P+1 to the instruction memory, and reads the instruction corresponding to the requested instruction address from the instruction memory. Instructions from instruction address I+P+1 to instruction address I+2P+1 are stored in the cache. If the processor requests access to any instruction address from I+P+1 to I+2P+1, the processor reads the instruction corresponding to the requested instruction address from the cache. Finally, the processor sends the target instruction address J to the instruction memory, reads the instructions from the instruction memory from the target instruction address J to instruction address J+P and stores them in the cache. If the processor requests access to any instruction address from J to J+P, the processor reads the instruction corresponding to the requested instruction address from the cache.

[0007] In some embodiments, the step size is P+1.

[0008] In some embodiments, P = 1 or 2.

[0009] In some embodiments, the cache includes multiple cache regions, each cache region being used to store an instruction and the instruction address of that instruction.

[0010] In some embodiments, the cache is a first-in-first-out (FIFO) cache.

[0011] In some embodiments, the cache is a static random access memory or a register, and the instruction memory is a non-volatile memory.

[0012] According to another aspect of the present invention, a control method for a microcontroller is provided. The microcontroller includes: a processor, an instruction memory, and an instruction fetch circuit. The microcontroller includes: a processor configured to issue instruction addresses; an instruction memory configured to store a plurality of instructions; and an instruction fetch circuit including a cache, a decoder, a branch predictor, and an address arbitrator. The operation method includes: the cache of the instruction fetch circuit receiving a request from the processor to access the current instruction address I, where I is an integer; if the cache stores an instruction corresponding to the next instruction address I+1 of the current instruction address I, the decoder retrieves the instruction corresponding to the instruction address I+1 from the cache, the decoder decodes the instruction corresponding to the instruction address I+1 and determines whether the instruction corresponding to the instruction address I+1 is a branch instruction, and the branch predictor, when the instruction corresponding to the instruction address I+1 is a branch instruction and the branch instruction jumps, determines a target instruction address J, where J is an integer, and the instruction address is... The instruction corresponding to address J is not in the cache; the target instruction address J is sent to the instruction memory after arbitration by the address arbitrator; when the instruction memory receives the instruction address as the target instruction address J, the instruction fetch circuit reads the instructions corresponding to the target instruction address J to the instruction address J+P from the instruction memory and stores them in the cache; if the processor requests to access any instruction address from the target instruction address J to the instruction address J+P, the processor reads the instruction corresponding to the requested instruction address from the cache, where P is a positive integer greater than or equal to 1 and P is less than the maximum number of instructions that can be stored in the cache.

[0013] In some embodiments, the instruction fetch circuit further includes a multiplexer. The operation method further includes: if the cache contains the instruction corresponding to instruction address I, the instruction corresponding to instruction address I is provided to the processor via the multiplexer; if the cache does not contain the instruction corresponding to instruction address I, the instruction address I and the target instruction address J are arbitrated by the address arbitrator, the instruction address I is first sent to the instruction memory, the instructions corresponding to instruction address I to instruction address I+P are read from the instruction memory and stored in the cache; if the processor requests any instruction address from instruction address I to instruction address I+P, the instruction corresponding to the requested instruction address is read from the cache, the target instruction address J is then sent to the instruction memory, the instructions corresponding to target instruction address J to instruction address J+P are read from the instruction memory and stored in the cache; if the processor requests access to any instruction address from target instruction address J to instruction address J+P, the processor reads the instruction corresponding to the requested instruction address from the cache.

[0014] In some embodiments, if the cache contains the instruction corresponding to instruction address I, the instruction corresponding to instruction address I is provided to the processor via the multiplexer; if the cache does not contain the instruction corresponding to instruction address I or the instruction corresponding to instruction address I+P+1, the instruction address I, the instruction address I+P+1, and the target instruction address J are arbitrated by the address arbitrator, the instruction address I is first sent to the instruction memory, the instructions corresponding to instruction address I to instruction address I+P are read from the instruction memory and stored in the cache, and if the processor requests any instruction address from instruction address I to instruction address I+P, the instruction corresponding to the requested instruction address is read from the cache, and then the instruction is... The processor sends instruction address I+P+1 to instruction address I+2P+1 from the instruction memory and stores the instructions in the cache. If the processor requests access to any instruction address from I+P+1 to I+2P+1, the processor reads the instruction corresponding to the requested instruction address from the cache. Finally, the processor sends the target instruction address J to the instruction memory and reads the instructions corresponding to the target instruction address J+P from the instruction memory and stores them in the cache. If the processor requests access to any instruction address from J to J+P, the processor reads the instruction corresponding to the requested instruction address from the cache.

[0015] In some embodiments, P = 1 or 2.

[0016] According to the microcontroller and control method of embodiments of the present invention, instructions are prefetched from the instruction memory using a combination of sequential prefetching and branch prediction. Before the processor executes a branch instruction, the instruction fetch circuit predicts the target instruction of the branch instruction and prefetches it from the instruction memory into the cache. By decoding and branch predicting the instruction corresponding to the next instruction address of the current instruction address requested by the processor and stored in the cache, in the case of a branch instruction jump, the target instruction address of the branch instruction jump can be determined in advance and the target instruction can be prefetched from the instruction memory into the cache. When the processor performs the instruction fetch operation for the target instruction, it can fetch the instruction from the cache, thereby improving the processor's instruction fetching speed.

[0017] Furthermore, the instruction memory has an extended output bit width. The instruction fetch circuit retrieves instructions corresponding to at least two consecutive instruction addresses from the instruction memory. Therefore, when retrieving the instruction corresponding to the currently requested instruction address from the instruction memory, the next instruction address of the currently requested instruction address is also stored in the cache. This allows for branch prediction of the instruction at the next instruction address of the currently requested instruction address.

[0018] Furthermore, the instruction fetch circuit sequentially prefetches the instructions corresponding to instruction addresses I+P+1 to I+2P+1. Before the processor requests instruction addresses I+P+1 to I+2P+1, it can access the instruction memory in advance to store the instructions from I+P+1 to I+2P+1 into the cache. Thus, when the processor requests instruction addresses I+P+1 to I+2P+1, it can directly read the instructions corresponding to the requested instruction addresses from the cache, thereby improving the processor's instruction fetch speed. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 This illustrates a microcontroller in the related art;

[0021] Figure 2 This illustrates an instruction sequence prefetching method in related technologies;

[0022] Figure 3 An exemplary microcontroller of the present invention is shown;

[0023] Figure 4 An exemplary instruction reading circuit of the present invention is shown;

[0024] Figure 5 An exemplary cache of the present invention is shown;

[0025] Figure 6 An exemplary address arbiter of the present invention is shown;

[0026] Figure 7A and Figure 7B The cached contents are shown after two instruction prefetch operations;

[0027] Figure 8 An exemplary address arbitration process is shown;

[0028] Figure 9 An exemplary operation method of the instruction readout circuit is shown;

[0029] Figure 10 An exemplary method of operating a microcontroller is shown;

[0030] Figure 11 The processing timing of multiple instruction addresses is shown;

[0031] Figure 12 The processor's instruction pipeline timing is shown;

[0032] Figures 13A to 13E It shows Figure 11 Changes in cached content corresponding to the operation methods. Detailed Implementation

[0033] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0034] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0035] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0036] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0037] Figure 1This is a schematic block diagram of a microcontroller based on related technologies. To improve the speed at which the processor fetches instructions from instruction memory, caches are set up in both the processor and instruction memory. While the processor is processing an already fetched instruction, the instruction corresponding to the sequential address is prefetched into the cache. If the processor determines that the instructions are sequential (i.e., the next instruction is a sequential instruction from the previous one) after executing the previous instructions, the processor can directly read the next instruction from the cache. Instruction prefetching reduces the processor's instruction fetching time overhead. Figure 2 This is a flowchart of instruction sequential prefetching in related technologies. The processor performs an instruction fetch operation, sending instruction address N to the cache. The processor accesses the cache, comparing instruction address N with the instruction address in the cache. If a cache hit occurs, the processor retrieves the instruction corresponding to instruction address N from the cache. Furthermore, it reads the instruction corresponding to instruction address N+1 from instruction memory and writes that instruction into the cache. It can be understood that instruction addresses N and N+1 are addresses recognized and used by the processor, which can be mapped to addresses recognized by instruction memory. If instruction address N is not found in the cache, instruction memory needs to be accessed to retrieve the instruction corresponding to instruction address N. Then, the instruction corresponding to instruction address N+1 is read from instruction memory and written into the cache. In the above method, when instructions are not executed sequentially, the processor's instruction fetch operation needs to wait for instruction memory read operations. When there are many branch instructions, sequential prefetching is inefficient, limiting processor performance.

[0038] Figure 3 An exemplary microcontroller of the present invention is illustrated. The microcontroller includes a processor 20, an instruction memory 30, and an instruction fetch circuit 10. The processor 20 sends a fetch request and an instruction address to the instruction fetch circuit 10, and the instruction fetch circuit 10 provides the corresponding instruction to the processor. The processor 20 is configured to execute the instruction. The instruction memory 30 is a non-volatile memory used to store instructions. Non-volatile memory may be, for example, flash memory, resistive random access memory (RRAM), ferroelectric RAM, magnetic random access memory (MRAM), phase-change RAM (PCRAM), etc. Flash memory may be NOR Flash or NAND Flash. The microcontroller may also include one or more of sensors, analog-to-digital converters, and counters.

[0039] Processor 20 is, for example, a central processing unit based on an ARM or RISC-V core. Processor 20 may include an instruction address register, an instruction register, a data register, an arithmetic logic unit (ALU), a control unit, etc. The instruction address register, also known as the program counter, is used to store instruction addresses. The instruction address is, for example, a binary number. By incrementing the program counter by 1, instruction address I becomes instruction address I+1. Instruction memory 30 includes multiple memory locations, which are addressed using memory addresses. Memory addresses are used to identify the storage location of data in instruction memory 30. Instruction addresses can be converted to memory addresses using a mapping table.

[0040] The instruction processing process of processor 20 includes a fetch stage, a decode stage, and an execute stage. In the fetch stage, processor 20 sends a fetch request and instruction address to instruction fetch circuit 10 based on the instruction address in instruction address register. Instruction fetch circuit 10 then provides processor 20 with the instruction corresponding to the instruction address. Processor 20 processes instructions in a pipelined manner. For example, processor 20 executes instruction fetch for instruction n+1 simultaneously during the decode operation of instruction n, and executes instruction decode for instruction n+1 and instruction fetch for instruction n+2 simultaneously during the execute operation of instruction n. The sequential fetching of instructions n, n+1, and n+2 is achieved by incrementing the program counter. For branch instructions, processor 20 only knows the next instruction to be executed after its execution stage is completed and modifies the value in instruction address register. Instruction fetch circuit 10 is used for instruction fetching operations of processor 20. In this invention, instruction fetch circuit 10 performs branch prediction on branch instructions before processor 20 executes them and prefetches instructions from instruction memory 30 based on the prediction result. The branch predictor predicts the jump direction and the target instruction address. The jump direction includes "taken" and "not taken". If the jump direction of the instruction corresponding to instruction address I is "not taken", the target instruction address is instruction address I+1. In this article, a branch instruction with a "not taken" jump direction is simply referred to as a "non-jump branch instruction", and a branch instruction with a "jump" jump direction is simply referred to as a "jump branch instruction".

[0041] In some embodiments, the processor 20, instruction memory 30, and instruction fetch circuitry 10 are fabricated on the same wafer. The instruction memory 30 is also referred to as embedded or on-chip memory. In other embodiments, the processor 20 and instruction fetch circuitry 10 are fabricated on the same wafer, while the instruction memory 30 is fabricated on a different wafer. The processor 20 and instruction memory 30 are manufactured using different processes; fabricating them on different wafers allows both the processor 20 and instruction memory 30 to be manufactured using suitable processes.

[0042] Figure 4 An exemplary instruction fetch circuit of the present invention is shown. The instruction fetch circuit 10 includes: a cache 100, a decoder 300, a branch predictor 500, an address arbiter 700, and a multiplexer 900. When the processor 20 performs an instruction fetch operation on the current instruction address I, the processor 20 sends a request for instruction address I to the instruction fetch circuit 10. The cache 100 of the instruction fetch circuit 10 receives the request from the processor to access the current instruction address I, where I is an integer. The decoder 300 retrieves the instruction corresponding to the next instruction address I+1 after the current instruction address I from the cache 100 and decodes it. The branch predictor 500 determines whether the instruction corresponding to instruction address I+1 is a branch instruction; when the instruction corresponding to instruction address I+1 is a branch instruction, the branch predictor 500 further determines whether the branch instruction jumps and determines the target instruction address J, where J is an integer, and the instruction corresponding to instruction address J is not in the cache. The instruction fetch circuit 10 reads the instructions corresponding to the target instruction address J to instruction address J+P from the instruction memory 30 and stores them in the cache 100.

[0043] Cache 100 is, for example, static random access memory (SRAM) or registers. Compared to instruction memory 30, cache 100 has a faster read and write speed. Figure 5 An exemplary cache 100 of the present invention is shown. Cache 100 includes multiple cache regions, each cache region storing an instruction address and the corresponding instruction, which is retrieved from the instruction memory 30. Figure 5 In the illustrated embodiment, cache 100 includes cache regions 111-116, each used to store a set of instructions and addresses. The number of cache regions in cache 100 is not limited to 6, but can be any other integer greater than 6. Instruction memory 30 has an extended output bit width. Therefore, each time instruction fetch circuit 10 accesses instruction memory 30, instruction fetch circuit 10 retrieves instructions corresponding to at least two consecutive instruction addresses from instruction memory 30. For example, each time instruction memory 30 is accessed, instruction fetch circuit 10 retrieves instructions corresponding to P+1 consecutive instruction addresses from instruction memory 30, where P+1 is the step size. P is a positive integer greater than or equal to 1, and P is less than the maximum number of instructions that cache 100 can store. P is, for example, equal to 1 or 2. Cache 100 is, for example, a first-in, first-out cache. Instructions retrieved by instruction fetch circuit 10 from instruction memory 30 are written into cache 100. Figure 7A and Figure 7BThe diagram shows cache 100 after two write operations (cache areas 115 and 116 are omitted). For example, after the first write operation, instruction n and its corresponding instruction address N are stored in cache area 112, and instruction n+1 and its corresponding instruction address N+1 are stored in cache area 111. After the second write operation, instruction n and its corresponding instruction address N are moved to cache area 114, instruction n+1 and its corresponding instruction address N+1 are moved to cache area 113, instruction m and its corresponding instruction address M are stored in cache area 112, and instruction m+1 and its corresponding instruction address M+1 are stored in cache area 111.

[0044] The instruction fetch circuit 10 obtains instruction address I from the processor 20 and compares instruction address I with the instruction address stored in cache 100. If instruction address I is in cache 100, the instruction fetch circuit 10 sends the instruction corresponding to instruction address I stored in cache 100 to the processor 20. If instruction address I is not in cache 100, the instruction fetch circuit 10 reads the instruction corresponding to instruction address I from instruction memory 30.

[0045] The instruction fetch circuit 10 also prefetches the corresponding instruction address I+P+1 according to the instruction address I in the order generated, and compares the instruction address I+P+1 with the instruction address in the cache 100.

[0046] The instruction read circuit 10 includes, for example, an address comparator, which is used to perform address comparison. The address comparator can be implemented using digital circuitry.

[0047] Decoder 300 decodes instructions retrieved from cache 100. Branch predictor 500 determines whether the decoded instruction is a branch instruction, and if so, determines whether to jump and the target instruction address J. Branch predictor 500 can be, for example, a history-based branch predictor, a local / global branch predictor, a static branch predictor, a dynamic branch predictor, a bimodal branch predictor, etc. In some embodiments, decoder 300 and branch predictor 500 are implemented through a single circuit module.

[0048] Each time the instruction memory 30 is accessed, the number of instructions read from the instruction memory 30 is equal to the step size P+1, which depends on the output bit width of the instruction memory 30. The instruction memory 30 of the present invention has an extended output bit width, and each access can output instructions corresponding to at least two consecutive instruction addresses.

[0049] The instruction fetch circuit 10 accesses the instruction memory 30 according to the instruction address C. The instruction address C is determined by the address arbitrator 700. For example, the address arbitrator 700 selects the instruction address C from instruction address I, instruction address I+P+1, and target instruction address J. Figure 6As shown, the exemplary address arbitrator 700 includes a multiplexer and control circuitry. The control circuitry determines, based on signals 1-3, whether the output address C is instruction address I, instruction address I+P+1, or the target instruction address J. Signal 1 indicates whether instruction address I was hit in cache 100. Signal 2 indicates whether instruction address I+P+1 was hit in cache 100. Signal 3 indicates whether the instruction corresponding to instruction address I+1 is a branch instruction with a jump. The instruction fetch circuit 10 performs a prefetch operation based on instruction address C, fetching instructions from instruction memory 30 and storing them in cache 100. During each prefetch operation, P+1 consecutive instructions are fetched from instruction memory 30, starting at address C.

[0050] Multiplexer 900 is controlled by signal 1. When signal 1 indicates that instruction address I has been hit in cache 100, processor 20 reads the instruction corresponding to instruction address I from cache 100. When signal 1 indicates that instruction address I has not been hit in cache 100, processor 20 reads the instruction corresponding to instruction address I from instruction memory 30.

[0051] Figure 8 An exemplary address arbitration process is illustrated. Each time the instruction fetch circuit 10 receives an instruction address from the processor 20, it performs one execution cycle as one duty cycle of the instruction fetch circuit 10. Figure 8 The address arbitration process is shown below. The example given is where the instruction fetch circuit 10 receives a request from the processor 20 to access the current instruction address I.

[0052] In step S01, it is determined whether instruction address I is hit in cache 100. For example, instruction address I can be compared with the instruction address in cache 100 using an address comparator.

[0053] If instruction address I is not in cache 100, signal 1 indicates that instruction address I was not hit in cache 100, and address C output by address arbitrator 700 is instruction address I. In step S02, the instruction memory 30 is accessed, and the instructions corresponding to instruction addresses I to I+P are read from the instruction memory 30. Instruction addresses I to I+P are P+1 consecutive instruction addresses: instruction address I, instruction address I+1, ..., instruction address I+P. The instructions corresponding to instruction addresses I to I+P are stored in cache 100. If processor 20 requests any instruction address from instruction address I to instruction address I+P, it can read the instruction corresponding to the requested instruction address from cache 100. The instruction corresponding to instruction address I is sent to processor 20 through multiplexer 900, processor 20 completes instruction fetching for instruction address I, and proceeds to step S03.

[0054] If instruction address I is present in cache 100, processor 20 reads the instruction corresponding to instruction address I from cache 100, processor 20 completes instruction fetching for instruction address I, and proceeds to step S03.

[0055] In step S03, it is determined whether instruction address I+P+1 is hit in cache 100. For example, an address comparator can be used to compare instruction address I+P+1 with the instruction address in cache 100. In some embodiments, the instruction fetch circuit 10 includes two address comparators: one for comparing instruction address I with the instruction address in cache 100 and generating signal 1, and the other for comparing instruction address I+P+1 with the instruction address in cache 100 and generating signal 2.

[0056] If instruction address I+P+1 is not in cache 100, signal 2 indicates that instruction address I+P+1 was not hit in cache 100, and address C output by address arbitrator 700 is instruction address I+P+1, then step S04 is executed. In step S04, instruction memory 30 is accessed, and the instructions corresponding to instruction addresses I+P+1 to I+2P+1 are read from instruction memory 30 and stored in cache 100. Signal 2 changes to the level indicating that instruction address I+P+1 was hit in cache 100, sequential prefetching is completed, and step S05 is executed. Instruction addresses I+P+1 to I+2P+1 are P+1 consecutive instruction addresses: instruction address I+P+1, instruction address I+P+2, ..., instruction address I+2P+1. If processor 20 requests access to any instruction address among instruction addresses I+P+1 to I+2P+1, processor 20 reads the instruction corresponding to the requested instruction address from cache 100.

[0057] If the instruction address I+P+1 is in cache 100, step S04 is not required; proceed to step S05.

[0058] In step S05, it is determined whether the instruction corresponding to instruction address I+1 is a branch instruction. If the instruction corresponding to instruction address I+1 is a branch instruction, it is further predicted whether to jump and the target instruction address J. Step S05 is completed by decoder 300 and branch predictor 500. For example, decoder 300 obtains the instruction corresponding to instruction address I+1 from cache 100 and decodes the instruction. Branch predictor 500, based on the decoded instruction, determines whether the instruction corresponding to instruction address I+1 is a branch instruction, determines whether to jump, and predicts the target instruction address J. If the instruction corresponding to instruction address I+1 is a branch instruction and jumps, signal 3 indicates that the instruction corresponding to instruction address I+1 jumps, and the address C output by address arbitrator 700 is the target instruction address J.

[0059] In step S06, the instruction memory 30 is accessed, and the instructions corresponding to the target instruction addresses J to J+P are read from the instruction memory 30 and stored in the cache 100. Instruction addresses J to J+P are P+1 consecutive instruction addresses: instruction address J, instruction address J+1, ..., instruction address J+P. If the processor 20 requests access to any instruction address among the target instruction addresses J to J+P, the processor 20 reads the instruction corresponding to the requested instruction address from the cache 100.

[0060] exist Figure 8 In the illustrated embodiment, step S03 is performed first, and step S04 is performed based on the judgment result. After storing the instructions corresponding to instruction addresses I+P+1 to I+2P+1 into cache 100 (for example, after a change in the level of signal 2), step S05 is performed, and step S06 is performed based on the judgment result. In an optional embodiment, while performing steps S03 and S04, decoder 300 and branch predictor 500 perform decoding of the instruction corresponding to instruction address I+1, branch prediction judgment, and prediction of the target instruction address J (step S05). After storing the instructions corresponding to instruction addresses I+P+1 to I+2P+1 into cache 100 (after step S04 is completed), step S06 is performed.

[0061] When signal 1 is high ("1"), it indicates that instruction address I was not hit in cache 100; when signal 1 is low ("0"), it indicates that instruction address I was hit in cache 100. After step S02 is executed, signal 1 changes from 1 to 0. When signal 2 is high ("1"), it indicates that instruction address I+P+1 was not hit in cache 100; when signal 2 is low ("0"), it indicates that instruction address I+P+1 was hit in cache 100. After step S04 is executed, signal 2 changes from 1 to 0. When signal 3 is high ("1"), it indicates that the instruction corresponding to instruction address I+1 is a branch instruction with a jump; when signal 3 is low ("0"), it indicates that the instruction corresponding to instruction address I+1 is not a branch instruction, or the instruction corresponding to instruction address I+1 is a branch instruction without a jump. The address arbitrator 700 determines the output address C based on signals 1-3. The instruction fetch circuit 10 first determines whether signal 1 is 1 or 0. When signal 1 is 1, regardless of whether signals 2 and 3 are 1 or 0, the instruction reading circuit 10 executes step S2. After signal 1 becomes 0, if signal 2 is 1, step S04 is executed; if signal 3 is 1, step S06 is executed.

[0062] In another embodiment, the address arbitration process includes steps S01-S02 and steps S05 and S06, but excludes steps S03-S04. When the processor 20 completes the fetch of instruction address I, it proceeds to step S05.

[0063] Figure 9An exemplary operation method of the instruction read circuit 10 is shown. (Refer to...) Figure 4 and 9 The operation method of the instruction fetch circuit 10 includes the following steps. Each time the instruction fetch circuit receives an instruction address from the processor 20, the instruction fetch circuit 10 executes... Figure 9 The operating method is shown.

[0064] In step S101, the instruction fetch circuit 10 receives instruction address I from the processor 20. Specifically, the cache 100 of the instruction fetch circuit 10 receives a request from the processor 20 to access the current instruction address I.

[0065] Step S102: Determine whether instruction address I is stored in cache 100. For example, compare each instruction address in cache 100 with instruction address I to determine whether instruction address I is stored in cache 100. If instruction address I is in cache 100, the instruction corresponding to instruction address I stored in cache 100 is sent to processor 20 through multiplexer 900. If instruction address I is not in cache 100, proceed to step S103.

[0066] In step S103, the instruction memory 300 is accessed, and the instructions corresponding to instruction addresses 1 to 1+P are read from the instruction memory 300 and stored in the cache 100. The instruction corresponding to instruction address 1 is sent to the processor 20 via the multiplexer 900. Thus, if the processor 20 requests any instruction address from instruction address 1 to instruction address 1+P, the processor 20 can read the instruction corresponding to the requested instruction address from the cache 100.

[0067] In step S104, processor 20 fetches the instruction corresponding to instruction address I.

[0068] Step S105: Determine whether the instruction address I+P+1 is stored in cache 100. For example, compare each instruction address in cache 100 with instruction address I+P+1 to determine whether instruction address I+P+1 is stored in cache 100. If instruction address I+P+1 is not stored in cache 100, proceed to step S106.

[0069] Step S106: Access instruction memory 300, read the instructions corresponding to instruction addresses I+P+1 to I+2P+1 from instruction memory 300 and store the instructions in cache 100. Thus, if processor 20 requests access to any instruction address from I+P+1 to I+2P+1, processor 20 reads the instruction corresponding to the requested instruction address from cache 100.

[0070] In step S107, the decoder 300 retrieves the instruction corresponding to instruction address I+1 from the cache 100 and decodes the instruction corresponding to instruction address I+1.

[0071] In step S108, the branch predictor 500 obtains the decoded instruction and determines whether the instruction corresponding to instruction address I+1 is a branch instruction. If the branch predictor 500 determines that the instruction corresponding to instruction address I+1 is a branch instruction, step S109 is executed.

[0072] In step S109, the branch predictor 500 determines whether a jump has occurred in the instruction corresponding to instruction address I+1. If a jump has occurred in the instruction corresponding to instruction address I+1, step S110 is executed.

[0073] In step S110, the branch predictor 500 determines the target instruction address J when the instruction corresponding to instruction address I+1 jumps.

[0074] Step S111: Access instruction memory 300, read the instructions corresponding to instruction addresses J to J+P from instruction memory 300 and store the instructions in cache 100. Thus, if processor 20 requests access to any instruction address from target instruction address J to instruction address J+P, processor 20 reads the instruction corresponding to the requested instruction address from cache 100.

[0075] Figure 10 An exemplary method of operating a microprocessor is illustrated. This method of operation is performed in cooperation with a processor 20, an instruction fetch circuit 10, and an instruction memory 30. Figure 10 In the diagram, steps S203-S206 within the red dashed box are executed by the processor 20, while other steps are executed by the instruction fetch circuit 10. This operation method, for example, begins at the instruction fetch stage of instruction address I. During the instruction fetch stage of instruction address I, the processor 20 sends a request to access instruction address I to the instruction fetch circuit 10.

[0076] Step S201: Determine whether instruction address I is in cache 100 by accessing cache 100.

[0077] If instruction address I is hit in cache 100, proceed to step S202.

[0078] If instruction address I is not hit in cache 100, proceed to step S212. In step S212, access instruction memory 30 and read the instructions corresponding to instruction addresses I to I+P. The instructions corresponding to instruction addresses I to I+P are stored in cache 100 (step S211).

[0079] In step S202, processor 20 receives the instruction corresponding to instruction address I, and the instruction fetch operation corresponding to instruction address I is completed. If instruction address I is hit in cache 100, processor 20 retrieves the instruction corresponding to instruction address I from cache 100. If instruction address I is not hit in cache 100, the instruction corresponding to instruction address I read from instruction memory 30 in step S212 is sent to processor 20. Steps S202 and S211 can be performed simultaneously.

[0080] In step S203, the processor 20 decodes the instruction corresponding to instruction address I. That is, the decoding stage of the instruction corresponding to instruction address I.

[0081] In step S204, the processor 20 sends the instruction address I+1 to the instruction fetch circuit 10 for sequential instruction fetching. That is, the instruction fetching stage begins for the instruction corresponding to instruction address I+1. The instruction address I+1 is obtained by incrementing the value in the instruction counter. Since the processor 20 processes instructions in a pipelined manner, steps S203 and S204 are performed simultaneously.

[0082] In step S205, processor 20 executes the instruction corresponding to instruction address I. That is, the execution phase of the instruction corresponding to instruction address I. During the execution phase, processor 20 determines whether the instruction corresponding to instruction address I is a branch instruction. After the instruction corresponding to instruction address I is executed, processor 20 can determine whether the branch instruction should jump or not. If the branch instruction does not jump, the next instruction address to be processed is I+1. If the branch instruction jumps, the operations related to step S204 are discarded, and processor 20 determines the target instruction address J' of the jump from instruction address I based on the execution result of the instruction corresponding to instruction address I.

[0083] In step S206, the processor 20 sends the target instruction address J' to the instruction fetch circuit 10 to perform a jump instruction fetch.

[0084] When the processor 20 decodes and executes the instruction corresponding to instruction address I (steps S203 and S205), the instruction fetch circuit 10 performs sequential prefetching based on step size P+1, determines whether the instruction corresponding to instruction address I+1 is a branch instruction and whether it requires a jump, predicts the target instruction address J of the jump of the instruction corresponding to instruction address I+1, and performs jump prefetching based on the target instruction address J. For example, after the instruction fetching of instruction address I is completed (step S202), step S207 is executed.

[0085] Step S207 involves pre-decoding the instruction corresponding to instruction address I+1. Specifically, the decoder 300 of the instruction fetch circuit 10 reads the instruction corresponding to instruction address I+1 from the cache 100 and decodes it. Steps S207 and S203 are performed simultaneously. Step S207 is executed by the decoder 300 of the instruction fetch circuit 10, and step S203 is executed by the processor 20.

[0086] The branch predictor 300 of the instruction fetch circuit 10 receives the decoded instruction and determines whether the instruction corresponding to instruction address I+1 is a branch instruction. When the instruction corresponding to instruction address I+1 is a branch instruction, the branch predictor 300 determines whether the instruction corresponding to instruction address I+1 should jump. When the instruction corresponding to instruction address I+1 is a branch instruction and jumps, step S208 is executed.

[0087] In step S208, the branch predictor 300 predicts the target instruction address J.

[0088] In step S213, the instruction fetch circuit 10 calculates the sequential prefetch of the corresponding instruction address I+P+1 based on the received instruction address I and step size P+1. It can be understood that after receiving instruction address I from processor 20, the instruction fetch circuit 10 can calculate the sequential prefetch of the corresponding instruction address I+P+1.

[0089] Step S209: Perform address arbitration to determine the address C used by the instruction memory 30.

[0090] For example, if signal 2 indicates that instruction address I+P+1 was not hit in cache 100, then address C is instruction address I+P+1. If signal 3 indicates that the instruction corresponding to instruction address I+1 is a branch instruction and a jump occurs, then address C is the target instruction address J.

[0091] Step S210: Access instruction memory 30 according to address C.

[0092] Step S211: Store the read instruction into cache 100.

[0093] In this embodiment, based on the timing sequence of signals 2 and 3, address arbitration is used to sequentially prefetch based on instruction address I+P+1 and then perform a jump region based on instruction address J. For example, first, instruction memory 30 is accessed based on instruction address I+P+1, the instructions corresponding to instruction address I+P+1 to instruction address I+2P+1 are read and stored in cache 100, and then instruction memory 30 is accessed based on target instruction address J, the instructions corresponding to instruction address J to instruction address J+P are read and stored in cache 100.

[0094] After processor 20 sends instruction address I+1 to instruction fetch circuit 10 (step S204), instruction fetch circuit 10 executes steps S201-S202 and S207-S213 in response to instruction address I+1. After receiving the instruction corresponding to instruction address I+1 (step S202), processor 20 executes steps S203-S206 corresponding to instruction address I+1. If the instruction corresponding to instruction address I+1 is a branch instruction that involves a jump, processor 20 determines the target instruction address J for the jump of the instruction corresponding to instruction address I+1 in step S206. Figure 10 In step S206, instruction address J'; in step S204, instruction address I+1; in step S207, instruction address I+1; in step S213, instruction address I+P; and in step S208, instruction address J is the instruction address involved in the process corresponding to instruction address I. That is, after the processor 20 sends instruction address I to the instruction fetch circuit 10, Figure 10 The method shown may involve instruction addresses.

[0095] Steps S207-S213 based on instruction address I are completed before step S206 based on instruction address I+1. Thus, when cache 100 is accessed based on instruction address J, instruction address J can be hit in cache 100, reducing the instruction fetch time for instruction address J.

[0096] Steps S212 and S211 based on instruction address I are completed before the instruction fetch request for instruction address I+1. Thus, when accessing cache 100 to fetch an instruction based on instruction address I+1, instruction address I+1 can be hit in cache 100, reducing the fetch time for instruction address I+1. The timing of the microcontroller processing multiple instruction addresses according to another embodiment of the present invention is described below. The processor 20 executes instructions corresponding to multiple instruction addresses in a pipelined manner. Figure 11 It is the processing timing of multiple instruction addresses. Figure 12 The pipeline timing of instructions processed by processor 20 is shown. Figures 13A to 13E The changes in the content stored in cache 100 are shown.

[0097] In the example, instruction addresses I0-I10 are consecutive instruction addresses, where instruction address I0 is the first instruction, with a step size P+1 = 2. Instruction D1 corresponding to instruction address I1 is a branch instruction that causes a jump; the instructions at other instruction addresses are either non-branch instructions or branch instructions that do not cause a jump. Instruction address I8 is the target instruction address for the jump of instruction D1. For example... Figure 12As shown, after instruction D1 corresponding to instruction address I1 is executed, processor 20 will know that the jump target instruction address of instruction D1 is I8, and will fetch the instruction based on instruction address I8 in the next instruction fetch operation. Although processor 20 performs instruction fetch operations for the instructions corresponding to instruction address I2 and instruction address I3, it does not execute these two instructions, or discards the execution results of these two instructions.

[0098] First, the instruction fetch operation for instruction address I0 is performed. In clock cycle 2, processor 20 sends a read request and instruction address I0 to instruction fetch circuit 10. Instruction fetch circuit 10 compares instruction address I0 with the instruction address in cache 100 and determines that instruction address I0 is not in cache 100. The address C output by address arbitrator 700 is the instruction address I0.

[0099] During clock cycles 3 and 4, read operations are performed on instruction memory 30 to obtain instruction D0 corresponding to instruction address I0 and instruction D1 corresponding to instruction address I1. Processor 20 obtains instruction D0 corresponding to instruction address I0 in clock cycle 5, completing the instruction fetch phase for instruction address I0. Instructions D0 and D1 read from instruction memory 30 are stored in cache 100. Specifically, refer to... Figure 11 and Figure 13A During clock cycles 5 and 6, instruction address I0 and instruction D0 are stored in cache area 112, and instruction address I1 and instruction D1 are stored in cache area 111.

[0100] After instruction fetching at instruction address I0 is completed, instruction fetch circuit 10 determines the corresponding instruction address I2 to be prefetched sequentially based on prefetch step size P+1 = 2. Instruction fetch circuit 10 compares instruction address I2 with the instruction address in cache 100, and determines that instruction address I2 is not in cache 100, therefore sequential prefetching is required. The address C output by address arbitrator 700 is instruction address I2. Instruction D2 corresponding to instruction address I2 and instruction D3 corresponding to instruction address I3 are read from instruction memory 30 and stored in cache 100. Specifically, refer to... Figure 11 and Figure 13B During clock cycles 7 and 8, instruction address I0 and instruction D0 are stored in cache area 114, instruction address I1 and instruction D1 are stored in cache area 113, instruction address I2 and instruction D2 are stored in cache area 112, and instruction address I3 and instruction D3 are stored in cache area 111.

[0101] Decoder 300 reads instruction D1 corresponding to instruction address I1 from cache 100. Branch predictor 500 determines that instruction D1 is a branch instruction requiring a jump, and a jump prefetch needs to be performed. Branch predictor 500 predicts the target instruction address J to be I8. Address arbitrator 700 outputs address C as instruction address I8. Instructions D8 corresponding to instruction address I8 and instruction D9 corresponding to instruction address I9 are read from instruction memory 30 and stored in cache 100. Specifically, refer to... Figure 11 and Figure 13C During clock cycles 9 and 10, instruction addresses I0 and D0 are stored in cache area 116, instruction addresses I1 and D1 are stored in cache area 115, instruction addresses I2 and D2 are stored in cache area 114, instruction addresses I3 and D3 are stored in cache area 113, instruction addresses I8 and D8 are stored in cache area 112, and instruction addresses I9 and D9 are stored in cache area 111.

[0102] After clock cycles 2-5, the instruction fetch stage for instruction address I0 is completed. The instruction fetch circuit 10 performs three checks during clock cycles 2-8 (whether instruction address I0 is hit in cache 100, whether instruction address I2 is hit in cache, and whether instruction D1 corresponding to instruction address I1 is a branch instruction that jumps to another instruction) and accesses instruction memory 30 three times based on the check results.

[0103] In clock cycle 6, processor 20 sequentially fetches instruction I1, sending a read request and instruction address I1 to instruction fetch circuit 10. For example... Figure 12 As shown, processor 20 processes the instruction stream in a pipelined manner. After the instruction fetch operation at instruction address I0 is completed, processor 20 simultaneously performs the decoding operation of instruction D0 corresponding to instruction address I0 and the instruction fetch operation at instruction address I1. Instruction fetch circuit 10 receives the request for instruction address I1. Instruction fetch circuit 10 compares instruction address I1 with the instruction address in cache 100 and hits instruction address I1 in cache 100. In clock cycle 7, processor 20 fetches instruction D1 corresponding to instruction address I1 from cache 100, and the instruction fetch stage of instruction address I1 is completed.

[0104] like Figure 12As shown, after the instruction fetch operation at instruction address I1 is completed, processor 20 simultaneously performs the decoding operation of instruction D1 corresponding to instruction address I1 and the instruction fetch operation at instruction address I2. Simultaneously, instruction fetch circuit 10 also performs sequential prefetch and branch prediction based on instruction address I1. Instruction fetch circuit 10 determines the instruction address I3 corresponding to sequential prefetch according to the prefetch step size P+1 = 2. Instruction fetch circuit 10 compares instruction address I3 with the instruction address in cache 100 and determines that instruction address I3 is present in cache 100, therefore sequential prefetch is not required. Decoder 300 reads instruction D2 corresponding to instruction address I2 from cache 100. Branch predictor 500 determines that instruction D2 corresponding to instruction address I2 is a non-branch instruction or a branch instruction that does not involve a jump, therefore jump prefetch is not required.

[0105] In clock cycle 8, processor 20 sequentially fetches instruction I2, sending a read request and instruction address I2 to instruction fetch circuit 10. Instruction fetch circuit 10 hits instruction address I2 in cache 100. In clock cycle 9, processor 20 retrieves instruction D2 corresponding to instruction address I2 from cache 100, completing the instruction fetch phase for instruction address I2.

[0106] After instruction fetching at instruction address I2 is completed, instruction fetch circuit 10 determines the corresponding instruction address I4 for sequential prefetching based on prefetch step size P+1 = 2. Instruction fetch circuit 10 compares instruction address I4 with the instruction address in cache 100. Instruction address I4 is not found in cache 100, therefore sequential prefetching is required. The address C output by address arbitrator 700 is instruction address I4. Instruction D4 corresponding to instruction address I4 and instruction D5 corresponding to instruction address I5 are read from instruction memory 30 and stored in cache 100. Specifically, refer to... Figure 11 and Figure 13D During clock cycles 11 and 12, instruction address I2 and instruction D2 are stored in cache area 116, instruction address I3 and instruction D3 are stored in cache area 115, instruction address I8 and instruction D8 are stored in cache area 114, instruction address I9 and instruction D9 are stored in cache area 113, instruction address I4 and instruction D4 are stored in cache area 112, and instruction address I5 and instruction D5 are stored in cache area 111.

[0107] Decoder 300 reads instruction D3 corresponding to instruction address I3 from cache 100. Branch predictor 500 determines that instruction D3 corresponding to instruction address I3 is a non-branch instruction or a branch instruction that does not involve a jump, therefore no jump prefetch is required.

[0108] In clock cycle 10, processor 20 sequentially fetches instruction I3, sending a read request and instruction address I3 to instruction fetch circuit 10. Instruction fetch circuit 10 hits instruction address I3 in cache 100. In clock cycle 11, processor 20 retrieves instruction D3 corresponding to instruction address I3 from cache 100, completing the instruction fetch phase for instruction address I3.

[0109] After instruction fetching at instruction address I3 is completed, instruction fetch circuit 10 compares instruction address I5 with the instruction address in cache 100, and determines that instruction address I5 is present in cache 100, therefore sequential prefetching is not required. Decoder 300 reads instruction D4 corresponding to instruction address I4 from cache 100. Branch predictor 500 determines that instruction D4 corresponding to instruction address I4 is a non-branch instruction or a branch instruction that does not involve a jump, therefore jump prefetching is not required.

[0110] like Figure 12 As shown, during the instruction fetch phase at instruction address I3, processor 20 simultaneously executes instruction D1 corresponding to instruction address I1. After executing instruction D1, processor 20 determines that the jump target address of instruction D1 is I8. In clock cycle 12, processor 20 sends a read request and instruction address I8 to instruction fetch circuit 10. Instruction fetch circuit 10 hits instruction address I8 in cache 100. In clock cycle 13, processor 20 fetches instruction D8 corresponding to instruction address I8 from cache 100, completing the instruction fetch phase for instruction address I8.

[0111] If the instruction fetch circuit 10 does not perform branch prediction for instruction D1 in advance, and the instruction D8 corresponding to instruction address I8 is not in the cache 100, the instruction memory 30 needs to be accessed to obtain the instruction D8 corresponding to instruction address I8, which requires more time overhead and causes the pipeline to pause.

[0112] After instruction fetching at instruction address I8 is completed, instruction fetch circuit 10 determines the sequential prefetching of the corresponding instruction address I10 based on the prefetch step size P+1 = 2. Instruction fetch circuit 10 compares instruction address I10 with the instruction address in cache 100. Instruction address I10 is not found in cache 100, therefore sequential prefetching is required. The address C output by address arbitrator 700 is instruction address I10. Instruction D10 corresponding to instruction address I10 and instruction D11 corresponding to instruction address I11 are read from instruction memory 30 and stored in cache 100. Specifically, refer to... Figure 11 and Figure 13EDuring clock cycles 15 and 16, instruction addresses I8 and D8 are stored in cache area 116, instruction addresses I9 and D9 are stored in cache area 115, instruction addresses I4 and D4 are stored in cache area 114, instruction addresses I5 and D5 are stored in cache area 113, instruction addresses I10 and D10 are stored in cache area 112, and instruction addresses I11 and D11 are stored in cache area 111.

[0113] Decoder 300 reads instruction D9 corresponding to instruction address I9 from cache 100. Branch predictor 500 determines that instruction D9 corresponding to instruction address I9 is ​​a non-branch instruction or a branch instruction that does not cause a jump, therefore no jump prefetch is required.

[0114] In clock cycle 14, processor 20 sequentially fetches instruction I9, sending a read request and instruction address I9 to instruction fetch circuit 10. Instruction fetch circuit 10 hits instruction address I9 in cache 100. In clock cycle 15, processor 20 retrieves instruction D9 corresponding to instruction address I9 from cache 100, completing the instruction fetch phase for instruction address I9.

[0115] After instruction fetching at instruction address I9 is ​​completed, instruction fetch circuit 10 hits instruction address I11 in cache 100, so sequential prefetching is not required.

[0116] Decoder 300 reads instruction D10 corresponding to instruction address I10 from cache 100. Branch predictor 500 determines that instruction D10 is a non-branch instruction or a branch instruction that does not involve a jump, therefore no jump prefetch is required.

[0117] In clock cycle 16, processor 20 sequentially fetches instruction I10, sending a read request and instruction address I10 to instruction fetch circuit 10. Instruction fetch circuit 10 hits instruction address I10 in cache 100. In clock cycle 17, processor 20 fetches instruction D10 corresponding to instruction address I10 from cache 100, completing the instruction fetch phase for instruction address I10.

[0118] In the above embodiment, fetching instruction D0 requires 4 clock cycles. Figure 11 The pipeline operates on clock cycles 2-5. Other instruction addresses require 2 cycles to fetch, while the target instruction D8 of branch instruction D1 only requires 2 cycles to fetch. The pipeline is uninterrupted, reducing the fetch time when branch instructions occur.

[0119] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A microcontroller, comprising: The processor issues the instruction address; Instruction memory stores a number of instructions; as well as The instruction fetch circuit includes a buffer, a decoder, a branch predictor, and an address arbitrator. Wherein, the cache of the instruction fetch circuit receives a request from the processor to access the current instruction address I, where I is an integer; If the cache stores the instruction corresponding to the next instruction address I+1 of the current instruction address I, the decoder retrieves the instruction corresponding to instruction address I+1 from the cache, the decoder decodes the instruction corresponding to instruction address I+1 and determines whether the instruction corresponding to instruction address I+1 is a branch instruction, and the branch predictor determines the target instruction address J when the instruction corresponding to instruction address I+1 is a branch instruction and the branch instruction jumps, where J is an integer and the instruction corresponding to instruction address J is not in the cache; If the instruction corresponding to instruction address I is not in the cache, the instruction address I and the target instruction address J are arbitrated by the address arbitrator. First, the instruction address I is sent to the instruction memory. Then, the instructions corresponding to instruction address I to instruction address I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from instruction address I to instruction address I+P, the instruction corresponding to the requested instruction address is read from the cache. Then, the target instruction address J is sent to the instruction memory. The instruction fetch circuit reads the instructions corresponding to target instruction address J to instruction address J+P from the instruction memory and stores them in the cache. If the processor requests access to any instruction address from target instruction address J to instruction address J+P, the processor reads the instruction corresponding to the requested instruction address from the cache. Here, P is a positive integer greater than or equal to 1 and P is less than the maximum number of instructions that the cache can store.

2. The microcontroller according to claim 1, characterized in that, The instruction reading circuit also includes a multiplexer. If the cache contains the instruction corresponding to instruction address I, the instruction corresponding to instruction address I is provided to the processor via a multiplexer; If the instruction corresponding to instruction address I is not in the cache, the instruction address I and the target instruction address J are arbitrated by the address arbitrator. First, the instruction address I is sent to the instruction memory. Then, the instructions corresponding to instruction address I to instruction address I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from instruction address I to instruction address I+P, the instruction corresponding to the requested instruction address is read from the cache. Then, the target instruction address J is sent to the instruction memory. Then, the instructions corresponding to target instruction address J to instruction address J+P are read from the instruction memory and stored in the cache. If the processor requests access to any instruction address from target instruction address J to instruction address J+P, the processor reads the instruction corresponding to the requested instruction address from the cache.

3. The microcontroller according to claim 2, characterized in that, If the cache contains the instruction corresponding to instruction address I, then the instruction corresponding to instruction address I is provided to the processor via the multiplexer; If the cache does not contain the instruction corresponding to instruction address I and the instruction corresponding to instruction address I+P+1, the instruction address I, the instruction address I+P+1, and the target instruction address J are arbitrated by the address arbitrator. First, instruction address I is sent to the instruction memory. Instructions corresponding to instruction addresses I to I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from I to I+P, the instruction corresponding to the requested instruction address is read from the cache. Then, instruction address I+P+1 is sent to the instruction memory. Instructions corresponding to instruction addresses I+P+1 are read from the instruction memory. Instructions from instruction address I+P+1 to instruction address I+2P+1 are stored in the cache. If the processor requests access to any instruction address from I+P+1 to I+2P+1, the processor reads the instruction corresponding to the requested instruction address from the cache. Finally, the processor sends the target instruction address J to the instruction memory, reads the instructions from the instruction memory from the target instruction address J to instruction address J+P and stores them in the cache. If the processor requests access to any instruction address from J to J+P, the processor reads the instruction corresponding to the requested instruction address from the cache.

4. The microcontroller according to claim 3, characterized in that, The step size is P+1.

5. The microcontroller according to claim 3, characterized in that, P = 1 or 2.

6. The microcontroller according to claim 1, characterized in that, The cache includes multiple cache regions, each of which stores an instruction address and the instruction corresponding to that instruction address.

7. The microcontroller according to claim 6, characterized in that, The cache is a first-in-first-out (FIFO) cache.

8. The microcontroller according to claim 1, characterized in that, The cache is a static random access memory or a register, and the instruction memory is a non-volatile memory.

9. A method for operating a microcontroller, the microcontroller comprising: The processor is set to the address where instructions are issued; Instruction memory, configured to store a number of instructions; And instruction fetch circuitry, including buffers, decoders, branch predictors, and address arbitrators. The operation method includes: The instruction fetch circuit's cache receives a request from the processor to access the current instruction address I, where I is an integer; If the cache stores the instruction corresponding to the next instruction address I+1 of the current instruction address I, the decoder retrieves the instruction corresponding to instruction address I+1 from the cache, the decoder decodes the instruction corresponding to instruction address I+1 and determines whether the instruction corresponding to instruction address I+1 is a branch instruction, and the branch predictor determines the target instruction address J when the instruction corresponding to instruction address I+1 is a branch instruction and the branch instruction jumps, where J is an integer and the instruction corresponding to instruction address J is not in the cache; If the instruction corresponding to instruction address I is not in the cache, the instruction address I and the target instruction address J are arbitrated by the address arbitrator. First, the instruction address I is sent to the instruction memory. Then, the instructions corresponding to instruction address I to instruction address I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from instruction address I to instruction address I+P, the instruction corresponding to the requested instruction address is read from the cache. Then, the target instruction address J is sent to the instruction memory. The instruction fetch circuit reads the instructions corresponding to target instruction address J to instruction address J+P from the instruction memory and stores them in the cache. If the processor requests access to any instruction address from target instruction address J to instruction address J+P, the processor reads the instruction corresponding to the requested instruction address from the cache. Here, P is a positive integer greater than or equal to 1 and P is less than the maximum number of instructions that the cache can store.

10. The operating method according to claim 9, characterized in that, The instruction reading circuit further includes a multiplexer, and the operation method further includes: If the cache contains the instruction corresponding to instruction address I, the instruction corresponding to instruction address I is provided to the processor via a multiplexer; If the instruction corresponding to instruction address I is not in the cache, the instruction address I and the target instruction address J are arbitrated by the address arbitrator. First, the instruction address I is sent to the instruction memory. Then, the instructions corresponding to instruction address I to instruction address I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from instruction address I to instruction address I+P, the instruction corresponding to the requested instruction address is read from the cache. Then, the target instruction address J is sent to the instruction memory. Then, the instructions corresponding to target instruction address J to instruction address J+P are read from the instruction memory and stored in the cache. If the processor requests access to any instruction address from target instruction address J to instruction address J+P, the processor reads the instruction corresponding to the requested instruction address from the cache.

11. The operating method according to claim 10, characterized in that, If the cache contains the instruction corresponding to instruction address I, then the instruction corresponding to instruction address I is provided to the processor via the multiplexer; If the cache does not contain the instruction corresponding to instruction address I and the instruction corresponding to instruction address I+P+1, the instruction address I, the instruction address I+P+1, and the target instruction address J are arbitrated by the address arbitrator. First, instruction address I is sent to the instruction memory. Instructions corresponding to instruction addresses I to I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from I to I+P, the instruction corresponding to the requested instruction address is read from the cache. Then, instruction address I+P+1 is sent to the instruction memory. Instructions corresponding to instruction addresses I+P+1 are read from the instruction memory. Instructions from instruction address I+P+1 to instruction address I+2P+1 are stored in the cache. If the processor requests access to any instruction address from I+P+1 to I+2P+1, the processor reads the instruction corresponding to the requested instruction address from the cache. Finally, the processor sends the target instruction address J to the instruction memory, reads the instructions from the instruction memory from the target instruction address J to instruction address J+P and stores them in the cache. If the processor requests access to any instruction address from J to J+P, the processor reads the instruction corresponding to the requested instruction address from the cache.

12. The operating method according to any one of claims 9-11, characterized in that, P = 1 or 2.

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