Configuration loading method of multi-core chip system, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a configuration loading method of a multi-core chip system, electronic equipment and a storage medium. In some embodiments, the multi-core chip system stores a package of configuration files. The configuration file package comprises configuration files which are respectively used for configuring different chips in the multi-core chip system. The configuration loading method is applied to a chip in a multi-core chip system, and comprises the following steps: determining chip parameter information of the chip according to a pin state of a specified pin of the chip; and loading the configuration file in response to matching of the chip parameter information and the configuration parameter information of the configuration file in the configuration file package indicated by the loading instruction.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and more specifically, to a configuration loading method, electronic device and storage medium of a multi-core chip system. Background Art

[0002] To realize window display and voice broadcast, each terminal device usually uses a windowing foundation display (WFD) system, a voice system, etc. The code of such a system can usually be configured with parameters.

[0003] However, to meet the increasing computing power requirements, many terminals use multi-core systems. In a multi-core system, how to configure the parameters of each chip is an urgent problem to be solved. Summary of the invention

[0004] The embodiments of the present application provide a configuration loading method, electronic device and storage medium for a multi-core chip system that can at least partially solve the above-mentioned problems or other problems existing in the prior art.

[0005] On the one hand, an embodiment of the present application provides a configuration loading method for a multi-core chip system. The multi-core chip system stores a configuration file package. The configuration file package includes configuration files for configuring different chips in the multi-core chip system. The configuration loading method is applied to the chip in the multi-core chip system, and includes the following steps: determining the chip parameter information of the chip according to the pin state of the designated pin of the chip; in response to the chip parameter information and the configuration parameter information of the configuration file in the configuration file package indicated by the loading instruction matching, loading the configuration file.

[0006] Another aspect of the embodiments of the present application provides an electronic device, comprising at least one processor and a memory, wherein the memory is in communication with the at least one processor and stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the configuration loading method of the multi-core chip system mentioned in the above embodiments.

[0007] On the other hand, an embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the configuration loading method of the multi-core chip system mentioned in the above embodiment is implemented.

[0008] According to the configuration loading method, electronic device and storage medium of the multi-core chip system provided by the embodiment of the present application, the multi-core chip system stores a configuration file package, which includes configuration files for configuring different chips in the multi-core chip system respectively. Each chip in the multi-core chip system can find the configuration file it needs in the configuration file package, so as to achieve the purpose of compatibility with different chip configurations through a set of codes. At the same time, the chip determines the chip parameter information of the chip according to the pin status of the designated pin of the chip, and loads the configuration file indicated by the configuration instruction when the chip parameter information matches the configuration parameter information of the configuration file in the configuration file package indicated by the loading instruction, so that each chip in the multi-core chip system can selectively execute the configuration loading instruction for itself, thereby reducing the situation of configuration file loading errors.

[0009] In some embodiments, parameter information of a chip is determined based on a pin state of a designated pin of the chip, including: in response to the pin state of the designated pin being a first state, determining the chip parameter information of the chip to be first chip parameter information, the first chip parameter information indicating that the chip is a first core chip in a multi-core chip system; in response to the pin state of the designated pin being a second state, determining the chip parameter information of the chip to be second chip parameter information, the second chip parameter information indicating that the chip is a second core chip in the multi-core chip system.

[0010] In some embodiments, the designated pin includes a first pin and a second pin, and the method further includes: in response to the resistance states of the first pin and the second pin being the first resistance state, determining that the pin state of the designated pin is the first state; in response to the resistance states of the first pin and the second pin being the second resistance state, determining that the pin state of the designated pin is the second state; wherein the first resistance state is a pull-up resistance state and the second resistance state is a pull-down resistance state, or the first resistance state is a pull-down resistance state and the second resistance state is a pull-up resistance state.

[0011] In some embodiments, the configuration parameter information of the configuration file includes first configuration parameter information or second configuration parameter information, the first configuration parameter information indicates that the configuration file is a configuration file for the first core chip, and the second configuration parameter information indicates that the configuration file is a configuration file for the second core chip, and the method further includes: in response to the chip parameter information of the chip being the first chip parameter information, and the configuration parameter information of the configuration file being the first configuration parameter information, determining that the chip parameter information and the configuration parameter information match; or, in response to the chip parameter information of the chip being the second chip parameter information, and the configuration parameter information of the configuration file being the second configuration parameter information, determining that the chip parameter information and the configuration parameter information match.

[0012] In some implementations, the designated pin is a general purpose input / output pin.

[0013] In some implementations, the number of designated pins is determined according to the number of chips in the multi-core chip system.

[0014] In some implementations, the configuration loading method further includes: acquiring configuration parameter information of the configuration file from the file name of the configuration file.

[0015] In some implementations, the configuration file includes a screen display configuration file or a voice configuration file. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0017] Figure 1 is a schematic block diagram of a system for illustrating a configuration loading method for a multi-core chip system mentioned in an embodiment of the present application;

[0018] Figure 2 is a flowchart of a configuration loading method for a multi-core chip system according to the first embodiment of the present application;

[0019] Figure 3 is a flow chart of a configuration loading method according to a second embodiment of the present application;

[0020] Figure 4 is a schematic block diagram of an electronic device according to some embodiments of the present application. DETAILED DESCRIPTION

[0021] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0023] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0024] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0025] Figure 1 1 is a schematic block diagram of a system for a configuration loading method of a multi-core chip system mentioned in an embodiment of the present application. The system 100 may include at least a first core chip 110 and a second core chip 120. The first core chip 110 and the second core chip 120 may exchange data through a transmission channel 130.

[0026] In some embodiments, the first core chip 110 and the second core chip 120 may be used for display control, data processing, etc. Both may be used for different data processing and jointly provide computing power support for the system 100 to meet the computing power requirements required for the operation of the system 100.

[0027] In some embodiments, the transmission channel 130 may be constructed by a transmission circuit or a communication path, which is not limited herein.

[0028] It should be understood that the number of core chips in the system 100 can be set as needed without departing from the teachings of the present application, for example, three or more core chips can be set. The present application does not limit the number of core chips.

[0029] Figure 2 is a flow chart of a configuration loading method for a multi-core chip system according to the first embodiment of the present application. The configuration loading method 200 may be performed by Figure 1 The illustrated chip execution includes the following steps:

[0030] Step 201, determining chip parameter information of the chip according to the pin status of the designated pin of the chip.

[0031] In this embodiment, the multi-core chip system stores a configuration file package. The configuration file package includes configuration files for configuring different chips in the multi-core chip system. For example, the multi-core chip system may also include at least one memory, and each chip in the multi-core chip system may perform read and write operations on the memory after receiving relevant instructions.

[0032] It should be understood that, without departing from the teachings of the present application, the number of memories and the corresponding relationship between memories and chips can be set as needed and are not limited here.

[0033] In some embodiments of the present application, the configuration file package stored in the multi-core chip system may be burned before the multi-core chip system leaves the factory, or may be subsequently obtained from a remote server through Over-the-Air Technology (OTA) or other technologies, or may be obtained from the outside through a data transmission port. After obtaining the configuration file package, the multi-core chip system may store the configuration file package locally so that each chip can be configured and loaded based on the configuration file package.

[0034] It should be understood that, without departing from the teaching of this application, the method for obtaining the configuration file package can be configured as needed, and this application does not impose any restrictions on this.

[0035] In this embodiment, since the multi-core chip system includes at least two chips, for each chip, it is necessary to determine the chip parameter information (such as chip number or chip name, etc.) of the chip in the multi-core chip system to distinguish which instructions or data in the multi-core chip system need to be processed by this chip. In order to distinguish each chip, in this embodiment, the multi-core chip system can mark each chip by the pin status of the designated pin of the chip. Therefore, the chip can determine the chip parameter information of the chip according to the pin status of its own designated pin. In this example, the chip determines its own chip parameter information by reading the pin status of the designated pin, which is conducive to the chip to realize its own positioning, and then load the configuration file suitable for itself.

[0036] It should be understood that, without departing from the teachings of the present application, the chip parameter information mentioned in the present embodiment is mainly used to distinguish between each chip, and its specific data type can be set as needed. For example, for a multi-core chip system having two chips (such as a first core chip and a second core chip), the chip parameter information may include first chip parameter information and second chip parameter information. Among them, the first chip parameter information is used to indicate that the chip is a first core chip, and the second chip parameter information is used to indicate that the chip is a second core chip. The data type of the first chip parameter information and the second chip parameter information may be a character type. For example, if the first core chip and the second core chip are graphics cards (graphics), the first chip parameter information may be graphics_a, and the second chip parameter information may be graphics_b. The data type of the first chip parameter information and the second chip parameter information may be an integer type. For example, the first chip parameter information may be 00, and the second chip parameter information may be 11. The present application does not limit the data type and numbering method of the chip parameter information.

[0037] In some embodiments of the present application, the process of determining the chip parameter information of each chip according to the pin state of the designated pin of the chip may include: in response to the pin state of the designated pin being the first state, determining the chip parameter information of the chip as the first chip parameter information, the first chip parameter information indicating that the chip is the first core chip in the multi-core chip system; in response to the pin state of the designated pin being the second state, determining the chip parameter information of the chip as the second chip parameter information, the second chip parameter information indicating that the chip is the second core chip in the multi-core chip system. In other words, the number of pin states of the designated pins of the chip is greater than or equal to the number of chips in the multi-core chip system. Each pin state corresponds to each chip parameter information one by one, so that the chip can determine its own chip parameter information by reading the pin state of the designated pin. In this embodiment, taking the multi-core chip system including two chips (such as the first core chip and the second core chip mentioned above) as an example, the pin state of the designated pin may include a first state and a second state. Among them, the first state corresponds to the first core chip, the chip parameter information is the first chip parameter information, the second state corresponds to the second core chip, and the chip parameter information is the second chip parameter information. Each chip can determine chip parameter information based on the pin status information read from the designated pin, and further determine whether it is the first core chip or the second core chip.

[0038] As an example, the designated pin mentioned above may include a first pin and a second pin. The chip may combine the resistance states of the two pins to comprehensively determine its own pin state. For example, the chip may determine that the pin state of the designated pin is the first state after determining that the resistance states of the first pin and the second pin are both the first resistance state. The chip may determine that the pin state of the designated pin is the second state after determining that the resistance states of the first pin and the second pin are both the second resistance state. Among them, the first resistance state is a pull-up resistance state, and the second resistance state is a pull-down resistance state, or the first resistance state is a pull-down resistance state, and the second resistance state is a pull-up resistance state. In this example, the chip is informed of its chip parameter information by controlling the resistance state of the pin, and the chip does not need to repeatedly request chip parameter information from a memory or other channels, thereby improving the speed at which the chip determines the chip parameter information, thereby improving the configuration efficiency. In addition, in this example, by comprehensively determining the pin state through multiple pins, problems such as pin state identification errors caused by pin failures and other reasons can be reduced, and the probability of configuration errors can be reduced.

[0039] In some embodiments of the present application, the designated pins mentioned above may be general purpose input / output pins (GPIO). Among them, GPIO is a type of interface in a digital electronic system that can be used to communicate and control with external devices. The GPIO interface can be used as an input or output pin and has a variety of functions and application scenarios. The GPIO pins can support digital signal input and output, can read or output analog signals, and can also support analog signal input and output, and can read or output analog signals. Therefore, the chips in a multi-core chip system can distinguish their own chip parameter information through their own states from their respective GPIO pins.

[0040] Optionally, the number of designated pins may be determined based on the number of chips in the multi-core chip system. For example, the number of designated pins may be equal to the number of chips, or the number of states that can be represented when the number of designated pins is the number of binary coding bits is greater than or equal to the number of chips. Reasonable use of designated pins based on the number of chips can reduce the situation where too many pins are occupied.

[0041] It should be understood that, without departing from the teachings of the present application, the number of pins used as designated pins may also be determined in combination with other parameters, and the present application does not impose any limitation on this.

[0042] Step 202: In response to the chip parameter information matching the configuration parameter information of the configuration file in the configuration file package indicated by the loading instruction, load the configuration file.

[0043] In this embodiment, after receiving the loading instruction, the chip can lock the configuration parameter information of the configuration file that needs to be loaded this time in the configuration file package according to the loading instruction. The chip determines whether its own chip parameter information and the determined configuration parameter information match; if it is determined that the two match, the loading instruction is executed to load the configuration file indicated by the loading instruction; if it is determined that the two match, the loading instruction is not executed, and the chip will not load the configuration file indicated by the loading instruction.

[0044] For ease of understanding, the process of determining whether the chip parameter information itself matches the determined configuration parameter information is exemplarily described below.

[0045] In some embodiments of the present application, the multi-core chip system may include two chips, namely, a first core chip and a second core chip. The configuration parameter information of the configuration file includes the first configuration parameter information or the second configuration parameter information, the first configuration parameter information indicates that the configuration file is the configuration file of the first core chip, and the second configuration parameter information indicates that the configuration file is the configuration file of the second core chip. The chip may determine that the chip parameter information matches the configuration parameter information when it is determined that the chip parameter information of the chip is the first chip parameter information, and the configuration parameter information of the configuration file is the first configuration parameter information. Alternatively, the chip may determine that the chip parameter information matches the configuration parameter information when it is determined that the chip parameter information of the chip is the second chip parameter information, and the configuration parameter information of the configuration file is the second configuration parameter information. Correspondingly, if the chip determines that the chip parameter information of the chip is the first chip parameter information, and the configuration parameter information of the configuration file indicated in the configuration instruction is the second configuration parameter information, it is determined that the chip parameter information and the configuration parameter information do not match. If the chip determines that the chip parameter information of the chip is the second chip parameter information, and the configuration parameter information of the configuration file indicated in the configuration instruction is the first configuration parameter information, it can also be determined that the chip parameter information and the configuration parameter information do not match.

[0046] As an example, the data type of the configuration parameter information may be the same as the data type of the chip parameter information. For example, if the data type of the first chip parameter information and the second chip parameter information is character type, the data type of the first configuration parameter information and the second configuration parameter information is also character type. If the data type of the first chip parameter information and the second chip parameter information is integer type, the data type of the first configuration parameter information and the second configuration parameter information is also integer type. In this example, the data type of the configuration parameter information is the same as the data type of the chip parameter information, which is conducive to information matching of the chip, reduces the difficulty of matching, improves the judgment speed, and thus improves the configuration loading efficiency.

[0047] It should be understood that, without departing from the teachings of this application, the data type of the configuration parameter information can be set as needed, and this application does not impose any restrictions on this.

[0048] As an example, the data type of the configuration parameter information may be the same as the data type of the chip parameter information, and the naming rules for the same chip are the same. For example, if the data type of the first chip parameter information and the second chip parameter information is character type, the data type of the first configuration parameter information and the second configuration parameter information is also character type. If the first core chip and the second core chip are graphics cards (graphics), the first chip parameter information may be graphics_a, and the second chip parameter information may be graphics_b. Correspondingly, the first configuration parameter information may be graphics_a.conf, and the second configuration parameter information may be graphics_b.conf. Among them, ".conf" may indicate that it is a configuration file. If the data type of the first chip parameter information and the second chip parameter information is integer type, the data type of the first configuration parameter information and the second configuration parameter information is also integer type. The first chip parameter information may be 00, and the second chip parameter information may be 11. Correspondingly, the first configuration parameter information may be 00.conf, and the second configuration parameter information may be 11.conf. In this example, the data type of the configuration parameter information is the same as the data type of the chip parameter information and the naming rules are the same, so that when the chip performs information matching, it only needs to determine whether there are identical characters in the two information. There is no need to configure complex matching rules, which reduces the matching difficulty, increases the judgment speed, and thus improves the configuration loading efficiency.

[0049] It should be understood that, without departing from the teachings of this application, the method of determining whether the chip parameter information and configuration parameter information match can be set according to the data type, naming method, etc. of the chip parameter information and configuration parameter information, and this application does not impose any restrictions on this.

[0050] In some embodiments of the present application, the chip can obtain the configuration parameter information of the configuration file from the file name of the configuration file indicated by the loading instruction. In other words, each configuration file in the configuration file package can be named using the configuration parameter information. Therefore, the loading instruction can carry the configuration parameter information of the configuration file that is instructed to be loaded this time, so that the chip can directly obtain the configuration parameter information from the loading instruction without parsing the configuration file, thereby improving the speed at which the chip determines whether to load the configuration file.

[0051] It should be understood that, without departing from the teachings of this application, the configuration parameter information may also be carried in other locations, such as the file details of a configuration file, and this application does not limit the location where the configuration parameter information is carried.

[0052] According to some embodiments of the present application, a multi-core chip system stores a configuration file package, which includes configuration files for configuring different chips in the multi-core chip system. Each chip in the multi-core chip system can find the configuration file it needs in the configuration file package, so as to achieve the purpose of compatibility with different chip configurations through a set of codes. At the same time, the chip determines the chip parameter information of the chip according to the pin status of the designated pin of the chip, and loads the configuration file indicated by the configuration instruction when the chip parameter information matches the configuration parameter information of the configuration file in the configuration file package indicated by the loading instruction, so that each chip in the multi-core chip system can selectively execute the configuration loading instruction for itself, thereby reducing the situation of configuration file loading errors.

[0053] Figure 3 1 is a flow chart of a configuration loading method according to a second embodiment of the present application. This embodiment is substantially the same as the first embodiment, with the main difference being that this embodiment takes the configuration file as a screen display configuration file as an example, that is, takes the display configuration loading scenario as an example, and exemplarily illustrates the configuration loading method.

[0054] In this embodiment, the multi-core chip system can deploy the QNX system (a real-time operating system). The code of the Windowing Foundation Display (WFD) system based on the QNX system can load parameters through a screen display configuration (config) file. After the multi-core chip system is started, at least a loading instruction for loading a screen display configuration file can be triggered to enable the QNX system to load the display configuration.

[0055] It should be understood that other real-time operating systems may be deployed in a multi-core chip system without departing from the teachings of the present application. The QNX system is used as an example for illustrative description.

[0056] In some embodiments, the multi-core chip system is designed with two chips as the first core chip and the second core chip. Among them, the chip can be selected as an 8155 chip or a chip of other models. However, a set of codes is usually used when loading the display configuration, and there is only one graphics.conf in the code. Due to the different display mode requirements of the first core chip and the second core chip, modifying graphics.conf results in a set of codes being unable to simultaneously meet the different display configurations and loading of the two chips.

[0057] In the implementation manner of the present application, the configuration file package of the multi-core chip system includes configuration files for configuring different chips in the multi-core chip system. Taking the multi-core chip system as an example, the configuration file package includes a first screen display configuration file for display configuration loading of the first core chip and a second screen display configuration file for display loading of the second core chip. After the multi-core chip system is started, the preset code is executed. The preset code may include multiple loading instructions. Taking the display configuration loading as an example, the multiple loading instructions include at least one first loading instruction indicating the loading of the first screen display configuration file and a second loading instruction indicating the loading of the second screen display configuration file. Among them, the first loading instruction can be written as screen-cgraphics_a.conf, for example, and the second loading instruction can be written as screen-cgraphics_b.conf, for example. Among them, screen-c is a screen display loading command, graphics_a.conf is the file name of the first screen display configuration file, and graphics_b.conf is the file name of the second screen display configuration file. The order of the first loading instruction and the second loading instruction in the code can be set as needed. For the sake of ease of explanation, the following text takes the example of the first load instruction coming first and the second load instruction coming later (the first load instruction is executed first and the second load instruction is executed later) as an example for illustrative explanation. In other implementations, the second load instruction may come first and the first load instruction may come later, that is, the second load instruction is executed first and the first load instruction is executed later. This application does not impose any restrictions on this.

[0058] It should be understood that, without departing from the teachings of this application, the number of loading instructions in the preset code can be determined according to the number of chips, the number of configuration files that the chips need to load, etc., and is not limited here.

[0059] In this embodiment, under the above architecture, the configuration loading method 300 can be as follows: Figure 3 As shown. Figure 3 As shown, the configuration loading method 300 executed by the chip may include the following steps:

[0060] Step 301: The chip runs to a first loading instruction, and determines chip parameter information of the chip according to the pin status of a designated pin of the chip.

[0061] In this implementation, after the chip runs to the first loading instruction (such as graphics_a.conf mentioned above), the chip parameter information can be determined by referring to the method exemplified in the first implementation, which will not be described in detail here.

[0062] Step 302: The chip determines whether the chip parameter information matches the configuration parameter information of the first screen display configuration file indicated by the first loading instruction.

[0063] In this embodiment, the first loading configuration instruction indicates the first screen display configuration file, the file name is graphics_a.conf, and the configuration parameter information can be graphics_a.conf or graphics_a. If the chip parameter information determined by the chip in step 301 is graphics_a, that is, the chip is the first core chip, it can be determined that the two match, and step 303 is executed. If the chip parameter information determined by the chip is graphics_b, that is, the chip is the second core chip, it can be determined that the two do not match, and step 304 is executed.

[0064] Step 303: The chip executes a first loading instruction to load a first screen display configuration file.

[0065] In this implementation manner, after determining that the chip parameter information matches the configuration parameter information of the first screen display configuration file indicated by the first loading instruction, the chip may execute the first loading instruction to load the first screen display configuration file.

[0066] Step 304: the chip runs to the second loading instruction to determine whether the chip parameter information matches the configuration parameter information of the second screen display configuration file indicated by the second loading instruction.

[0067] In this embodiment, after the chip runs to the second loading instruction, if the storage operation is performed on the determined chip parameter information in step 301, it can be determined based on the stored chip parameter information whether the configuration parameter information of the screen display configuration file in the configuration file package indicated by the second loading instruction matches; if the storage operation is not performed on the determined chip parameter information in step 301, the chip parameter information of the chip can be determined again according to the pin status of the designated pin of the chip, and it can be determined whether the determined chip parameter information matches the configuration parameter information of the screen display configuration file in the configuration file package indicated by the second loading instruction.

[0068] In this embodiment, the second loading configuration instruction indicates the second screen display configuration file, the file name is graphics_b.conf, and the configuration parameter information can be graphics_b.conf or graphics_b. If the chip parameter information determined by the chip is graphics_a, that is, the chip is the first core chip, it can be determined that the two do not match, and step 306 is executed. If the chip parameter information determined by the chip is graphics_b, that is, the chip is the second core chip, it can be determined that the two match, and step 305 is executed.

[0069] Step 305: The chip executes a second loading instruction to load a second screen display configuration file.

[0070] In this implementation manner, after determining that the chip parameter information matches the configuration parameter information of the second screen display configuration file indicated by the second loading instruction, the chip may execute the second loading instruction to load the second screen display configuration file.

[0071] Step 306: The chip executes other instructions in the code.

[0072] In this embodiment, considering that there are many configurations that need to be loaded after the system starts, the default code has other instructions after the first loading instruction and the second loading instruction. After the chip runs the first loading instruction and the second loading instruction, it can continue to execute subsequent instructions.

[0073] It should be understood that, without departing from the teaching of the present application, there may be no other instructions after the first load instruction and the second load instruction. In this case, the chip may not execute step 306 after step 305, but terminate the loading process of the startup phase. The present application does not limit the operation of the chip after executing the first load instruction and the second load instruction.

[0074] From the above content, it can be seen that no matter the chip is the first core chip or the second core chip, after executing the above steps, it can complete the loading of its own screen display configuration, and achieve the purpose of being compatible with the WFD configuration of different chips through a set of codes.

[0075] It should be understood that, without departing from the teaching of the present application, the configuration file package may also include configuration files for other functions. For example, the configuration file in the configuration file package may be a voice configuration file or other function configuration file, that is, the configuration loading method may also be applied to voice configuration loading scenarios or other configuration loading scenarios. In voice configuration loading scenarios or other configuration loading scenarios, the chip executes the logic of the configuration loading method and Figure 3 The logic of the configuration loading method shown is roughly the same, the difference is that the configuration files indicated by the loading instructions are different, which will not be repeated here. This application does not limit the usage scenario of the configuration loading method.

[0076] According to some embodiments of the present application, a multi-core chip system stores a configuration file package, which includes configuration files for configuring different chips in the multi-core chip system. Each chip in the multi-core chip system can find the configuration file it needs in the configuration file package, so as to achieve the purpose of compatibility with different chip configurations through a set of codes. At the same time, the chip determines the chip parameter information of the chip according to the pin status of the designated pin of the chip, and loads the configuration file indicated by the configuration instruction when the chip parameter information matches the configuration parameter information of the configuration file in the configuration file package indicated by the loading instruction, so that each chip in the multi-core chip system can selectively execute the configuration loading instruction for itself, thereby reducing the situation of configuration file loading errors.

[0077] It should be noted that in the technical solution of this disclosure, the acquisition, storage and application of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good customs. It should also be noted that the information in this embodiment is obtained after the user authorizes it (that is, with the user's consent).

[0078] The step division of the various methods above is only for clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the protection scope of this disclosure. Adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the protection scope of this disclosure.

[0079] The embodiment of the present application also provides an electronic device, such as Figure 4 As shown, the electronic device 400 may include: at least one processor and a memory, the memory is communicatively connected to the at least one processor and stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the configuration loading method of the multi-core chip system mentioned in the above embodiment.

[0080] For example, the electronic device 400 may be a vehicle-mounted terminal, which may use a multi-core chip system to meet the computing power requirements for processing vehicle data and realizing vehicle configuration functions. Each chip in the multi-core chip system may realize configuration loading through the configuration loading method of the multi-core chip system mentioned in the above embodiment.

[0081] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the configuration loading method of the multi-core chip system mentioned in the above embodiment is implemented.

[0082] Figure 4 4 is a schematic block diagram of an electronic device 400 according to some embodiments of the present application. Figure 4 As shown, the electronic device 400 includes a processor 401, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 402 or a computer program loaded from a memory 408 into a random access memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the electronic device 400 can also be stored. The processor 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0083] Multiple components in the electronic device 400 are connected to the I / O interface 405, including: an input unit 406, such as buttons and touch screens of the vehicle computer; an output unit 407, connected to, for example, various types of displays, speakers, etc., to output various forms of signals; a memory 408, including any medium for storing computer executable programs; and a communication unit 409, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 409 allows the electronic device 400 to exchange information / data with other devices through a local area network or other wireless communication network.

[0084] The processor 401 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 401 performs the various methods and processes described above, such as the configuration loading method of the multi-core chip system mentioned in the above embodiment. For example, in some embodiments, the configuration loading method of the multi-core chip system mentioned in the above embodiment may be implemented as a computer software program, which is tangibly contained in a computer-readable storage medium, such as a memory 408. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 400 via the ROM 402 and / or the communication unit 409. When the computer program is loaded into the RAM 403 and executed by the processor 401, one or more steps of the configuration loading method of the multi-core chip system mentioned in the above embodiment may be performed. Alternatively, in other embodiments, the processor 401 may be configured in any other appropriate manner (eg, by means of firmware) to execute the configuration loading method of the multi-core chip system mentioned in the above embodiment.

[0085] Various aspects of the present application are described herein with reference to the flowcharts and / or timing diagrams of the methods, devices (systems), and computer program products according to the exemplary embodiments of the present application. It should be understood that each step of the flowchart and / or timing diagram and the combination of the steps in the flowchart and / or timing diagram can be implemented by computer-readable program instructions.

[0086] These computer-readable program instructions can be provided to a processor in an electronic device, a general-purpose computer, a special-purpose computer, or a processing unit of other programmable data processing devices, thereby producing a machine, so that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device that implements the functions / steps specified in one or more steps in the flowchart and / or timing diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / steps specified in one or more steps in the flowchart and / or timing diagram.

[0087] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / steps specified in one or more steps in the flowchart and / or timing diagram.

[0088] The flowchart and timing diagram in the accompanying drawings show the possible architecture, functions and operations of the equipment, methods and computer program products according to multiple embodiments of the present application. In this regard, each step in the flowchart or timing diagram can represent a part of a module, a program segment or an instruction, and a part of the module, a program segment or an instruction contains one or more executable instructions for realizing the specified logical function. In some alternative embodiments, the functions marked in the steps can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each step in the timing diagram and / or the flowchart, and the combination of the steps in the timing diagram and / or the flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0089] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A configuration loading method for a multi-core chip system, wherein the multi-core chip system stores a configuration file package, wherein the configuration file package includes configuration files respectively used to configure different chips in the multi-core chip system; The method is applied to a chip in the multi-core chip system, and includes: Determining chip parameter information of the chip according to the pin status of the designated pin of the chip; In response to the chip parameter information matching the configuration parameter information of the configuration file in the configuration file package indicated by the loading instruction, the configuration file is loaded.

2. The method according to claim 1, wherein: Determining the parameter information of the chip according to the pin state of the designated pin of the chip includes: In response to the pin state of the designated pin being a first state, determining that the chip parameter information of the chip is first chip parameter information, wherein the first chip parameter information indicates that the chip is a first core chip in a multi-core chip system; In response to the pin state of the designated pin being the second state, the chip parameter information of the chip is determined to be second chip parameter information, and the second chip parameter information indicates that the chip is a second core chip in a multi-core chip system.

3. The method according to claim 2, wherein: The designated pin includes a first pin and a second pin, and the method further includes: In response to the resistance states of the first pin and the second pin being both in the first resistance state, determining that the pin state of the designated pin is in the first state; In response to the resistance states of the first pin and the second pin being both in the second resistance state, determining that the pin state of the designated pin is in the second state; Wherein, the first resistance state is a pull-up resistance state, the second resistance state is a pull-down resistance state, or, The first resistance state is a pull-down resistance state, and the second resistance state is a pull-up resistance state.

4. The method according to claim 2, wherein: The configuration parameter information of the configuration file includes first configuration parameter information or second configuration parameter information, the first configuration parameter information indicates that the configuration file is a configuration file of the first core chip, and the second configuration parameter information indicates that the configuration file is a configuration file of the second core chip, and the method further includes: In response to the chip parameter information of the chip being the first chip parameter information, and the configuration parameter information of the configuration file being the first configuration parameter information, determining that the chip parameter information matches the configuration parameter information; or, In response to the chip parameter information of the chip being the second chip parameter information and the configuration parameter information of the configuration file being the second configuration parameter information, it is determined that the chip parameter information matches the configuration parameter information.

5. The method according to claim 1, wherein: The designated pin is a general input / output port pin.

6. The method according to claim 5, wherein: The number of the designated pins is determined according to the number of chips in the multi-core chip system.

7. The method according to any one of claims 1 to 6, further comprising: The configuration parameter information of the configuration file is obtained from the file name of the configuration file.

8. The method according to any one of claims 1 to 6, wherein: The configuration file includes a screen display configuration file or a voice configuration file.

9. An electronic device, characterized in that: include: at least one processor; as well as, A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor so that the at least one processor can execute the configuration loading method for a multi-core chip system as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the configuration loading method of the multi-core chip system according to any one of claims 1 to 8 is implemented.

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