CPLD-based CPU reset method, device and system and storage medium

By adopting a CPLD-based hardware and software collaborative design method in the CPU reset system, the problems of DDR data loss, long reset waiting time and abnormal CPU reset in the prior art are solved, and precise control of CPU reset and system stability and reliability are realized.

CN119645735APending Publication Date: 2025-03-18SUPCON TECH CO LTD
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Patent Information

Application Number
CN202411869363.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-18
Publication Date
2025-03-18

AI Technical Summary

Technical Problem

The existing CPU reset technology has problems such as DDR data loss, long waiting time for CPU reset, inability to respond to interrupts in certain CPU states, and the possibility of CPLD to cause abnormal CPU reset.

Method used

Through the coordinated design of hardware and software, a CPU reset method based on CPLD is adopted, including CPLD receiving the pulse signal sent by the CPU to determine whether it exceeds the first time threshold, and if so, a CPU reset pulse is sent to the CPU; a watchdog receiving the feeding signal sent by the CPLD determines whether it exceeds the second time threshold, and if so, a CPLD reset pulse is sent to the CPLD and the CPU.

Benefits of technology

Accurate control of CPU reset is achieved, reset wait time is reduced, reset risk is reduced, key information before reset is retained, and system maintenance and troubleshooting is facilitated.

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Abstract

The invention provides a CPLD (Complex Programmable Logic Device)-based CPU (Central Processing Unit) resetting method, device and system and a storage medium, which solve the problems of DDR (Double Data Rate) data loss, long CPU resetting waiting time, incapability of responding to interruption in some states of a CPU, possibility of abnormal resetting of the CPU caused by the CPLD and the like in the prior art through collaborative design of hardware and software, realize accurate control on CPU resetting and improve the CPU resetting efficiency. The stability and reliability of the system are improved, and meanwhile key information before resetting is reserved so as to facilitate system maintenance and troubleshooting.
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