Error injection test method, device and system

Abstract

The invention provides an error injection test method, device and system. The method comprises the following steps: determining an error injection test mode for performing an error injection test on to-be-tested server hardware; in any error injection test mode, setting a working state of a short circuit device to generate a target test scene; the short-circuit device comprises at least one short-circuit wire of which one end is connected with a hole slot of the to-be-tested server hardware, a short-circuit wire of which one end is connected with a preset error injection scene circuit, and a switch arranged on the short-circuit wire; and based on the target test scene, executing an error injection test on the to-be-tested server hardware. According to the method, the error injection test can be more efficiently and flexibly carried out on the to-be-tested server hardware, and meanwhile, the to-be-tested server hardware cannot be damaged in the test process.

Description

Technical Field

[0001] The present invention relates to the technical field of server testing, and in particular to an injection error testing method, device and system. Background Art

[0002] With the rapid advancement of network technology and computer technology, the role played by servers in the system is becoming increasingly critical. In this process, in order to improve user experience and ensure data security, users have put forward more stringent requirements on the stability, availability and serviceability of server equipment. These requirements have strongly promoted the rapid development of server reliability, availability and maintainability (RAS) technology.

[0003] In the development of server RAS technology, the central processing unit (CPU), memory and high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) have become the three core modules. Currently, the verification test of the RAS function of the basic input output system (BIOS) has become an indispensable part of the RAS verification process.

[0004] In the RAS testing process, the relevant technologies are mainly implemented by software simulation and hardware construction. However, for the software simulation method, as the devices under test are updated, the relevant software simulation tools between different generations of devices under test may not be universal; and the corresponding hardware construction method may cause damage to the devices under test. Therefore, there is an urgent need for an injection error test method, device and system to solve the above problems. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides an injection error testing method, device and system.

[0006] The present invention provides an injection error testing method, comprising: Determine the error injection test mode for performing error injection test on the server hardware to be tested; In any of the injection error test modes, the working state of the short-circuit device is set to generate a target test scenario; the short-circuit device includes at least one short-circuit wire having one end connected to the hole slot of the server hardware to be tested, one end connected to the preset injection error scenario circuit, and a switch arranged on the short-circuit wire; Based on the target test scenario, an error injection test is performed on the server hardware to be tested.

[0007] According to a method for error injection testing provided by the present invention, determining an error injection testing mode for performing an error injection test on server hardware to be tested comprises: If the server hardware to be tested is a memory device, it is determined that the error injection test mode of the server hardware to be tested is a memory failure test mode.

[0008] According to an injection error test method provided by the present invention, the preset injection error scenario circuit includes a first injection error scenario circuit and a second injection error scenario circuit, wherein the first injection error scenario circuit is used to simulate the situation of short-circuiting a data signal line; the second injection error scenario circuit is used to simulate the situation of short-circuiting two data signal lines; In any of the injection error test modes, setting the working state of the short-circuit device to generate a target test scenario includes: Based on the conduction state between the target output end in the multi-way switch module of the short-circuiting device and the preset error injection scenario circuit, the connection relationship information between the server hardware to be tested and the short-circuiting device is obtained; wherein, the target output end is an output end connected to the corresponding preset error injection scenario circuit among the multiple output ends of the multi-way switch module; the target hole slot of the server hardware to be tested is connected to the corresponding input end in the multi-way switch module through a DuPont male pin; the target hole slot is a hole slot connected to the ground wire at the slot of the server hardware to be tested; If the injection error test mode is the memory fault test mode, determining whether the current test phase is a server startup phase; When determining that the current test phase is the server startup phase, if the conduction state corresponding to the connection relationship information is the first conduction state, and after a preset time, the conduction state corresponding to the connection relationship information is switched from the first conduction state to the disconnection state, it is determined that the target test scenario is a memory single-bit fault repair scenario; wherein the first conduction state is a state in which the target output end in the multi-way switch module is connected to the first injection error scenario circuit; If the conduction state corresponding to the connection relationship information is the first conduction state, it is determined that the target test scenario is a memory isolation test scenario.

[0009] According to a wrong injection test method provided by the present invention, in any of the wrong injection test modes, setting the working state of the short-circuit device to generate a target test scenario also includes: When determining that the current test phase is the server operation phase, if the conduction state corresponding to the connection relationship information is the second conduction state, determining that the target test scenario is a memory uncorrectable fault test scenario; wherein the second conduction state is a state in which the target output terminal in the multi-way switch module is conductive with the second injection error scenario circuit; If the conduction state corresponding to the connection relationship information is the first conduction state, it is determined that the target test scenario is a memory correctable fault test scenario.

[0010] According to a method for testing injection errors provided by the present invention, the method further comprises: When it is determined that the current test phase is the server operation phase, if the conduction state corresponding to the connection relationship information is the first conduction state or the second conduction state, and each input end in the multi-way switch module is connected to a corresponding server hardware to be tested, it is determined that the target test scenario is a multiple memory failure test scenario.

[0011] According to a method for testing injection errors provided by the present invention, the method further comprises: If the server hardware to be tested is a high-speed serial computer expansion bus standard device, determining that the error injection test mode of the server hardware to be tested is a high-speed serial computer expansion bus standard device fault test mode; It is determined whether the conduction state corresponding to the connection relationship information is the first conduction state, and if so, it is determined that the target test scenario is a high-speed serial computer expansion bus standard device fault test scenario.

[0012] The present invention also provides an injection error testing device, comprising: A test mode determination module, used to determine an error injection test mode for performing an error injection test on the server hardware to be tested; A test scenario determination module, used to set the working state of the short-circuit device in any of the injection error test modes to generate a target test scenario; the short-circuit device includes at least one short-circuit wire having one end connected to the hole slot of the server hardware to be tested, one end connected to the preset injection error scenario circuit, and a switch arranged on the short-circuit wire; The error injection test module is used to perform an error injection test on the server hardware to be tested based on the target test scenario.

[0013] The present invention also provides an injection error test system, comprising the injection error test device and a short-circuit device, wherein the short-circuit device is based on a DuPont male pin, a multi-way switch module and a plurality of preset injection error scenario circuits, wherein: The first end of the DuPont male pin is connected to the target hole slot of the server hardware to be tested, and the second end of the DuPont male pin is connected to the corresponding input end of the multi-way switch module, wherein the target hole slot is the hole slot connected to the ground wire at the slot of the server hardware to be tested; The target output end in the multi-way switch module is connected to the corresponding preset error injection scenario circuit, wherein the target output end is an output end among the multiple output ends of the multi-way switch module connected to the corresponding preset error injection scenario circuit.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the injection error testing method described above is implemented.

[0015] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the injection error testing method described in any one of the above methods is implemented.

[0016] The error injection test method, device and system provided by the present invention determine the error injection test mode of the server hardware to be tested by acquiring the device type information, and then determine the target test scenario according to the connection relationship information between the short-circuit device constructed by multiple preset error injection scenario circuits and the server hardware to be tested, so as to perform the error injection test on the server hardware to be tested more efficiently and flexibly, and at the same time, will not cause damage to the server hardware to be tested during the test process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the flow chart of the injection error testing method provided by the present invention; Figure 2 A schematic diagram of the overall process of the injection error testing method provided by the present invention; Figure 3 A schematic diagram of the structure of the injection error testing device provided by the present invention; Figure 4 A schematic diagram of the structure of the injection error test system provided by the present invention; Figure 5 This is a schematic structural diagram of an electronic device provided by the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] With the rapid development of network technology and computer technology, servers have gradually become an especially important part, showing a trend of rapid development. In this development process, in order to provide better user experience and data security, people have higher and higher requirements for the stability, availability and serviceability of server equipment, which has gradually promoted the rapid development of server RAS technology.

[0021] In the server RAS technology, the main modules involved are CPU, memory and PCIE. Nowadays, in order to improve the core competitiveness of their products, various chip manufacturers and server manufacturers in the industry have invested a lot of energy and research in the important link of RAS function. Therefore, for test engineers, BIOS RAS function verification test has gradually become a necessary process in the RAS verification link.

[0022] In the related art, the RAS testing process is usually carried out in the form of software simulation and hardware construction. Among them, the software simulation method can generally use relevant error injection testing tools, error injection tools developed by various chip manufacturers, and other error injection scripts and software. Hardware error injection methods are more abundant, such as error injection testing tools used in conjunction with software testing. In addition, according to the requirements of different test scenarios, some corresponding hardware error injection tools can also be made. For example, in the BIOS field, when testing some RAS functions of the memory, such as memory storm suppression scenarios, single-particle memory failures during the operation phase, multi-particle memory failures during the operation phase, single-particle memory failures during the startup phase, one memory line has problems during the startup phase, and multiple memory lines have problems during the startup phase, etc., error injection testing can be performed through hardware construction.

[0023] For the above-mentioned memory failure-related test scenarios, the most convenient and suitable method is to use professional customized memory test tools. However, with the development of technology, the memory is often updated at a faster speed. The memory test tools for DDR4 and DDR5 cannot be shared, and the flying wires are fixed after welding, and can only be used for individual test cases. If you test again, you need to manually connect the flying wires led out of the memory test. Therefore, although this method can protect the memory and meet the requirements of most test scenarios, it is not very convenient to execute the test, and the test cost is relatively high.

[0024] In addition, due to the particularity of the fault type and the special requirements for the fault frequency or the problem of error injection scenario, the ordinary software error injection method cannot meet the test requirements, and it is necessary to use hardware methods to construct the test conditions. A relatively economical memory fault hardware simulation method is to directly short-circuit the memory pins with a sharp object or directly stick tape on the memory to be tested. However, this method is extremely inconvenient to operate and is very likely to cause damage to the motherboard or memory due to improper operation, resulting in huge economic losses.

[0025] It can be seen that in the relevant technologies, during the injection error test process, either a dedicated memory test kit tool is required, or the scene simulation is performed through rough methods such as sticking tape and pulling flying wires, resulting in low injection error test efficiency and the risk of equipment damage.

[0026] In response to the problems existing in the related technology, the present invention simulates the startup phase fault detection required in the RAS test and the corresponding fault detection in the operation phase without damaging any test equipment or materials, making the construction process of the error injection test scenario simpler and improving the efficiency of the error injection test.

[0027] Figure 1 A flow chart of the injection error testing method provided by the present invention is shown in FIG. Figure 1 As shown, the present invention provides an injection error testing method, comprising: Step 101, determining an error injection test mode for performing an error injection test on the server hardware to be tested.

[0028] Before conducting server hardware testing, it is first necessary to obtain the device type information of the server hardware to be tested to ensure the accuracy and effectiveness of the test, so as to formulate a test plan and test strategy in a targeted manner. In the present invention, for different types of server hardware, the construction of injection error scenarios can be achieved through a short-circuit device, wherein the server hardware is mainly memory devices and PCIE devices. In view of the fact that the PCIE test method in the relevant technology is relatively mature, the present invention mainly explains the injection error test process of the memory device.

[0029] In the memory fault handling process of the server's RAS solution, for the startup (POST) phase, the memory used by the server during the power-on process has a single-bit fault. After the memory initialization is completed, it has a single-bit error correction capability and can correct the single-bit memory fault in the environment. During the power-on process, when the server detects a faulty memory, it will issue an alarm and isolate the memory bar. For the allowed (Runtime) phase, if a single-bit fault occurs in the memory during operation, the system should have the ability to correct it; when a multi-bit fault occurs in the memory, the system no longer has the ability to correct it.

[0030] In the present invention, the corresponding error injection test mode will be pre-built for the above-mentioned memory fault handling process, that is, in the field of server hardware testing, the error injection test mode of the server hardware to be tested is first determined according to the device type information. For example, when the device type information is a memory device type, a specific test scenario can be designed to simulate memory failures, such as random access errors, data corruption, memory leaks, etc. These test scenarios can help evaluate the stability and fault tolerance of the system under memory abnormalities. Error injection testing. When the device type information is a PCIE device type, various faults on the PCIE bus can be simulated, such as data transmission errors, device loss, hot plug problems, etc. These test scenarios help verify the system's response and processing capabilities to PCIE device failures.

[0031] Step 102, in any of the injection error test modes, set the working state of the short-circuit device to generate a target test scenario; the short-circuit device includes at least one short-circuit wire having one end connected to the hole slot of the server hardware to be tested, one end connected to the preset injection error scenario circuit, and a switch arranged on the short-circuit wire.

[0032] In the present invention, based on the determined error injection test mode, it is necessary to determine the specific target test scenario based on the connection relationship information between the server hardware to be tested and the short-circuit device. In the present invention, the short-circuit device is a specially designed test tool, which contains a variety of preset error injection scenario circuits. These circuits are used to simulate various possible hardware failures, such as power failure, signal line break, device identification error, etc. Each preset error injection scenario circuit can generate a specific test scenario to evaluate the performance and stability of the server hardware when facing specific failures. The connection relationship information refers to how the server hardware to be tested and the short-circuit device are related to each other through physical connections (such as cables, slots, etc.).

[0033] Furthermore, according to the connection relationship information obtained by analysis and the determined injection error test mode, a target injection error scenario circuit is determined from a plurality of preset injection error scenario circuits in the short-circuiting device, and the circuit can simulate a specific fault type related to the server hardware to be tested. It should be noted that in the present invention, the server hardware to be tested has been connected to the short-circuiting device, wherein a multi-way switch is provided in the short-circuiting device, and the required switches can be closed through corresponding control instructions to form a path between the server hardware to be tested and the corresponding injection error scenario circuit.

[0034] Step 103: Based on the target test scenario, perform an error injection test on the server hardware to be tested.

[0035] After determining the target test scenarios, the next step is to perform error injection testing based on these scenarios. In the present invention, a short-circuit device is used to inject preset faults into the server hardware to be tested, and the response of the hardware is observed and recorded, including but not limited to whether the system can run stably, whether the data remains intact, whether the fault is detected and processed in time, etc. The key to error injection testing is to simulate the fault conditions in the real environment and evaluate the fault tolerance and recovery mechanism of the server hardware. Through repeated testing and adjustment, the design and configuration of the hardware can be gradually optimized to improve its reliability and stability.

[0036] The error injection test method provided by the present invention determines the error injection test mode of the server hardware to be tested by acquiring the device type information, and then determines the target test scenario according to the connection relationship information between the short-circuit device constructed by a plurality of preset error injection scenario circuits and the server hardware to be tested, thereby more efficiently and flexibly performing the error injection test on the server hardware to be tested, and at the same time, no damage is caused to the server hardware to be tested during the test process.

[0037] Based on the above embodiment, the step of determining the error injection test mode for performing an error injection test on the server hardware to be tested includes: If the server hardware to be tested is a memory device, it is determined that the error injection test mode of the server hardware to be tested is a memory failure test mode.

[0038] In the present invention, different testing strategies and methods need to be formulated for different types of hardware devices to ensure their quality and reliability. Device type information, as an important input in the test preparation phase, provides detailed information about the hardware to be tested, so that the appropriate test mode can be accurately determined.

[0039] Specifically, the device type information covers various types of hardware devices, including memory devices and devices that follow high-speed serial computer expansion bus standards (such as PCIE). Memory devices, such as DRAM (dynamic random access memory), NAND flash memory, etc., are core components used to store and access data in servers. High-speed serial computer expansion bus standard devices, such as PCIE devices, are used to connect various high-speed peripherals, such as graphics cards, network interface cards, solid-state drives, etc., which transmit data with processors through high-speed serial communication.

[0040] If the server hardware to be tested is a memory device, its injection test mode can be determined to be a memory failure test mode. The memory failure test mode is designed to simulate various memory failures, such as data corruption, address conflicts, and access delays, to evaluate the performance of memory devices under these abnormal conditions. Through the memory failure test mode, the performance, stability, and fault tolerance of memory devices can be fully evaluated to ensure their reliability and durability in actual applications. At the same time, this also provides strong data support for subsequent hardware improvements and optimizations.

[0041] On the basis of the above embodiment, the preset injection error scenario circuit includes a first injection error scenario circuit and a second injection error scenario circuit, wherein the first injection error scenario circuit is used to simulate the situation of short-circuiting one data signal line; the second injection error scenario circuit is used to simulate the situation of short-circuiting two data signal lines; In any of the injection error test modes, setting the working state of the short-circuit device to generate a target test scenario includes: Based on the conduction state between the target output end in the multi-way switch module of the short-circuiting device and the preset error injection scenario circuit, the connection relationship information between the server hardware to be tested and the short-circuiting device is obtained; wherein, the target output end is an output end connected to the corresponding preset error injection scenario circuit among the multiple output ends of the multi-way switch module; the target hole slot of the server hardware to be tested is connected to the corresponding input end in the multi-way switch module through a DuPont male pin; the target hole slot is a hole slot connected to the ground wire at the slot of the server hardware to be tested; If the injection error test mode is the memory fault test mode, determining whether the current test phase is a server startup phase; When determining that the current test phase is the server startup phase, if the conduction state corresponding to the connection relationship information is the first conduction state, and after a preset time, the conduction state corresponding to the connection relationship information is switched from the first conduction state to the disconnection state, it is determined that the target test scenario is a memory single-bit fault repair scenario; wherein the first conduction state is a state in which the target output end in the multi-way switch module is connected to the first injection error scenario circuit; If the conduction state corresponding to the connection relationship information is the first conduction state, it is determined that the target test scenario is a memory isolation test scenario.

[0042] In the present invention, a test method for implementing fault simulation based on a switch button is provided. Specifically, with DuPont public pins as wiring terminals, according to the circuit design, several lines are led out to a switch button (i.e., a multi-way switch module), and each line can be connected to a server hardware to be tested; then, according to the test needs, during the test process, each DuPont public pin is inserted into the corresponding small hole slot next to the memory stick slot, i.e., the target hole slot. In the present invention, this target hole slot is the hole slot on both sides of the gold finger of the memory stick slot, and the hole slot needs to be connected to the ground wire to ensure that the equipment is not damaged during the test process; then, after receiving the corresponding operation instruction and driving the corresponding switch button to realize the path between the server hardware to be tested and the preset error injection scenario circuit, the corresponding memory fault is simulated (it can also be realized for PCIE faults), so as to achieve the test purpose of the memory part test scenario during the RAS test process.

[0043] In the present invention, the short-circuit device contains a variety of preset error injection scenario circuits, each of which is designed to simulate a specific hardware failure. For the memory failure test scenario, the first error injection scenario circuit is used to simulate the situation of short-circuiting a data signal line. This short-circuit may cause data transmission errors or system instability, which is an important part of the memory failure test. The second error injection scenario circuit is used to simulate the situation of short-circuiting two data signal lines. This failure may be more complicated because it may trigger more error detection and recovery mechanisms.

[0044] In order to determine the target test scenario, it is first necessary to configure the multi-way switch module according to the connection relationship information between the server hardware to be tested and the short-circuit device, as well as the currently set error injection test mode (such as memory failure test mode). The multi-way switch module selectively turns on or off different preset error injection scenario circuits as needed. The multi-way switch module has multiple output terminals, each of which can be connected to a specific preset error injection scenario circuit.

[0045] In the present invention, the connection relationship information includes the slot position of the server hardware to be tested, the input terminal connected to the multi-way switch module, and the physical connection established by the DuPont male pin. The DuPont male pin is used to be inserted into the hole groove connected to the ground wire at the slot of the server hardware to be tested, so as to establish a connection with the multi-way switch module.

[0046] Figure 2 The overall flow chart of the injection error test method provided by the present invention can be referred to Figure 2As shown, in the memory fault test mode, for the server startup phase, if the target output end of the multi-way switch module and the first error scenario circuit are in the on state (i.e., the first on state), and after a preset time, the on state is switched to the off state, it indicates that the system has successfully detected and repaired a single-bit fault. This scenario is used to evaluate the system's ability to detect and repair single-bit faults.

[0047] If during the server startup phase, the target output end of the multi-way switch module and the first error scenario circuit remain in the on state and do not switch to the off state, it indicates that the system may not be able to correctly identify or isolate the fault. This scenario is used to evaluate the system's isolation capabilities when facing continuous faults. In the actual test process, according to the preset test plan information, the switches on the multi-way switch module can be switched through control instructions to switch different conduction states, thereby simulating different fault scenarios and providing a test environment that is more in line with actual scenarios. At the same time, monitor the system's response and output to evaluate the system's performance and stability under different fault scenarios.

[0048] On the basis of the above embodiments, in any of the injection error test modes, setting the working state of the short-circuit device to generate a target test scenario also includes: When determining that the current test phase is the server operation phase, if the conduction state corresponding to the connection relationship information is the second conduction state, determining that the target test scenario is a memory uncorrectable fault test scenario; wherein the second conduction state is a state in which the target output terminal in the multi-way switch module is conductive with the second injection error scenario circuit; If the conduction state corresponding to the connection relationship information is the first conduction state, it is determined that the target test scenario is a memory correctable fault test scenario.

[0049] In the present invention, a three-position multi-way switch module is provided on the short-circuit device as a push button switch, wherein switch position 0 corresponds to the first injection error scenario circuit, switch position 1 corresponds to the open circuit, and switch position 2 corresponds to the second injection error scenario circuit. Six flying wires are led out of the push button switch, and DuPont male pins are welded on the wires for inserting into the corresponding slot holes of the server hardware to be tested.

[0050] When the server is in the operation stage, when the button switch is in switch position 1, it is in the disconnected state without any short circuit; when the button switch is turned to switch position 0, a data signal line (DQ line) is short-circuited, which can construct a memory correctable fault (Correctable Error, referred to as CE); when the button switch is turned to switch position 2, two DQ lines are short-circuited at the same time, constructing a memory uncorrectable fault (UnCorrectable Error, referred to as UCE).

[0051] Specifically, according to different test scenario requirements, corresponding control instructions for the multi-way switch module are generated to achieve the corresponding path status. Figure 2 As shown, if you need to test memory storm suppression during the running stage, you can turn the switch to switch gear 0 and keep this state; when testing memory CE fault reporting during the running stage, turn the switch to switch gear 0 and keep this state, or turn the switch to switch gear 0 and then turn it back to switch gear 1; when testing memory UCE fault reporting during the running stage, turn the switch to switch gear 2 and keep this state, or turn the switch to switch gear 2 and then turn it back to switch gear 1.

[0052] When testing the memory isolation scenario in the startup phase, turn the switch to switch position 0 and maintain this state. When testing the memory single-bit failure in the startup phase and the failure will be repaired, turn the switch to switch position 0 in the startup phase mode and quickly turn it back to switch position 1 to avoid continuous short circuit and triggering of the failure.

[0053] In the present invention, reference may be made to Figure 2 As shown in the figure, when a memory fault occurs during the test server startup phase: If a single-bit memory fault can be repaired during the test startup phase, turn the switch to position 0, and then quickly turn it back to position 1. If the faulty memory can be isolated during the test startup phase, turn the switch to position 0 and keep this state until the startup is complete, so as to check the isolation status of the memory bar and the alarm status of the BMC page.

[0054] When testing a memory failure during the server operation phase: If testing the memory storm suppression scenario, or testing the memory CE fault reporting function scenario, turn the test switch to switch gear 0. When testing the memory storm suppression, it is necessary to keep the short circuit state, that is, the switch remains in switch gear 0, and does not turn it back at this time; when testing the memory CE fault reporting, you can quickly turn the switch to switch gear 0, and then quickly turn it back to switch gear 1. When testing a memory failure during the server operation phase, for the UCE failure of the test memory, you can switch the scene by shorting the two memory DQ lines, that is, turning the switch to switch gear 2. During the test, you can keep this switch state or turn it back.

[0055] The present invention provides a test method by simulating hardware faults, and uses an economical and applicable short-circuit switch to construct a simple short-circuit device, so as to achieve the effect of simply constructing CE faults and UCE faults. At the same time, by using the above short-circuit device to construct a fault memory, the test scene can be flexibly changed according to the test needs, and the damage to normal equipment can be avoided. Moreover, the test is very convenient to execute, and only the switch button needs to be adjusted as needed, which effectively reduces the test cost.

[0056] Based on the above embodiment, the method further includes: If the server hardware to be tested is a high-speed serial computer expansion bus standard device, determining that the error injection test mode of the server hardware to be tested is a high-speed serial computer expansion bus standard device fault test mode; It is determined whether the conduction state corresponding to the connection relationship information is the first conduction state, and if so, it is determined that the target test scenario is a high-speed serial computer expansion bus standard device fault test scenario.

[0057] The test method of PCIE device is similar to the memory test method. In view of the problem that the PCIe module in the related art has quite mature test tools and test software, but there are few test tools and test software for ARM platform, the short-circuit device provided by the present invention can also simulate PCIe device failure to make up for the lack of test methods for PCIe module. In the present invention, for the scenario of constructing PCIE failure, it is only necessary to connect a pair of DuPont male pins to the slot of the PCIE device, and when testing, turn the switch to switch gear 0 (conducting with the first error scenario circuit).

[0058] Based on the above embodiment, the method further includes: When it is determined that the current test phase is the server operation phase, if the conduction state corresponding to the connection relationship information is the first conduction state or the second conduction state, and each input end in the multi-way switch module is connected to a corresponding server hardware to be tested, it is determined that the target test scenario is a multiple memory failure test scenario.

[0059] In the present invention, a multi-way switch module is a hardware component that can selectively connect multiple inputs to a single output. In this test scenario, each input terminal is connected to a server hardware component to be tested (such as a memory stick, etc.). When the server is running, the connection relationship is in a specific conduction state (the first conduction state or the second conduction state), and the multi-way switch module is connected to the server hardware to be tested, the test system determines that the current target test scenario is a multi-memory fault test scenario, which will focus on detecting memory-related faults, especially faults that may occur when multiple memory components work at the same time, thereby ensuring the stability and reliability of the server in high load and complex task processing.

[0060] The following is a description of the injection error testing device provided by the present invention. The injection error testing device described below and the injection error testing method described above can be referenced to each other.

[0061] Figure 3 The structural diagram of the injection error testing device provided by the present invention is as follows: Figure 3As shown, the present invention provides an error injection test device, including a test mode determination module 301, a test scenario determination module 302 and an error injection test module 303, wherein the test mode determination module 301 is used to determine the error injection test mode for performing an error injection test on the server hardware to be tested; the test scenario determination module 302 is used to set the working state of a short-circuit device under any of the error injection test modes to generate a target test scenario; the short-circuit device includes at least one short-circuit wire with one end connected to a hole slot of the server hardware to be tested, one end of a short-circuit wire connected to a preset error injection scenario circuit, and a switch arranged on the short-circuit wire; the error injection test module 303 is used to perform an error injection test on the server hardware to be tested based on the target test scenario.

[0062] The error injection test device provided by the present invention determines the error injection test mode of the server hardware to be tested by acquiring the device type information, and then determines the target test scenario according to the connection relationship information between the short-circuit device constructed by a plurality of preset error injection scenario circuits and the server hardware to be tested, thereby performing the error injection test on the server hardware to be tested more efficiently and flexibly, and at the same time, will not cause damage to the server hardware to be tested during the test process.

[0063] The device provided by the present invention is used to execute the above-mentioned method embodiments. Please refer to the above-mentioned embodiments for the specific processes and detailed contents, which will not be repeated here.

[0064] Figure 4 The structural diagram of the injection error test system provided by the present invention is as follows: Figure 4 As shown, the present invention provides an injection error test system, including the injection error test device 401 and the short-circuit device 402 described in the above embodiment, wherein the short-circuit device 401 is based on a DuPont male pin, a multi-way switch module and a plurality of preset injection error scenario circuits, wherein: The first end of the DuPont male pin is connected to the target hole slot of the server hardware to be tested, and the second end of the DuPont male pin is connected to the corresponding input end of the multi-way switch module, wherein the target hole slot is the hole slot connected to the ground wire at the slot of the server hardware to be tested; The target output end in the multi-way switch module is connected to the corresponding preset error injection scenario circuit, wherein the target output end is an output end among the multiple output ends of the multi-way switch module connected to the corresponding preset error injection scenario circuit.

[0065] In the present invention, the injection error test system is composed of two main parts: an injection error test device 401 and a short-circuit device 402. The purpose of this system is to test the reliability and fault tolerance of server hardware by simulating hardware failures. Specifically, the function of the injection error test device 401 can refer to the injection error test device described in the above embodiment. The device can be used to control the operation of the short-circuit device 402, and receive and process feedback data from the short-circuit device and the server hardware to be tested.

[0066] The short-circuit device 402 is composed of a DuPont male pin, a multi-way switch module, and a plurality of preset error injection scenario circuits. The DuPont male pin is a commonly used connection device with reliable electrical connection performance. In this system, the first end of the DuPont male pin is connected to the target hole slot of the server hardware to be tested, and these target hole slots are the hole slots connected to the ground wire at the server hardware slot. The second end of the DuPont male pin is connected to the corresponding input end in the multi-way switch module, so that the conduction state between the server hardware to which the DuPont male pin is connected and the different preset error injection scenario circuits can be controlled by the multi-way switch module.

[0067] A multi-way switch module is an electronic device that can selectively connect multiple inputs to a single or multiple outputs. In the present invention, the input end of the multi-way switch module is connected to the second end of the DuPont male pin, and the output end is connected to the corresponding preset error injection scenario circuit. By changing the connection state of the multi-way switch module, different preset error injection scenario circuits can be selectively activated to simulate different hardware failures.

[0068] The preset error injection scenario circuit is an electronic circuit that simulates a specific hardware failure. Each preset error injection scenario circuit corresponds to a specific hardware failure, such as a memory module failure, a hard disk failure, etc. When the output end of the multi-way switch module is connected to a preset error injection scenario circuit, the circuit will be activated, thereby simulating the corresponding hardware failure.

[0069] In the present invention, the server hardware to be tested is installed in the test environment, and the first end of the DuPont male pin is connected to the target hole slot. The multi-way switch module is controlled by the injection error test device 401 to selectively activate different preset injection error scenario circuits, thereby obtaining the performance of the server hardware to be tested under simulated fault conditions and recording relevant data. Finally, the reliability and fault tolerance of the server hardware are analyzed based on the test results.

[0070] The error injection test system provided by the present invention determines the error injection test mode of the server hardware to be tested by acquiring the device type information, and then determines the target test scenario according to the connection relationship information between the short-circuit device constructed by a plurality of preset error injection scenario circuits and the server hardware to be tested, thereby performing the error injection test on the server hardware to be tested more efficiently and flexibly, and at the same time, will not cause damage to the server hardware to be tested during the test process.

[0071] Figure 5 A schematic diagram of the structure of an electronic device provided by the present invention, such as Figure 5 As shown, the electronic device may include: a processor (Processor) 501, a communication interface (Communications Interface) 502, a memory (Memory) 503 and a communication bus 504, wherein the processor 501, the communication interface 502, and the memory 503 complete mutual communication through the communication bus 504. The processor 501 may call the logic instructions in the memory 503 to execute the error injection test method, which includes: determining the error injection test mode for performing the error injection test on the server hardware to be tested; in any of the error injection test modes, setting the working state of the short-circuit device to generate a target test scenario; the short-circuit device includes at least one short-circuit wire with one end connected to the hole slot of the server hardware to be tested, one end of the short-circuit wire connected to the preset error injection scenario circuit, and a switch set on the short-circuit wire; based on the target test scenario, performing the error injection test on the server hardware to be tested.

[0072] In addition, the logic instructions in the above-mentioned memory 503 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0073] On the other hand, the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the error injection test method provided by the above methods, and the method includes: determining an error injection test mode for performing an error injection test on the server hardware to be tested; in any of the error injection test modes, setting the working state of a short-circuit device to generate a target test scenario; the short-circuit device includes at least one short-circuit wire having one end connected to a hole slot of the server hardware to be tested, one end of a short-circuit wire connected to a preset error injection scenario circuit, and a switch arranged on the short-circuit wire; based on the target test scenario, performing an error injection test on the server hardware to be tested.

[0074] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the error injection test method provided by the above-mentioned embodiments, the method comprising: determining an error injection test mode for performing an error injection test on the server hardware to be tested; in any of the error injection test modes, setting a working state of a short-circuit device to generate a target test scenario; the short-circuit device comprises at least one short-circuit wire having one end connected to a hole slot of the server hardware to be tested, a short-circuit wire having one end connected to a preset error injection scenario circuit, and a switch arranged on the short-circuit wire; based on the target test scenario, performing an error injection test on the server hardware to be tested.

[0075] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0076] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing injection errors, characterized in that: include: Determine the error injection test mode for performing error injection test on the server hardware to be tested; In any of the injection error test modes, the working state of the short-circuit device is set to generate a target test scenario; the short-circuit device includes at least one short-circuit wire having one end connected to the hole slot of the server hardware to be tested, one end connected to the preset injection error scenario circuit, and a switch arranged on the short-circuit wire; Based on the target test scenario, an error injection test is performed on the server hardware to be tested.

2. The injection error testing method according to claim 1, characterized in that: Determining the error injection test mode for performing an error injection test on the server hardware to be tested includes: If the server hardware to be tested is a memory device, it is determined that the error injection test mode of the server hardware to be tested is a memory failure test mode.

3. The injection error testing method according to claim 2, characterized in that: The preset injection error scenario circuit includes a first injection error scenario circuit and a second injection error scenario circuit, wherein the first injection error scenario circuit is used to simulate a situation where one data signal line is short-circuited; the second injection error scenario circuit is used to simulate a situation where two data signal lines are short-circuited; In any of the injection error test modes, setting the working state of the short-circuit device to generate a target test scenario includes: Based on the conduction state between the target output end in the multi-way switch module of the short-circuiting device and the preset error injection scenario circuit, the connection relationship information between the server hardware to be tested and the short-circuiting device is obtained; wherein, the target output end is an output end connected to the corresponding preset error injection scenario circuit among the multiple output ends of the multi-way switch module; the target hole slot of the server hardware to be tested is connected to the corresponding input end in the multi-way switch module through a DuPont male pin; the target hole slot is a hole slot connected to the ground wire at the slot of the server hardware to be tested; If the injection error test mode is the memory fault test mode, determining whether the current test phase is a server startup phase; When determining that the current test phase is the server startup phase, if the conduction state corresponding to the connection relationship information is the first conduction state, and after a preset time, the conduction state corresponding to the connection relationship information is switched from the first conduction state to the disconnection state, it is determined that the target test scenario is a memory single-bit fault repair scenario; wherein the first conduction state is a state in which the target output end in the multi-way switch module is connected to the first injection error scenario circuit; If the conduction state corresponding to the connection relationship information is the first conduction state, it is determined that the target test scenario is a memory isolation test scenario.

4. The injection error testing method according to claim 3, characterized in that: In any of the injection error test modes, setting the working state of the short-circuit device to generate a target test scenario also includes: When determining that the current test phase is the server operation phase, if the conduction state corresponding to the connection relationship information is the second conduction state, determining that the target test scenario is a memory uncorrectable fault test scenario; wherein the second conduction state is a state in which the target output terminal in the multi-way switch module is conductive with the second injection error scenario circuit; If the conduction state corresponding to the connection relationship information is the first conduction state, it is determined that the target test scenario is a memory correctable fault test scenario.

5. The injection error testing method according to claim 4, characterized in that: The method further comprises: When it is determined that the current test phase is the server operation phase, if the conduction state corresponding to the connection relationship information is the first conduction state or the second conduction state, and each input end in the multi-way switch module is connected to a corresponding server hardware to be tested, it is determined that the target test scenario is a multiple memory failure test scenario.

6. The injection error testing method according to claim 3, characterized in that: The method further comprises: If the server hardware to be tested is a high-speed serial computer expansion bus standard device, determining that the error injection test mode of the server hardware to be tested is a high-speed serial computer expansion bus standard device fault test mode; It is determined whether the conduction state corresponding to the connection relationship information is the first conduction state, and if so, it is determined that the target test scenario is a high-speed serial computer expansion bus standard device fault test scenario.

7. A mis-injection testing device, characterized in that: include: A test mode determination module, used to determine an error injection test mode for performing an error injection test on the server hardware to be tested; A test scenario determination module, used to set the working state of the short-circuit device in any of the injection error test modes to generate a target test scenario; the short-circuit device includes at least one short-circuit wire having one end connected to the hole slot of the server hardware to be tested, one end connected to the preset injection error scenario circuit, and a switch arranged on the short-circuit wire; The error injection test module is used to perform an error injection test on the server hardware to be tested based on the target test scenario.

8. A mis-injection testing system, characterized in that: The invention comprises the injection error test device and the short-circuit device as described in claim 7, wherein the short-circuit device is composed of a DuPont male pin, a multi-way switch module and a plurality of preset injection error scenario circuits, wherein: The first end of the DuPont male pin is connected to the target hole slot of the server hardware to be tested, and the second end of the DuPont male pin is connected to the corresponding input end of the multi-way switch module, wherein the target hole slot is the hole slot connected to the ground wire at the slot of the server hardware to be tested; The target output end in the multi-way switch module is connected to the corresponding preset error injection scenario circuit, wherein the target output end is an output end among the multiple output ends of the multi-way switch module connected to the corresponding preset error injection scenario circuit.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the injection error testing method according to any one of claims 1 to 6 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the injection error testing method according to any one of claims 1 to 6 is implemented.

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