Heterogeneous shared dynamic adjustment cache method, equipment and medium
By monitoring memory access information in the GPGPU source program and dynamically adjusting cache division rules and replacement policies, the problem of GPGPU occupying a large amount of LLC space is solved, and efficient cache resource allocation and system performance improvement are achieved.
CN119645898AActive Publication Date: 2025-03-18SHANDONG INSPUR SCI RES INST CO LTD
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Patent Information
- Application Number
- CN202510188599.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-20
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2045-02-20
AI Technical Summary
Technical Problem
During heterogeneous program execution, GPGPU occupies a large amount of last-level cache (LLC) space, limiting the cache usage of CPU applications, resulting in a reduced cache hit rate and increasing time waste and power consumption.
Method used
By using the memory fetch counter and the memory fetch miss counter in the GPGPU source program, the memory fetch miss rate of the GPGPU is dynamically calculated, and the cache division rules and replacement strategies are adjusted according to this rate to ensure the reasonable allocation and efficient utilization of cache resources.
Benefits of technology
It realizes improving CPU performance, improving cache hit rate, and optimizing overall system processing performance without affecting GPGPU performance.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention discloses a heterogeneous sharing dynamic adjustment cache method, equipment and a medium, belongs to the technical field of computers, and aims to solve the technical problem of how to fully consider the characteristics of a CPU application program and a GPGPU application program and reasonably divide the cache capacity so as to relieve the competition of the CPU application program and the GPGPU application program for a memory and improve the cache hit rate. According to the technical scheme, a second-level cache receives a cache request from a first-level cache, an LRU replacement strategy or an LFU replacement strategy is used, and an initialization proportion is distributed to the second-level cache; the memory access information of the GPGPU is monitored in the GPGPU source program through a GPGPU memory access counter and a GPGPU memory access missing counter at a self-defined time interval; and calculating the memory access missing rate of the GPGPU in the corresponding time interval according to the memory access counting information and the memory access missing information collected in the continuous time interval.
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