Data transmission / reception circuit, data training circuit, and semiconductor device

Abstract

The invention relates to a data transmitting / receiving circuit, a data training circuit, and a semiconductor device including the same. The data receiving circuit includes a first inductor, a second inductor, and a T-coil equalization circuit. The first inductor is coupled between the second node and a first node coupled to the data input / output pad. The second inductor is coupled between the second node and the internal circuit. The T-coil equalization circuit includes a T-coil having at least one capacitor coupled with the second node. The T-coil equalization circuit is configured to adjust an induction peak of the T-coil in response to a control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Application No. 10-2023-0123868 filed on September 18, 2023 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to semiconductor circuits, and more particularly to a data transmission / reception circuit, a data training circuit, and a semiconductor device including the same. Background Art

[0004] Figure 1 is a diagram showing a configuration of a data receiving circuit according to the prior art. Figure 1 , the semiconductor device according to the related art receives data DIN transmitted by a host through a channel via a data input / output pad 11 and transmits it to a deserializer (DESER) 13 .

[0005] Because the channel degrades the quality of the transmitted signal due to inter-symbol interference (ISI), the data is received through a continuous time linear equalizer (CTLE) 12 to compensate for this.

[0006] However, there are problems in that the circuit area and current consumption of the data receiving circuit are increased by using the continuous time linear equalizer 12 , and there is a problem in that the DC gain is reduced according to the operation of the time linear equalizer 12 . Summary of the invention

[0007] In an embodiment, the data receiving circuit may include a first inductor, a second inductor, and a T-coil balancing circuit. The first inductor may be coupled between the second node and the first node coupled to the data input / output pad. The second inductor may be coupled between the second node and the internal circuit. The T-coil balancing circuit may include a T-coil having at least one capacitor coupled to the second node, and may be configured to adjust the inductive peak of the T-coil in response to a control signal.

[0008] In an embodiment, the data training circuit may include a data receiving circuit, a deserializer, a data verification circuit, and a control circuit. The data receiving circuit may be coupled to the data input / output pad. The data receiving circuit may be configured to control the induction peak according to the control signal, and to receive data sent via the data input / output pad. The deserializer may be configured to deserialize the data output from the data receiving circuit to generate parallel data. The data verification circuit may be configured to verify the parallel data to generate a data verification signal. The control circuit may be configured to change the value of the control signal until the data verification signal has a value indicating that the parallel data has been sent normally.

[0009] In an embodiment, the data transmission / reception circuit may include a data reception circuit and a data transmission circuit. The data reception circuit may include: a first inductor coupled between a second node and a first node coupled to a data input / output pad; a second inductor coupled between the second node and a third node; and a T-coil balancing circuit including a T-coil, the T-coil including at least one capacitor coupled between the second node and a ground terminal. The T-coil balancing circuit is configured to adjust an inductive peak of the T-coil in response to a control signal. The data transmission circuit may be coupled to the second node and configured to perform a driving operation and a balancing operation on internally generated data.

[0010] In an embodiment, the data receiving circuit includes a T-coil, which includes a first inductor, a second inductor and a capacitor, wherein the first inductor and the second inductor are connected in series so that the second end of the first inductor is connected to the first end of the second inductor, and wherein the first end of the capacitor is connected to the second end of the first inductor and the first end of the second inductor. The data receiving circuit also includes a plurality of switches, wherein the first end of each of the plurality of switches is connected to the second end of the capacitor. The data receiving circuit also includes a plurality of resistors, wherein the first end of each of the plurality of resistors is respectively connected to the second end of the associated switch in the plurality of switches, and wherein the second end of each of the plurality of resistors is coupled to a ground terminal. The data receiving circuit further includes a terminal resistor, wherein the first end of the terminal resistor is coupled to a power supply, and wherein the second end of the terminal resistor is coupled to the first end of the first inductor, between the second end of the first inductor and the first end of the second inductor, or coupled to the second end of the second inductor. The first end of the first inductor is coupled to a data input / output pad. The second end of the second inductor is coupled to an internal circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram showing a configuration of a data receiving circuit according to the related art.

[0012] Figure 2 is a diagram showing a configuration of a data receiving circuit according to an embodiment of the present disclosure.

[0013] Figure 3 is a diagram showing a configuration of a data receiving circuit according to an embodiment of the present disclosure.

[0014] Figure 4 is a diagram showing a configuration of a data receiving circuit according to an embodiment of the present disclosure.

[0015] Figure 5 is a diagram showing a configuration of a data transmission / reception circuit according to an embodiment of the present disclosure.

[0016] Figure 6is a diagram showing a configuration of a data training circuit according to an embodiment of the present disclosure.

[0017] Figure 7 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Various embodiments may improve signal quality without reducing DC gain, and may increase layout margin and reduce current consumption.

[0019] Hereinafter, various embodiments will be described in more detail with reference to the accompanying drawings.

[0020] Figure 2 is a diagram showing a configuration of a data receiving circuit 100 according to the embodiment.

[0021] Reference Figure 2 , the data receiving circuit 100 may be coupled between the data input / output pad 11 and an internal circuit (eg, a deserializer (DESER) 13 ).

[0022] The deserializer 13 is given here as an example of an internal circuit because when data transmitted via the data input / output pad 11 is input in a serial form, it is necessary to deserialize the data received by the data receiving circuit 100. Therefore, the deserializer 13 as an example of an internal circuit is only an example, and the internal circuit may be changed according to the data transmission method.

[0023] The data receiving circuit 100 may be coupled to the host via the data input / output pad 11 and a data transmission channel (hereinafter referred to as a channel). The data receiving circuit 100 may output the data DIN received via the data input / output pad 11 to the deserializer 13. The deserializer 13 may deserialize the data received from the data receiving circuit 100 to generate output data DOUT.

[0024] The data receiving circuit 100 may include a terminal resistor 110, a first inductor 121, a second inductor 122, and a T-coil equalization circuit 130. The data receiving circuit 100 may further include a buffer 140 coupled between the second inductor 122 and the deserializer 13 for buffering the data DIN after passing through the second inductor 122.

[0025] The terminal resistor 110 may be coupled between a power source and a first node ND11. The first node ND11 may be associated with the data input / output pad 11. The first inductor 121 may be coupled between the first node ND11 and a second node ND12. The second inductor 122 may be coupled between the second node ND12 and the deserializer 13.

[0026] The T-coil balancing circuit 130 may be coupled to the second node ND12. The T-coil balancing circuit 130 may include a T-coil having at least one capacitor coupled to the second node ND12, the second node ND12 being coupled to the first inductor 121 and the second inductor 122, and the T-coil balancing circuit 130 may be configured to adjust the inductive peak value of the T-coil in response to the control signal CTRL<1:N>.

[0027] The T-coil balancing circuit 130 may include a capacitor 131 , a resistor array 132 , and a switch circuit 133 .

[0028] The capacitor 131 may be associated with the second node ND12. The capacitor 131 may be coupled with the first inductor 121 and the second inductor 122 via the second node ND12 to form a T coil.

[0029] The resistor array 132 may include a plurality of resistors R1-Rn. The plurality of resistors R1-Rn may be designed to have substantially the same resistance value as each other. The plurality of resistors R1-Rn may also be designed to have different resistance values.

[0030] The switch circuit 133 may be coupled between the capacitor 131 and the plurality of resistors R1-Rn, and may operate in response to the control signal CTRL<1:N>. The switch circuit 133 may control the inductive peak of the T coil by selectively connecting the plurality of resistors R1-Rn to the capacitor 131 according to each signal bit of the control signal CTRL<1:N> to adjust the impedance. The switch circuit 133 may include a plurality of switches SW1-SWn. Each of the plurality of switches SW1-SWn may have one end commonly coupled to the capacitor 131, and the other end may be coupled to one of the plurality of resistors R1-Rn.

[0031] If the plurality of resistors R1-Rn are designed to have substantially the same resistance value as each other, the impedance can be adjusted by changing the number of resistors selected in the plurality of resistors R1-Rn according to the control signal CTRL<1:N>. On the other hand, when the plurality of resistors R1-Rn are designed to have different resistance values, the impedance can be adjusted by selecting different resistors in the plurality of resistors R1-Rn according to the control signal CTRL<1:N>, and in addition to this, the impedance can be adjusted by selecting the plurality of resistors R1-Rn in a variety of ways according to the control signal CTRL<1:N>.

[0032] The data receiving circuit 100 according to the embodiment can change the AC (alternating current) resistance of the T-coil equalizing circuit 130 by adjusting the value of the control signal CTRL<1:N>, while the DC (direct current) resistance of the terminal resistor 110 is constant, to compensate for the signal quality degradation caused by the inter-symbol interference in the channel. By using the T-coil equalizing circuit 130, the DC gain is not reduced and the current consumption can be reduced compared with the use of a continuous time linear equalizer in the prior art.

[0033] Figure 3 is a diagram showing a configuration of a data receiving circuit 200 according to the embodiment.

[0034] Reference Figure 3 , the data receiving circuit 200 may be coupled between the data input / output pad 11 and the deserializer (DESER) 13 .

[0035] The data receiving circuit 200 may be coupled to the data input / output pad 11 and coupled to the host via a channel. The data receiving circuit 200 may output data DIN received via the data input / output pad 11 to the deserializer 13. The deserializer 13 may deserialize the data received from the data receiving circuit 200 to generate output data DOUT.

[0036] The data receiving circuit 200 may include a terminal resistor 210, a first inductor 221, a second inductor 222, and a T-coil equalization circuit 230. The data receiving circuit 200 may further include a buffer 240 coupled between the second inductor 222 and the deserializer 13 for buffering the data DIN after passing through the second inductor 222.

[0037] The first inductor 221 may be coupled between the data input / output pad 11 and the first node ND21. The second inductor 222 may be coupled between the first node ND21 and the deserializer 13. The terminal resistor 210 may be coupled between a power source and the first node ND21.

[0038] The T-coil balancing circuit 230 may be coupled to the first node ND21. The T-coil balancing circuit 230 may include a T-coil having at least one capacitor coupled to the first node ND21, the first node ND21 being coupled to the first inductor 221 and the second inductor 222, and the T-coil balancing circuit 230 may be configured to adjust the inductive peak value of the T-coil in response to the control signal CTRL<1:N>.

[0039] The T-coil equalization circuit 230 may correspond to Figure 2The T-coil balancing circuit 130 is shown. The T-coil balancing circuit 230 may include a capacitor 231, a resistor array 232 including a plurality of resistors R1-Rn, and a switch circuit 233 including a plurality of switches SW1-SWn.

[0040] The capacitor 231 may be associated with the first node ND21. The capacitor 231 may be coupled with the first inductor 221 and the second inductor 222 via the first node ND21 to form a T coil.

[0041] The switch circuit 233 is coupled between the capacitor 231 and the plurality of resistors R1-Rn and can be operated in response to the control signal CTRL<1:N>. The switch circuit 233 can adjust the impedance and control the inductive peak of the T coil by selectively connecting the plurality of resistors R1-Rn to the capacitor 231 according to each signal bit of the control signal CTRL<1:N>. In different embodiments, one or more of the plurality of resistors R1-Rn can be selectively connected to the capacitor 231 in different combinations according to the control signal CTRL<1:N>.

[0042] The data receiving circuit 200 according to the embodiment can change the AC resistance of the T-coil equalizing circuit 230 by adjusting the value of the control signal CTRL<1:N>, while the DC resistance of the terminal resistor 210 is constant, to compensate for the signal degradation caused by the inter-symbol interference in the channel. By using the T-coil equalizing circuit 230, the DC gain is not reduced and the current consumption can be reduced compared with the use of the time linear equalizer in the prior art.

[0043] Figure 4 is a diagram showing a configuration of a data receiving circuit 300 according to the embodiment.

[0044] Reference Figure 4 , the data receiving circuit 300 may be coupled between the data input / output pad 11 and the deserializer (DESER) 13 .

[0045] The data receiving circuit 300 may be coupled to the data input / output pad 11 and coupled to the host via a channel. The data receiving circuit 300 may output data DIN received via the data input / output pad 11 to the deserializer 13. The deserializer 13 may deserialize the data received from the data receiving circuit 300 to generate output data DOUT.

[0046] The data receiving circuit 300 may include a terminal resistor 310, a first inductor 321, a second inductor 322, and a T-coil equalization circuit 330. The data receiving circuit 300 may further include a buffer 340 coupled between the second inductor 322 and the deserializer 13 for buffering the data DIN after passing through the second inductor 322.

[0047] The first inductor 321 may be coupled between the data input / output pad 11 and the first node ND31. The second inductor 322 may be coupled between the first node ND31 and the second node ND32. The terminal resistor 310 may be coupled between the power source and the second node ND32.

[0048] The T-coil balancing circuit 330 may be coupled to the first node ND31. The T-coil balancing circuit 330 may include a T-coil having at least one capacitor coupled to the first node ND31, the first node ND31 is coupled to the first inductor 321 and the second inductor 322, and the T-coil balancing circuit 330 may be configured to adjust the inductive peak value of the T-coil in response to the control signal CTRL<1:N>.

[0049] The T-coil equalization circuit 330 may correspond to Figure 2 The T-coil balancing circuit 130 is shown. The T-coil balancing circuit 330 may include a capacitor 331, a resistor array 332 including a plurality of resistors R1-Rn, and a switch circuit 333 including a plurality of switches SW1-SWn.

[0050] The capacitor 331 may be associated with the first node ND31. The capacitor 331 may be coupled with the first inductor 321 and the second inductor 322 via the first node ND31 to form a T coil.

[0051] The switch circuit 333 is coupled between the capacitor 331 and the plurality of resistors R1-Rn and can be operated in response to the control signal CTRL<1:N>. The switch circuit 333 can adjust the impedance and control the inductive peak of the T coil by selectively connecting the plurality of resistors R1-Rn to the capacitor 331 according to each signal bit of the control signal CTRL<1:N>. In different embodiments, one or more of the plurality of resistors R1-Rn can be selectively connected to the capacitor 331 in different combinations according to the control signal CTRL<1:N>.

[0052] The data receiving circuit 300 according to the embodiment can change the AC resistance of the T-coil equalizing circuit 330 by adjusting the value of the control signal CTRL<1:N>, while the DC resistance of the terminal resistor 310 is constant, to compensate for the signal degradation caused by the inter-symbol interference in the channel. By using the T-coil equalizing circuit 330, the DC gain is not reduced and the current consumption can be reduced compared with the use of the time linear equalizer in the prior art.

[0053] Figure 5 is a diagram showing a configuration of a data transmission / reception circuit 400 according to an embodiment of the present invention.

[0054] Reference Figure 5 , the data transmission / reception circuit 400 may include a data reception circuit 401 and a data transmission circuit 402 .

[0055] The data receiving circuit 401 may include a terminal resistor 410, a first inductor 421, a second inductor 422, and a T-coil equalization circuit 430. The data receiving circuit 401 may further include a buffer 440 coupled to the second inductor 422 for buffering the data DIN after passing through the second inductor 422.

[0056] The terminal resistor 410 may be coupled between the power supply and the first node ND41. The first inductor 421 may be coupled between the first node ND41 and the second node ND42. The second inductor 422 may be coupled between the second node ND42 and the third node ND43. The T-coil balancing circuit 430 may be coupled between the second node ND42 and the ground terminal. The T-coil balancing circuit 430 may correspond to Figure 2 The T-coil equalizing circuit 130 is shown. The buffer 440 may be associated with the third node ND43.

[0057] The data transmission circuit 402 may include a pre-driver (DRV&EQ) 450 having an equalization function, a main driver 460, and a capacitor 470. The data transmission circuit 402 may further include a buffer 480 associated with the third node ND43.

[0058] The pre-driver 450 may receive an input of internally generated data (i.e., read data Data_in) and perform an equalization operation on the read data Data_in. The pre-driver 450 may perform an equalization operation on the read data Data_in in a pre-enhanced manner. The main driver 460 may be coupled to the second node ND42 via a capacitor 470. The main driver 460 may drive the second node ND42 based on the output of the pre-driver 450. The buffer 480 may buffer the read data Data_in and output it to a third node ND43.

[0059] Figure 6 is a diagram showing a configuration of a data training circuit 500 according to an embodiment.

[0060] Reference Figure 6 The data training circuit 500 may include a data receiving circuit 501 , a deserializer 13 , a data verification circuit 502 and a control circuit 503 .

[0061] The data receiving circuit 501 may be coupled to the data input / output pad 11 and configured to control a sensing peak according to a control signal CTRL<1:N> and receive data transmitted via the data input / output pad 11 .

[0062] The data receiving circuit 501 can selectively apply the reference Figures 2 to 5 The invention may be configured by any one of the data receiving circuits 100, 200, 300, 401 described above.

[0063] The deserializer 13 may deserialize the data output from the data receiving circuit 501 to generate parallel data DOUT.

[0064] The data verification circuit 502 can verify the parallel data DOUT to generate a data verification signal DF. The data verification circuit 502 can determine whether the parallel data DOUT is normal based on the parity signal included in the parallel data DOUT, that is, whether it is the same as the data sent from the host, and can generate a data verification signal DF based on the determination result. The data verification circuit 502 can determine whether the parallel data DOUT is normal by performing an operation on the parallel data DOUT to generate a parity signal and comparing it with the parity signal included in the parallel data DOUT. The data verification circuit 502 may include parity signal operation logic. If the parallel data DOUT is normal, the data verification circuit 502 can output a high-level data verification signal DF, and if the parallel data DOUT is abnormal, the data verification circuit 502 can output a low-level data verification signal DF.

[0065] The control circuit 503 may receive the data verification signal DF and the test mode signal TM as inputs, and output the control signal CTRL<1:N>. The control circuit 503 may control the data training operation by changing the value of the control signal CTRL<1:N> until the data verification signal DF is at a value (i.e., a high level) indicating that the parallel data DOUT has been normally transmitted. The control circuit 503 may include control logic for changing the value of the control signal CTRL<1:N> based on the value of the data verification signal DF.

[0066] Alternatively, the control circuit 503 may set the value of the control signal CTRL<1:N> according to the test mode signal TM. The control circuit 503 may monitor the parallel data DOUT outside the data training circuit 500 to determine whether it is normal, and accordingly use the test mode signal TM to set the value of the control signal CTRL<1:N>.

[0067] Next, the data training operation of the data training circuit 500 is described.

[0068] Data output from the host is input to the data receiving circuit 501 via the channel and the data input / output pad 11 .

[0069] The data receiving circuit 501 receives data with an impedance according to a control signal CTRL<1:N> of a default value (hereinafter referred to as DFT).

[0070] The deserializer 13 deserializes the data output from the data receiving circuit 501 to generate parallel data DOUT.

[0071] At this time, if the signal compensation capability of the data receiving circuit 501 according to the default value of the control signal CTRL<1:N> cannot compensate for the signal degradation caused by the channel, the data verification circuit 502 may output a low-level data verification signal DF, indicating that the data is abnormal.

[0072] Because the data verification signal DF is at a low level, the control circuit 503 changes the value of the control signal CTRL<1:N> to a value (DFT+1) one level higher than the default value (DFT).

[0073] The data receiving circuit 501 receives data with an impedance according to the control signal CTRL<1:N> of a one-stage increase value (DFT+1).

[0074] The data training operation may be performed by the control circuit 503 repeatedly changing the value of the control signal CTRL<1:N> to a value one level higher than the previous value until the data verification signal DF becomes a high level, indicating that the data is normal.

[0075] The above training method is just an example of increasing the value of the control signal CTRL<1:N> by one level, but the training can also be performed by reducing the value of the control signal CTRL<1:N> by one level, or by repeating the process of increasing and decreasing the value of the control signal CTRL<1:N>. In other words, the value of the control signal CTRL<1:N> can be changed, such as DFT, DFT+1, DFT-1, DFT+2, DFT-2, etc., until the data verification signal DF is at a high level, indicating that the data is normal.

[0076] Figure 7is a diagram showing a configuration of a semiconductor device 600 according to an embodiment.

[0077] Reference Figure 7 , the semiconductor device 600 may include a memory core 601 , an address decoder 602 , a data input / output circuit 604 , a memory control circuit 605 , and an input / output pad unit 606 .

[0078] The memory core 601 may include a plurality of unit cells, and the plurality of unit cells may include at least one of a volatile memory and a non-volatile memory. The volatile memory may include an SRAM (static RAM), a DRAM (dynamic RAM), and an SDRAM (synchronous DRAM). The non-volatile memory may include a ROM (read-only memory), a PROM (programmable ROM), an EEPROM (electrically erasable programmable ROM), an EPROM (electrically programmable ROM), a flash memory, a PRAM (phase change RAM), an MRAM (magnetic RAM), an RRAM (resistive RAM), and a FRAM (ferroelectric RAM). The unit cells of the memory core 601 may be divided into a plurality of storage areas, such as a plurality of storage bodies BK0-BKn-1.

[0079] The address decoder 602 may be associated with the memory control circuit 605 and the memory core 601. The address decoder 602 may decode an address signal provided by the memory control circuit 605, and may access the memory core 601 in response to the decoding result.

[0080] The data input / output circuit 604 may be coupled to the memory core 601 via a global input / output line GIO. The data I / O circuit 604 may exchange data with an external system or the memory core 601.

[0081] The data input / output circuit 604 may include Figures 2 to 4 The data receiving circuits 100, 200 and 300, Figure 5 The data transmission / reception circuit 400 and Figure 6 At least one of the data training circuits 500.

[0082] The data input / output circuit 604 can compensate for the signal quality degradation caused by the inter-symbol interference in the channel by changing the AC resistance of the T-coil equalization circuit while the DC resistance caused by the terminal resistor is constant. By adopting the T-coil equalization circuit, the DC gain is not reduced and the current consumption can be reduced compared with the use of a continuous time linear equalizer in the prior art.

[0083] The memory control circuit 605 may be coupled to the memory core 601, the address decoder 602, and the data input / output circuit 604. The memory control circuit 605 may be provided with a command CMD, an address ADD, a clock signal WCK, etc. The memory control circuit 605 may provide an address decoded by the address decoder 602 to the data input / output circuit 604. The memory control circuit 605 may control a test operation and a normal operation of the semiconductor device 600. The normal operation may include a read operation, a write operation, and an address processing operation.

[0084] The input / output pad unit 606 may include a plurality of pads 607 for receiving a command CMD, an address ADD, and a clock signal WCK and for inputting and outputting data DQ. Hereinafter, the pads for inputting and outputting data DQ will be referred to as a plurality of data input / output pads. Any one of the plurality of data input / output pads may be used to input data provided by the host.

[0085] Those skilled in the art to which the present disclosure belongs will understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the above-mentioned embodiments are exemplary in all aspects and not restrictive. The scope of the present disclosure is defined by the attached claims rather than the detailed description, and it should be understood that the meaning and scope of the claims and all changes or modifications derived from their equivalent concepts are included in the scope of the present disclosure.

Claims

1. A data receiving circuit, comprising: a first inductor coupled between a first node and a second node, the first node being coupled to the data input / output pad; a second inductor coupled between the second node and the internal circuit; as well as The T-coil balancing circuit includes a T-coil having at least one capacitor coupled to the second node, and the T-coil balancing circuit adjusts an inductive peak of the T-coil in response to a control signal. 2 . The data receiving circuit of claim 1 , further comprising a terminal resistor coupled to the first node. 3 . The data receiving circuit of claim 1 , further comprising a terminal resistor coupled to the second node. 4 . The data receiving circuit of claim 1 , further comprising a terminal resistor coupled between the second node and the internal circuit.

5. The data receiving circuit according to claim 1, wherein: The internal circuit includes a deserializer.

6. The data receiving circuit according to claim 1, wherein: The T-coil balancing circuit comprises: a plurality of resistors coupled to the ground terminal; and A plurality of switches are coupled between the capacitor and the plurality of resistors, the plurality of switches operating in response to the control signal.

7. A data training circuit, comprising: A data receiving circuit coupled to the data input / output pad, the data receiving circuit controlling the sensing peak according to a control signal and receiving data sent via the data input / output pad; a deserializer that deserializes the data output from the data receiving circuit to generate parallel data; a data verification circuit that verifies the parallel data to generate a data verification signal; as well as A control circuit changes the value of the control signal until the data verification signal has a value indicating that the parallel data has been normally transmitted.

8. The data training circuit according to claim 7, wherein: The data receiving circuit comprises: a first inductor coupled between a first node and a second node, the first node being coupled to the data input / output pad; a second inductor coupled between the second node and an internal circuit; and The T-coil balancing circuit includes a T-coil having at least one capacitor coupled to the second node, and the T-coil balancing circuit adjusts an inductive peak of the T-coil in response to the control signal.

9. The data training circuit of claim 8, further comprising a terminal resistor coupled to the first node.

10. The data training circuit of claim 8, further comprising a terminal resistor coupled to the second node.

11. The data training circuit of claim 8, further comprising a terminal resistor coupled between the second node and the internal circuit.

12. The data training circuit according to claim 8, wherein: The T-coil balancing circuit comprises: a plurality of resistors coupled to the ground terminal; and A plurality of switches are coupled between the capacitor and the plurality of resistors, the plurality of switches operating in response to the control signal.

13. The data training circuit according to claim 7, wherein: The data verification circuit: determining whether the parallel data is normal according to a parity check signal included in the parallel data; and The data verification signal is generated according to the determination result.

14. The data training circuit according to claim 7, wherein: The data verification circuit includes a parity signal operation logic, which is used to generate the data verification signal based on a result of comparing a first parity signal with a second parity signal, wherein the first parity signal is included in the parallel data, and the second parity signal is generated by performing an operation on the parallel data.

15. The data training circuit according to claim 7, wherein: The control circuit changes a value of the control signal according to a test mode signal.

16. A data transmission / reception circuit, comprising: A data receiving circuit, comprising: a first inductor coupled between a first node and a second node, the first node being coupled to a data input / output pad; a second inductor coupled between the second node and a third node; and a T-coil balancing circuit comprising a T-coil having at least one capacitor coupled between the second node and a ground terminal, the T-coil balancing circuit adjusting an inductive peak of the T-coil in response to a control signal; and The data transmitting circuit is coupled to the second node and performs a driving operation and an equalizing operation on internally generated data. 17 . The data transmission / reception circuit of claim 16 , further comprising a terminal resistor coupled to the first node, the second node, or the third node.

18. The data transmission / reception circuit according to claim 16, further comprising: a first buffer coupled to the third node and buffering data input from the outside via the data input / output pad and passing through the second inductor; as well as A second buffer is coupled to the third node and buffers internally generated data and outputs it to the second inductor.

19. The data transmission / reception circuit according to claim 16, wherein: The T-coil balancing circuit comprises: a plurality of resistors coupled to the ground terminal; and A plurality of switches are coupled between the capacitor and the plurality of resistors, the plurality of switches operating in response to the control signal.

20. The data transmission / reception circuit according to claim 16, wherein: The data sending circuit comprises: a pre-driver that performs the equalization operation on the internally generated data; and A main driver drives the second node according to the output of the pre-driver.

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