Self-correcting device for multi-port data path delay in display application

Abstract

The invention aims to provide a self-correcting device for multi-port data path delay in display application. The device comprises a phase detection and conversion circuit, a delay detection circuit and a delay detection circuit, the phase detection and conversion circuit comprises a phase detection module and a phase conversion module. The phase detection module is connected with the output end of the phase-locked loop and the output of an RST signal, and is used for detecting the delay of the output signal of the phase-locked loop in each post; and the phase conversion module is connected with the phase detection module and is used for adjusting the signal delay output by the phase-locked loop of each port. According to the invention, the delay from the clock source to each port is ensured to be the same by adopting a self-correction mode, the influence of process, voltage and problems on path delay can be covered, high-quality data synchronization alignment is safely realized, the precision is improved, and the error rate is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a self-correcting device for multi-port data path delay in display applications. Background Art

[0002] ‌Display port‌ usually refers to the connection interface between the monitor and the computer or other devices, which is used to transmit video and audio signals. There are many types of display ports, the most common ones include DisplayPort, HDMI, DVI, VGA, etc. ‌DisplayPort‌: This is an external interface that connects the host and the monitor through a cable. DisplayPort technology is directly derived from PCIe, supports high resolution and large bandwidth, and is suitable for high-end monitors and graphics workstations. ‌HDMI‌: This interface is widely used to connect TVs, monitors and other video devices, supports audio and video transmission, and is suitable for home entertainment and office environments. ‌DVI‌: Digital video interface, transmits digital signals, suitable for high-definition display needs. ‌VGA‌: Analog video graphics array interface, suitable for lower resolution display needs. ‌DisplayPort‌: The maximum supported distance can reach 15 meters, the highest supported resolution can reach 8Kx4K, and the total data speed can reach 25.92Gbps, which is suitable for display needs that require high bandwidth and high resolution. ‌HDMI‌: Supports multiple resolutions and refresh rates, suitable for home entertainment and office environments, but the bandwidth and resolution may not be as high as DisplayPort. DVI‌: Fast transmission speed, suitable for high-definition display needs, but not as flexible as DisplayPort. VGA‌: Suitable for lower resolution display needs, lower cost, but has been gradually phased out.

[0003] The latency of a display's multi-port (such as HDMI, DisplayPort, etc.) refers to the time it takes for a signal to be transmitted from the input port to the display and ultimately display an image. This latency is the result of multiple factors, including cable latency, display processing latency, and latency in the operating system and application. In the display application, there are multiple groups of ports working together, and there has always been a screen flickering phenomenon caused by mismatched path latency, which seriously affects the performance and effect of the display. In the existing multi-port display design, due to different path latency, the process, voltage, and temperature also cause different latency. Summary of the invention

[0004] The purpose of the present invention is to provide a self-correction device for multi-port data path delay in display applications. The device ensures that the delay from the clock source to each port is the same by adopting a self-correction method, can cover the influence of process, voltage, and problems on path delay, safely realizes high-quality data synchronization alignment, improves accuracy and reduces bit error rate.

[0005] A self-correction device for multi-port data path delay in display applications, comprising: a phase detection and conversion circuit; The phase detection and conversion circuit comprises: a phase detection module and a phase conversion module; The phase detection module is connected to the output terminal of the phase-locked loop and the output of the RST signal, and is used to detect the delay of the phase-locked loop output signal in each post; The phase conversion module is connected to the phase detection module and is used to adjust the signal delay of the phase-locked loop output of each port.

[0006] Preferably, it further comprises: a phase-locked loop, a second AND gate, a first buffer and a plurality of ports; The input end of the second AND gate is respectively connected to the enable signal and the output signal of the phase-locked loop, and the output end is connected to the input end of the buffer; The output end of the buffer is connected to a plurality of the ports.

[0007] Preferably, the port comprises: an internal phase difference conversion module; The internal phase difference conversion module includes: a first trigger, a second trigger, a first NOT gate, a first AND gate, a first delay circuit and a phase detection and conversion circuit; The D terminal of the first trigger is electrically connected to the power supply voltage, the CK terminal is connected to the adjustment enable signal, and the Q terminal is connected to the input terminal of the first AND gate; The D terminal of the second trigger is connected to the power supply voltage, the CK terminal is connected to the output terminal of the first delay circuit, and the Q terminal is connected to the input terminal of the first NOT gate; The output end of the first NOT gate is connected to the input end of the first AND gate; The port clock signal is connected to the second trigger through the first delay circuit; The output terminal of the first AND gate is connected to the input terminal of the phase detection and conversion circuit.

[0008] Preferably, the phase detection and conversion circuit further comprises: a third D flip-flop, a second delay circuit and a CNT module; The D terminal of the third D flip-flop is connected to the phase difference output of the RST signal and the phase-locked loop signal, the reference clock signal is connected to the CK terminal through the second delay circuit, and the Q terminal is connected to the phase detection module; The output end of the phase detection module is connected to the input end of the CNT module, and the CNT module is used to adjust the delay parameter of the second delay circuit.

[0009] Preferably, the phase detection module comprises: two waveform conversion modules, two waveform extraction modules and a comparison module; The waveform conversion module is connected to the input signal and the waveform extraction module, and is used to convert the waveform into a square wave; The waveform extraction module is connected to the comparison module and is used to extract the transition edge of the square wave; The comparison module is used to detect the phase difference between two input signals.

[0010] Preferably, the first waveform conversion module includes: a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a first comparator; A first end of the first resistor is grounded, and a second end is connected to the second capacitor; The first plate of the first capacitor is connected to the input signal, and the second plate is connected to the first end of the second resistor and the positive input end of the first comparator; The second end of the second resistor is connected to the first end of the third resistor; The second end of the third resistor is connected to the power supply voltage, and the first end of the third resistor is connected to the negative input terminal of the first comparator.

[0011] Preferably, the first waveform extraction module comprises: a third capacitor, a fourth resistor, a fifth resistor and a first diode; The first plate of the third capacitor is connected to the output end of the first waveform conversion module, and the second plate is connected to the first end of the fourth resistor; The second end of the fourth resistor is grounded; The first end of the fifth resistor is connected to the power supply voltage, and the second end is connected to the first end of the fourth resistor; The cathode of the first diode is connected to the second plate of the third capacitor, and the anode is connected to the comparison module; The diode in the second waveform extraction module has the opposite positive and negative pole directions to the diode in the first waveform extraction module, so that the rising edge of the first waveform conversion module passes through and the falling edge of the second waveform conversion module passes through.

[0012] Preferably, the comparison module includes: a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first filter and a second comparator. The first end of the sixth resistor is connected to the power supply voltage, and the second end is connected to the first end of the seventh resistor and the waveform extraction module; A first end of the seventh resistor is connected to the waveform extraction module, and a second end thereof is grounded; A first end of the eighth resistor is connected to a power supply voltage, and a second end is connected to a first end of the tenth resistor; The second end of the tenth resistor is grounded; The negative input terminal of the second comparator is connected to the sixth resistor and the seventh resistor, the positive input terminal is connected to the ninth resistor, the eighth resistor and the tenth resistor, and the output terminal is connected to the first filter; The first end of the ninth resistor is connected to the positive input end of the second comparator, and the second end of the ninth resistor is connected to the first filter.

[0013] A method for controlling a self-correction device for multi-port data path delay in a display application, and a self-correction device for multi-port data path delay in a display application, comprising: Determine the phase difference between the RST signal and the phase-locked loop signal; Adjusting parameters of a phase detection and conversion circuit according to a phase difference between the RST signal and a phase-locked loop signal; Controlling the number of delay units connected in the delay circuit according to the parameters of the phase detection and conversion circuit; The phase of the phase-locked loop signal is adjusted according to the number of the delay units connected.

[0014] Preferably, the determining the phase difference between the RST signal and the phase-locked loop signal comprises: The reference clock passes through the second delay circuit to capture the phase difference information; Increase the number of delay units connected in the delay circuit. When a rising edge is detected, the number of delay units connected is N0. Increase the number of delay units connected in the delay circuit until a falling edge is detected, and the number of delay units connected is N1; The phase difference is the difference in the number of delay units in the delay circuit N1-N0.

[0015] The beneficial effects of the present invention are: 1. The present invention can align the delay differences on each port path in a self-correction manner, eliminate the path delay differences, and reduce the problem of delay asynchrony in the clock path; 2. The present invention detects the delay differences of the clock from the clock source output to each port through a simple design, and then automatically corrects and aligns. Compared with the prior art, the present invention is simple in design, can ensure that the bit error rate is low under the influence of process, voltage, and temperature, and has a great competitive advantage. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 It is a schematic diagram of the internal phase difference conversion structure of the port of the present invention; Figure 2 It is a schematic diagram of the structure of the phase difference detection and conversion module of the present invention; Figure 3 It is a schematic diagram of the structure of the phase detection module of the present invention; Figure 4 It is a schematic diagram of the waveform conversion module structure of the present invention; Figure 5 It is a schematic diagram of the waveform extraction module structure of the present invention; Figure 6 It is a schematic diagram of the comparison module structure of the present invention; Figure 7 The phase difference detection diagram of the present invention is shown in FIG. Figure 1 ; Figure 8 The phase difference detection diagram of the present invention is shown in FIG. Figure 2 ; Fig. 9 The phase difference detection diagram of the present invention is shown in FIG. Figure 3 . DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0021] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] The latency of a display's multi-port (such as HDMI, DisplayPort, etc.) refers to the time it takes for a signal to be transmitted from the input port to the display and ultimately display an image. This latency is the result of multiple factors, including cable latency, display processing latency, and latency in the operating system and application. In the display application, there are multiple groups of ports working together, and there has always been a screen flickering phenomenon caused by mismatched path latency, which seriously affects the performance and effect of the display. In the existing multi-port display design, due to different path latency, the process, voltage, and temperature also cause different latency.

[0023] The present invention can align the delay differences on each port path in a self-correction manner, eliminate the path delay differences, and reduce the problem of delay asynchrony in the clock path; the present invention detects the delay differences of the clock from the clock source output to each port through a simple design, and then automatically corrects and aligns. Compared with the prior art, the present invention is simple in design, can ensure that the bit error rate is low under the influence of process, voltage, and temperature, and has a great competitive advantage.

[0024] Example 1 A self-correction device for multi-port data path delay in display applications, reference Figure 2 , including: phase detection and conversion circuit; The phase detection and conversion circuit includes: a phase detection module and a phase conversion module; The phase detection module is connected to the output terminal of the phase-locked loop and the output of the RST signal, and is used to detect the delay of the phase-locked loop output signal in each post; The phase conversion module is connected to the phase detection module and is used to adjust the signal delay of the phase-locked loop output of each port.

[0025] One object of the present invention is to design a method for automatically adjusting the path delay from the phase-locked loop clock source output to each port in a multi-port display. The normal 4-port clock distribution is as follows Figure 1As shown in the figure, because the physical path distance is different, the delay of the phase-locked loop output reaching each port is different. During calibration, the output of the PLL is kept constant at 1, and then Training_en is started. The phase difference of each port is determined by detecting Training_en and the delay reaching each port.

[0026] like Figure 1 As shown, initially the RST signal will set the output of the first trigger to 0. When RST becomes 0, the Training_en signal will make the output of the D trigger become 1. Similarly, when the output of the Training_en signal at the phase-locked loop end reaches the port and passes through the delay chain, it will make the second trigger become 1, generating a path delayed signal pulse width signal Phase_diff.

[0027] The signal pulse width signal Phase_diff is passed through the phase difference detection and conversion device to obtain a 4-bit digital signal TDC_OUT<4:0>, and then the difference of TDC_OUT<4:0> inside each port is compared. For example, if the maximum delay is 15 and the minimum path delay output is 7, then the difference of the maximum minus the minimum value 15-7=8 needs to be added to the delay chain of the minimum path to ensure that the maximum and minimum path delays are the same, so as to achieve the purpose of internal alignment of the clock edge.

[0028] Preferably, it further comprises: a phase-locked loop, a second AND gate, a first buffer and a plurality of ports; The input end of the second AND gate is respectively connected to the enable signal and the output signal of the phase-locked loop, and the output end is connected to the input end of the buffer; The output of the buffer is connected to multiple ports.

[0029] In the whole multi-port working system, a phase-locked loop connects many ports. Due to different paths, the delay of each port will be different, which seriously affects the performance and effect of display. Therefore, the present invention sets a phase difference conversion circuit inside each port, such as Figure 1 As shown, a phase difference detection and conversion module is then set in the internal phase difference conversion module, such as Figure 2 As shown, each phase difference detection and conversion module has a phase detection module and a phase conversion module. The phase detection module is as shown in FIG. Figure 3 As shown, the phase conversion can be completed by relying on the control of the CNT module, thereby completing a method that can automatically adjust the path delay from the output of the phase-locked loop clock source to the inside of each port.

[0030] Preferably, the port comprises: an internal phase difference conversion module; The internal phase difference conversion module includes: a first trigger, a second trigger, a first NOT gate, a first AND gate, a first delay circuit and a phase detection and conversion circuit; The D terminal of the first trigger is electrically connected to the power supply voltage, the CK terminal is connected to the adjustment enable signal, and the Q terminal is connected to the input terminal of the first AND gate; The D terminal of the second trigger is connected to the power supply voltage, the CK terminal is connected to the output terminal of the first delay circuit, and the Q terminal is connected to the input terminal of the first NOT gate; An output terminal of the first NOT gate is connected to an input terminal of the first AND gate; The port clock signal is connected to the second trigger through the first delay circuit; The output terminal of the first AND gate is connected to the input terminal of the phase detection and conversion circuit.

[0031] Figure 2 It is the phase difference detection and conversion inside the port. REF_CLK captures the signal Phase_diff information through the second delay circuit, and continuously increases the number of delay units in the second delay circuit. When the rising edge is detected, the phase difference detection starts. The number of delay units at this time is counted as N0, and the number of delay units in the second delay circuit is continuously increased until the falling edge is detected. At this time, the detection and judgment of the phase detection ends. At this time, the number of delay units is counted as N1, and the phase difference is converted into the difference in the number of delay units in the second delay circuit, N1-N0, and converted into TDC_OUT<4:0>. The four PORTs detect the difference of four different sets of phase delays respectively, and convert them into different TDC_OUT<4:0>. The largest TDC_OUT<4:0> value is selected as the benchmark, and the LCDL<4:0> of other ports increases the code to finally achieve the same delay.

[0032] Preferably, reference Figure 2 , the phase detection and conversion circuit further includes: a third D flip-flop, a second delay circuit and a CNT module; The D terminal of the third D flip-flop is connected to the phase difference output of the RST signal and the phase-locked loop signal, the reference clock signal is connected to the CK terminal through the second delay circuit, and the Q terminal is connected to the phase detection module; The output end of the phase detection module is connected to the input end of the CNT module, and the CNT module is used to adjust the delay parameter of the second delay circuit.

[0033] The main function of the CNT module is to count. It counts up through external input signals. When the count reaches the set value, an interrupt will be generated or a specific event will be triggered. CNT counts up through external input signals. When the set value is reached, an interrupt will be generated or a specific event will be triggered. The counter can maintain the current count value after power failure to ensure data persistence. CNT can also set different working modes, such as automatic reload mode, capture mode and comparison mode.

[0034] Preferably, reference Figure 3 ,The phase detection module includes: two waveform conversion modules, two waveform extraction modules and a comparison module; The waveform conversion module is connected with the input signal and the waveform extraction module, and is used to convert the waveform into a square wave; The waveform conversion module can change the frequency, amplitude, and phase characteristics of the signal. For example, the filter can remove or enhance certain frequency components in the signal, thereby changing the frequency characteristics of the signal; phase modulation can change the phase of the signal to achieve signal modulation and transmission; amplitude modulation can control the energy and power of the signal. In addition, the waveform conversion module can also improve the quality of the signal, remove noise, and enhance specific frequency components.

[0035] The waveform extraction module is connected to the comparison module and is used to extract the transition edge of the square wave; Waveform extraction can obtain useful feature information from the signal, such as peak value, frequency, duration, etc. Extracting the transition edge of a square wave refers to the process of detecting the moment when the square wave signal jumps between high and low levels, that is, the rising edge (from 0 to 1) and the falling edge (from 1 to 0). The transition edge marks the change of the signal state. In square wave signal processing, the detection of the transition edge is usually used to trigger events, control the sampling time, etc. For example, at the rising edge of the clock, the signal is sampled and stored, and then the change is detected by comparing with the original signal. When the rising edge is detected, the signal is set high; when the falling edge is detected, the signal is set low.

[0036] The comparison module is used to detect the phase difference between two input signals.

[0037] ‌Input signal phase difference‌ refers to the difference in phase between two input signals. Phase difference is usually used to describe the relative position relationship between two signals, that is, the delay time of one signal relative to another signal.

[0038] Preferably, reference Figure 4 , the first waveform conversion module includes: a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a first comparator; A first end of the first resistor is grounded, and a second end is connected to the second capacitor; The first plate of the first capacitor is connected to the input signal, and the second plate is connected to the first end of the second resistor and the positive input end of the first comparator; The second end of the second resistor is connected to the first end of the third resistor; The second end of the third resistor is connected to the power supply voltage, and the first end of the third resistor is connected to the negative input terminal of the first comparator.

[0039] If the working circuit is a sine wave, converting it to a square wave can identify the phase situation more quickly, because the square wave signal has a simple waveform and is easy to generate and process. By using a voltage comparator, a complex sine wave signal can be converted into a square wave signal, thereby simplifying the circuit design and reducing the number of components and costs. The frequency component of the square wave signal is relatively single, and its electromagnetic radiation is smaller than that of the sine wave signal, which helps to reduce electromagnetic interference, especially in high-frequency applications. Square wave signals have advantages in signal processing and analysis. For example, in digital signal processing, square wave signals are easier to sample and quantize, which facilitates digital signal processing and analysis.

[0040] Preferably, reference Figure 5 , the first waveform extraction module includes: a third capacitor, a fourth resistor, a fifth resistor and a first diode; A first plate of the third capacitor is connected to the output end of the first waveform conversion module, and a second plate is connected to the first end of the fourth resistor; The second end of the fourth resistor is grounded; A first end of the fifth resistor is connected to the power supply voltage, and a second end of the fifth resistor is connected to the first end of the fourth resistor; The cathode of the first diode is connected to the second plate of the third capacitor, and the anode is connected to the comparison module; The diode in the second waveform extraction module has the opposite positive and negative pole directions to the diode in the first waveform extraction module, so that the rising edge of the first waveform conversion module passes through and the falling edge of the second waveform conversion module passes through.

[0041] The rising edge refers to the moment when the digital level changes from a low level (digital "0") to a high level (digital "1"). The falling edge refers to the moment when the digital level changes from a high level (digital "1") to a low level (digital "0"). Detecting the rising and falling edges can intuitively determine the phase difference between the two input signals.

[0042] Preferably, reference Figure 6 The comparison module includes: a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first filter and a second comparator A first end of the sixth resistor is connected to a power supply voltage, and a second end is connected to a first end of the seventh resistor and a waveform extraction module; A first end of the seventh resistor is connected to the waveform extraction module, and a second end thereof is grounded; A first end of the eighth resistor is connected to a power supply voltage, and a second end is connected to a first end of the tenth resistor; The second end of the tenth resistor is grounded; The negative input terminal of the second comparator is connected to the sixth resistor and the seventh resistor, the positive input terminal is connected to the ninth resistor, the eighth resistor and the tenth resistor, and the output terminal is connected to the first filter; A first end of the ninth resistor is connected to the positive input end of the second comparator, and a second end of the ninth resistor is connected to the first filter.

[0043] Example 2 A method for controlling a self-correction device for multi-port data path delay in a display application, and a self-correction device for multi-port data path delay in a display application, comprising: S100, determining the phase difference between the RST signal and the phase-locked loop signal; In the embodiment of the present invention, the phase-locked loop first inputs the signal to the port. Since the physical path distance is different, the delay of the phase-locked loop output to each port is different. During calibration, the output of the PLL is kept constant at 1, and then Training_en is started. The phase difference of each port is determined by detecting Training_en and the delay to each port.

[0044] S200, adjusting parameters of the phase detection and conversion circuit according to the phase difference between the RST signal and the phase-locked loop signal; Initially, the RST signal will set the output of the first trigger to 0. When RST becomes 0, the Training_en signal will make the output of the D trigger become 1. Similarly, when the output of the Training_en signal at the phase-locked loop end reaches the port and passes through the delay chain, it will make the second trigger become 1, generating a path delayed signal pulse width signal Phase_diff.

[0045] S300, controlling the number of delay units connected in the delay circuit according to the parameters of the phase detection and conversion circuit; S400, adjusting the phase of the phase-locked loop signal according to the number of connected delay units.

[0046] The signal pulse width signal Phase_diff is passed through the phase difference detection and conversion device to obtain a 4-bit digital signal TDC_OUT<4:0>, and then the difference of TDC_OUT<4:0> inside each port is compared. For example, if the maximum delay is 15 and the minimum path delay output is 7, then the difference of the maximum minus the minimum value 15-7=8 needs to be added to the delay chain of the minimum path to ensure that the maximum and minimum path delays are the same, so as to achieve the purpose of internal alignment of the clock edge.

[0047] Preferably, S100, determining the phase difference between the RST signal and the phase-locked loop signal includes: The reference clock passes through the second delay circuit to capture the phase difference information; Increase the number of delay units connected in the delay circuit. When a rising edge is detected, the number of delay units connected is N0. Increase the number of delay units connected in the delay circuit until a falling edge is detected, and the number of delay units connected is N1; The phase difference is the difference in the number of delay units in the delay circuit N1-N0.

[0048] REF_CLK passes through the second delay circuit to capture the signal Phase_diff information, and the number of delay units in the second delay circuit is continuously increased. When the rising edge is detected, the phase difference detection begins. The number of delay units at this time is counted as N0, and the number of delay units in the second delay circuit is continuously increased until the falling edge is detected. At this time, the detection and judgment phase detection ends. At this time, the number of delay units is counted as N1, and the phase difference is converted into the difference in the number of delay units in the second delay circuit N1-N0, and converted into TDC_OUT<4:0>. The four PORTs detect the difference in the four different groups of phase delays, which are converted into different TDC_OUT<4:0>. The largest TDC_OUT<4:0> value is selected as the benchmark, and the LCDL<4:0> of other ports increases the code, and finally reaches the same delay.

[0049] like Figure 7 When the reference clock REF_CLK is on the left side of the phase difference interval after passing through the delay chain, the pattern detection detects that the initial value is 0. At this time, the increase in the reference clock REF_CLK delay is adjusted by controlling the increase in CNT. When the pattern detection detects the rising edge of phase_det, the phase difference detection starts. The number of delayed units at this time is counted as N0, and the number of delay units in the delay chain is continuously increased until the falling edge of phase_det is detected. At this time, the detection determines that the phase detection is over. At this time, the number of delay units is counted as N1, and the phase difference is converted into the difference in the number of delay units in the delay chain, N1-N0, and converted into TDC_OUT<4:0>.

[0050] like Figure 8When the reference clock REF_CLK is in the middle of the phase difference interval after passing through the delay chain, the pattern detection detects that the initial value is 1. At this time, the reference clock REF_CLK delay is adjusted by controlling the decrease of CNT. When the pattern detection detects the rising edge of phase_det, the phase difference detection starts. The number of delayed units at this time is counted as N0, and the number of delay units in the delay chain is continuously increased until the falling edge of phase_det is detected. At this time, the detection determines that the phase detection is over. At this time, the number of delay units is counted as N1, and the phase difference is converted into the difference in the number of delay units in the delay chain, N1-N0, and converted into TDC_OUT<4:0>.

[0051] like Fig. 9 When the reference clock REF_CLK is on the right side of the phase difference interval after passing through the delay chain, the pattern detection detects that the initial value is 0. At this time, the increase in the reference clock REF_CLK delay is adjusted by controlling the increase in CNT. When CNT increases from 10000 to 1 1111, the rising edge of phase_det is still not detected. At this time, CNT needs to be set to 0, and then the value of CNT is increased from 0 0000. When the pattern detection detects the rising edge of phase_det, the phase difference detection starts. The number of delayed units at this time is counted as N0, and the number of delay units in the delay chain is continuously increased until the falling edge of phase_det is detected. At this time, the detection determines that the phase detection is over. At this time, the number of delay units is counted as N1, and the phase difference is converted into the difference in the number of delay units in the delay chain, N1-N0, and converted into TDC_OUT<4:0>.

[0052] The beneficial effects of the present invention are: 1. The present invention can align the delay differences on each port path in a self-correction manner, eliminate the path delay differences, and reduce the problem of delay asynchrony in the clock path; 2. The present invention detects the delay differences of the clock from the clock source output to each port through a simple design, and then automatically corrects and aligns. Compared with the prior art, the present invention is simple in design, can ensure that the bit error rate is low under the influence of process, voltage, and temperature, and has a great competitive advantage.

[0053] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A self-correction device for multi-port data path delay in display applications, characterized in that: include: Phase detection and conversion circuits; The phase detection and conversion circuit comprises: a phase detection module and a phase conversion module; The phase detection module is connected to the output terminal of the phase-locked loop and the output of the RST signal, and is used to detect the delay of the phase-locked loop output signal in each post; The phase conversion module is connected to the phase detection module and is used to adjust the signal delay of the phase-locked loop output of each port.

2. The self-correction device for multi-port data path delay in display application according to claim 1, characterized in that: Also includes: A phase-locked loop, a second AND gate, a first buffer and a plurality of ports; The input end of the second AND gate is respectively connected to the enable signal and the output signal of the phase-locked loop, and the output end is connected to the input end of the buffer; The output end of the buffer is connected to a plurality of the ports.

3. The self-correction device for multi-port data path delay in display application according to claim 1, characterized in that: The port includes: an internal phase difference conversion module; The internal phase difference conversion module includes: a first trigger, a second trigger, a first NOT gate, a first AND gate, a first delay circuit and a phase detection and conversion circuit; The D terminal of the first trigger is electrically connected to the power supply voltage, the CK terminal is connected to the adjustment enable signal, and the Q terminal is connected to the input terminal of the first AND gate; The D terminal of the second trigger is connected to the power supply voltage, the CK terminal is connected to the output terminal of the first delay circuit, and the Q terminal is connected to the input terminal of the first NOT gate; The output end of the first NOT gate is connected to the input end of the first AND gate; The port clock signal is connected to the second trigger through the first delay circuit; The output terminal of the first AND gate is connected to the input terminal of the phase detection and conversion circuit.

4. The self-correction device for multi-port data path delay in display application according to claim 3, characterized in that: The phase detection and conversion circuit also includes: a third D flip-flop, a second delay circuit and a CNT module; The D terminal of the third D flip-flop is connected to the phase difference output of the RST signal and the phase-locked loop signal, the reference clock signal is connected to the CK terminal through the second delay circuit, and the Q terminal is connected to the phase detection module; The output end of the phase detection module is connected to the input end of the CNT module, and the CNT module is used to adjust the delay parameter of the second delay circuit.

5. The self-correction device for multi-port data path delay in display application according to claim 1, characterized in that: The phase detection module includes: two waveform conversion modules, two waveform extraction modules and a comparison module; The waveform conversion module is connected to the input signal and the waveform extraction module, and is used to convert the waveform into a square wave; The waveform extraction module is connected to the comparison module and is used to extract the transition edge of the square wave; The comparison module is used to detect the phase difference between two input signals.

6. The self-correction device for multi-port data path delay in display application according to claim 5, characterized in that: The first waveform conversion module includes: a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a first comparator; A first end of the first resistor is grounded, and a second end is connected to the second capacitor; The first plate of the first capacitor is connected to the input signal, and the second plate is connected to the first end of the second resistor and the positive input end of the first comparator; The second end of the second resistor is connected to the first end of the third resistor; The second end of the third resistor is connected to the power supply voltage, and the first end of the third resistor is connected to the negative input terminal of the first comparator.

7. The self-correction device for multi-port data path delay in display application according to claim 5, characterized in that: The first waveform extraction module includes: a third capacitor, a fourth resistor, a fifth resistor and a first diode; The first plate of the third capacitor is connected to the output end of the first waveform conversion module, and the second plate is connected to the first end of the fourth resistor; The second end of the fourth resistor is grounded; The first end of the fifth resistor is connected to the power supply voltage, and the second end is connected to the first end of the fourth resistor; The cathode of the first diode is connected to the second plate of the third capacitor, and the anode is connected to the comparison module; The diode in the second waveform extraction module has the opposite positive and negative pole directions to the diode in the first waveform extraction module, so that the rising edge of the first waveform conversion module passes through and the falling edge of the second waveform conversion module passes through.

8. The self-correction device for multi-port data path delay in display application according to claim 5, characterized in that: The comparison module includes: a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first filter and a second comparator The first end of the sixth resistor is connected to the power supply voltage, and the second end is connected to the first end of the seventh resistor and the waveform extraction module; A first end of the seventh resistor is connected to the waveform extraction module, and a second end thereof is grounded; A first end of the eighth resistor is connected to a power supply voltage, and a second end is connected to a first end of the tenth resistor; The second end of the tenth resistor is grounded; The negative input terminal of the second comparator is connected to the sixth resistor and the seventh resistor, the positive input terminal is connected to the ninth resistor, the eighth resistor and the tenth resistor, and the output terminal is connected to the first filter; The first end of the ninth resistor is connected to the positive input end of the second comparator, and the second end of the ninth resistor is connected to the first filter.

9. A method for controlling a self-correction device for multi-port data path delay in a display application, applied to a self-correction device for multi-port data path delay in a display application as claimed in any one of claims 1 to 8, characterized in that: include: Determine the phase difference between the RST signal and the phase-locked loop signal; Adjusting parameters of a phase detection and conversion circuit according to a phase difference between the RST signal and a phase-locked loop signal; Controlling the number of delay units connected in the delay circuit according to the parameters of the phase detection and conversion circuit; The phase of the phase-locked loop signal is adjusted according to the number of the delay units connected.

10. The method for controlling a self-correcting device for multi-port data path delay in a display application according to claim 7, characterized in that: The determining of the phase difference between the RST signal and the phase-locked loop signal comprises: The reference clock passes through the second delay circuit to capture the phase difference information; Increase the number of delay units connected in the delay circuit. When a rising edge is detected, the number of delay units connected is N0. Increase the number of delay units connected in the delay circuit until a falling edge is detected, and the number of delay units connected is N1; The phase difference is the difference in the number of delay units in the delay circuit N1-N0.

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