Techniques for controlling access to provisioned integrated circuits

Abstract

The present disclosure relates to techniques for controlling access to provisioned integrated circuits. An integrated circuit includes a cryptographic engine that generates a cryptographic version of a password, a secure storage area, and a security controller circuit that stores an enable bit and at least a portion of the cryptographic version of the password in the secure storage area to enable a security feature. If an enable bit stored in the secure storage area indicates that the security feature is enabled, the security controller circuit enables provisioning of the integrated circuit in response to receiving a password from a user.

Description

Technical Field

[0001] The present disclosure relates to electronic integrated circuits and, more particularly, to techniques for controlling access to provisioning integrated circuits. Background Art

[0002] Configurable integrated circuits can be configured by users to implement desired custom logic functions. In a typical scenario, a logic designer uses a computer-aided design (CAD) tool to design a custom circuit design. When the design process is completed, the computer-aided design tool generates configuration data. The configuration data is then loaded into configuration memory elements, which configure the configurable logic circuits in the integrated circuit to perform the functions of the custom circuit design. Configurable logic integrated circuits can be used for collaborative processing in big data or fast data applications. For example, configurable logic integrated circuits can be used for application acceleration tasks in data centers and can be reprogrammed to perform different tasks during data center operations. Summary of the invention

[0003] According to one aspect of the present disclosure, an integrated circuit is provided, comprising: a cryptographic engine that generates a first cryptographic version of a password; a secure storage area; and a security controller circuit that stores an enable bit and at least a portion of the first cryptographic version of the password in the secure storage area to enable a security feature, wherein if the enable bit stored in the secure storage area indicates that the security feature is enabled, the security controller circuit enables configuration of the integrated circuit in response to receiving the password from a user.

[0004] According to one aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, comprising computer-readable instructions stored thereon, for causing an integrated circuit to: generate a first cryptographic version of a first password using a cryptographic function; store at least a first portion of the first cryptographic version of the first password in a secure storage circuit in the integrated circuit; and compare at least the first portion of the first cryptographic version of the first password accessed from the secure storage circuit with at least a second portion of a second cryptographic version of a second password to determine whether the integrated circuit is allowed to be configured.

[0005] According to one aspect of the present disclosure, a method for protecting access to an integrated circuit is provided, the method comprising: generating a first cryptographic version of a first password using a cryptographic function in the integrated circuit; storing at least a first portion of the first cryptographic version of the first password in a secure storage circuit in the integrated circuit; and comparing at least the first portion of the first cryptographic version of the first password received from the secure storage circuit with at least a second portion of a second cryptographic version of a second password received from a user to determine whether the integrated circuit is allowed to be configured. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram showing a configurable integrated circuit (IC) that may be used with the techniques disclosed herein.

[0007] Figure 2A is a schematic diagram illustrating an example of information transfer that may occur to enable security features for protecting the configuration flow of an integrated circuit (IC).

[0008] Figure 2B is a schematic diagram illustrating an example of information transfer that may occur to unlock security features protecting access to a configuration flow of an integrated circuit (IC).

[0009] Figure 3 is a schematic diagram of an illustrative configurable integrated circuit (IC) that can be configured according to a user circuit design.

[0010] Figure 4 is a schematic diagram of another illustrative example of a configurable integrated circuit (IC) that may include examples disclosed herein.

[0011] Figure 5 is a schematic diagram of a circuit design system that can be used to design an integrated circuit according to an embodiment.

[0012] Figure 6 is a schematic diagram of an illustrative computer-aided design (CAD) tool that may be used in a circuit design system according to one embodiment. DETAILED DESCRIPTION

[0013] Many integrated circuit (IC) devices provide configuration capabilities. Configuration of an IC device is to configure the IC device with key materials to enable security features, such as authentication and confidentiality of the code used to execute the IC device. For example, after configuration, the IC device can be protected using a digital signature created using a public key encryption security scheme, so that the IC device is under the control of a designated owner who has a private key corresponding to the configured public key. For example, once configured, a configurable IC device only accepts a configuration data bitstream signed with the owner's private key and decrypted using the public key. However, this system creates the possibility of a ransom attack. Some IC device owners are reluctant to go through the configuration process because the configuration process involves the complexity of key management. An adversary who has physical access to the IC device can complete the configuration flow and inject the public key into an unconfigured device. By design, without the adversary's private key, the device becomes useless to its legitimate owner.

[0014] Previously known configurable IC devices that have not been configured in the manner described above have no built-in way to block the configuration flow. An adversary typically needs to be physically present to operate the configuration flow through the IC device's Joint Test Action Group (JTAG) input. The new configuration flow and greater platform connectivity with the JTAG network increase the risk to the legitimate owner of the IC device. Although the owner can configure the device, the configuration actually involves complexities that the owner may not welcome and / or be unable to handle, such as the secure disposal of the corresponding private key in the HSM (high security module), the bitstream signing process, and the resale value in the event of a transfer of ownership of the IC device.

[0015] According to some examples disclosed herein, password-protected gating is provided as a security feature in the configuration flow of an IC device. The security feature can be enabled to prevent unauthorized access to the configuration flow of the IC device. The password is selected by a user (e.g., the owner of the IC device). For example, the security feature can be enabled by storing an enable bit and a hashed and truncated version of the password in a secure storage device of the IC device (e.g., in a fuse). In response to the enable bit being stored in the secure storage device, the security feature blocks access to the configuration flow of the IC device. The security feature then requires a password to allow access to the configuration flow.

[0016] The security features can provide low-cost, low-effort, and low-maintenance protection to the owner of the IC device while providing strong assurance against inadvertent and malicious configuration of the IC device. The password size can be established to provide adequate resistance to brute force attacks. A hash of the password is stored in the IC device to prevent readback by reverse engineering or observation techniques. Any password protection techniques can be applied, such as password salting, etc.

[0017] One or more specific examples are described below. In order to provide a concise description of these examples, not all features of actual implementations are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-dependent decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from implementation to implementation. In addition, it should be understood that such development work may be complex and time consuming, but for those of ordinary skill in the art who benefit from this disclosure, it is just a routine design, fabrication and manufacturing work.

[0018] Throughout the specification, and in the claims, the term "connected" means a direct electrical connection between connected circuits, without any intermediary devices. The term "coupled" means a direct electrical connection between circuits, or an indirect electrical connection through one or more passive or active intermediary devices, which connection allows information transfer between the circuits. The term "circuit" may refer to one or more passive and / or active electrical components arranged to cooperate with each other to provide a desired functionality.

[0019] The present disclosure discusses integrated circuit devices, including configurable (programmable) logic integrated circuits, such as field programmable gate arrays (FPGAs). As described herein, an integrated circuit (IC) may include hard logic and / or soft logic. As used herein, "hard logic" generally refers to circuits in an integrated circuit device that cannot be configured by an end user. Circuits in an integrated circuit device (e.g., a configurable logic IC) that can be configured by an end user are referred to as "soft logic."

[0020] Figure 1 1 is a schematic diagram illustrating a configurable integrated circuit (IC) 100 that can be used with the techniques disclosed herein. Configurable IC 100 includes security controller circuit 101, secure storage circuit 102 (e.g., fuse bank) in a secure storage area of ​​IC 100, cryptographic engine circuit 103, and core logic area 110. Core logic area 110 includes multiple areas of configurable logic circuits (soft logic), including areas 104 and 105. Each of areas 104 and 105 includes several configurable logic circuits. Figure 1 The arrangement of regions 104-105 shown in FIG. 1 is only an example. In other implementations, the regions of the configurable logic circuit may be arranged in any manner, for example, in an array of rows and columns. The security controller circuit 101 is configured to perform various security functions of the configurable IC 100, including encryption and decryption of configuration data, passwords, and the like.

[0021] Figure 2A is a schematic diagram illustrating an example of information transfer that may occur to enable security features for protecting the configuration flow of an integrated circuit (IC). Figure 2A In the example of FIG. 1 , the configuration flow of IC 100 is enhanced with a security feature. As described above, the user initially creates a password for the security feature. Figure 2A As shown, the password is transmitted to the input of the security controller circuit 101. Then, the security controller circuit 101 transmits the password to the input of the cryptographic engine circuit 103. The cryptographic engine circuit 103 includes firmware that calculates a cryptographic version CP of the password using any appropriate cryptographic function (e.g., a cryptographic hash function). As an example that is not intended to be limiting, the cryptographic engine circuit 103 can use the secure hash algorithm SHA-384 to calculate the hash of the password. Then, the cryptographic engine circuit 103 transmits the cryptographic version CP of the password to the security controller circuit 101. The cryptographic hash function mentioned herein is only used as an example. According to additional examples, other techniques can also be used to protect passwords, such as encryption with a device secret key, etc.

[0022] The security controller circuit 101 includes firmware that reduces the size of the cryptographic version CP of the password to generate a reduced size cryptographic version RCP1 of the password. As an example, which is not intended to be limiting, the security controller circuit 101 may truncate the hash of the password to generate a truncated hash of the password (i.e., a truncated hash). The security controller circuit 101 truncates the hash of the password to a predefined number of digital bits PN to generate the truncated hash. Truncation is just one example of a technique for reducing size. Other techniques may also be used instead of truncation to reduce the size of the cryptographic version of the password.

[0023] Then, if Figure 2AAs shown, the security controller circuit 101 transmits the reduced size cryptographic version RCP1 of the password and the enable bit to the secure storage circuit 102. The secure storage circuit 102 then stores the enable bit and the reduced size cryptographic version RCP1 of the password (e.g., in a fuse). The security controller circuit 101 enables the security feature by storing the enable bit in the secure storage circuit 102. After the security feature is enabled, the security controller circuit 101 requires the password to be correctly entered to configure the IC 100. Thus, the user must provide the correct password to the security controller circuit 101 to configure the IC 100 to create an authentication process for protecting access to the IC 100, for example, using a digital signature created using a public key encryption security scheme. This security feature protects the owner of the IC 100 from the financial consequences of inadvertent and / or malicious configuration of the IC, which may prevent the owner from using the IC. According to another example, the security feature may also be used to protect the IC device in transit, ie, from the manufacturer of the IC device to the buyer of the IC device, in case the manufacturer preconfigures a password in the IC device and communicates the password to the buyer by another means.

[0024] Figure 2B is a schematic diagram illustrating an example of information transfer that may occur to unlock security features that protect access to a configuration flow of an integrated circuit (IC). Figure 2B In the example, the reference Figure 2A The disclosed process enables a security feature. The security feature protects access to the configuration flow of IC 100. Before authorizing the configuration flow, the firmware in the security controller circuit 101 checks whether the security feature is enabled by accessing an enable bit from the secure storage circuit 102 (e.g., from a corresponding fuse value in the secure storage circuit 102). If the enable bit accessed from the secure storage circuit 102 indicates that the security feature is enabled in the IC 100, the firmware in the security controller circuit 101 requires the user to provide a correct password in order to begin configuring the IC 100. As an example, the security controller circuit 101 can accept the password as part of the configuration payload provided to configure the IC 100.

[0025] After receiving the password input by the user, the security controller circuit 101 transmits the received password to the input terminal of the cryptographic engine circuit 103. The firmware in the cryptographic engine circuit 103 uses Figure 2A The cryptographic engine circuit 103 may use the same cryptographic function used to enable the security feature during the process of computing the cryptographic version CP of the received password. As an example, which is not intended to be limiting, the cryptographic engine circuit 103 may use Figure 2A The same cryptographic hashing function is used in the process to calculate the hash of the password. Figure 2AIf a technique other than cryptographic functions is used to protect the password during Figure 2B The same technique is used to protect passwords during the authentication process.

[0026] Then, if Figure 2B As shown, the cryptographic engine circuit 103 transmits the cryptographic version CP of the received password to the security controller circuit 101. Then, the firmware in the security controller circuit 101 uses Figure 2A The size of the received cryptographic version of the password CP is reduced using the same technique used to reduce the size of the cryptographic version of the password in the process to generate a reduced size cryptographic version of the password RCP2.

[0027] As an example, the security controller circuit 101 may truncate the hash of the password to generate a truncated hash of the password. Figure 2B In the process, the security controller circuit 101 truncates the hash value of the password to Figure 2A In the process of circuit 101 is used to generate the same predefined digital bit number PN of the truncated hash. Figure 2A and Figure 2B In the process of truncation, other techniques can be used to reduce the size of the encrypted version of the password.

[0028] The firmware in the security controller circuit 101 then accesses the reduced size cryptographic version RCP1 of the password from the secure storage circuit 102 (e.g., from the fuse values ​​in the secure storage circuit 102). The security controller circuit 101 then compares the reduced size cryptographic version RCP1 of the password accessed from the secure storage circuit 102 with the Figure 2B The security controller circuit 101 compares RCP1 with a reduced size cryptographic version of the password RCP2 generated after the security feature has been enabled during the process of . If the security controller circuit 101 determines that RCP1 has the same value as RCP2 (i.e., RCP1=RCP2), the security controller circuit 101 enables the configuration flow of IC 100, thereby allowing the security controller circuit 101 to configure IC 100 by the user. If the security controller circuit 101 determines that RCP1 does not have the same value as RCP2 (i.e., RCP1≠RCP2), the security controller circuit 101 aborts the configuration flow of IC 100, prevents the user from configuring IC 100, and returns an error to the user.

[0029] In some implementations, the user who provides the correct password can also choose to disable the security feature. In these implementations, if the user provides the correct password and selects the option of disabling the security feature, the security controller circuit 101 disables the security feature.

[0030] To increase the resistance of IC 100 to brute force attacks, security controller circuit 101 may implement a forced power on reset (POR) cycle of IC 100 before processing a new request from a user to configure IC 100. Requiring a POR cycle of IC 100 before processing a new configuration request increases the mean time between attempts of the security feature and may result in a reduction in the amount of memory (e.g., fuse count) allocated in secure storage circuit 102 for storing a reduced size password version of the password.

[0031] For a transfer of ownership of IC 100, the current owner of IC 100 may provide the password to the new owner of IC 100 as part of the transfer agreement. When the new owner wants to configure IC 100, security controller circuit 101 follows the instructions in this document. Figure 2B Same process as public.

[0032] Figure 3 is a schematic diagram of an illustrative configurable logic integrated circuit (IC) 10 that can be configured according to a user circuit design. Configurable logic IC 10 is an example of an IC disclosed herein, such as Figure 1 IC 100. Figure 3 As shown, the configurable logic integrated circuit 10 may have input-output circuits 12 for driving signals out of the IC 10 and for receiving signals from other devices via input-output pads 14. Interconnect routing resources 16, such as global, regional, and local vertical and horizontal conductive lines and buses, may be used to route signals on the IC 10. The interconnect resources 16 include fixed interconnects (conductive lines) and programmable interconnects (i.e., programmable connections between various fixed interconnects). The IC 10 includes a region of configurable logic circuitry 18 that may be a partially reconfigurable region. The programmable logic circuitry 18 may include combinational logic and sequential logic circuits. The configurable logic circuitry 18 may be configured to perform custom logic functions.

[0033] The configurable logic IC 10 includes a memory element 20 into which configuration data can be loaded using the pads 14 and the input-output circuits 12. Once loaded, the memory elements 20 can each provide corresponding static control output signals that control the state of associated logic components in the configurable logic circuit 18. Typically, the memory element output signals are used to control the gates of field effect transistors. In the context of a configurable integrated circuit, the memory element 20 stores configuration data and is sometimes referred to as a configuration random-access memory (CRAM) cell. The configuration data programs the configurable logic circuit 18 to perform customized logic functions according to the circuit design.

[0034] Figure 4 4 is a schematic diagram of another illustrative example of a configurable integrated circuit (IC) 400. Configurable IC 400 is an example of an IC disclosed herein, such as Figure 1 IC 100. Figure 4 As shown, the configurable integrated circuit 400 includes a two-dimensional array of functional blocks, including a logic array block (LAB) 410 and other functional blocks, such as a random access memory (RAM) block 430 and a digital signal processing (DSP) block 420. Functional blocks, such as LAB 410, may include smaller programmable regions (e.g., logic elements, configurable logic blocks, or adaptive logic modules) that receive input signals and perform customized functions on the input signals to generate output signals.

[0035] In addition, the configurable integrated circuit 400 may have an input / output element (IOE) 402 for driving signals from the configurable integrated circuit 400 and for receiving signals from other devices. The input / output element 402 may include a parallel input / output circuit, a serial data transceiver circuit, a differential receiver and transmitter circuit, or other circuits for connecting one integrated circuit to another integrated circuit. As shown, the input / output element 402 may be located at the periphery of the IC. If desired, the configurable integrated circuit 400 may have input / output elements 402 arranged in different ways. For example, the input / output element 402 may form one or more columns of input / output elements, which may be located anywhere on the configurable integrated circuit 400 (e.g., evenly distributed on the width of the configurable integrated circuit). If desired, the input / output element 402 may form one or more rows of input / output elements (e.g., distributed on the height of the configurable integrated circuit). Alternatively, the input / output element 402 may form islands of input / output elements, which may be distributed on the surface of the configurable integrated circuit 400 or gathered in a selected area.

[0036] The configurable integrated circuit 400 may also include programmable interconnect circuits in the form of vertical routing channels 440 (i.e., interconnects formed along the vertical axis of the configurable integrated circuit 400) and horizontal routing channels 450 (i.e., interconnects formed along the horizontal axis of the configurable integrated circuit 400), each routing channel including at least one track to route at least one conductive line.

[0037] Note that except Figure 4In addition to the topology of the interconnect circuit depicted in , other routing topologies may be used. For example, the routing topology may include wires running diagonally or running horizontally and vertically along different portions of their extent, as well as wires perpendicular to the plane of the device in the case of a three-dimensional integrated circuit, and the driver of the wire may be located at a different point than one end of the wire. The routing topology may include global wires that span substantially all of the configurable integrated circuit 400, sporadic global wires, such as wires that span a portion of the configurable integrated circuit 400, staggered wires of a specific length, smaller local wires, or any other suitable arrangement of interconnect resources.

[0038] In addition, it should be understood that the embodiments disclosed herein can be implemented in any type of integrated circuit. If desired, the functional blocks of such an integrated circuit can be arranged in more levels or layers, wherein multiple functional blocks are interconnected to form larger blocks. Other device arrangements can use functional blocks that are not arranged in rows and columns.

[0039] The configurable integrated circuit 400 may include programmable memory elements. Configuration data (also referred to as programming data) may be loaded into the memory elements using input / output elements (IOEs) 402. Once loaded, the memory elements each provide a corresponding static control signal that controls the operation of an associated functional block (e.g., LAB 410, DSP 420, RAM 430, or input / output element 402).

[0040] In a typical scenario, the output of the loaded memory element is applied to the gate of a field effect transistor in a functional block to turn certain transistors on or off, thereby configuring the logic in the functional block, including routing paths. Programmable logic circuit elements that can be controlled in this manner include multiplexers (e.g., multiplexers used to form routing paths in interconnect circuits), lookup tables, logic arrays, AND, OR, NAND and NOR logic gates, transfer gates, and the like.

[0041] The memory elements may use any suitable volatile and / or nonvolatile memory structures, such as random access memory (RAM) cells, fuses, antifuses, programmable read-only memory cells, mask-programmed and laser-programmed structures, combinations of these structures, etc. Because the memory elements are loaded with configuration data during programming, the memory elements are sometimes referred to as configuration memory or programmable memory elements.

[0042] Programmable memory elements can be organized in a configuration memory array consisting of rows and columns. Data registers across all columns and address registers across all rows can receive configuration data. Configuration data can be transferred to the data registers. When the appropriate address register is asserted, the data registers write the configuration data to the configuration memory element of the row specified by the address register.

[0043] Configurable integrated circuit 400 may include configuration memory organized in sectors, whereby a sector may include configuration RAM bits that specify the functions and / or interconnections of subcomponents and wires in or across the sector.Each sector may include separate data and address registers.

[0044] Figure 4 The configurable IC is just one example of an IC that can be used with the embodiments disclosed herein. The embodiments disclosed herein can be used with any appropriate electronic integrated circuit or system. For example, the embodiments disclosed herein can be used with various types of electronic devices, such as processor integrated circuits, central processing units, memory integrated circuits, graphics processing unit integrated circuits, application specific standard products (ASSP), application specific integrated circuits (ASIC), and configurable logic integrated circuits. Examples of configurable logic integrated circuits include programmable arrays logic (PAL), programmable logic arrays (PLA), field programmable logic arrays (FPLA), electrically programmable logic devices (EPLD), electrically erasable programmable logic devices (EEPLD), logic cell arrays (LCA), complex programmable logic devices (CPLD), and field programmable gate arrays (FPGA), just to name a few.

[0045] The integrated circuit disclosed in one or more embodiments of the present invention may be part of a data processing system that includes one or more of the following components: a processor; a memory; an input / output circuit; and peripheral devices. The data processing system may be used in a variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other suitable application. The integrated circuit may be used to perform a variety of different logic functions.

[0046] Designing and implementing a desired (custom) logic circuit design in a configurable logic integrated circuit (IC) can be a daunting task. Therefore, logic designers typically use a logic design system based on a computer-aided design (CAD) tool to assist them in designing the circuit. The logic design system can help logic designers design and test the complex circuits of the system. When the design is complete, the logic design system can be used to generate configuration data in a bitstream for electrically programming the appropriate configurable logic IC.

[0047] exist Figure 5 An illustrative circuit design system 500 is shown according to one embodiment. If desired, Figure 5 The circuit design system 500 can be used in a logic design system. The circuit design system 500 can be implemented on an integrated circuit design computing device. For example, the circuit design system 500 may include one or more networked computer systems with processors, memories, mass storage devices, input / output devices, etc. For example, the system 500 may be based on one or more processors 503, such as personal computers, workstations, etc. (One or more) processors 503 can be linked using a network (e.g., a local area network or a wide area network). The memories in these computers or external memories and storage devices (in Figure 5 Memory / storage 504 ) may be used to store instructions and data.

[0048] Software-based components, such as computer-aided design (CAD) tool 501 and database(s) 502, are located on system 500. During operation, executable software (e.g., software of computer-aided design tool(s) 501) runs on processor(s) 503 of system 500. Database(s) 502 are used to store data for the operation of system 500. In general, software and data may be stored in a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium), such as memory / storage device 504. Software code may sometimes be referred to as software, data, program instructions, instructions, or code. Non-transitory computer-readable storage media may include computer memory chips, nonvolatile memory such as non-volatile random-access memory (NVRAM), one or more hard disk drives (e.g., magnetic drives or solid-state drives), one or more removable flash drives or other removable media, compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs (BDs), other optical media, as well as floppy disks, magnetic tapes, or any other suitable (one or more) memory or storage devices.

[0049] The software stored on the non-transitory computer-readable storage medium can be executed on the system 500. When the software of the system 500 is installed, there are instructions and data in the storage device of the system 500, and these instructions and data enable the computing devices in the system 500 to perform various methods (processes). When executing these processes, the computing devices are configured to implement the functions of the circuit design system 500.

[0050] (One or more) computer-aided design (CAD) tools 501 (some or all of which are sometimes collectively referred to as CAD tools, circuit design tools, or electronic design automation (EDA) tools) may be provided by a single vendor or multiple vendors. (One or more) tools 501 may be provided as one or more tool suites (e.g., compiler suites for performing tasks associated with implementing circuit design in a programmable IC) and / or as one or more separate software components (tools). (One or more) databases 502 may include one or more databases accessed only by one or more specific tools, and may include one or more shared databases. A shared database may be accessed by multiple tools. For example, a first tool may store data for a second tool in a shared database. A second tool may access a shared database to retrieve data stored by the first tool. This allows one tool to pass information to another tool. If desired, tools may also pass information between each other without storing information in a shared database.

[0051] exist Figure 6 A circuit design system (eg Figure 5 6. An illustrative computer-aided design tool 600 in a circuit design system 500 of FIG. 5. The design process may begin by formulating a functional specification of a circuit design (e.g., a functional or behavioral description of a circuit design). A circuit designer may specify the functional operation of a desired circuit design using a design and constraint input tool 602. The design and constraint input tool 602 may include tools such as a design and constraint input assistant 604 and a design editor 606. The design and constraint input assistant (e.g., assistant 604) may be used to help a circuit designer locate a desired design from a library of existing circuit designs, and may provide computer-aided assistance to a circuit designer in inputting (specifying) a desired circuit design. The design and constraint input tool 602 may allow a circuit designer to input timing constraints for a desired circuit design through assistant 604.

[0052] As an example, design and constraint entry aid 604 may be used to present a screen of options to a user. The user may click on options on the screen to select whether the circuit being designed should have certain features. Design editor 606 may be used to enter a design (e.g., by entering lines of hardware description language code), may be used to edit a design obtained from a library (e.g., using a design and constraint entry aid), or may assist a user in selecting and editing an appropriate pre-packaged code / design.

[0053] Design and constraint entry tools 602 may be used to allow a circuit designer to provide a desired circuit design using any suitable format. For example, design and constraint entry tools 602 may include tools that allow a circuit designer to input a circuit design using a truth table. A truth table may be specified using a text file or a timing diagram and may be imported from a library. Truth table circuit design and constraint entry may be used for a portion of a large circuit or for an entire circuit.

[0054] As another example, the design and constraint input tool 602 may include a schematic capture tool. The schematic capture tool may allow a circuit designer to intuitively construct an integrated circuit design from building blocks such as logic gates and logic gate groups. Libraries of existing integrated circuit designs may be used to allow the desired portion of the design to be imported using the schematic capture tool.

[0055] If desired, design and constraint entry tools 602 may allow a circuit designer to provide a circuit design to circuit design system 500 using a hardware description language (e.g., Verilog hardware description language (Verilog HDL), Very High Speed ​​Integrated Circuit Hardware Description Language (VHDL), SystemVerilog, or a higher level circuit description language (e.g., OpenCL or SystemC), etc.). The designer of the integrated circuit design may enter the circuit design by writing hardware description language code using editor 606. If desired, code blocks may be imported from a user maintained library or a commercial library.

[0056] After the circuit design is entered using the design and constraint input tool 602, the functionality of the circuit design may be simulated using the behavioral simulation tool 608. If the functionality of the design is incomplete or incorrect, the circuit designer may use the design and constraint input tool 602 to make changes to the circuit design. The functional operation of the new circuit design may be verified using the behavioral simulation tool 608 before performing a synthesis operation using the tool 610. If desired, simulation tools such as the behavioral simulation tool 608 may also be used in other stages of the design process (e.g., after logic synthesis). The output of the behavioral simulation tool 608 may be provided to the circuit designer in any suitable format (e.g., truth table, timing diagram, etc.).

[0057] After determining that the functional operation of the circuit design is satisfactory, the logic synthesis and optimization tool 610 can generate a gate-level netlist for the circuit design, for example, using gates from a specific library associated with a target process supported by the foundry that has been selected to produce the integrated circuit. Alternatively, the logic synthesis and optimization tool 610 can generate a gate-level netlist for the circuit design using the gates of the target configurable IC (i.e., in the logic and interconnect resources of a specific configurable IC product or product family).

[0058] The logic synthesis and optimization tool 610 can optimize the circuit design by appropriately selecting hardware to implement different logic functions in the circuit design based on the circuit design data and constraint data input by the logic designer using the tool 602. For example, the logic synthesis and optimization tool 610 can perform multi-level logic optimization and technology mapping based on the length of the combinational path between registers in the circuit design and the corresponding timing constraints input by the logic designer using the tool 602.

[0059] After performing logic synthesis and optimization using tools 610, circuit design system 500 may perform physical design steps (layout synthesis operations) using tools such as placement, routing, and physical synthesis tools 612. Tools 612 may be used to determine where to place each gate of the gate-level netlist generated by tools 610. For example, if two counters interact with each other, tools 612 may position these counters in adjacent areas to reduce interconnect delays or meet timing requirements that specify a maximum allowed interconnect delay. Tools 612 create an orderly and efficient circuit design implementation for any target integrated circuit (e.g., for a given configurable integrated circuit such as a field programmable gate array (FPGA)).

[0060] Tools such as tools 610 and 612 may be part of a compiler suite (e.g., part of a compiler tool suite provided by a programmable IC vendor). After an implementation of a desired circuit design is generated using tools 612, the implementation of the design may be analyzed and tested using analysis tools 614. For example, analysis tools 614 may include a timing analysis tool, a power analysis tool, or a formal verification tool, among others.

[0061] After satisfactory optimization operations have been completed using tool 600, tool 600 may generate a mask level layout description of an integrated circuit or configuration data for programming a configurable logic IC, depending on the target integrated circuit technology.

[0062] In general, software and data for performing any function disclosed herein can be stored in a non-transient computer-readable storage medium. A non-transient computer-readable storage medium is a tangible computer-readable storage medium that stores data and software for later access, rather than a medium (e.g., a wire) that transmits only propagating electrical signals. Software code may sometimes be referred to as software, data, program instructions, instructions, or code. A non-transient computer-readable storage medium may, for example, include a computer memory chip, a non-volatile memory, such as a non-volatile random-access memory (NVRAM), one or more hard disk drives (e.g., a magnetic drive or a solid-state drive), one or more removable flash drives or other removable media, a compact disc (CD), a digital versatile disc (DVD), a Blu-ray disc (BD), other optical media, and a floppy disk, a tape, or any other appropriate (one or more) memory or storage device.

[0063] Additional examples are now described. Example 1 is an integrated circuit comprising: a cryptographic engine that generates a first cryptographic version of a password; a secure storage area; and a security controller circuit that stores an enable bit and at least a portion of the first cryptographic version of the password in the secure storage area to enable a security feature, wherein the security controller circuit enables configuration of the integrated circuit in response to receiving the password from a user if the enable bit stored in the secure storage area indicates that the security feature is enabled.

[0064] In Example 2, the integrated circuit of Example 1 may optionally include, wherein the cryptographic engine generates a first hash of the password as a first cryptographic version of the password, and wherein the security controller circuit stores the first hash of the password in the secure storage area.

[0065] In Example 3, the integrated circuit as described in Example 2 may optionally include, wherein the cryptographic engine generates a second hash of the password in response to receiving the password from the user, and wherein the security controller circuit compares the first hash of the password accessed from the secure storage area with the second hash of the password to determine whether to allow configuration of the integrated circuit.

[0066] In Example 4, the integrated circuit as described in any of Examples 1-3 may optionally include, wherein the security controller circuit truncates the first cryptographic version of the password to generate a truncated cryptographic version of the password, and wherein the security controller circuit stores the truncated cryptographic version of the password in the secure storage area.

[0067] In Example 5, the integrated circuit as described in any of Examples 1-4 may optionally include, if the enable bit stored in the secure storage area indicates that the security feature is enabled and the user fails to provide the password to the security controller circuit, the security controller circuit prevents the user from configuring the integrated circuit.

[0068] In Example 6, the integrated circuit as described in any of Examples 1-5 may optionally include, wherein the security controller circuit allows access to the integrated circuit to be protected during configuration of the integrated circuit by authentication with a digital signature in response to receiving the password from the user.

[0069] In Example 7, the integrated circuit as described in any of Examples 1-6 may optionally include, wherein the security controller circuit is responsive to receiving the password from the user so that access to the integrated circuit is controlled by a private key and a public key during configuration of the integrated circuit.

[0070] Example 8 is a non-transitory computer-readable storage medium comprising computer-readable instructions stored thereon for causing an integrated circuit to: generate a first cryptographic version of a first password using a cryptographic function; store at least a first portion of the first cryptographic version of the first password in a secure storage circuit in the integrated circuit; and compare at least the first portion of the first cryptographic version of the first password accessed from the secure storage circuit with at least a second portion of a second cryptographic version of a second password to determine whether the integrated circuit is allowed to be configured.

[0071] In Example 9, the non-transitory computer-readable storage medium as described in Example 8 may optionally include, wherein the computer-readable instructions further cause the integrated circuit to store an enable value in the secure storage circuit, and if the enable value indicates that the security feature has been enabled, request the user to enter the second password to configure the integrated circuit.

[0072] In Example 10, the non-transitory computer-readable storage medium as described in any of Examples 8-9 may optionally include, wherein the computer-readable instructions further cause the integrated circuit to generate a first truncated cryptographic version of the first password using a security controller circuit and store the first truncated cryptographic version of the first password in the secure storage circuit.

[0073] In Example 11, the non-transitory computer-readable storage medium as described in Example 10 may optionally include, wherein the computer-readable instructions further cause the integrated circuit to generate a second truncated cryptographic version of the second password and compare the first truncated cryptographic version of the first password with the second truncated cryptographic version of the second password to determine whether to allow the integrated circuit to be configured.

[0074] In Example 12, the non-transitory computer-readable storage medium as described in any of Examples 8-11 may optionally include, wherein the computer-readable instructions further cause the integrated circuit to: in response to verifying that at least the first part of the first cryptographic version of the first password matches at least the second part of the second cryptographic version of the second password received from a user, allow access to the integrated circuit to be protected by authentication during configuration of the integrated circuit.

[0075] In Example 13, the non-transitory computer-readable storage medium as described in any of Examples 8-12 may optionally include, wherein the computer-readable instructions further cause the integrated circuit to generate a first hash of the first password, store a first part of the first hash of the first password in the secure storage circuit, and compare the first part of the first hash of the first password accessed from the secure storage circuit with a second part of the second hash of the second password received from a user to determine whether to allow the integrated circuit to be configured.

[0076] Example 14 is a method for protecting access to an integrated circuit, the method comprising: generating a first cryptographic version of a first password using a cryptographic function in the integrated circuit; storing at least a first portion of the first cryptographic version of the first password in a secure storage circuit in the integrated circuit; and comparing at least the first portion of the first cryptographic version of the first password received from the secure storage circuit with at least a second portion of a second cryptographic version of a second password received from a user to determine whether the integrated circuit is allowed to be configured.

[0077] In Example 15, the method of Example 14 further includes storing an enable bit in the secure storage circuit to enable a security feature, the security feature protecting configuration of the integrated circuit.

[0078] In Example 16, the method of Example 15 further includes: accessing the enable bit from the secure storage circuit to determine whether the security feature is enabled; and requesting the second password from the user if the security feature is enabled before allowing the integrated circuit to be configured.

[0079] In Example 17, the method as described in any of Examples 14-16 also includes: generating a first truncated cryptographic version of the first password stored in the secure storage circuit; and generating a second truncated cryptographic version of the second password received from the user, wherein the comparison further includes comparing the first truncated cryptographic version of the first password with the second truncated cryptographic version of the second password to determine whether the integrated circuit is allowed to be configured.

[0080] In Example 18, the method as in any one of Examples 14-17 further includes generating a second cryptographic version of the second password using the cryptographic function in response to receiving the second password from the user.

[0081] In Example 19, the method of any of Examples 14-18 further includes: if the first portion of the first cryptographic version of the first password matches the second portion of the second cryptographic version of the second password, enabling access to the integrated circuit to be protected by authentication during provisioning of the integrated circuit.

[0082] In Example 20, the method as described in any of Examples 14-19 further includes: if the first part of the first cryptographic version of the first password matches the second part of the second cryptographic version of the second password, controlling access to the integrated circuit by the private key and the public key during configuration of the integrated circuit.

[0083] In Example 21, the method of any of Examples 14-20, wherein the integrated circuit is a configurable logic integrated circuit.

[0084] The above description of the exemplary embodiments is given for illustration. The above description is not intended to be exhaustive or to limit the examples disclosed herein. The above content is only illustrative of the principles of the present disclosure, and various modifications may be made by those skilled in the art. The above embodiments may be implemented individually or in any combination.

Claims

1. An integrated circuit, comprising: a cryptographic engine that generates a first cryptographic version of a password; secure storage areas; as well as a security controller circuit that stores an enable bit and at least a portion of a first cryptographic version of the password in the secure memory area to enable a security feature, wherein the security controller circuit enables configuration of the integrated circuit in response to receiving the password from a user if the enable bit stored in the secure memory area indicates that the security feature is enabled.

2. The integrated circuit of claim 1, wherein: The cryptographic engine generates a first hash of the password as a first cryptographic version of the password, and wherein the security controller circuit stores the first hash of the password in the secure storage area.

3. The integrated circuit of claim 2, wherein: The cryptographic engine generates a second hash of the password in response to receiving the password from the user, and wherein the security controller circuit compares the first hash of the password accessed from the secure storage area with the second hash of the password to determine whether to allow configuration of the integrated circuit.

4. An integrated circuit as claimed in any one of claims 1 to 3, wherein: The security controller circuit truncates the first cryptographic version of the password to generate a truncated cryptographic version of the password, and wherein the security controller circuit stores the truncated cryptographic version of the password in the secure storage area.

5. The integrated circuit according to any one of claims 1 to 3, wherein: If the enable bit stored in the secure memory area indicates that the security feature is enabled and the user fails to provide the password to the security controller circuit, the security controller circuit prevents the user from configuring the integrated circuit.

6. The integrated circuit according to any one of claims 1 to 3, wherein: The security controller circuitry, in response to receiving the password from the user, allows access to the integrated circuit to be protected during configuration of the integrated circuit by authentication with a digital signature.

7. An integrated circuit as claimed in any one of claims 1 to 3, wherein: The security controller circuit is responsive to receiving the password from the user so that access to the integrated circuit is controlled via a private key and a public key during provisioning of the integrated circuit.

8. A non-transitory computer-readable storage medium comprising computer-readable instructions stored thereon for causing an integrated circuit to: generating a first cryptographic version of the first password using a cryptographic function; storing at least a first portion of a first cryptographic version of the first password in secure storage circuitry in the integrated circuit; and At least the first portion of a first cryptographic version of the first password accessed from the secure storage circuit is compared with at least a second portion of a second cryptographic version of a second password to determine whether the integrated circuit is allowed to be configured.

9. The non-transitory computer-readable storage medium of claim 8, wherein: The computer-readable instructions further cause the integrated circuit to store an enablement value in the secure storage circuit and, if the enablement value indicates that the security feature has been enabled, request a user to enter the second password to configure the integrated circuit.

10. The non-transitory computer-readable storage medium of any one of claims 8-9, wherein: The computer-readable instructions further cause the integrated circuit to generate a first truncated cryptographic version of the first password using the security controller circuit and to store the first truncated cryptographic version of the first password in the secure storage circuit.

11. The non-transitory computer-readable storage medium of claim 10, wherein: The computer-readable instructions also cause the integrated circuit to generate a second truncated cryptographic version of the second password and compare the first truncated cryptographic version of the first password to the second truncated cryptographic version of the second password to determine whether to allow the integrated circuit to be configured.

12. The non-transitory computer-readable storage medium of any one of claims 8-9, wherein: The computer-readable instructions also cause the integrated circuit to: in response to verifying that at least the first portion of a first cryptographic version of the first password matches at least the second portion of a second cryptographic version of the second password received from a user, allow access to the integrated circuit to be protected by authentication during configuration of the integrated circuit.

13. The non-transitory computer-readable storage medium of any one of claims 8-9, wherein: The computer-readable instructions further cause the integrated circuit to generate a first hash of the first password, store a first portion of the first hash of the first password in the secure storage circuit, and compare the first portion of the first hash of the first password accessed from the secure storage circuit with a second portion of a second hash of the second password received from a user to determine whether the integrated circuit is allowed to be configured.

14. A method for protecting access to an integrated circuit, the method comprising: generating a first cryptographic version of a first password using a cryptographic function in the integrated circuit; storing at least a first portion of a first cryptographic version of the first password in secure storage circuitry in the integrated circuit; and At least the first portion of a first cryptographic version of the first password received from the secure storage circuit is compared with at least a second portion of a second cryptographic version of a second password received from a user to determine whether to allow the integrated circuit to be configured.

15. The method of claim 14, further comprising: An enable bit is stored in the secure storage circuit to enable a security feature that protects configuration of the integrated circuit.

16. The method of claim 15, further comprising: accessing the enable bit from the secure storage circuit to determine whether the security feature is enabled; and Before allowing the integrated circuit to be configured, the second password is requested from the user if the security feature is enabled.

17. The method of any one of claims 14 to 16, further comprising: generating a first truncated cryptographic version of the first password that is stored in the secure storage circuit; and A second truncated cryptographic version of the second password received from the user is generated, wherein the comparing further comprises comparing the first truncated cryptographic version of the first password with the second truncated cryptographic version of the second password to determine whether the integrated circuit is allowed to be configured.

18. The method of any one of claims 14 to 16, further comprising: A second cryptographic version of the second password is generated using the cryptographic function in response to receiving the second password from the user.

19. The method of any one of claims 14 to 16, further comprising: Access to the integrated circuit is protected by authentication during provisioning of the integrated circuit if the first portion of the first cryptographic version of the first password matches the second portion of the second cryptographic version of the second password.

20. The method of any one of claims 14-16, further comprising: If the first portion of the first cryptographic version of the first password matches the second portion of the second cryptographic version of the second password, access to the integrated circuit is controlled by a private key and a public key during provisioning of the integrated circuit.

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