Verification system for multi-core chip in low power consumption mode

Abstract

The invention relates to a verification system for a low power consumption mode of a multi-core chip. The system comprises a normal working state checking layer, a low-power-consumption decision-making entering layer, a low-power-consumption checking entering layer, a low-power-consumption state checking layer, a wake-up decision-making executing layer and a wake-up checking layer. According to the system, all coverage of a multi-core scene can be realized, all multi-core low-power-consumption scenes can be covered by entering the low-power-consumption decision-making layer and awakening the decision-making layer, automatic check of multiple scenes can be completed in a check section, and verification coverage of multiple characteristics of a complex scene in a low-power-consumption mode of a multi-core chip is realized.

Description

Technical Field

[0001] The present application relates to the technical field of integrated chips, and in particular to a verification system for a multi-core chip low power consumption mode. Background Art

[0002] In embedded and IoT devices, low power consumption is a critical feature that can reduce the number of times the device needs to be charged and extend the device's usage time.

[0003] Therefore, for chips used in this field, the design of low-power mode is very important. At the same time, in order to cope with different working scenarios, multiple low-power modes are often designed, so that power consumption can be reduced to different degrees. The low-power mode of the chip is mainly reflected in the following aspects: stopping the work of the core, turning off the clock of the peripherals, turning off the use of the storage space, and turning off the regional power supply. Therefore, the verification of the low-power mode of the chip needs to cover its state characteristics of entering and exiting the low-power mode, as well as different low-power scenarios. Including the start and stop of the core in the above low-power characteristics, whether the clocks of different peripherals are turned off, the opening and closing of the storage space, the power off and power on, etc. The verification of these characteristics is relatively simple to cover in a single-core system. Because there is only one core, the entry and exit of the low-power mode is single and serial, and it only needs to be verified for its different mode configurations. However, in a multi-core scenario, with multiple cores, the verification scenario of the low-power mode becomes complicated. It is mainly reflected in: a chip with multiple cores can be a single core, some cores or all cores, successively or simultaneously, entering or exiting the low-power mode. At the same time, peripherals that enter low power consumption mode can be set to be subordinate to different cores or require permissions of all cores, and the entry and exit of low power consumption mode of storage space can also be set to follow the low power consumption mode of different cores. Therefore, the verification of low power consumption mode in multi-core scenarios is multi-scenario and multi-feature, and cannot be verified in a serial single mode like single core. Summary of the invention

[0004] Based on this, it is necessary to provide a verification system for the low power consumption mode of a multi-core chip to address the above technical issues.

[0005] A multi-core chip low power consumption mode verification system, the system comprising: The normal working state check layer is used to check whether each core in queue A is in normal working state at the current moment; it is also used to check whether each core in queue B is still in low power consumption mode; queue A is composed of cores in normal working state, and queue B is composed of cores in low power consumption mode; Enter the low-power decision layer, which is used to decide which cores to enter low-power mode, and then issue instructions to the cores in queue A that want to enter low-power mode, and push them out of queue A and into queue B; Entering the low power consumption check layer is used to check the intermediate states of the cores entering low power consumption modes in different scenarios according to the cores ready to enter low power consumption and the corresponding configurations; The low-power state check layer is used to check whether each core in queue B that enters low-power state is correct, and whether each core in queue A that is working normally is still working normally. The execution wake-up decision layer is used to determine the awakened core and the corresponding wake-up method, wake up the awakened core in the corresponding method, push the awakened core out of queue B, and then push it into queue A; The wake-up check layer is used to check the intermediate states of the wake-up process of different cores under different configurations according to the awakened cores and the configuration of the corresponding wake-up mode determined in the wake-up decision layer.

[0006] In one of the embodiments, the normal working state of a core that is working normally includes: normal state, normal instruction reading and writing, normal peripheral clock, and normal storage access.

[0007] In one of the embodiments, the decision to enter the low power decision layer is a random decision, and then a directed decision is made by reloading the task or function.

[0008] In one of the embodiments, the check items of the low power state check layer can be written in different use cases according to the scenario to be overloaded or inherited.

[0009] In one embodiment, the wake-up method in the wake-up decision layer is random wake-up or targeted wake-up by overloading a function.

[0010] In one of the embodiments, the wake-up check layer adds checks or rewrites checks in subsequent use cases by overloading or inheriting the function.

[0011] The above-mentioned verification system for the low-power mode of multi-core chips includes: a normal working state inspection layer, a low-power decision layer, a low-power inspection layer, a low-power state inspection layer, an execution wake-up decision layer, and a wake-up inspection layer. The system can achieve all coverage of multi-core scenarios. The entry into the low-power decision layer and the wake-up decision layer can help cover all multi-core low-power scenarios, and can also complete automatic inspection of multiple scenarios within one inspection segment. This system solves the verification coverage of complex scenarios and multiple features of the low-power mode of multi-core chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a verification system for a multi-core chip in a low power consumption mode according to an embodiment; Figure 2 Schematic diagram of the process of pushing out from queue A and into queue B in one embodiment. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0014] In one embodiment, Figure 1 As shown, a verification system for a multi-core chip low power consumption mode is provided. The verification system for a multi-core chip low power consumption mode is designed based on an object-oriented method. Figure 1 Each block diagram is an independent object. The system includes: The normal working state check layer is used to check whether each core in queue A is in a normal working state at the current moment; it is also used to check whether each core in queue B is still in low power consumption mode; queue A is composed of cores that are working normally, and queue B is composed of cores that are in low power consumption mode.

[0015] Specifically, the normal working state check layer is used to check whether each normally working core in queue A is in a normal state, whether instructions can be read and written normally, whether the corresponding peripheral clock is normal, and whether the storage is accessed normally. It is also used to check whether each low-power core in queue B is still in low-power mode.

[0016] Enter the low-power decision layer, which is used to decide which cores to enter low-power mode, and then issue instructions to the cores in queue A that want to enter low-power mode, and push them out of queue A and into queue B.

[0017] Specifically, the low power decision layer is used to decide which cores will enter low power and what low power mode they will enter. The decision here can be random or directed by reloading the task or function. After the decision is made, the cores that will enter low power are pushed out of queue A and pushed into queue B. Figure 2 shown.

[0018] Instruction: Based on the decision to enter low power consumption, an instruction is given to the corresponding core to enter low power consumption mode.

[0019] The low power check layer is used to check the intermediate states of the cores entering low power modes in different scenarios according to the cores ready to enter low power and the corresponding configurations.

[0020] Specifically, the input to the low power check layer is the low power core to be entered and the corresponding configuration. Based on these two inputs, the intermediate state of the core entering the low power mode in different scenarios is checked.

[0021] The low power state check layer is used to check whether each core in queue B that enters low power state is correct, and to check whether each core in queue A that is working normally is still working normally.

[0022] Specifically, the low power state check layer can check whether the state of all the cores entering the low power state is correct according to queue B, check the core instruction reading and writing to determine whether the core is shut down, whether the peripheral clock is shut down, check whether the corresponding storage enters the low power state, etc. According to queue A, check whether the cores that are working normally at this time are still working normally.

[0023] The execution wake-up decision layer is used to determine the awakened core and the corresponding wake-up method, wake up the awakened core in the corresponding way, push the awakened core out of queue B, and then push it into queue A.

[0024] Specifically, the execution wake-up decision layer decides which cores to wake up and how to wake them up. The decision here can be a random wake-up or a targeted modification by overloading a function. After the decision is made, the cores to be woken up are pushed out of queue B and into queue A, such as Figure 2 shown.

[0025] Wake-up: Wake up the corresponding core in the corresponding way according to the wake-up decision.

[0026] The entry into the low power decision layer and the wake-up decision layer can help cover all multi-core low power scenarios. For example, you can enter only A or B, or both A and B; in the wake-up decision layer, you can wake up only A or B, or both at the same time. Combined with the loops in the architecture, multiple loops can cover all the scenarios of the two cores entering and waking up.

[0027] The wake-up check layer is used to check the intermediate states of the wake-up process of different cores under different configurations according to the awakened cores and the configuration of the corresponding wake-up mode determined in the wake-up decision layer.

[0028] Specifically, the input of the wake-up check layer is the core to be awakened in the wake-up decision and the configuration of the wake-up method. Based on these two inputs, the intermediate states of the wake-up process of different cores under different configurations are checked.

[0029] After waking up, it returns to the normal working state and starts the next round of entering and waking up low power consumption. At the same time, in a multi-core scenario, not all low-power cores will be woken up every time, so there are still cores in queue B. When returning to the normal working layer again, you can check whether the cores in queue B are still in low power consumption mode.

[0030] Entering the low power check layer, low power state check layer, wake-up check layer, and normal working state check layer can realize automatic checks of different scenarios according to different input variables. That is to say, the check items in the check layer are fixed branches according to different variables. When running different scenarios, the input to the check layer is different, so as to realize automatic checks of corresponding scenarios, without having to write corresponding checks serially for each executed scenario.

[0031] The working process of the verification system of the low power mode of multi-core chips: Assume that a multi-core chip has three cores A0, A1 and A2. After the first power-on, the multi-core chip starts to work normally for a period of time. Then, it is ready to enter the low power state. Here, it enters the low power decision layer (the decision is for random scenarios, a random possible real scenario, here can be A0 core alone enters low power mode, A1 core alone enters low power mode, A0 core and A1 core enter together, A1 core and A2 core, etc. 7 cases). Assuming that A0 core and A1 core enter, then at this time, give instructions to A0 core and A1 core to enter low power mode, and then check the state that A0 core and A1 core enter and the state that A2 core should not enter in the low power check layer. (For example: low power handshake signal, etc.), then check that A0 core and A1 core have entered the low power state in the low power state check layer, and A2 core should be in a normal working state. Then make a decision to wake up, and the decision here is also just a random scenario. Assuming that only A1 core is woken up here, then A0 core will continue to be in a low power state. Then, in the wake-up check layer, the A1 core's wake-up intermediate state is checked. Then the system returns to the normal working state. At this time, the A0 core and the A2 core are in the normal working state, and the A1 core is still in the low power consumption state. The check layer can perform the corresponding check. Then the next cycle can be continued.

[0032] In the verification system of the multi-core chip low power mode, the system includes: a normal working state inspection layer, a low power decision layer, a low power inspection layer, a low power state inspection layer, an execution wake-up decision layer, and a wake-up inspection layer. The system can achieve all coverage of multi-core scenarios. The entry low power decision layer and the wake-up decision layer can help cover all multi-core low power scenarios, and can also complete automatic inspection of multiple scenarios in one inspection segment. This system solves the verification coverage of complex scenarios and multiple features of the low power mode of multi-core chips.

[0033] In one of the embodiments, the normal working state of a core that is working normally includes: normal state, normal instruction reading and writing, normal peripheral clock, and normal storage access.

[0034] In one of the embodiments, the decision to enter the low power decision layer is a random decision, and then a directed decision is made by reloading the task or function.

[0035] In one of the embodiments, the check items of the low power state check layer can be written in different use cases according to the scenario to be overloaded or inherited.

[0036] In one embodiment, the wake-up method in the wake-up decision layer is random wake-up or targeted wake-up by overloading a function.

[0037] In one of the embodiments, the wake-up check layer adds checks or rewrites checks in subsequent use cases by overloading or inheriting the function.

[0038] All layers of the architecture can be overloaded and inherited. Even if the scenario is modified or added, it can be rewritten or added by overloading or inheriting the corresponding tasks or functions, thereby improving the flexibility and reusability of the verification architecture.

[0039] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0040] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A verification system for a multi-core chip low power consumption mode, characterized in that: The system comprises: The normal working state check layer is used to check whether each core in queue A is in normal working state at the current moment; it is also used to check whether each core in queue B is still in low power consumption mode; queue A is composed of cores in normal working state, and queue B is composed of cores in low power consumption mode; Enter the low-power decision layer, which is used to decide which cores to enter low-power mode, and then issue instructions to the cores in queue A that want to enter low-power mode, and push them out of queue A and into queue B; Entering the low power consumption check layer is used to check the intermediate states of the cores entering low power consumption modes in different scenarios according to the cores ready to enter low power consumption and the corresponding configurations; The low-power state check layer is used to check whether each core in queue B that enters the low-power state is correct, and whether each core in queue A that is working normally is still working normally. The wake-up decision layer is used to determine the awakened core and the corresponding wake-up method, and wake up the core that is determined to be awakened in the corresponding method, and push the awakened core out of queue B and then push it into queue A. The wake-up check layer is used to check the intermediate states of the wake-up process of different cores under different configurations according to the awakened cores and the configuration of the corresponding wake-up mode determined in the wake-up decision layer.

2. The system according to claim 1, characterized in that The normal working status of a normally working core includes: normal status, normal instruction reading and writing, normal peripheral clock, and normal storage access.

3. The system according to claim 1, characterized in that The decision to enter the low-power decision layer is a random decision, and then a directional decision is made by overloading the task or function.

4. The system according to claim 1, characterized in that The check items of the low power state check layer can be written in different use cases according to the scenario to be overloaded or inherited.

5. The system according to claim 1, characterized in that The wake-up method in the execution wake-up decision layer is random wake-up or targeted wake-up through overloading functions.

6. The system according to claim 1, characterized in that The wake-up check layer adds checks or rewrites checks in subsequent use cases by overloading or inheriting this function.

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