Virtual system-on-chip, I / O pin multiplexing simulation method, device and storage medium

Abstract

This invention relates to the field of virtual system-on-a-chip (SoC) technology, and discloses a virtual SoC, its I / O pin multiplexing simulation method, apparatus, and storage medium. Each virtual on-chip device in the virtual SoC includes several virtual ports. The virtual I / O module includes multiple virtual off-chip ports, multiple virtual on-chip ports, and multiple input / output flags. The virtual off-chip ports and input / output flags correspond one-to-one with multiple pins of the virtualized chip, and the virtual on-chip ports correspond one-to-one with multiple functions of multiple pins of the virtualized chip. An on-chip port configuration module records the pairing relationships between virtual on-chip ports and virtual ports, and a pin configuration detection module confirms the pairing relationships between virtual off-chip ports and virtual on-chip ports according to the user program. An input driver module and an output driver module are used for driving data input and output, respectively. This system can realistically simulate the I / O pin multiplexing function of a SoC chip and can completely verify the user program.

Description

Technical Field

[0001] This invention relates to the field of virtual system-on-a-chip (SoC) technology, specifically to a virtual SoC, an I / O pin multiplexing simulation method, apparatus, and storage medium. Background Technology

[0002] A System-on-Chip (SoC) is a technology that integrates most or all of the electronic components of a traditional computer or other electronic system onto a single integrated circuit (chip). I / O modules (input / output modules) are crucial bridges for interaction between the SoC and external devices, responsible for handling data transmission and signal conversion between internal and external devices. In practical applications, most I / O pins of an I / O module often perform multiple functions; they can function as ordinary input / output pins or be configured to be assigned as functional pins to internal devices.

[0003] As the design complexity and integration of SoCs continue to increase, the interaction between user code (such as drivers and firmware) and SoC hardware becomes increasingly complex. This leads to rising costs and inefficiencies associated with traditional methods of directly verifying user code using hardware prototypes, resulting in long verification cycles and poor flexibility, making it difficult to meet the demands of rapid iterative development. To address these issues, current methods often involve constructing virtual on-chip systems (SoCs) using modeling languages ​​to simulate SoC behavior, structure, and timing for user code verification. However, current SoCs typically neglect the pin multiplexing functionality of I / O modules. Designers often allow virtual on-chip devices to communicate directly with external devices without going through the I / O module's multiplexing function, resulting in functional gaps in the SoC simulation. This neglect can prevent the simulation system from fully verifying all the functionalities of the SoC design, especially advanced functions that rely on I / O pin multiplexing. Therefore, a pin multiplexing simulation method for I / O modules is needed to improve the accuracy and reliability of SoC simulation. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a virtual system-on-a-chip that can realistically simulate the pin multiplexing function of the I / O module of a system-on-a-chip, thereby improving the reliability and accuracy of the virtual system-on-a-chip's simulation of a real SoC chip.

[0005] To solve the above problems, the technical solution adopted by the present invention is as follows: A virtual system-on-a-chip, comprising: multiple virtual on-chip devices for simulating the functions of on-chip devices of a virtualized chip, each virtual on-chip device including several virtual ports; a virtual I / O module including multiple virtual off-chip ports, multiple virtual on-chip ports, and multiple input / output flags, wherein the multiple virtual off-chip ports correspond one-to-one with multiple pins of the virtualized chip, the multiple virtual on-chip ports correspond one-to-one with multiple functions of multiple pins of the virtualized chip, and the multiple input / output flags correspond one-to-one with multiple pins of the virtualized chip; an on-chip port configuration module for recording the pairing relationship between the multiple virtual on-chip ports and the multiple virtual ports; and a pin configuration detection module for confirming the pairing relationship between the multiple virtual off-chip ports and the multiple virtual on-chip ports according to a user program. An input driver module is used to monitor the values ​​of multiple virtual off-chip ports and multiple input / output flags. When an input / output flag is an input flag, it drives the value of the corresponding virtual on-chip port to the corresponding virtual on-chip port according to the pairing relationship confirmed by the pin configuration detection module, and drives the value of the virtual on-chip port to the corresponding virtual port according to the pairing relationship recorded by the on-chip port configuration module. An output driver module is used to monitor the values ​​of multiple virtual ports and multiple input / output flags. When an input / output flag is an output flag, it drives the value of the virtual port to the corresponding virtual on-chip port according to the pairing relationship recorded by the on-chip port configuration module, and drives the value of the virtual on-chip port to the corresponding virtual off-chip port according to the pairing relationship confirmed by the pin configuration detection module.

[0006] Compared with the prior art, the beneficial effects of the present invention are as follows: by establishing a virtual I / O module including multiple virtual on-chip ports and virtual off-chip ports to simulate the I / O module in the real SoC chip, and by simulating the forwarding mechanism of the I / O module through a pin configuration detection module, an input driver module and an output driver module, the pin multiplexing function of the real SoC chip can be realized. This can improve the accuracy and reliability of the virtual on-chip system's simulation of the real SoC, more accurately verify the integrity of the user code's functions, and reduce the development cost of the SoC's supporting programs.

[0007] The virtual on-chip system described above includes virtual on-chip input ports and virtual on-chip output ports.

[0008] In the aforementioned virtual on-chip system, multiple virtual off-chip ports form a group of numbered off-chip registers, with each number corresponding to a pin number of the virtualized chip. Multiple virtual on-chip input ports form a group of numbered input on-chip registers, with each number corresponding to a pin number of the virtualized chip. Each input on-chip register group includes multiple numbered input on-chip registers, and each input on-chip register corresponds to multiple input functions of each pin. Multiple virtual on-chip output ports form a group of numbered output on-chip registers, with each output on-chip register group including multiple numbered output on-chip registers, and each output on-chip register corresponds to multiple output functions of each pin.

[0009] In the aforementioned virtual system-on-a-chip, the pin configuration detection module includes a set of configuration registers with defined serial numbers. The serial numbers of the multiple configuration registers correspond one-to-one with the serial numbers of the multiple pins of the virtual chip. The pin configuration detection module confirms the function selected by each pin according to the user program and writes the serial number of the output on-chip register or the input on-chip register corresponding to the selected function into the corresponding configuration register.

[0010] A method for simulating I / O pin multiplexing in a virtual on-chip system includes:

[0011] Define a set of off-chip registers and at least one set of on-chip registers, where each off-chip register corresponds to a pin of a virtual chip and each on-chip register corresponds to a function of a pin of a virtual chip.

[0012] Based on the pairing relationship between the pins of the virtual chip and the ports of the on-chip devices, multiple on-chip registers are paired with the virtual ports of multiple virtual on-chip devices.

[0013] The user program executes the real-time pin configuration of the virtual chip.

[0014] Based on the confirmed functional configuration of each pin of the virtualized chip, the off-chip registers corresponding to the same pin are paired with the on-chip registers.

[0015] Monitor the input / output status of each pin, drive the value of the external register corresponding to the pin with the input status to the paired internal register, and drive the value of the internal register corresponding to the pin with the input status to the paired virtual port; drive the value of the virtual port to the internal register corresponding to the pin with the output status, and drive the value of the internal register corresponding to the pin with the output status to the external register.

[0016] The above-described IO pin multiplexing simulation method, specifically including the step of defining a set of off-chip registers and at least one set of on-chip registers, where each off-chip register corresponds to a virtual chip pin and each on-chip register corresponds to a virtual chip pin, includes the following steps:

[0017] Define a set of external registers, number them consecutively, and set the maximum number of the external register to be equal to the maximum pin number of the virtual chip.

[0018] Define a set of input on-chip register groups, number the input on-chip register groups consecutively, the maximum sequence number of the input on-chip register group is equal to the maximum pin sequence number of the virtual chip, and the number of registers in each input on-chip register group is the same as the number of input functions of the corresponding pin;

[0019] Define a set of output on-chip register groups, number the output on-chip register groups consecutively, the maximum sequence number of the output on-chip register group is equal to the maximum pin sequence number of the virtual chip, and the number of registers in each set of output on-chip register groups is the same as the number of output function types of the corresponding pins;

[0020] The input function number of each pin of the virtual chip is assigned to each input on-chip register in the corresponding input on-chip register group;

[0021] The output function number of each pin of the virtual chip is assigned to each input on-chip register in the corresponding output on-chip register group.

[0022] The aforementioned IO pin multiplexing simulation method, wherein the step of obtaining the real-time functional configuration of the virtual chip's pins based on the executed user program includes:

[0023] Define a set of configuration registers, number them consecutively, and set the maximum sequence number of the configuration register to be equal to the maximum pin number of the virtual chip.

[0024] The real-time functional configuration of each virtual chip pin is obtained based on the executed user program;

[0025] Obtain the input / output flags for each pin, and determine the input / output status of each pin based on the input / output flags;

[0026] Query the corresponding function number based on the function configuration and input / output status of each pin;

[0027] Write the function number of each pin into the configuration register with the same number as that pin.

[0028] The aforementioned IO pin multiplexing simulation method, wherein the step of pairing the off-chip registers and on-chip registers corresponding to the same pin according to the confirmed functional configuration of each pin of the virtualized chip includes:

[0029] Based on the pin number, query the value of the corresponding input / output flag for that pin, and retrieve the value pin_afr[x] stored in the configuration register with the same pin number;

[0030] If the value of the input / output flag of the pin indicates the output status, then the output on-chip register with the same sequence number as the pin and the same sequence number as the pin in the output on-chip register group with the sequence number pin_afr[x] will be paired.

[0031] If the value of the input / output flag of the pin indicates the input state, then the input on-chip register with the same sequence number as the pin and the input on-chip register with the same sequence number as the pin, with the sequence number pin_afr[x], will be paired.

[0032] A storage medium storing a computer program, characterized in that, when the computer program is invoked and executed by a processor, it implements the above-described virtual on-chip system I / O pin multiplexing simulation method.

[0033] A virtual device for a system-on-a-chip includes a processor and a memory, the memory being electrically connected to the processor, and the processor being able to implement the above-described virtual system-on-a-chip I / O pin multiplexing simulation method by calling and executing a computer program in the memory.

[0034] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0035] Figure 1 This is a schematic block diagram of the virtual on-chip system according to an embodiment of the present invention;

[0036] Figure 2 This is a flowchart illustrating the virtual on-chip system I / O pin multiplexing simulation method according to an embodiment of the present invention. Detailed Implementation

[0037] The embodiments of the present invention are described in detail below, with reference to... Figure 1This invention provides a virtual system-on-a-chip (SoC) comprising multiple virtual on-chip devices, a virtual I / O module, an on-chip port configuration module, a pin configuration detection module, an input driver module, and an output driver module. The virtual on-chip devices simulate the functions of on-chip devices within the virtualized SoC chip, such as serial ports, SPI, I2C, or ADCs. Each on-chip device includes several virtual ports, which serve as input / output ports. The virtual I / O module includes multiple virtual external ports, multiple virtual on-chip ports, and multiple input / output flags. The virtual external ports correspond one-to-one with multiple pins of the virtualized SoC chip, the virtual on-chip ports correspond one-to-one with multiple functions of multiple pins of the virtualized SoC chip, and the input / output flags correspond one-to-one with multiple pins of the virtualized SoC chip. The on-chip port configuration module records the pairing relationships between virtual on-chip ports and virtual ports of virtual on-chip devices. The pairing relationship is determined based on the functions of each pin of the virtualized SoC chip, pairing the virtual on-chip port with the virtual port of the virtual on-chip device performing the corresponding function. The pin configuration detection module confirms the pairing relationship between virtual external ports according to the executed user program. It obtains the real-time function configuration of each pin based on the user program and pairs the virtual external port corresponding to the configured function with the virtual internal port corresponding to that function. The input driver module and output module monitor the values ​​of virtual ports, virtual internal ports, virtual external ports, and input / output flags. They determine the input / output status of the pins based on the input / output flags and drive the values ​​according to the input / output status to transmit data between the paired virtual ports, virtual internal ports, and virtual external ports, simulating the interaction of data signals between virtual internal devices and external devices.

[0038] The virtual on-chip system of this invention simulates the forwarding mechanism of a real SoC chip's I / O module when implementing pin multiplexing functionality by setting up a virtual I / O module and a pin configuration detection module. This allows for the simulation of the I / O pin multiplexing function of a real SoC chip, providing a more complete and reliable simulation of the SoC chip to be verified. Using this virtual on-chip system for user program verification verifies the configuration functionality of I / O pins within the user program, enabling complete functional verification of the user program, ensuring the reliability and accuracy of the verification, and reducing user development costs.

[0039] Understandably, the virtual on-chip devices, virtual I / O modules, on-chip port configuration modules, pin configuration detection modules, input driver modules, and output driver modules are all built using the SystemC language. SystemC is a high-level modeling language based on C++, specifically developed for system-level design and modeling. It has a rich set of class libraries, enabling designers to describe and simulate the behavior, structure, and timing of systems at a higher level of abstraction.

[0040] In this embodiment, for ease of description, virtual ports, virtual off-chip ports, virtual on-chip ports, and input / output flags are all described and defined in the form of registers. A virtual off-chip port is a group of consecutively numbered off-chip registers, where the maximum sequence number of the off-chip register is equal to the maximum pin number of the virtualized SoC chip's pin. Each on-chip register corresponds to a pin with the same sequence number. A virtual on-chip port includes a group of consecutively numbered input on-chip registers and a group of consecutively numbered output on-chip registers, where the maximum sequence number of both the input and output on-chip register groups is also equal to the maximum pin number of the virtualized SoC chip's pin. Each group of input on-chip registers corresponds to multiple input functions of a pin with the same sequence number, and the number of input on-chip registers in each group is equal to the number of input functions of the pin with the same sequence number. Each group of output on-chip registers corresponds to multiple output functions of a pin with the same sequence number, and the number of output on-chip registers in each group corresponds to the number of output functions of the pin with the same sequence number. Taking the virtual on-chip system of the SoC chip with model number MM32F5270 as an example, its IO module contains 16 pins, and each pin has 16 multiplexed input and output functions. Therefore, it is necessary to define an external register group pin

[16] with 16 external registers, a two-dimensional input on-chip register group afio_pin_in

[16]

[16] composed of 16 input on-chip register groups with 16 input on-chip registers, and a two-dimensional output on-chip register group afio_pin_out

[16]

[16] composed of 16 output on-chip register groups with 16 output on-chip registers.

[0041] The input / output flags are multiple consecutively numbered input / output flag registers. The maximum sequence number of the input / output flag register is equal to the maximum pin number of the virtual chip pin. The input / output status of the pin can be determined by querying the value of the input / output flag register with the same sequence number. The pin configuration detection module includes multiple consecutively numbered configuration registers. The maximum sequence number of the configuration register is equal to the maximum pin number of the virtual chip. Taking the virtual on-chip system of the SoC chip with model number MM32F5270 as an example, it is necessary to define an input / output flag register group pin_cnf

[16] consisting of 16 input / output flag registers and a configuration register group pin_afr

[16] consisting of 16 configuration registers.

[0042] In this embodiment, a pin configuration detection function `pin_check-func` is defined using SystemC language to detect the input / output status and functional configuration of each pin. Based on the input / output status and functional configuration of each pin, the values ​​of the input / output flag register and configuration register of each pin are modified, thus realizing the function of the pin configuration detection module. Furthermore, input driver functions `pin_in_fun` and output driver functions `pin_out_fun` are defined using SystemC language to implement the functions of the input driver and output driver respectively. The values ​​of the external registers are driven to the paired virtual ports through paired input on-chip registers, and the values ​​of the virtual ports are driven to the external registers through paired output on-chip registers, thus simulating the pin multiplexing forwarding mechanism of the I / O module of a real SoC chip.

[0043] Understandably, real SoC chips typically also have corresponding flag registers to indicate the input / output status and function configuration of pins. Pin configuration detection functions can obtain the real-time function configuration and input / output configuration of pins by monitoring write operations to the pin's flag register in the user program, and synchronize the written values ​​to the corresponding input / output flag registers and configuration registers. Furthermore, real SoC chips typically configure pin functions by modifying the values ​​of the pin's function configuration register. The on-chip system predefines function numbers for each pin's function, and specific function configurations are achieved by writing the required function numbers into the function configuration register. Therefore, by defining the pin's function number as the corresponding input on-chip register or input off-chip register, the input driver function `pin_in_fun` and the output driver function `pin_out_fun` can use the configuration register as a pointer to query the input on-chip register or output on-chip register paired with the off-chip register.

[0044] Reference Figure 2Based on the same inventive concept, the virtual on-chip system I / O pin multiplexing simulation method of this application includes the following steps:

[0045] Define a set of off-chip registers and at least one set of on-chip registers, where each off-chip register corresponds to a pin of a virtual chip and each on-chip register corresponds to a function of a pin of a virtual chip.

[0046] Based on the pairing relationship between the pins of the virtual chip and the ports of the on-chip devices, multiple on-chip registers are paired with the virtual ports of multiple virtual on-chip devices.

[0047] The user program executes the real-time pin configuration of the virtual chip.

[0048] Based on the confirmed functional configuration of each pin of the virtualized chip, the off-chip registers corresponding to the same pin are paired with the on-chip registers.

[0049] Monitor the input / output status of each pin, drive the value of the external register corresponding to the pin with the input status to the paired internal register, and drive the value of the internal register corresponding to the pin with the input status to the paired virtual port; drive the value of the virtual port to the internal register corresponding to the pin with the output status, and drive the value of the internal register corresponding to the pin with the output status to the external register.

[0050] Specifically, the number of off-chip registers and on-chip registers needs to be defined based on the pins of the virtual real SoC chip and the number of multiplexed functions of the pins. This ensures that each pin has a corresponding off-chip register, each function of each pin has a corresponding on-chip register, the output function of the same pin corresponds to an output on-chip register group, and the input function of the same pin corresponds to an input on-chip register group, thus simulating the pin's input and output functions. Since the pins of a real SoC chip are typically numbered consecutively, and each function of each pin also has a corresponding function number, in this embodiment, the on-chip registers, input on-chip registers, and output on-chip registers can be consecutively numbered to ensure a one-to-one correspondence between them and the pins. Furthermore, since each function of a pin in a real SoC chip is typically assigned a function number, the input function number and output function number of each pin of the SoC chip can be directly assigned to the registers in the corresponding input on-chip register group and output on-chip register group, respectively, so that the on-chip registers and pin functions can correspond one-to-one.

[0051] Taking the virtual on-chip system of the SoC chip with model number MM32F5270 as an example, the pin configuration detection function pin_check_func is defined to monitor the input and output status and function configuration of the pins by the user program, and synchronize them to the input and output flag register group pin_cnf

[16] and the configuration register group pin_afr

[16] . Then, according to the input and output status marked in the input and output flag registers of each pin, the input driving function pin_in_fun and the output driving function pin_out_fun are called to drive the value to be passed between the off-chip register group pin

[16] , the two-dimensional input on-chip register group afio_pin_in

[16]

[16] , the two-dimensional output on-chip register group afio_pin_out

[16]

[16] and the virtual port of the virtual on-chip device.

[0052] In this embodiment, the pin configuration detection function includes 16 sub-pin configuration detection functions pin_check_func0 to pin_check_func15, the input driving function pin_in_fun includes 16 sub-input driving functions pin_in_fun0 to pin_in_fun15, and the output driving function pin_out_fun includes 16 output driving functions pin_out_fun0 to pin_out_fun15.

[0053] The input state is represented by a value of 0 in the input / output flag register group pin_cnf, and the output state is represented by a value of 1. Assuming that the sub-pin configuration detection function pin_check_func6 of pin 6 and the sub-pin configuration detection function pin_check_func7 of pin 7 obtain the user program's requirement to configure pin 6 as the input of the 7th function and pin 7 as the output of the 7th function, then the sub-pin configuration detection function pin_check_func6 writes 0 and 7 into the input / output flag register pin_cnf[6] and the configuration register pin_afr[6] respectively, and the sub-pin configuration detection function pin_check_func7 writes 1 and 7 into the input / output flag register pin_cnf[7] and the configuration register pin_afr[7] respectively. Subsequently, after detecting that the value in the input / output flag register pin_cnf[6] is 0, the sub-input driving function pin_in_fun6 drives the value in the external register pin[6] to the input on-chip register acio_pin_in[6][7] according to the value in the configuration register pin_afr[6], and drives the value in the input on-chip register acio_pin_in[6][7] to the virtual port of the paired virtual on-chip device. After detecting that the value in the input / output flag register pin_cnf[7] is 1, the sub-output driving function pin_in_fun7 drives the virtual port value of the virtual on-chip device paired with the output on-chip register acio_pin_out[7][7] to the register according to the value in the configuration register pin_afr[7], and drives the value in the output on-chip register acio_pin_out[7][7] to the external register pin[7].

[0054] Based on the same inventive concept, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the above-described virtual on-chip system IO pin multiplexing simulation method.

[0055] In some possible implementations, various aspects of the virtual on-chip system I / O pin multiplexing simulation method provided by the present invention can also be implemented in the form of a program product, which includes program code that, when the program product is run on a device, causes the control device to perform the steps in the virtual on-chip system I / O pin multiplexing simulation method according to various exemplary embodiments of the present application described above.

[0056] Based on the same inventive concept, embodiments of the present invention also provide a virtual device for implementing the above-described virtual on-chip system IO pin multiplexing simulation method, including a processor and a memory, the memory being electrically connected to the processor, and the processor implementing the above-described virtual on-chip system IO pin multiplexing simulation method when executing a computer program stored in the memory.

[0057] In one possible design, the processor may include one or more processing units. The processor and memory may be implemented on the same chip or on separate chips. The processor may be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the virtual on-chip system I / O pin multiplexing simulation method disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules in the processor.

[0058] Memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc. Memory is any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. The memory in the embodiments of this application can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0059] By designing and programming the processor, the code corresponding to the virtual on-chip system I / O pin multiplexing simulation method described in the foregoing embodiments can be embedded into the chip, thereby enabling the chip to execute the steps of the virtual on-chip system I / O pin multiplexing simulation method of the embodiments of the present invention during operation. How to design and program the processor is a technique well known to those skilled in the art, and will not be elaborated here.

[0060] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0061] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0062] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0063] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0064] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A virtual system-on-a-chip, characterized in that, include: Multiple virtual on-chip devices are used to simulate the functions of on-chip devices of the virtualized chip, and each virtual on-chip device includes several virtual ports; The virtual I / O module includes multiple virtual off-chip ports, multiple virtual on-chip ports, and multiple input / output flags. The multiple virtual off-chip ports correspond one-to-one with multiple pins of the virtualized chip, the multiple virtual on-chip ports correspond one-to-one with multiple functions of multiple pins of the virtualized chip, and the multiple input / output flags correspond one-to-one with multiple pins of the virtualized chip. An on-chip port configuration module is used to record the pairing relationship between multiple virtual on-chip ports and multiple virtual ports; A pin configuration detection module is used to confirm the pairing relationship between multiple virtual off-chip ports and multiple virtual on-chip ports according to the user program; An input driver module is used to monitor the values ​​of multiple virtual off-chip ports and multiple input / output flags. When an input / output flag is an input flag, the module drives the value of the corresponding virtual on-chip port to the corresponding virtual on-chip port according to the pairing relationship confirmed by the pin configuration detection module, and drives the value of the virtual on-chip port to the corresponding virtual port according to the pairing relationship recorded by the on-chip port configuration module. The output driver module is used to monitor the values ​​of multiple virtual ports and the values ​​of multiple input / output flags. When the input / output flag is an output flag, it drives the value of the virtual port to the corresponding virtual on-chip port according to the pairing relationship recorded by the on-chip port configuration module, and drives the value of the virtual on-chip port to the corresponding virtual off-chip port according to the pairing relationship confirmed by the pin configuration detection module.

2. The virtual on-chip system according to claim 1, characterized in that, The virtual on-chip ports include virtual on-chip input ports and virtual on-chip output ports.

3. The virtual on-chip system according to claim 2, characterized in that, The multiple virtual off-chip ports form a group of numbered off-chip registers, with each number corresponding to a pin number of the virtualized chip. The multiple virtual on-chip input ports form a group of numbered input on-chip registers, with each number corresponding to a pin number of the virtualized chip. Each input on-chip register group includes multiple numbered input on-chip registers, and each input on-chip register corresponds to multiple input functions of each pin. The multiple virtual on-chip output ports form a group of numbered output on-chip registers, with each output on-chip register group including multiple numbered output on-chip registers, and each output on-chip register corresponds to multiple output functions of each pin.

4. The virtual on-chip system according to claim 3, characterized in that, The pin configuration detection module includes a set of configuration registers with defined serial numbers. The serial numbers of the multiple configuration registers correspond one-to-one with the serial numbers of the multiple pins of the virtual chip. The pin configuration detection module confirms the function selected by each pin according to the user program and writes the serial number of the output on-chip register or the input on-chip register corresponding to the selected function into the corresponding configuration register.

5. A method for simulating I / O pin multiplexing in a virtual on-chip system according to any one of claims 1 to 4, characterized in that, include: Define a set of off-chip registers and at least one set of on-chip registers, where each off-chip register corresponds to a pin of a virtual chip and each on-chip register corresponds to a function of a pin of a virtual chip. Based on the pairing relationship between the pins of the virtual chip and the ports of the on-chip devices, multiple on-chip registers are paired with the virtual ports of multiple virtual on-chip devices. The user program executes the real-time pin configuration of the virtual chip. Based on the confirmed functional configuration of each pin of the virtualized chip, the off-chip registers corresponding to the same pin are paired with the on-chip registers. Monitor the input / output status of each pin, drive the value of the external register corresponding to the pin with the input status to the paired internal register, and drive the value of the internal register corresponding to the pin with the input status to the paired virtual port; The value of the virtual port is driven to the on-chip register corresponding to the pin with the paired output state, and the value of the on-chip register corresponding to the pin with the output state is driven to the off-chip register.

6. The IO pin multiplexing simulation method according to claim 5, characterized in that, The step of defining a set of off-chip registers and at least one set of on-chip registers, where each off-chip register corresponds to a pin of a virtual chip and each on-chip register corresponds to a pin of a virtual chip, specifically includes the following steps: Define a set of external registers and number them consecutively. The maximum number of the external register is equal to the maximum pin number of the virtual chip. Define a set of input on-chip register groups, number the input on-chip register groups consecutively, the maximum sequence number of the input on-chip register group is equal to the maximum pin sequence number of the virtual chip, and the number of registers in each input on-chip register group is the same as the number of input functions of the corresponding pin; Define a set of output on-chip register groups, number the output on-chip register groups consecutively, the maximum sequence number of the output on-chip register group is equal to the maximum pin sequence number of the virtual chip, and the number of registers in each set of output on-chip register groups is the same as the number of output function types of the corresponding pins; The input function number of each pin of the virtual chip is assigned to each input on-chip register in the corresponding input on-chip register group; The output function number of each pin of the virtual chip is assigned to each input on-chip register in the corresponding output on-chip register group.

7. The IO pin multiplexing simulation method according to claim 6, characterized in that, The step of obtaining the real-time pin configuration of the virtual chip according to the executed user program includes: Define a set of configuration registers, number them consecutively, and set the maximum sequence number of the configuration register to be equal to the maximum pin number of the virtual chip. The real-time functional configuration of each virtual chip pin is obtained based on the executed user program; Obtain the input / output flags for each pin, and determine the input / output status of each pin based on the input / output flags; Query the corresponding function number based on the function configuration and input / output status of each pin; Write the function number of each pin into the configuration register with the same number as that pin.

8. The IO pin multiplexing simulation method according to claim 7, characterized in that, The step of pairing the off-chip registers and on-chip registers corresponding to the same pin according to the confirmed functional configuration of each pin of the virtualized chip includes: Based on the pin number, query the value of the corresponding input / output flag for that pin, and retrieve the value pin_afr[x] stored in the configuration register with the same pin number; If the value of the input / output flag of the pin indicates the output status, then the output on-chip register with the same sequence number as the pin and the same sequence number as the pin in the output on-chip register group with the sequence number pin_afr[x] will be paired. If the value of the input / output flag of the pin indicates the input state, then the input on-chip register with the same sequence number as the pin and the input on-chip register with the same sequence number as the pin, with the sequence number pin_afr[x], will be paired.

9. A storage medium storing a computer program, characterized in that, When the computer program is called and executed by the processor, it implements the virtual on-chip system I / O pin multiplexing simulation method according to any one of claims 5 to 8.

10. A virtual device for a system-on-a-chip, characterized in that, It includes a processor and a memory, the memory being electrically connected to the processor, the processor being able to implement the I / O pin multiplexing simulation method of the virtual on-chip system according to any one of claims 5 to 8 by calling and executing a computer program in the memory.

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