Static time series statistical analysis system, method, computer equipment and storage media

Abstract

This invention relates to the field of chip technology and discloses a static timing statistical analysis system, method, computer device, and storage medium. The system includes: a first processing module configured to acquire input data; determine filtering conditions based on threshold values ​​in the input data; and determine a target timing path based on the filtering conditions; a second processing module configured to extract target features from the target timing path to obtain extraction results and write them to a timing path feature source file; a third processing module configured to determine feature data of the target timing path based on the timing path feature source file; a fourth processing module configured to determine violation timing paths, generate violation diagnosis reports, and determine timing path optimization strategies; and a fifth processing module configured to generate a statistical distribution table and a statistical distribution graph. This invention can automatically extract the logical and physical features of timing paths in large batches and automatically generate timing path optimization strategies, eliminating the need for designers to analyze timing paths one by one.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more specifically to static timing statistical analysis systems, methods, computer equipment, and storage media. Background Technology

[0002] In chip design, timing analysis is a crucial technical step, ensuring that the chip operates correctly at a specified clock frequency. Timing analysis is present in various design flows, including front-end, mid-end, DFT, and back-end. Conventional timing analysis methods require designers to analyze the causes of timing violations line by line based on detailed timing path reports, which is inefficient. Furthermore, when there are many timing violations, designers often can only analyze a small subset of paths with significant violations, using the causes of violations in this subset as the causes of violations for the entire timing path group. This method cannot perform batch analysis, and the results are neither comprehensive nor accurate.

[0003] Therefore, there is an urgent need for a time series statistical method that can achieve batch analysis and improve the comprehensiveness and accuracy of the analysis results. Summary of the Invention

[0004] In view of this, the present invention provides a static time series statistical analysis system, method, computer device and storage medium to solve the problems of low efficiency, lack of comprehensiveness and low accuracy of time series statistical analysis in related technologies.

[0005] In a first aspect, the present invention provides a static time-series statistical analysis system, the static time-series statistical analysis system comprising:

[0006] The system includes a feature extraction subsystem and a statistical analysis subsystem; the feature extraction subsystem includes a first processing module and a second processing module; the statistical analysis subsystem includes a third processing module, a fourth processing module, and a fifth processing module.

[0007] The first processing module is configured to acquire input data; the input data includes a target database and a condition threshold, the target database includes time-series path information and physical location information stored in a corresponding relationship, the time-series path information includes time-series path groups and related information of time-series path groups, and a time-series path group includes multiple time-series paths; when the input data is acquired, filtering conditions are determined according to the condition threshold, and target time-series paths are determined according to the filtering conditions, the target time-series paths include: time-series paths in the target database that satisfy the filtering conditions;

[0008] The second processing module is configured to, when a target time-series path is determined according to the filtering conditions, extract target features from the target time-series path to obtain a target extraction result, and write the target extraction result into a time-series path feature source file; the target extraction result includes: target logical features, or, target logical features and target physical features; the time-series path feature source file includes feature values ​​of the target time-series path;

[0009] The third processing module is configured to determine the feature data of the target time-series path based on the time-series path feature source file;

[0010] The fourth processing module is configured to determine the violation timing path based on the feature data of the target timing path, generate a violation diagnosis report, and determine the timing path optimization strategy based on the violation diagnosis report.

[0011] The fifth processing module is configured to generate a statistical distribution table and a statistical distribution graph based on the feature data of the target time-series path and the violation diagnosis report.

[0012] In an optional implementation, when the condition thresholds include a first quantity, a first threshold, a second threshold, and a preset depth, the first processing module is specifically configured to determine a first condition based on the first quantity, a second condition based on the first threshold, and a third condition based on the second threshold; the first condition is that the total number of target time-series paths is less than or equal to the first quantity; the second condition is that the maximum margin in the target time-series paths is less than or equal to the first threshold; the third condition is that the minimum margin in the target time-series paths is greater than or equal to the second threshold; and the preset depth is used to classify the modules to which the start and end points of the target time-series paths belong.

[0013] In one optional implementation, the second processing module includes a feature extraction unit; the feature extraction unit is configured to extract logical features from the target time-series path to obtain target logical features, and to extract physical features from the target time-series path to obtain target physical features.

[0014] In one optional implementation, the feature extraction unit is specifically configured to extract logical features from the target time-series path to obtain target logical features, determine whether to extract physical features from the target time-series path, and, if it is determined that physical features should be extracted from the target time-series path, extract physical features from the target time-series path to obtain target physical features.

[0015] In one optional implementation, the fourth processing module includes a diagnostic report determination unit configured to generate a violation diagnostic report based on the name of the target feature in the violation time sequence path, the feature data of the violation time sequence path, and the violation cause determined based on the feature data of the violation time sequence path.

[0016] In an optional implementation, the fourth processing module further includes an optimization strategy determination unit. The optimization strategy determination unit is configured to read the violation diagnosis report, traverse the violation timing path, group the violation timing paths according to the starting module and ending module of the violation timing path to obtain at least one violation timing path group, determine the violation cause corresponding to each violation timing path group for each violation timing path group, determine whether the violation cause corresponding to the violation timing path group meets the preset conditions, and determine the timing path optimization strategy when the violation cause corresponding to the violation timing path group meets the preset conditions.

[0017] In one optional implementation, the statistical distribution table includes: a timing margin distribution table, a clock domain timing margin distribution table, a module timing margin distribution table, a path start point timing margin distribution table, a series distribution table, a combinational logic series distribution table, a unit series delay distribution table, a unit distance delay distribution table, a path length distribution table, a path redundancy ratio distribution table, and a crosstalk delay distribution table.

[0018] The statistical distribution charts include: timing margin distribution chart, timing margin cumulative distribution chart, series distribution chart, combinational logic series distribution chart, path group unit series delay distribution chart, path group unit distance delay distribution chart, unit series delay distribution chart, unit distance delay distribution chart, path length distribution chart, path redundancy ratio distribution chart, path group path redundancy ratio distribution chart, crosstalk delay distribution chart, path group crosstalk delay distribution chart, violation diagnosis distribution chart, and path group violation diagnosis distribution chart.

[0019] In a second aspect, the present invention provides a static time-series statistical analysis method, applied to a static time-series statistical analysis system of the first aspect above or any corresponding embodiment thereof, the static time-series statistical analysis method comprising:

[0020] The process involves acquiring input data, which includes a target database and conditional thresholds. The target database includes time-series path information and physical location information stored in a corresponding relationship. The time-series path information includes time-series path groups and related information of the time-series path groups. A time-series path group includes multiple time-series paths. Upon acquiring the input data, filtering conditions are determined based on the conditional thresholds, and target time-series paths are determined based on the filtering conditions. The target time-series paths include time-series paths in the target database that satisfy the filtering conditions.

[0021] When a target time-series path is determined according to the filtering conditions, target feature extraction is performed on the target time-series path to obtain target extraction results. When the target extraction results are obtained, the target extraction results are written into the time-series path feature source file. The target extraction results include: target logical features, or target logical features and target physical features. The time-series path feature source file includes the feature values ​​of the target time-series path.

[0022] The feature data of the target time-series path are determined based on the source file of the time-series path features.

[0023] Based on the characteristic data of the target time path, the violation time path is determined, a violation diagnosis report is generated, and the time path optimization strategy is determined based on the violation diagnosis report;

[0024] Statistical distribution tables and statistical distribution maps are generated based on the characteristic data of the target time sequence path and the violation diagnosis report.

[0025] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the static timing statistical analysis system of the second aspect above or any corresponding embodiment thereof.

[0026] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the static timing statistical analysis system of the second aspect or any corresponding embodiment described above.

[0027] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the static time-series statistical analysis system described in the first aspect or any corresponding embodiment thereof.

[0028] The technical solution provided by this invention has the following technical effects:

[0029] Based on the technical solution of this invention, the logical and physical characteristics of timing paths can be automatically extracted in large quantities, greatly improving the efficiency of timing analysis and providing a comprehensive data foundation for the overall timing analysis of the entire design and the overall timing analysis of timing path groups. This invention can automatically diagnose the causes of violations in a large number of timing paths. Compared with conventional timing analysis methods, this invention eliminates the need for designers to analyze each timing path individually. The automated diagnostic capability greatly improves the efficiency of timing analysis, and the analysis results are more comprehensive and reliable, thereby reducing the number of additional timing optimization iterations caused by incomplete single analyses. This invention can automatically generate timing path optimization strategies based on the causes of violations for designers to reference, improving the iteration speed of synthesis and physical design. Through automatically generated statistical distribution tables and graphs of a series of timing paths, this invention can perform statistical analysis on a large number of specified timing paths from different dimensions, comprehensively and quantitatively reflecting the statistical distribution characteristics of the logical and physical features of a large number of timing paths. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 This is a flowchart illustrating a conventional time series analysis method.

[0032] Figure 2 This is a structural block diagram of the static time-series statistical analysis system according to an embodiment of the present invention;

[0033] Figure 3 This is a structural block diagram of another static time-series statistical analysis system according to an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of the timing path optimization process according to an embodiment of the present invention;

[0035] Figure 5 This is a flowchart of the feature extraction subsystem according to an embodiment of the present invention;

[0036] Figure 6 This is a flowchart of the statistical analysis subsystem according to an embodiment of the present invention;

[0037] Figure 7 This is a flowchart illustrating the static time-series statistical analysis method according to an embodiment of the present invention;

[0038] Figure 8This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] like Figure 1 As shown, conventional time series analysis methods typically involve the following steps:

[0041] (1) Generate a summary report and a detailed report of timing violations. The summary report of timing violations typically includes information on the worst-case negative timing margin, the total negative timing margin, and the number of timing violation timing paths in the entire design, as well as information on the worst-case negative timing margin, the total negative timing margin, and the number of timing violation timing paths in each timing path group. Among these, grouping timing paths for analysis is a common method in timing analysis. This involves grouping the timing paths in the entire design according to the designer's preset rules, analyzing each group of timing paths separately, thereby achieving the effect of refining the granularity of timing analysis and making it easier for the designer to identify timing bottlenecks in the entire design. The detailed report of timing violations contains specific path information for each timing path group.

[0042] (2) By analyzing the timing violation summary report, identify the timing path group with poor timing violations.

[0043] (3) Analyze the detailed reports of timing path groups with poor timing violations. When there are many timing path violations, the detailed report often contains tens of thousands of timing path information. Designers often only analyze a small portion of the paths with larger timing violations to find out the reasons for their timing violations.

[0044] (4) Adjust the timing optimization strategy based on the timing violation reasons analyzed in step 3.

[0045] Conventional timing analysis methods require designers to analyze the causes of timing violations one by one based on detailed timing path reports, which is inefficient. Furthermore, when there are many timing violations, designers often can only analyze a small subset of paths with a large number of violations, using the causes of violations in this small subset as the causes of violations for the entire timing path group. This analysis method cannot achieve batch analysis, and the results are neither comprehensive nor accurate.

[0046] The main drawbacks of conventional time series analysis methods are as follows:

[0047] 1) Conventional timing analysis methods require designers to analyze the causes of timing violations one by one based on the detailed timing path reports, which is very inefficient. Furthermore, when there are many timing violations, designers can often only analyze a small subset of paths with a large number of violations, using the causes of violations in this small subset as the causes of violations for the entire timing path group. This analysis method cannot achieve batch analysis, and the results are neither comprehensive nor accurate.

[0048] 2) Although the timing path detail report contains detailed information about the timing path of each violation, it cannot intuitively reflect the distribution characteristics of timing violations. Therefore, it is difficult for designers to grasp the overall timing distribution of the entire module or path group through the timing path detail report.

[0049] 3) Timing violation summary reports and detailed reports typically only contain information about the timing paths of the violations. However, the distribution of timing paths with positive timing margins is also worth noting, as designers can use this information to identify opportunities to further optimize design frequency, area, and power consumption.

[0050] Therefore, embodiments of the present invention provide a static time series statistical analysis system, method, computer device, and storage medium to solve the above problems.

[0051] This invention provides a static time-series statistical analysis system for implementing the embodiments and optional implementations described below. As used herein, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the system described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0052] Figure 2 This is a structural block diagram of the static time series statistical analysis system according to an embodiment of the present invention.

[0053] like Figure 2 As shown, this embodiment of the invention provides a static time series statistical analysis system, which includes:

[0054] The system includes a feature extraction subsystem 1111 and a statistical analysis subsystem 1212. The feature extraction subsystem 1111 includes a first processing module 111111 and a second processing module 112112. The statistical analysis subsystem 1212 includes a third processing module 121121, a fourth processing module 122122, and a fifth processing module 123123.

[0055] The first processing module 111 is configured to acquire input data. The input data includes a target database and conditional thresholds. The target database includes time-series path information and physical location information stored in a correspondence relationship. The time-series path information includes time-series path groups and related information for each time-series path group; a time-series path group includes multiple time-series paths. Upon acquiring the input data, filtering conditions are determined based on the conditional thresholds, and target time-series paths are determined based on these filtering conditions. The target time-series paths include time-series paths in the target database that satisfy the filtering conditions.

[0056] The second processing module 112 is configured to, upon determining the target time-series path based on the filtering conditions, extract target features from the target time-series path to obtain target extraction results, and write these results into a time-series path feature source file. The target extraction results include: target logical features, or target logical features and target physical features. The time-series path feature source file includes the feature values ​​of the target time-series path.

[0057] The third processing module 121 is configured to determine the feature data of the target time path based on the time path feature source file.

[0058] The fourth processing module 122 is configured to determine the violation timing path based on the characteristic data of the target timing path, generate a violation diagnosis report, and determine the timing path optimization strategy based on the violation diagnosis report.

[0059] The fifth processing module 123 is configured to generate a statistical distribution table and a statistical distribution graph based on the characteristic data of the target time-series path and the violation diagnosis report.

[0060] For the first processing module 111:

[0061] The first processing module 111 is configured to acquire input data. The input data includes a target database and conditional thresholds. The target database includes time-series path information and physical location information stored in a correspondence relationship. The time-series path information includes time-series path groups and related information for each time-series path group; a time-series path group includes multiple time-series paths. Upon acquiring the input data, filtering conditions are determined based on the conditional thresholds, and target time-series paths are determined based on these filtering conditions. Target time-series paths include time-series paths in the target database that meet the filtering conditions. Related information for the time-series path groups includes necessary information for time-series analysis, such as parasitic resistance and capacitance values ​​and timing constraints.

[0062] In this embodiment, the target database is the input to the static timing statistical analysis system of the present invention. This static timing statistical analysis system can be applied to various stages of the mid-to-back-end design process, supporting databases from each stage as input, and can use databases from each stage of the mid-to-back-end design process as the target database. The mid-to-back-end design process includes the synthesis stage, physical design stage, and timing analysis stage. In the synthesis stage, the database of a synthesis EDA tool can be used as input; commonly used synthesis EDA tools include GENUS and DC. In the physical design stage, the database of a physical design EDA tool can be used as input; commonly used physical design tools include INNVOUS and ICC2. In the timing analysis stage, the database of a timing analysis EDA tool can be used as input; commonly used timing analysis tools include PrimeTime and Tempus.

[0063] In this embodiment, when the condition thresholds include a first quantity, a first threshold, a second threshold, and a preset depth, the first processing module 111 is specifically configured to determine a first condition based on the first quantity, a second condition based on the first threshold, and a third condition based on the second threshold. The first condition is that the total number of target time-series paths is less than or equal to the first quantity; the second condition is that the maximum margin in the target time-series paths is less than or equal to the first threshold; and the third condition is that the minimum margin in the target time-series paths is greater than or equal to the second threshold. The preset depth is used to delineate the starting and ending points of the target time-series paths.

[0064] In this embodiment, the first quantity refers to the maximum number of time-series paths. Designers can set and modify the upper limit of the number of time-series paths according to actual needs for feature extraction. As an example, the default upper limit is 1,000,000. The total number of target time-series paths is less than or equal to 1,000,000, indicating that feature extraction can be performed on a maximum of 1,000,000 time-series paths. The first threshold refers to the maximum margin of time-series paths. Designers can set and modify the maximum margin of time-series paths according to actual needs to limit the time-series paths participating in feature extraction. The default value is 0. The second threshold refers to the minimum margin of time-series paths. Designers can set and modify the minimum margin of time-series paths according to actual needs to limit the time-series paths participating in feature extraction. The first threshold and the second threshold refer to the slack value. The preset depth refers to the logical module depth. The preset depth is used to divide the modules to which the start and end points of the time-series paths belong, determining the granularity of the module division. The larger the preset depth, the finer the granularity of the module division.

[0065] In this embodiment, users or designers can set different condition thresholds according to actual needs and input these thresholds into the static time series statistical analysis system. The first processing module 111 can obtain input data based on the user's or designer's input. Specifically, data input can be achieved through a visual interface, either by importing a table or by filling in the condition thresholds in the visual interface.

[0066] In this embodiment, the first processing module 111 can perform time-series path filtering. When the input data is obtained, it automatically traverses the target database according to the filtering conditions (the first condition corresponding to the first quantity, the second condition corresponding to the first threshold, the third condition corresponding to the second threshold, and the preset depth) to filter out the target time-series paths in the target database that meet the filtering conditions.

[0067] Regarding the second processing module 112:

[0068] The second processing module 112 is configured to, upon determining the target time-series path based on the filtering conditions, extract target features from the target time-series path to obtain target extraction results, and write these results into a time-series path feature source file. The target extraction results include: target logical features, or target logical features and target physical features. The time-series path feature source file includes the feature values ​​of the target time-series path.

[0069] like Figure 3 As shown, in this invention, the second processing module 112 includes a feature extraction unit 1121. The feature extraction unit 1121 is configured to extract logical features from the target temporal path to obtain target logical features, and to extract physical features from the target temporal path to obtain target physical features.

[0070] The feature extraction unit 1121 is specifically configured to extract logical features from the target time-series path to obtain target logical features, determine whether to extract physical features from the target time-series path, and extract physical features from the target time-series path to obtain target physical features when it is determined that physical features should be extracted from the target time-series path.

[0071] If the static time series statistical analysis system does not require physical feature extraction, the target database only includes time series path information and does not include physical location information. The corresponding feature extraction unit 1121 does not need to determine whether to extract physical features from the target time series path, and does not need to extract physical features from the target time series path to obtain target physical features.

[0072] In this embodiment, the target extraction result specifically includes target logical features, or target logical features and target physical features. The feature extraction unit 1121 includes a logical feature extraction subunit (specifically a logical feature extractor) and a physical feature extraction subunit (specifically a physical feature extractor). The logical feature extraction subunit can specifically be a logical feature extractor. The logical feature extractor automatically extracts logical features from the target time-series path selected by the first processing module 111 to obtain the target logical features. The extracted target logic features include the timing margin, preceding timing margin, following timing margin, data path level, data path combinational logic level, data path delay, data path crosstalk delay, data path unit delay, data path line delay, data path unit level delay, starting clock, ending clock, clock skew, starting clock delay, ending clock delay, clock path pessimism removal value, timing path starting point, timing path ending point, timing path starting module, timing path ending module, timing path group to which the timing path belongs, timing path mode and process corner, timing path check synchronous / asynchronous type, timing path ending setup / hold time, and additional constraints of the timing path.

[0073] In this embodiment, the designer can control whether the feature extraction subsystem 11 performs physical feature extraction on the target temporal path as needed. When it is determined that physical feature extraction will be performed on the target temporal path, the physical feature extraction subunit is started. The physical feature extraction subunit is configured to extract physical features from the target temporal path to obtain target physical features after it is started. The extracted target physical features include the Manhattan distance between the start and end points of the target temporal path, the cumulative Manhattan distance of the target temporal path, etc.

[0074] In this invention, the second processing module 112 further includes a source file generation unit 1122, which is configured to write the target extraction result into a time-series path feature source file when the target extraction result is obtained, thereby realizing the automatic generation of the time-series path feature source file. As an example, the time-series path feature source file adopts CSV format, and the time-series path feature source file contains the feature values ​​of each feature of all analyzed time-series paths.

[0075] Regarding the third processing module 121:

[0076] The third processing module 121 is configured to determine the feature data of the target time path based on the time path feature source file.

[0077] In this embodiment, the third processing module 121 is specifically configured to read the timing path feature source file, load the timing path feature source file into memory, and generate a two-dimensional data structure, which, as an example, is a matrix. Other feature values ​​are calculated based on the feature values ​​of each target timing path in the timing path feature source file, including the number of driving unit levels of the data path, the data path redundancy ratio, the average latency per unit level, and the average latency per unit distance. Based on the feature values ​​of the target timing paths and the inferred other feature values, the complete feature data of the target timing paths is summarized in memory.

[0078] The fourth processing module 122 is configured to determine the violation timing path based on the characteristic data of the target timing path, generate a violation diagnosis report, and determine the timing path optimization strategy based on the violation diagnosis report.

[0079] like Figure 3 As shown, in this invention, the fourth processing module 122 includes a diagnostic report determination unit 1221, which is configured to generate a violation diagnostic report based on the name of the target feature in the violation time sequence path, the feature data of the violation time sequence path, and the violation cause determined based on the feature data of the violation time sequence path.

[0080] The diagnostic report determination unit 1221 automatically writes the violation timing paths in memory into the violation diagnostic report. This invention can use an Excel file as the violation diagnostic report format. The first line of the violation diagnostic report is the name of each feature, including the features in the feature source file, the inferred features, and the reason for the violation. Starting from the second line, the violation diagnostic report lists the feature values ​​corresponding to each violation timing path. The feature name row automatically includes a filtering function, supporting filtering and viewing one or more columns of features, facilitating more detailed timing analysis by designers.

[0081] In this embodiment, the diagnostic report determination unit 1221 is further configured to perform batch violation diagnosis based on the feature data of the target time-series path according to automatic diagnostic rules to determine the violation time-series path. Specifically, a time-series path violation diagnostic tool can be developed based on the automatic diagnostic rules. The violation time-series path is determined by performing diagnosis through the time-series path violation diagnostic tool.

[0082] Static timing analysis involves analyzing all possible timing paths in a circuit, calculating signal propagation delays, and checking if they meet timing constraints. Among various timing constraints, setup and hold times are typically the most important to chip designers. As an example, a "virtual optimization weighted algorithm" can be used to diagnose violations related to setup and hold times. The rules for automatic diagnosis of setup and hold times are as follows:

[0083] For violation diagnosis during setup time, firstly, virtual optimization condition trigger values ​​are calculated based on the characteristic data of each target time-series path. These virtual optimization condition trigger values ​​are then used to determine whether a feature is a potential violation cause. Finally, virtual optimization time-series margin is calculated for each potential violation cause. The specific calculation method is as follows:

[0084] Diagnostic requirements for combinational logic series:

[0085] Virtual optimization condition trigger value calculation formula: k1 = L combo -Lth combo .

[0086] Where k1 represents the virtual optimization condition trigger value during combinational logic level diagnosis, and L combo Lth represents the combinational logic series. combo This indicates a preset threshold for the combinational logic level. Virtual optimization calculation is triggered when k1>0.

[0087] Virtual optimization timing margin calculation formula: Δ 1slack =D avg *k1*ε1.

[0088] Where, Δ 1slack D represents the virtual optimization timing margin. avg ε1 represents the average delay per stage of the current timing path, and ε1 represents the virtual optimization weight coefficient of the combinational logic stages.

[0089] Diagnostic requirements for drive unit level:

[0090] Virtual optimization condition trigger value calculation formula: k2 = L repeater -Lth repeater .

[0091] Where k2 represents the virtual optimization condition trigger value during the stage diagnosis of the drive unit, L repeater Lth represents the number of drive unit levels. repeater This indicates the preset threshold for the number of driving unit levels. Virtual optimization calculation is triggered when k2>0.

[0092] Virtual optimization timing margin calculation formula: Δ 2slack =D avg *k2*ε2.

[0093] Where, Δ 2slack D represents the virtual optimization timing margin. avg ε1 represents the average delay per stage of the current timing path, and ε2 represents the virtual optimization weight coefficient of the driving unit stage.

[0094] For unit series delay diagnosis:

[0095] Virtual optimization condition trigger value calculation formula: k3 = Davg -Dth avg .

[0096] Where k3 represents the virtual optimization condition trigger value during unit-level delay diagnosis, D avg Dth represents the average delay per stage of the current timing path. avg This indicates a preset unit level delay threshold, which triggers virtual optimization calculations when k3>0.

[0097] Virtual optimization timing margin calculation formula: Δ 3slack =k3*L*ε3.

[0098] Where, Δ 3slack ε3 represents the virtual optimization timing margin, L represents the number of stages in the current data path, and ε3 represents the virtual optimization weight coefficient per unit stage delay.

[0099] For crosstalk delay diagnosis:

[0100] Virtual optimization condition trigger value calculation formula: k4 = D si -D path *α th .

[0101] Where k4 represents the virtual optimization condition trigger value during crosstalk delay diagnosis, and D si D represents the total crosstalk delay of the current data path. path α represents the total latency of the current data path. th This represents the preset crosstalk threshold ratio. Virtual optimization calculation is triggered when k4 > 0.

[0102] Virtual optimization timing margin calculation formula: Δ 4slack =k4*ε4.

[0103] Where, Δ 4slack ε4 represents the virtual optimization timing margin, and ε4 represents the virtual optimization weight coefficient for crosstalk delay.

[0104] Diagnostic for data path redundancy:

[0105] Virtual optimization condition trigger value calculation formula: k5 = P ac -P se *β th .

[0106] Where k5 represents the virtual optimization condition trigger value during data path redundancy diagnosis, P ac P represents the cumulative Manhattan distance of the current data path. se β represents the Manhattan distance between the start and end points of the current time-series path. th This represents the preset path redundancy threshold ratio. Virtual optimization calculation is triggered when k5 > 0.

[0107] Virtual optimization timing margin calculation formula: Δ 5slack =k5*D avgd *ε5.

[0108] Where, Δ 5slack D represents the virtual optimization timing margin. avgd ε5 represents the unit distance delay of the current data path, and ε5 represents the virtual optimization weight coefficient for the lengthy data path.

[0109] Diagnostic requirements for setup time:

[0110] Virtual optimization condition trigger value calculation formula: k6 = T setup -T th .

[0111] Where k6 represents the virtual optimization condition trigger value when establishing time-based diagnostics, T setup T represents the establishment time of the current time-series path endpoint. th This represents the preset setup time threshold. Virtual optimization calculations are triggered when k6 > 0.

[0112] Virtual optimization timing margin calculation formula: Δ 6slack =k6*ε6.

[0113] Where, Δ 6slack ε represents the virtual optimization timing margin, and ε6 represents the virtual optimization weight coefficient for setup time.

[0114] Diagnostic requirements for additional constraints:

[0115] Virtual optimization condition trigger value calculation formula: k7 = CC th .

[0116] Where k7 represents the virtual optimization condition trigger value during additional constraint diagnosis, and C represents the additional constraint value of the current timing path. th This represents the preset additional constraint threshold. Virtual optimization calculation is triggered when k7 > 0.

[0117] Virtual optimization timing margin calculation formula: Δ 7slack =k7*ε7.

[0118] Where, Δ 7slack ε7 represents the virtual optimization timing margin, and ε7 represents the virtual optimization weight coefficient of the additional constraints.

[0119] For diagnosing clock skew:

[0120] Virtual optimization condition trigger value calculation formula: k8 = SS th .

[0121] Where k8 represents the virtual optimization condition trigger value during clock skew diagnosis, and S represents the clock skew value of the current timing path. th This represents the preset clock skew threshold. Virtual optimization calculations are triggered when k8 > 0.

[0122] Virtual optimization timing margin calculation formula: Δ 8slack =min(k8,(M+N)*τ)*ε8.

[0123] Where, Δ 8slack ε₀ represents the virtual optimized timing margin, M represents the positive timing margin of the next-level timing path of the current timing path, N represents the positive timing margin of the previous-level timing path of the current timing path, τ represents the built-in timing margin coefficient of the system, and ε₀ represents the virtual optimized weight coefficient of clock skew.

[0124] Based on the type of input database and the type of diagnostic features, the system automatically assigns appropriate virtual optimization weight coefficients to each feature, as shown in Table 1.

[0125] Table 1 Virtual Optimization Weight Coefficient ε Value

[0126] comprehensive Physical Design Time series analysis Combinational Logic Series 0.9 0.8 0.4 number of drive unit stages 0.6 0.9 0.6 Unit series delay 0.7 0.8 0.8 Crosstalk delay N / A 0.7 0.8 Long data path 0.5 0.9 0.6 Establishment time 0.7 0.6 0.8 Additional constraints 0.3 0.3 0.7 Clock tilt N / A 0.8 0.8

[0127] After calculating the virtual optimization timing margin for each feature that triggers virtual optimization, the system automatically finds the timing violation cause corresponding to the largest virtual optimization timing margin as the main violation cause of the timing violation path. At the same time, the system automatically adds a "violation cause" feature to the timing violation path and uses the specific violation cause as the feature value of the feature.

[0128] Regarding the fourth processing module 122:

[0129] The fourth processing module 122 also includes an optimization strategy determination unit 1222. The optimization strategy determination unit 1222 is configured to read the violation diagnosis report, traverse the violation timing paths, group them according to the starting and ending modules of the violation timing paths to obtain at least one violation timing path group, determine the violation cause corresponding to each violation timing path group for each group, determine whether the violation cause corresponding to the individual violation timing path group meets preset conditions, and determine the timing path optimization strategy when the violation cause corresponding to the individual violation timing path group meets the preset conditions. The timing path optimization strategy is used for further comprehensive optimization or physical design optimization.

[0130] The optimization strategy determination unit 1222 can be configured to automatically traverse all violation timing paths. Preset conditions include: the violation cause of the violation timing path group is found to have triggered the preset optimization strategy by querying the timing path optimization scheme comparison table shown in Table 2; and the absolute value of the worst negative timing margin of the violation timing path group is less than the clock cycle (timing constraint) involved in the violation. If the violation cause corresponding to the violation timing path group meets the preset conditions, a timing path optimization strategy is generated, including setting a high optimization intensity and an appropriate optimization weight for the violation timing path group. The calculation formula for the optimization weight is as follows: ω = 10 - [T] worst / 0.015].

[0131] Among them, T worst It is the worst negative timing margin for this violation timing path group.

[0132] If the absolute value of the worst negative timing margin in the violation timing path group is not less than the clock cycle involved in the violation, the system will list the violation timing paths and prompt the designer that the negative timing margin of the violation timing path is too large, and the designer needs to pay attention to whether there are unreasonable timing constraints or other reasons.

[0133] After generating a timing path optimization strategy corresponding to a violation timing path group, the optimization strategy determination unit 1222 can also generate timing path optimization strategies corresponding to other violation timing path groups based on the violation cause of each violation timing path in the group, according to Table 2. The specific scheme is as follows:

[0134] Reduce timing over-constraints: Based on the current additional constraints of the violation timing path, the system automatically calculates the optimized additional constraint value. The formula for calculating the reduction in additional constraints is as follows: Δ c =CC th .

[0135] Among them, C and C th These are the additional constraint values ​​for the current timeline path and the preset additional constraint thresholds, respectively.

[0136] Optimize clock skew: Based on the current negative timing margin of the violation timing path and the timing margins of its predecessor and successor stages, the system automatically calculates the optimization amount for the starting and ending clock paths. The calculation formula for the ending clock path optimization amount is as follows: Φ e =min(|T slack |,M*τ).

[0137] Where M is the positive timing margin of the next-level timing path of the current timing path, and τ is the built-in timing margin coefficient of the system.

[0138] When |T slack When |> M*τ, the system continues to calculate the starting clock path optimization amount, and the calculation formula is as follows:

[0139] Φ s =min(|T slack |-M*τ,N*τ).

[0140] Where N is the positive timing margin of the previous timing path of the current timing path.

[0141] Optimize transition time: When the cause of the violation is unit-level delay, crosstalk delay, or setup time, the system prompts the designer to pay attention to the optimization of transition time and summarizes the timing paths of the violations that need to be optimized for transition time.

[0142] Timing path overreduction: This optimization scheme is typically used to address timing consistency issues between different design phases and different tools. The system automatically generates a timing path overreduction script based on the negative timing margin of the current timing path, where the overreduction value is calculated using the following formula: δ = T r -T slack .

[0143] Among them, T r T represents the timing margin of the current path in the implementation tool. slack This represents the timing margin of the current path.

[0144] Table 2 Comparison of Timing Path Optimization Schemes

[0145]

[0146] As shown in Table 2, the system's built-in preset optimization strategies are mainly divided into five types: optimizing timing path groups, timing path over-reduction, reducing timing over-reduction, optimizing clock skew, and optimizing transition time. Specifically, when the violation is caused by one of the following reasons: combinational logic levels, driver unit levels, single-level delay, crosstalk delay, or data path redundancy, optimization of timing path groups and timing path over-reduction schemes will be triggered. When the violation is caused by additional constraints, reduction of timing over-reduction schemes will be triggered. When the violation is caused by clock skew, optimization of clock skew schemes will be triggered. When the violation is caused by one of the following reasons: single-level delay, crosstalk delay, or setup time, optimization of transition time schemes will be triggered.

[0147] like Figure 4As shown, the optimization strategy determination unit first reads the violation diagnosis report, automatically traverses all violation timing paths, and groups the violation timing paths according to the starting module and the ending module. Then, it takes the union of the violation causes in each violation timing path group to obtain the violation causes involved in that group of violation timing paths. Next, the optimization strategy determination unit calculates whether the violation timing path group meets the preset conditions. Meeting the preset conditions indicates that the preset optimization strategy has been triggered, and the absolute value of the worst negative timing margin of the violation timing path group is less than the clock cycle involved in the violation. When the preset conditions are met, the unit generates the timing path optimization strategy corresponding to the violation timing path group, as well as the timing path optimization strategies corresponding to other violation timing path groups. When the preset conditions are not met, the unit determines whether the timing constraint settings are reasonable. If the timing constraint settings are determined to be unreasonable, the unit adjusts the timing constraints (e.g., adjusts the clock cycle involved in the violation) or optimizes the design (e.g., circuit structure), and re-determines whether the adjusted preset conditions are met.

[0148] Regarding the fifth processing module 123:

[0149] The fifth processing module 123 is configured to generate a statistical distribution table and a statistical distribution graph based on the characteristic data of the target time-series path and the violation diagnosis report.

[0150] In this embodiment, the statistical distribution tables include: timing margin distribution table, clock domain timing margin distribution table, module timing margin distribution table, path start point timing margin distribution table, series distribution table, combinational logic series distribution table, unit series delay distribution table, unit distance delay distribution table, path length distribution table, path redundancy ratio distribution table, and crosstalk delay distribution table.

[0151] In this embodiment, the fifth processing module 123 includes a distribution table generation unit 1231 and a distribution graph generation unit 1232. Specifically, the distribution table generation unit 1231 can be a system-built-in statistical distribution table generator, which automatically generates a series of statistical distribution tables. The distribution graph generation unit 1232 can be a system-built-in statistical distribution graph generator, which automatically generates a series of statistical distribution graphs. These statistical distribution graphs include timing margin distribution graphs, timing margin cumulative distribution graphs, series distribution graphs, combinational logic series distribution graphs, path group unit series delay distribution graphs, path group unit distance delay distribution graphs, unit series delay distribution graphs, unit distance delay distribution graphs, path length distribution graphs, path redundancy ratio distribution graphs, path group path redundancy ratio distribution graphs, crosstalk delay distribution graphs, path group crosstalk delay distribution graphs, violation diagnosis distribution graphs, and path group violation diagnosis distribution graphs, etc. The statistical distribution graphs generated by this invention can be displayed in the form of histograms, stacked histograms, and pie charts, which can more intuitively reflect the overall distribution characteristics of timing paths and the distribution characteristics of timing path groups.

[0152] The functions of the statistical distribution table generator and the statistical distribution plot generator are implemented by script programs. It should be noted that the script programs are written by developers according to system requirements, and can be automatically executed code segments stored in the system in advance. They can be configured according to actual conditions, and this embodiment does not impose specific limitations on them. The statistical distribution plot generator can be configured with different drawing algorithms for display methods such as histograms, stacked histograms, and pie charts.

[0153] The algorithm for drawing histograms is as follows: The statistical distribution plot generator generates a feature data list based on the feature data of the target time-series path and the path features to be drawn. The binning algorithm is used to calculate the appropriate distribution intervals using the data in the feature data list. Then, for each distribution interval, the number of values ​​in the feature data list that fall into that distribution interval is calculated to form a distribution value list. Finally, the distribution value list is used to draw the histogram and mark the coordinate axes.

[0154] The algorithm for drawing a stacked histogram is as follows: A statistical distribution plot generator generates a feature data list and a grouped feature data dictionary based on the feature data of the target time-series path and the path features to be plotted. The key of the dictionary is the group name, and the value is the feature data list corresponding to that group. Next, the generator uses a binning algorithm to calculate suitable distribution intervals based on the data in the feature data list. Then, for each distribution interval, it calculates the number of values ​​from each group's feature data list that fall within that interval, forming a distribution value dictionary. The key of this dictionary is the group name, and the value is the number of distribution values ​​for that group within that interval. The generator then randomly assigns a color to each group. Finally, the distribution value dictionary is used to draw the stacked histogram and label the axes.

[0155] The pie chart drawing algorithm is as follows: The statistical distribution chart generator generates a feature data list based on the feature data of the target time-series path and the path features to be drawn. Then, it calculates the frequency of occurrence of the same data in the feature data list, generating a data frequency dictionary. The keys of the dictionary are data, and the values ​​are the frequencies of that data. The generator then calculates the optimal arrangement of pie chart blocks based on the frequencies of each data point and randomly assigns a color to each data point. Finally, it uses the data frequency dictionary to draw the pie chart and add markers.

[0156] The flowchart of the feature extraction subsystem 11 is as follows: Figure 5 As shown, the flowchart of the statistical analysis subsystem 12 is as follows: Figure 6 As shown. Figure 5 As shown, when the input data includes one or more specified time-series path groups, the target features of the one or more specified time-series path groups in the input data are extracted. If not specified, the present invention will analyze all time-series path groups in the target database.

[0157] The static timing statistical analysis system in this embodiment is presented in the form of functional units. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0158] This invention provides an automated static time series statistical analysis system. Compared with conventional time series analysis methods, this invention mainly has the following characteristics:

[0159] 1) The present invention can automatically extract logical and physical features of timing paths in large quantities through the built-in feature extraction subsystem 11, and calculate other features, such as logical and physical features, through the automatic timing path feature inference method. This can greatly improve the efficiency of timing analysis and provide a comprehensive data foundation for the overall timing analysis of the entire design and the overall timing analysis of the timing path group.

[0160] 2) This invention can automatically diagnose the causes of violations in a large number of timing paths through its built-in timing path violation diagnostic tool. Compared with conventional timing analysis methods, this invention eliminates the need for designers to analyze each timing path individually. The automated diagnostic capability greatly improves the efficiency of timing analysis, and the analysis results are more comprehensive and reliable, thereby reducing the number of additional timing optimization iterations caused by incomplete analysis in a single instance.

[0161] 3) This invention can automatically generate timing path optimization strategies based on violation diagnosis reports. Designers can directly use or refer to these timing path optimization strategies for further optimization.

[0162] 4) This invention automatically generates a series of statistical distribution tables through a built-in statistical distribution table generator, and performs statistical analysis on a large number of time-series paths from different dimensions, comprehensively and quantitatively reflecting the statistical distribution characteristics of the logical and physical features of a large number of time-series paths.

[0163] 5) This invention automatically generates a series of statistical distribution maps through a built-in statistical distribution map generator, performs statistical analysis on a large number of specified time-series paths from different dimensions, and can more intuitively and in detail reflect the statistical distribution characteristics of the logical and physical features of the entire design and each time-series path group.

[0164] 6) The static time series statistical analysis system of the present invention can extract features from the databases of various EDA tools in the middle and back end, and can be applied to time series analysis work in various stages of the middle and back end process.

[0165] 7) The static timing statistical analysis system of this invention is not limited to analyzing timing paths with violations. It can perform batch statistical analysis on timing paths with any timing margin range according to the designer's needs. It can not only help designers quickly converge timing, but also provide an important data foundation for further improving the chip's key indicators PPA (Performance, Power, Area).

[0166] It should be noted that the logical and physical features extracted in the above embodiments are only some examples listed, and the extraction of other features for statistical analysis should also be within the scope of protection of this invention.

[0167] The various statistical distribution tables and graphs generated in the above embodiments are only some examples. The generation of statistical distribution tables and graphs with other content or other formats should also be within the protection scope of this invention.

[0168] The time-series path feature source file generated by this invention uses CSV format, but other file formats that can achieve the same purpose are also within the scope of protection of this invention.

[0169] The violation diagnosis report generated by this invention uses Excel format, but other file formats that can achieve the same purpose are also within the scope of protection of this invention.

[0170] In the above embodiments, the description of the automatic timing path diagnosis section uses the establishment of timing violations as an example for illustration. The present invention can also be applied to the analysis of holding timing violations and asynchronous timing violations, and should also fall within the protection scope of the present invention.

[0171] The diagnostic rules of the automatic timing path diagnostic tool mentioned in this invention are only some examples. Using other standards or rules for diagnosis should also fall within the protection scope of this invention.

[0172] Key technical points of the present invention:

[0173] This invention provides an automated static time series statistical analysis system. Unlike conventional time series analysis methods, this invention uses a combination of statistical analysis and data visualization to achieve a more comprehensive and intuitive analysis of a large number of time series paths.

[0174] This invention can automatically extract logical and physical features of timing paths in large quantities, and calculate other logical and physical features through an automatic timing path feature inference method, which can greatly improve the efficiency of timing analysis.

[0175] This invention can automatically diagnose the causes of violations in a large number of timing paths without requiring designers to analyze each timing path individually, thus greatly improving the efficiency of timing analysis.

[0176] This invention automatically generates statistical distribution tables and statistical distribution graphs, and performs statistical analysis on a large number of time-series paths from multiple dimensions through the statistical tables and statistical graphs, quantitatively and intuitively representing the overall statistical distribution characteristics of time-series paths and the statistical distribution characteristics of time-series path groups.

[0177] This invention can be applied to time-series analysis at various stages of mid-to-back-end processes. The feature extraction subsystem 11 and statistical analysis subsystem 12 possess strong scalability. The built-in feature extraction subsystem 11 takes the databases of each stage as input, automatically extracts the logical and physical features of the time-series path, generates a time-series path feature source file, and then inputs it into the statistical analysis subsystem 12. The statistical analysis subsystem 12 takes the time-series path feature source file as input, automatically performs batch diagnostics and statistical analysis on the time-series path, and generates violation diagnosis reports, time-series path optimization strategies, and a series of multi-dimensional statistical distribution tables and graphs.

[0178] This invention is not limited to analyzing paths with timing violations; it can analyze the timing of any specified timing margin range and timing path group as needed.

[0179] It should be noted that the contents not described in detail in this specification are common knowledge to those skilled in the art.

[0180] This invention provides an embodiment of a static time series statistical analysis method. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0181] Figure 7 This is a flowchart illustrating the static time series statistical analysis method according to an embodiment of the present invention.

[0182] like Figure 7 As shown, this embodiment of the invention provides a static time series statistical analysis method, which includes:

[0183] S101: Obtain input data.

[0184] In this embodiment, the input data includes a target database and a condition threshold. The target database includes time-series path information and physical location information stored in a correspondence relationship. The time-series path information includes time-series path groups and related information of time-series path groups. A time-series path group includes multiple time-series paths.

[0185] S102: When the input data is obtained, the filtering conditions are determined according to the condition threshold, and the target time sequence path is determined according to the filtering conditions.

[0186] In this embodiment, the target time-series path includes: time-series paths in the target database that meet the filtering criteria.

[0187] S103: When the target time-series path is determined according to the screening conditions, target features are extracted from the target time-series path to obtain the target extraction result. When the target extraction result is obtained, the target extraction result is written into the time-series path feature source file.

[0188] In this embodiment, the target extraction result includes: target logical features, or target logical features and target physical features. The temporal path feature source file includes feature values ​​of the target temporal path.

[0189] S104: Determine the feature data of the target time path based on the time path feature source file.

[0190] S105: Determine the violation timing path based on the characteristic data of the target timing path, generate a violation diagnosis report, and determine the timing path optimization strategy based on the violation diagnosis report.

[0191] S106: Generate a statistical distribution table and a statistical distribution graph based on the characteristic data of the target time sequence path and the violation diagnosis report.

[0192] In an optional implementation, when the condition threshold includes a first quantity, a first threshold, a second threshold, and a preset depth, determining the filtering conditions based on the condition threshold in step S102 specifically includes:

[0193] The first condition is determined based on a first quantity, the second condition is determined based on a first threshold, and the third condition is determined based on the second threshold. The first condition is that the total number of target time-series paths is less than or equal to the first quantity. The second condition is that the maximum margin in the target time-series paths is less than or equal to the first threshold. The third condition is that the minimum margin in the target time-series paths is greater than or equal to the second threshold. A preset depth is used to delineate the modules to which the start and end points of the target time-series paths belong.

[0194] In an optional implementation, the target feature extraction in step S103 to obtain the target extraction result from the target temporal path specifically includes:

[0195] Logical features are extracted from the target time-series path to obtain target logical features, and physical features are extracted from the target time-series path to obtain target physical features.

[0196] In an optional implementation, step S103, which involves extracting target features from the target temporal path to obtain the target extraction result, further includes:

[0197] Logical features are extracted from the target time-series path to obtain target logical features. It is then determined whether physical features should be extracted from the target time-series path. If it is determined that physical features should be extracted from the target time-series path, physical features are extracted from the target time-series path to obtain target physical features.

[0198] In one optional implementation, generating the violation diagnosis report in S105 specifically includes:

[0199] A violation diagnosis report is generated based on the name of the target feature in the violation time sequence path, the feature data of the violation time sequence path, and the violation cause determined based on the feature data of the violation time sequence path.

[0200] In one optional implementation, determining the timing path optimization strategy based on the violation diagnosis report in step S105 specifically includes:

[0201] Read the violation diagnosis report, traverse the violation timing path, group the violation timing path according to the starting module and ending module, and obtain at least one violation timing path group. For each violation timing path group, determine the violation cause corresponding to the individual violation timing path group. Determine whether the violation cause corresponding to the individual violation timing path group meets the preset conditions. When the violation cause corresponding to the individual violation timing path group meets the preset conditions, determine the timing path optimization strategy.

[0202] In one optional implementation, the statistical distribution table includes: a timing margin distribution table, a clock domain timing margin distribution table, a module timing margin distribution table, a path start point timing margin distribution table, a series distribution table, a combinational logic series distribution table, a unit series delay distribution table, a unit distance delay distribution table, a path length distribution table, a path redundancy ratio distribution table, and a crosstalk delay distribution table.

[0203] In one optional implementation, the statistical distribution chart includes: timing margin distribution chart, timing margin cumulative distribution chart, series distribution chart, combinational logic series distribution chart, path group unit series delay distribution chart, path group unit distance delay distribution chart, unit series delay distribution chart, unit distance delay distribution chart, path length distribution chart, path redundancy ratio distribution chart, path group path redundancy ratio distribution chart, crosstalk delay distribution chart, path group crosstalk delay distribution chart, violation diagnosis distribution chart, and path group violation diagnosis distribution chart.

[0204] This invention also provides a computer device having the above-described features. Figure 2 The static time series statistical analysis system shown.

[0205] Please see Figure 8 , Figure 8 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention, such as... Figure 8As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In an alternative implementation, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 8 Take a processor 10 as an example.

[0206] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0207] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0208] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function. The data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In an alternative embodiment, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0209] Memory 20 may include volatile memory, such as random access memory. Memory may also include non-volatile memory, such as flash memory, hard disk, or solid-state drive. Memory 20 may also include combinations of the above types of memory.

[0210] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0211] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc. Further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0212] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0213] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A static time-series statistical analysis system, characterized in that, include: A feature extraction subsystem and a statistical analysis subsystem; the feature extraction subsystem includes a first processing module and a second processing module; The statistical analysis subsystem includes a third processing module, a fourth processing module, and a fifth processing module; The first processing module is configured to acquire input data; the input data includes a target database and a condition threshold, the target database includes time-series path information and physical location information stored in a corresponding relationship, the time-series path information includes time-series path groups and related information of time-series path groups, and a time-series path group includes multiple time-series paths; when the input data is acquired, filtering conditions are determined according to the condition threshold, and target time-series paths are determined according to the filtering conditions, the target time-series paths include: time-series paths in the target database that satisfy the filtering conditions; The second processing module is configured to, when a target time-series path is determined according to the filtering conditions, extract target features from the target time-series path to obtain a target extraction result, and write the target extraction result into a time-series path feature source file; the target extraction result includes: target logical features, or, target logical features and target physical features; the time-series path feature source file includes feature values ​​of the target time-series path; The third processing module is configured to determine the feature data of the target time-series path based on the time-series path feature source file; The fourth processing module is configured to determine the violation timing path based on the feature data of the target timing path, generate a violation diagnosis report, and determine the timing path optimization strategy based on the violation diagnosis report. The fifth processing module is configured to generate a statistical distribution table and a statistical distribution graph based on the feature data of the target time-series path and the violation diagnosis report.

2. The system according to claim 1, characterized in that, When the condition thresholds include a first quantity, a first threshold, a second threshold, and a preset depth, the first processing module is specifically configured to determine a first condition based on the first quantity, a second condition based on the first threshold, and a third condition based on the second threshold; the first condition is that the total number of target time-series paths is less than or equal to the first quantity, and the second condition is that the maximum margin in the target time-series paths is less than or equal to the first threshold. The third condition is that the minimum margin in the target time-series path is greater than or equal to the second threshold; the preset depth is used to divide the modules to which the start and end points of the target time-series path belong.

3. The system according to claim 1, characterized in that, The second processing module includes a feature extraction unit; The feature extraction unit is configured to extract logical features from the target time-series path to obtain target logical features, and to extract physical features from the target time-series path to obtain target physical features.

4. The system according to claim 3, characterized in that, The feature extraction unit is specifically configured to extract logical features from the target time-series path to obtain target logical features, determine whether to extract physical features from the target time-series path, and extract physical features from the target time-series path to obtain target physical features when it is determined that physical features should be extracted from the target time-series path.

5. The system according to claim 1, characterized in that, The fourth processing module includes a diagnostic report determination unit, which is configured to generate a violation diagnostic report based on the name of the target feature in the violation time sequence path, the feature data of the violation time sequence path, and the violation cause determined based on the feature data of the violation time sequence path.

6. The system according to claim 1, characterized in that, The fourth processing module further includes an optimization strategy determination unit. The optimization strategy determination unit is configured to read the violation diagnosis report, traverse the violation timing path, group the violation timing paths according to the starting module and ending module of the violation timing path to obtain at least one violation timing path group, determine the violation cause corresponding to each violation timing path group for each violation timing path group, determine whether the violation cause corresponding to the violation timing path group meets the preset conditions, and determine the timing path optimization strategy when the violation cause corresponding to the violation timing path group meets the preset conditions.

7. The system according to claim 1, characterized in that, The statistical distribution tables include: timing margin distribution table, clock domain timing margin distribution table, module timing margin distribution table, path start point timing margin distribution table, series distribution table, combinational logic series distribution table, unit series delay distribution table, unit distance delay distribution table, path length distribution table, path redundancy ratio distribution table, and crosstalk delay distribution table. The statistical distribution charts include: timing margin distribution chart, timing margin cumulative distribution chart, series distribution chart, combinational logic series distribution chart, path group unit series delay distribution chart, path group unit distance delay distribution chart, unit series delay distribution chart, unit distance delay distribution chart, path length distribution chart, path redundancy ratio distribution chart, path group path redundancy ratio distribution chart, crosstalk delay distribution chart, path group crosstalk delay distribution chart, violation diagnosis distribution chart, and path group violation diagnosis distribution chart.

8. A static time series statistical analysis method, characterized in that, The static time series statistical analysis method, applied to the system as described in any one of claims 1 to 7, comprises: The process involves acquiring input data, which includes a target database and conditional thresholds. The target database includes time-series path information and physical location information stored in a corresponding relationship. The time-series path information includes time-series path groups and related information of the time-series path groups. A time-series path group includes multiple time-series paths. Upon acquiring the input data, filtering conditions are determined based on the conditional thresholds, and target time-series paths are determined based on the filtering conditions. The target time-series paths include time-series paths in the target database that satisfy the filtering conditions. When a target time-series path is determined according to the filtering conditions, target feature extraction is performed on the target time-series path to obtain target extraction results. When the target extraction results are obtained, the target extraction results are written into the time-series path feature source file. The target extraction results include: target logical features, or target logical features and target physical features. The time-series path feature source file includes the feature values ​​of the target time-series path. The feature data of the target time-series path are determined based on the source file of the time-series path features. Based on the characteristic data of the target time path, the violation time path is determined, a violation diagnosis report is generated, and the time path optimization strategy is determined based on the violation diagnosis report; Statistical distribution tables and statistical distribution maps are generated based on the characteristic data of the target time sequence path and the violation diagnosis report.

9. A computer device, characterized in that, include: The system includes a memory and a processor, which are interconnected. The memory stores computer instructions, and the processor executes the computer instructions to perform the steps of the static timing statistical analysis method of claim 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause the computer to perform the steps of the static time-series statistical analysis method of claim 8.

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