Chip ID layout determination method and device, equipment and storage medium

Abstract

The invention discloses a chip ID layout determination method and device, equipment and a storage medium, and the method comprises the steps: selecting a plurality of non-test chips located in a wafer boundary line from a chip arrangement layout as target chips, and determining the first position coordinates of a plurality of target chips; selecting a reference chip from the plurality of target chips, and determining the offset of the reference chip relative to the origin of the coordinate system; correcting the position coordinates of the plurality of target chips based on the offset; based on the size of each chip and the corrected position coordinate, determining a chip ID coordinate code of each chip; determining a third position coordinate of the chip ID coordinate code of each chip based on the first position coordinate and a preset code movement amount; and generating a chip ID layout based on the chip ID coordinate code corresponding to each chip and the third position coordinate of each chip. According to the method, efficient, accurate and automatic determination of the chip ID layout can be realized.

Description

Technical Field

[0001] The present invention relates to the field of micro-electromechanical system manufacturing technology, and in particular to a method, device, equipment and storage medium for determining a chip ID layout. Background Art

[0002] With the rapid development of micro-electromechanical system (MEMS) technology, the scale of the industry continues to expand, and the market demand for MEMS products has also shown an increasing trend year by year. MEMS products often require identity identification (chip ID, Identity Document) management during the wafer manufacturing process to meet the needs of tracking and failure analysis of each independent chip. In the IC field, the chip ID is usually recorded inside the chip circuit, while MEMS products, due to their special application scenarios, often need to directly make the chip ID in physical form on the chip surface through 1X contact lithography and etching processes. This not only facilitates rapid identification during the subsequent packaging and cutting process, but also allows the specific chip position and arrangement on the wafer to be quickly located during failure analysis.

[0003] In the related art, the corresponding chip ID code is usually generated according to the chip arrangement layout and the arrangement order of the chips, and the chip ID code position is determined according to the fixed spacing of the chip size, so as to generate a wafer-level chip ID layout, which records the position of each chip in the wafer and its corresponding ID code information; finally, the corresponding photomask is made according to the generated chip ID layout, and the chip is photoetched using the photomask to form the corresponding chip ID on the chip surface. Since the chip layout is usually pre-designed based on the chip size, it means that it cannot fully reflect the arrangement of the chips that need to generate ID on the wafer actually manufactured. When the arrangement of the chips that need to generate ID on the wafer actually manufactured is different from the arrangement of the chips in the chip layout layout, the chip ID layout generated by the above method will be inaccurate. If the generated chip ID layout is manually adjusted according to the arrangement of the chips on the wafer actually manufactured, the manufacturing cost and time cost will increase. Therefore, it is difficult to automatically and accurately generate a chip ID layout for the arrangement of the chips that need to generate ID on the wafer actually manufactured using the above method.

[0004] In view of the above problems, there is an urgent need for a method that can accurately, automatically and efficiently generate chip ID layout to meet the growing flexibility and diversity requirements in the MEMS product manufacturing process. Summary of the invention

[0005] In view of the above problems, the present invention is proposed to provide a method, device, equipment and storage medium for determining a chip ID layout that overcomes the above problems or at least partially solves the above problems. A non-test chip located within the wafer boundary line is selected from the chip layout layout as a target chip, and a chip ID layout that matches the target chip is determined based on the layout of the target chip. The layout of the target chip is closer to the layout of the chip that needs to generate an ID in the wafer actually manufactured, thereby achieving efficient, accurate and automatic determination of the chip ID layout.

[0006] In a first aspect, a method for determining a chip ID layout is provided, which is applied to an electronic device, and the method comprises:

[0007] Selecting a plurality of non-test chips located within a wafer boundary line from a chip layout as target chips, wherein the wafer boundary line is a wafer outer edge contour line with a center point of the chip layout as a midpoint;

[0008] Determine the first position coordinates of the plurality of target chips based on a pre-established layout coordinate system, wherein the layout coordinate system is a two-dimensional coordinate system established with the center point of the chip arrangement layout as the origin of the coordinate system;

[0009] Selecting a target chip closest to the origin of the coordinate system from the plurality of target chips as a reference chip, and determining an offset of the reference chip relative to the origin of the coordinate system;

[0010] Based on the offset, correcting the first position coordinates of the plurality of target chips to obtain corrected second position coordinates;

[0011] Determine the chip ID coordinate code of each target chip based on the size of each target chip and the corresponding second position coordinate;

[0012] Based on the first position coordinates of each of the target chips and a preset encoding movement amount, determining the third position coordinates of the chip ID coordinate code of each of the target chips;

[0013] A chip ID layout is generated based on the chip ID coordinate code of each target chip and the corresponding third position coordinates.

[0014] Optionally, the first position coordinates of the target chip include first position sub-coordinates of a first vertex and a second vertex of the target chip boundary box, and the first vertex and the second vertex are two diagonal vertices of the target chip boundary box.

[0015] Optionally, selecting a target chip closest to the origin of the coordinate system from the plurality of target chips as a reference chip includes:

[0016] Based on the first position coordinates of each of the target chips, determining the minimum distance from each of the target chips to the origin of the coordinate system;

[0017] The target chip having the shortest minimum distance to the origin of the coordinate system is selected as the reference chip.

[0018] Optionally, determining the offset of the reference chip relative to the origin of the coordinate system includes:

[0019] The first vertex or the second vertex of the reference chip boundary box is selected as a reference point, and the distance from the reference point to the origin of the coordinate system is determined as the offset.

[0020] Optionally, the second position coordinates include the second position sub-coordinates of the first vertex or the second vertex, and the first position coordinates of the plurality of target chips are corrected based on the offset to obtain the corrected second position coordinates, including:

[0021] When the reference point is the first vertex, adding the offset to the first position sub-coordinate of the first vertex to obtain a corrected second position sub-coordinate of the first vertex;

[0022] When the reference point is the second vertex, the offset is added to the first position sub-coordinate of the second vertex to obtain a corrected second position sub-coordinate of the second vertex.

[0023] Optionally, determining the chip ID coordinate code of each chip based on the size of each chip and the corresponding second position coordinates includes:

[0024] Determine the chip ID coordinate code for each chip according to the following formula:

[0025] ID nX=Die nX0 / width(nX);

[0026] ID nY=Die nY0 / height(nY);

[0027] Among them, the ID coordinate encoding of the nth chip is (ID nX, ID nY), the second position coordinate corresponding to the nth chip is (Die nX0, Die nY0), width(nX) represents the length of the nth chip along the X direction of the layout coordinate system, and height(nY) represents the width of the nth chip along the Y direction of the layout coordinate system.

[0028] Optionally, selecting a plurality of non-test chips located within the wafer boundary line as target chips from the chip layout diagram includes:

[0029] Extracting a bounding box layout diagram of all valid chips from a preset chip layout layout to obtain a valid chip layout layout, wherein the chip layout layout includes the arrangement of bounding boxes of pre-designed valid chips for exposure and invalid chips for testing;

[0030] From the effective chip layout, a valid chip whose four vertices of a chip boundary box are all located within the wafer boundary line is selected as the target chip.

[0031] In a second aspect, a device for determining a chip ID layout is provided, comprising:

[0032] A chip selection module is used to select a plurality of non-test chips located within a wafer boundary line from a chip layout as target chips, wherein the wafer boundary line is a wafer outer edge contour line with a center point of the chip layout as a midpoint;

[0033] A coordinate determination module, used to determine the first position coordinates of the plurality of target chips based on a pre-established layout coordinate system, wherein the layout coordinate system is a two-dimensional coordinate system established with the center point of the chip arrangement layout as the origin of the coordinate system;

[0034] An offset determination module, used for selecting a target chip closest to the origin of the coordinate system from the plurality of target chips as a reference chip, and determining an offset of the reference chip relative to the origin of the coordinate system;

[0035] A coordinate correction module, used for correcting the first position coordinates of the plurality of target chips based on the offset to obtain corrected second position coordinates;

[0036] An ID code determination module, configured to determine a chip ID coordinate code of each of the target chips based on the size of each of the target chips and the corresponding second position coordinates;

[0037] A coding coordinate determination module, used for determining a third position coordinate of the chip ID coordinate code of each of the target chips based on the first position coordinate of each of the target chips and a preset coding movement amount;

[0038] The ID layout determination module is used to generate a chip ID layout based on the chip ID coordinate code of each target chip and the corresponding third position coordinates.

[0039] In a third aspect, an electronic device is provided, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method for determining the chip ID layout as described in the first aspect by executing the computer instructions.

[0040] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the method for determining the chip ID layout as described in the first aspect.

[0041] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:

[0042] The embodiments of the present invention provide a method, device, equipment and storage medium for determining a chip ID layout. By selecting a non-test chip located within the wafer boundary line from the chip layout layout as a target chip that needs to form a chip ID in the chip layout layout, the target chip is arranged in a manner closer to the arrangement of chips that need to generate an ID in the wafer actually manufactured, thereby effectively avoiding the problem of inaccurate chip ID layout caused by the inconsistency between the chip layout layout and the arrangement of chips that need to form an ID on the actual manufactured wafer in the traditional method.

[0043] At the same time, according to the offset of the reference chip relative to the origin of the coordinate system, the position coordinates of each target chip are corrected to ensure the accuracy of the position coordinates of each chip, thereby improving the accuracy of the chip ID layout. Moreover, this method can automatically generate the corresponding chip ID layout according to the arrangement of the chips that need to generate IDs in the wafer actually manufactured, without the need to manually adjust the generated chip ID layout according to the arrangement of the chips on the wafer actually manufactured, significantly reducing the manufacturing cost and time cost, improving production efficiency, and being able to adapt well to chips of different sizes and different arrangements. Without making major modifications or adjustments to the method itself, it can efficiently achieve accurate generation of chip ID layouts for various MEMS products, demonstrating extremely high flexibility and applicability.

[0044] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0046] Figure 1 is a flow chart of a method for determining a chip ID layout provided by an embodiment of the present invention;

[0047] Figure 2 is a schematic diagram of an effective chip layout provided by an embodiment of the present invention;

[0048] Figure 3 is a schematic diagram of another effective chip layout provided by an embodiment of the present invention;

[0049] Figure 4 is a schematic diagram of the arrangement of a target chip provided by an embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of chip ID coordinate encoding provided by an embodiment of the present invention;

[0051] Figure 6 It is a schematic diagram of a chip ID encoding font layout file provided by an embodiment of the present invention;

[0052] Figure 7 It is a structural block diagram of a device for determining a chip ID layout provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to better understand the above-mentioned technical scheme, the above-mentioned technical scheme will be described in detail below in combination with the accompanying drawings and specific implementation methods of the specification. It should be understood that the embodiments of the present disclosure and the specific features in the embodiments are detailed descriptions of the technical scheme of the present application, rather than limitations on the technical scheme of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0054] Many MEMS products require the chip ID to be directly printed on the chip through 1X contact lithography and etching process, so as to facilitate the tracing of the position and arrangement of the failed chip on the wafer after cutting and packaging. For this method, a wafer-level chip ID layout needs to be made, and a corresponding mask needs to be made according to the chip ID layout, and the chip needs to be photolithographically etched using the mask to form the corresponding chip ID on the chip surface.

[0055] In the related art, the corresponding chip ID code is usually generated according to the chip layout according to the arrangement order of the chips, and the chip ID code position is determined according to the fixed spacing of the chip size, thereby generating a wafer-level chip ID layout, which records the position of each chip in the wafer and its corresponding ID code information. However, the chip layout is a layout diagram of the chip boundary box pre-designed based on the chip size, and the chip layout includes the arrangement of the boundary boxes of valid chips for exposure and invalid chips for testing. Among them, the valid chip is a chip that needs to form a chip ID, and the test chip is a chip used for PCM (process control monitoring) testing during the wafer manufacturing process. The test chip in the test area does not need to form a chip ID. Because there is a test chip in the chip layout, and the size and position of the test area where the test chip is located are not fixed. If the above method is used to generate a chip ID layout based on the chip layout and the chip size is fixed The distance, the test chip located within the wafer boundary line will also generate a corresponding chip ID in the chip ID layout, resulting in an error in the final generated chip ID layout. If the wrong chip layout ID is used for exposure and etching, the chip ID will also be etched on the test chip, thereby affecting the formation of the test pattern on the test chip. Therefore, it is difficult to automatically and accurately generate a chip ID layout based on the arrangement of chips that need to generate IDs on the wafers actually manufactured using the above method.

[0056] Therefore, in order to solve the technical problems existing in the related art, the embodiments of the present invention provide a method, device, equipment and storage medium for determining a chip ID layout. The inventive concept is to select a non-test chip located within the wafer boundary line from the chip layout layout as a target chip, and determine a chip ID layout that matches the target chip according to its layout. The layout of the target chip is closer to the layout of the chip that needs to generate an ID in the actually manufactured wafer, thereby realizing efficient, accurate and automatic determination of the chip ID layout.

[0057] Figure 1 is a flow chart of a method for determining a chip ID layout provided by an embodiment of the present invention, such as Figure 1 As shown, the method includes:

[0058] Step S110 , selecting a plurality of non-test chips located within a wafer boundary line from the chip layout as target chips, wherein the wafer boundary line is a wafer outer edge contour line with a center point of the chip layout as the midpoint.

[0059] In the specific implementation, the staff can draw the chip layout layout on the terminal device according to the chip size and chip type (including exposure chips and test chips), or can import the pre-drawn chip layout layout into the terminal device. After the chip layout layout is prepared, the chip ID layout can be generated by clicking the chip ID layout generation button on the terminal device. After clicking the generate button, the terminal device transmits the start instruction carrying the chip layout layout to the electronic device (such as a server), and the server responds to the start instruction and starts executing S110.

[0060] Optionally, step S110 includes:

[0061] Extracting the bounding box layout of all valid chips from a preset chip layout to obtain a valid chip layout, wherein the chip layout includes the layout of bounding boxes of pre-designed valid chips for exposure and invalid chips for testing;

[0062] From the effective chip layout, select the effective chip whose four vertices of the chip boundary box are all located within the wafer boundary line as the target chip.

[0063] Figure 2 is a schematic diagram of an effective chip layout provided by an embodiment of the present invention, such as Figure 2 As shown in the figure, each red square represents a valid chip a, the blue rectangular box represents the main exposure area S1, the main exposure area S1 includes multiple valid chips a that need to form chip IDs, the blank area is the test area S2 formed by the test chip for PCM (process control monitoring) test, and the black circle represents the wafer boundary line. Since the test chip has been selected when making the chip layout, the arrangement of the test chip and the valid chip can be determined according to the chip function when making the chip layout. In step S110, after extracting Figure 2 After the effective chip layout is shown, it is necessary to further select the chip whose four vertices of the chip boundary box are all located within the wafer boundary line as the target chip, so as to obtain an arrangement method of the chip that needs to generate an ID in the wafer that is closer to the actual manufacturing. It should be noted that the wafer boundary line in this embodiment is the outer edge contour line of the wafer with the center point of the effective chip layout as the midpoint, and the circular radius of the wafer boundary line can be set by the designer according to the radius of the actual effective chip area of ​​the wafer.

[0064] In this embodiment, selecting a chip whose four vertices of a chip boundary box are all located within the wafer boundary line from the effective chip layout as a target chip may specifically include:

[0065] Based on a pre-established layout coordinate system, the position coordinates of each valid chip in the valid chip layout are determined, and the position coordinates include at least the position coordinates of two opposite vertices of the valid chip boundary box; based on the position coordinates of each valid chip, the distances from the four vertices of each valid chip boundary box to the origin of the coordinate system are determined; and valid chips whose distances from the four vertices of the boundary box to the origin of the coordinate system are less than or equal to the wafer radius are selected as target chips.

[0066] To better understand this step, Figure 3 The selection of target chips is briefly described below: Figure 3 is a schematic diagram of another effective chip layout provided by an embodiment of the present invention, such as Figure 3 As shown in the figure, NO.1~NO.13, NO.16, NO.18~NO.21, NO.23~NO.25 represent valid chips, and the layout coordinate system is a two-dimensional coordinate system established with the center point O of the valid chip arrangement layout as the origin of the coordinate system. The horizontal coordinate of the layout coordinate system is the X-axis, and the vertical coordinate is the Y-axis. Based on this coordinate system, the position coordinates of each valid chip can be determined. The position coordinates of each valid chip can include the position coordinates of two opposite vertices of the bounding box. For example, the position coordinates of the lower left and upper right opposite vertices can be selected to represent the position coordinates of the valid chip, that is, the position coordinates of the nth valid chip are (DieLeft nX, DieLeft nY, DieRight nX, DieRight nY), and the position coordinates of the origin of the coordinate system are (0, 0).

[0067] In the specific implementation, a specific GDS NO in the GDS file can be used as a chip identification layer to represent the position and size of each chip. In this embodiment, GDS:101 / 1 can be used as the chip identification layer. It should be noted that GDS:101 / 1 only draws the chip position that needs to encode the chip ID and is not used for drawing other graphics. Furthermore, the .shape function in the klayout library can be used to extract the actual position coordinates of the two pairs of vertices of each valid chip in the chip identification layer, and then Python can be used to count the coordinate data into a table data column (DieLeft nX, DieLeft nY, DieRight nX, DieRightnY) to facilitate subsequent calculations and conversions.

[0068] After obtaining the position coordinates of each chip, the distances from the four vertices of each chip boundary box to the origin of the coordinate system can be determined according to the following formula:

[0069] The distance from the lower left vertex to the origin of the coordinate system: ((DieLeft nX)2+(DieLeft nY)2) 0.5 ;

[0070] The distance from the upper left vertex to the origin of the coordinate system: ((DieLeft nX)2+(DieRight nY)2) 0.5 ;

[0071] The distance from the upper right vertex to the origin of the coordinate system: ((DieRight nX)2+(DieRight nY)2) 0.5 ;

[0072] The distance from the lower right vertex to the origin of the coordinate system: ((DieRight nX)2+(DieLeft nY)2) 0.5 ;

[0073] The distances from the four vertices to the origin of the coordinate system are calculated one by one. If the distances from the four vertices of the chip boundary box to the origin of the coordinate system are all less than or equal to the wafer radius, the target chip of the chip is selected; if the distance from any of the four vertices to the origin of the coordinate system is greater than the wafer radius, the chip is not selected as the target chip, and the corresponding position coordinates of the chip are deleted from the table data column.

[0074] Figure 4 is a schematic diagram of the arrangement of a target chip provided by an embodiment of the present invention, such as Figure 4 As shown, according to the above method, Figure 3 Valid chips NO.7, NO.8, NO.9, NO.12, NO.13, NO.18 and NO.19 can be selected as target chips. The arrangement of each target chip is as follows: Figure 4 shown.

[0075] It should be noted that Figure 3 and Figure 4 The arrangement and size of the chips in the figure are only examples. The arrangement and size of the actual chips can be set according to the chips on the wafer actually manufactured, and the present invention is not limited to this.

[0076] Step S120: determining first position coordinates of a plurality of target chips based on a pre-established layout coordinate system, wherein the layout coordinate system is a two-dimensional coordinate system established with the center point of the chip arrangement layout as the origin of the coordinate system.

[0077] In this embodiment, the first position coordinate of the target chip includes the first position sub-coordinate (DieLeft nX, DieLeft nY) of the first vertex of the target chip boundary box, and the first position sub-coordinate (DieRight nX, DieRight nY) of the second vertex. The first vertex and the second vertex are two diagonal vertices of the target chip boundary box (for example, the lower left and upper right, or the lower right and upper left vertices). The corresponding first position coordinate of the target chip can be expressed as (DieLeft nX, DieLeft nY, DieRight nX, DieRight nY). Figure 4 As shown, taking target chip NO.7 as an example, the lower left vertex P7a of target chip NO.7 can be selected as the first vertex, and the upper right vertex P7b can be selected as the second vertex, then the first position coordinates of target chip NO.7 are ((DieLeft 7X, DieLeft 7Y, DieRight 7X, DieRight 7Y).

[0078] Step S130 : selecting a target chip closest to the origin of the coordinate system from the multiple target chips as a reference chip, and determining an offset of the reference chip relative to the origin of the coordinate system.

[0079] Optionally, step S130 includes:

[0080] Based on the first position coordinates of each target chip, the minimum distance from each target chip to the origin of the coordinate system is determined; and a target chip having the shortest minimum distance to the origin of the coordinate system is selected as a reference chip.

[0081] In one implementation of this embodiment, the distances from the four vertices of each target chip boundary box to the origin of the coordinate system can be calculated according to the calculation formula in step S110, and then the minimum value is selected from the four distances as the minimum distance from each target chip to the origin of the coordinate system. After the minimum distances corresponding to all target chips are calculated, the target chip with the smallest corresponding minimum distance can be further selected as the reference chip.

[0082] In another implementation of this embodiment, the boundary lines of each target chip may be extracted based on the first position coordinates of each target chip, and then a target chip whose boundary line is closest to the origin of the coordinate system is selected as the reference chip.

[0083] Optionally, determining the offset of the reference chip relative to the origin of the coordinate system in step S130 includes:

[0084] The first vertex or the second vertex of the reference chip boundary box is selected as the reference point, and the distance from the reference point to the origin of the coordinate system is determined as the offset.

[0085] Specifically, Figure 4 As shown in the figure, after selecting the target chip NO.13 as the reference chip, the lower left vertex P13a of the target chip NO.13 can be selected as the reference point, and the distance from the reference point P13a to the origin of the coordinate system is determined as the offset. At this time, the offset includes the offset DieShiftX in the X-axis direction and the two-part offset DieShiftY in the Y-axis direction, and the offset can be expressed as (DieShiftX, DieShiftY).

[0086] In other implementations of this embodiment, the upper right, upper left, and lower right vertices of the reference chip may also be selected as reference points, and the present invention is not limited to this.

[0087] Step S140: Based on the offset, correct the first position coordinates of the plurality of target chips to obtain corrected second position coordinates.

[0088] In this embodiment, the second position coordinates include the second position sub-coordinates of the first vertex (DieLeft nX', DieLeft nY') or the second position sub-coordinates of the second vertex (DieRight nX', DieRight nY'), and the second position coordinates can be uniformly expressed as (Die nX0, Die nY0), wherein Die nX0=DieLeft nX' or Die nX0=DieRight nX'; Die nY0=DieLeft nY' or Die nY0=DieRight nY'.

[0089] Optionally, when the reference point selected in step S130 is the first vertex, the corresponding step S140 may include:

[0090] The first position sub-coordinate of the first vertex is added with the offset to obtain a corrected second position sub-coordinate of the first vertex.

[0091] Specifically, when the first position sub-coordinate of the first vertex is (DieLeft nX, DieLeft nY), the X-axis coordinate DieLeft nX in the first position sub-coordinate of the first vertex can be added with the offset DieShiftX of the X-axis part, and the Y-axis coordinate DieLeft nY in the first position sub-coordinate of the first vertex can be added with the offset DieShiftY of the Y-axis part to obtain the corrected second position sub-coordinate of the first vertex (DieLeft nX', DieLeft nY'), where DieLeftnX'=DieLeft nX+DieShiftX+; DieLeft nY'=DieLeft nY+DieShiftY.

[0092] Optionally, when the reference point selected in step S130 is the second vertex, the corresponding step S140 may include:

[0093] The first position sub-coordinate of the second vertex is added with the offset to obtain a corrected second position sub-coordinate of the second vertex.

[0094] Specifically, when the first position sub-coordinate of the second vertex is (DieRight nX, DieRight nY), the X-axis coordinate DieRight nX in the first position sub-coordinate of the second vertex can be added with the offset DieShiftX of the X-axis part, and the Y-axis coordinate DieRight nY in the first position sub-coordinate of the second vertex can be added with the offset DieShiftY of the Y-axis part, so as to obtain the corrected second position sub-coordinate of the second vertex (DieRight nX', DieRight nY'), wherein DieRight nX'=DieRight nX+DieShiftX; DieRight nY'=DieRight nY+DieShiftY. At this time, the corrected second position coordinate corresponding to the reference chip NO.13 is (0, 0).

[0095] Step S150: Determine the chip ID coordinate code of each target chip based on the size of each target chip and the corresponding second position coordinates.

[0096] Optionally, step S150 includes:

[0097] Determine the chip ID coordinate code for each target chip according to the following formula:

[0098] ID nX=Die nX0 / width(nX);

[0099] ID nY=Die nY0 / height(nY);

[0100] Among them, the ID coordinate encoding of the nth target chip is (ID nX, ID nY), the second position coordinate corresponding to the nth target chip is (Die nX0, Die nY0), width(nX) represents the length of the nth target chip along the X direction of the layout coordinate system, and height(nY) represents the width of the nth chip along the Y direction of the layout coordinate system.

[0101] Since the center point of the layout coordinate system may not be at a certain vertex of the chip when determining the first position coordinates of each target chip, this will make the X-axis coordinate of the first position coordinates a non-integer multiple of the chip length, and the Y-axis coordinate a non-integer multiple of the chip width. If the chip ID coordinate code is determined according to the first position coordinates and the chip size, the determined chip ID coordinate code will be a non-integer. Therefore, the embodiment of the present invention adds an offset to the first position coordinates of each target chip to obtain the second position coordinates, which is equivalent to taking a vertex of one of the target chips (i.e., the reference chip) as the center point, so that the X-axis coordinates in the second position coordinates of each target chip are integer multiples of the chip length, and the Y-axis coordinates are integer multiples of the chip width. In the second position coordinates, the X-axis coordinate DienX0 divided by the chip length width (nX) and the Y-axis coordinate DienY0 divided by the chip width height (nY) can both be integers, so that the chip ID coordinate code of each target chip finally obtained can be an integer.

[0102] Figure 5 is a schematic diagram of chip ID coordinate encoding provided by an embodiment of the present invention, such as Figure 5 As shown, at this time, the chip ID coordinate encoding of the target chip NO.7 is (1, -1); the chip ID coordinate encoding of the target chip NO.8 is (1, 0); the chip ID coordinate encoding of the target chip NO.9 is (1, 1); the chip ID coordinate encoding of the target chip NO.12 is (-1, 0); the chip ID coordinate encoding of the target chip NO.13 is (0, 0); the chip ID coordinate encoding of the target chip NO.18 is (-1, 0); and the chip ID coordinate encoding of the target chip NO.19 is (-1, 1).

[0103] Step S160 : determining the third position coordinates of the chip ID coordinate code of each target chip based on the first position coordinates of each target chip and the preset code movement amount.

[0104] Specifically, the encoding movement amount can be customized by the designer, including the encoding movement amount in the X-axis direction and the encoding movement amount in the Y-axis direction, and the encoding movement amount can be expressed as (DieID nX, DieID nY). In this embodiment, the first position coordinate of each target chip includes the position sub-coordinates of two pairs of vertices of the target chip boundary box, and when actually calculating the third position coordinate of the chip ID coordinate code, it is only necessary to select the position sub-coordinate of one of the vertices. Exemplarily, for example, when the first position sub-coordinate (DieLeft nX, DieLeft nY) of the first vertex is selected to calculate the third position coordinate, if the third position coordinate of the chip ID coordinate code is (Die nX1, Die nY1), then the corresponding Die nX1 = DieLeft nX + DieID nX; Die nY1 = DieLeft nY + Die nY0); when the first position sub-coordinate (DieRightnX, DieRight nY) of the second vertex is selected to calculate the third position coordinate, if the third position coordinate of the chip ID coordinate code is (Die nX1, DieNY1), then the corresponding Die nX1 = DieRight nX + DieID nX; Die nY1 = DieRight nY + Die nY0). By determining the third position coordinate, the etching position of the chip ID coordinate code of each chip on the chip can be determined.

[0105] Step S170 : generating a chip ID layout based on the chip ID coordinate code of each target chip and the corresponding third position coordinates.

[0106] In this embodiment, after determining the chip ID coordinate code of each target chip and the third position coordinates corresponding to the corresponding chip ID coordinate code, the relevant coding information of the chip ID coordinate code can also be customized and customized. The coding information includes at least the number of code display digits, the coding system, the coding font size, the coding font type and the coding font spacing. The number of code display digits can be set to 3 digits, 4 digits, etc. as needed, and the number of insufficient digits is automatically filled with zeros, such as (0001, -0001), etc. The coding system can be set to decimal, hexadecimal, vigesimal, etc. The coding font size and coding font spacing will affect the position of the coding display. Therefore, when setting, it is necessary to ensure that the chip ID code finally formed on the chip can be displayed correctly; and the coding font type can be arbitrarily designed, and this embodiment does not limit this.

[0107] It should be noted that the chip ID layout generation in the prior art usually relies on paid software such as EDA (Electronic Design Automation, electronic design automation software). For example, Virtuoso software can be implemented by programming language, and Tanner software has its own Label mapping layout function, but this limits the layout designers to EDA software, increasing the cost of using the software. By adopting the above method provided by the implementation of the present invention, the chip coordinates can be converted into a database using open source Python and Klayout software, and the method of combining database statistical processing and layout text conversion can be used to realize the automatic, editable, and customizable generation of chip ID layout data. The design requirements for chip ID are realized by editing and converting the text, and the text content can be finally converted into GDS layout data, reducing the designer's dependence on EDA software, avoiding the limitations of some EDA software on chip ID design, and also reducing the demand cost for EDA software, realizing the automatic, customizable, and low-cost generation of chip ID layout.

[0108] The following is a brief description of how to use the open source Python and Klayout software to implement the determination of the chip ID layout provided in this embodiment:

[0109] Step S201: Prepare a valid chip layout for which chip IDs need to be made, and use a specific GDS NO as a chip identification layer to represent the position and size of each chip.

[0110] Step S202: Use the .shape function in the klayout library to extract the actual coordinate positions of the two opposite corners of each valid chip in the chip identification layer, and use Python to count the coordinate data into a table data column (DieLeft nX, DieLeft nY, DieRight nX, DieRight nY) to facilitate subsequent calculations and conversions.

[0111] Step S203: Based on the position coordinates (DieLeft nX, DieLeftnY, DieRight nX, DieRight nY) of each valid chip obtained in S202, calculate the distances from the four vertex corners of the valid chip to the center of the wafer (i.e., the origin of the coordinate system), and calculate the distances from the four vertices to the origin of the coordinate system one by one. If the distances from the four vertices of the chip boundary box to the origin of the coordinate system are all less than or equal to the wafer radius, the target chip of the valid chip is selected; if the distance from any of the four vertices to the origin of the coordinate system is greater than the wafer radius, the chip is not selected as the target chip, and the position coordinates corresponding to the chip are deleted from the table data column.

[0112] Step S204: Find a target chip closest to the wafer center in the layout as the reference chip, and obtain the actual coordinate value of the lower left vertex of the reference chip, which is set as the offset (DieShiftX, DieShiftY) of the lower left corner of the reference chip relative to the wafer center.

[0113] Step S205: Use Python language to add the offsets (DieShiftX, DieShiftY) obtained in step S204 to the data table in step S202 to obtain the corrected chip position coordinates (Die nX0, Die nY0). That is, Die nX0 = DieLeft nX + DieShiftX; Die nY0 = DieLeft nY + DieShiftY.

[0114] Step S206: Divide the corrected chip position coordinates (Die nX0, Die nY0) by the chip length: X, width: Y, i.e., GDS:101 width (nX) and height (nY), respectively, and take integers to obtain the chip ID coordinate code (ID nX, ID nY) in order. At this time, the code (0, 0) is at the center of the wafer.

[0115] Step S207: Use the Python.zfill() function to set the number of digits to be displayed for ID nX and ID nY to two digits, three digits, etc., and automatically fill in the leading zeros for the missing digits.

[0116] Step S208: The starting position of the chip ID on the wafer can be adjusted by adding or subtracting the maximum or minimum values ​​of ID nX and ID nY generated by the chip ID in step S206, i.e., ID nX+ / -min / max(ID nX), ID nY+ / -min / max(ID nY).

[0117] Step S209: The ID nX and ID nY generated in step S207 or step S208 can be converted into any base such as decimal, hexadecimal, or vigesimal using a Python function. For example, in the example (AF, FF), the base conversion can reduce the number of digits in the chip ID. If the three-digit decimal 255 can be represented by the two-digit hexadecimal FF, the size of the space occupied by one digit of the chip ID on the chip is reduced.

[0118] Step S210: Prepare the layout font of the chip code and generate the DIE_ID_Label GDS file. The file name is not restricted. Each cell in the file contains a font graphic corresponding to the cell name. There are two layers in the cell. Layer GDS: 1 / 0 is used to draw the font graphic. The font graphic form is not required. Layer GDS: 2 / 0 is used to draw the spacing of a single chip ID font. Figure 6 is a schematic diagram of a chip ID encoding font layout file provided by an embodiment of the present invention, such as Figure 3 As shown, there are 17 cells in the example GDS file. The top cell: all contains all ID fonts. This embodiment uses hexadecimal as an example, so there are 16 characters from 0 to F. Figure 3 -①. There are two layers such as Figure 3 -②, Figure 3 -③ and 3-④ are examples of fonts. Cell 0 uses GDS:1 / 0 to draw the number 0, and GDS:2 / 0 is used as the font spacing boundary. Cell F uses GDS:1 / 0 to draw the number F, and GDS:2 / 0 is used as the font spacing boundary. All character cells need to be embedded in topcell:all and arranged in order. Figure 3 -⑤, the spacing between each font is the GDS:2 / 0 boundary, so the spacing between chip ID fonts can be adjusted according to the size of the GDS:2 / 0 rectangular frame. The specific number or letter layout graphic style under the cell name is not restricted, and can be designed according to your own needs, not limited to any font format in any EDA software.

[0119] Step S211: The final required ID nX and ID nY values ​​formed before the above step S210 are called by the load_from_file function in the Klayout library to retrieve the DIE_ID_Label GDS file prepared in step S210. The gen.TextGenerator() function of the Klayout library is used to create a text generator, and the text generator gen is used to create the text area region of ID nX and ID nY region = gen.text(Die_ID, ly.dbu, mag).moved(xy), where Die_ID is used to obtain the position coordinates of the corrected chip, ly.dbu represents the design unit, and mag represents the magnification of the font, which affects the size of the generated text. Move moves the text generated by region to the appropriate position according to the given offset to ensure the correct display of the chip ID on the chip, thereby realizing the position setting of the chip ID layout inside the chip as required.

[0120] Step S212: Use klayout library.Shape().insert(region) to insert the moved text object region into the specified layer. Then use Python.apply() to apply the text generator function to each row in the data frame formed before step S211 to add a chip ID for each chip.

[0121] Step S213: Use Python.write() function to write the modified layout object into GDS file, and finally form the DIE ID layout data of all chips on the whole wafer, and the file format is the universal format .gds. GDS format file can be well applied to any EDA software. Use Pythonpd.pivot_table function to convert the final set ID nX, ID nY into a chip ID Mapping excel file with row: Die_ID nX, column: Die_ID nY, which is convenient for product testing to locate the effective chip position and arrangement.

[0122] Based on the same inventive concept, an embodiment of the present invention further provides a device for determining a chip ID layout, which is used to determine a chip ID layout. Figure 7 is a structural block diagram of a device for determining a chip ID layout provided by an embodiment of the present invention, such as Figure 7 As shown, the device includes a chip selection module 710, a coordinate determination module 720, an offset determination module 730, a coordinate correction module 740, an ID code determination module 750, a code coordinate determination module 760 and an ID layout determination module 770.

[0123] The chip selection module 710 is used to select a plurality of non-test chips located within the wafer boundary line from the chip layout as target chips, wherein the wafer boundary line is an outer edge contour line of the wafer with the center point of the chip layout as the midpoint;

[0124] A coordinate determination module 720 is used to determine the first position coordinates of the plurality of target chips based on a pre-established layout coordinate system, where the layout coordinate system is a two-dimensional coordinate system established with the center point of the chip arrangement layout as the origin of the coordinate system;

[0125] An offset determination module 730 is used to select a target chip closest to the origin of the coordinate system from multiple target chips as a reference chip, and determine an offset of the reference chip relative to the origin of the coordinate system;

[0126] A coordinate correction module 740 is used to correct the first position coordinates of the plurality of target chips based on the offset to obtain corrected second position coordinates;

[0127] An ID code determination module 750 is used to determine a chip ID coordinate code of each target chip based on the size of each target chip and the corresponding second position coordinate;

[0128] The coding coordinate determining module 760 is used to determine the third position coordinate of the chip ID coordinate code of each target chip based on the first position coordinate of each target chip and a preset coding movement amount;

[0129] The ID layout determination module 770 is used to generate a chip ID layout based on the chip ID coordinate code of each target chip and the corresponding third position coordinates.

[0130] Optionally, the chip selection module 710 is further used for:

[0131] Providing a chip layout diagram, the chip layout diagram is a layout diagram of chip boundary boxes pre-designed based on chip size, and the chip layout diagram includes the arrangement of boundary boxes of valid chips for exposure and invalid chips for testing;

[0132] Extracting the bounding box layout diagrams of all valid chips from the chip layout diagram to obtain a valid chip layout diagram;

[0133] From the effective chip layout, a chip whose four vertices of the chip boundary box are all located within the wafer boundary line is selected as the target chip.

[0134] Optionally, the first position coordinates of the target chip include first position sub-coordinates of a first vertex and a second vertex of a bounding box of the target chip, and the first vertex and the second vertex are two diagonal vertices of the bounding box of the target chip.

[0135] Optionally, the offset determination module 730 is further configured to:

[0136] Based on the first position coordinates of each target chip, determining the minimum distance from each target chip to the origin of the coordinate system;

[0137] A target chip with the shortest distance to the origin of the coordinate system is selected as the reference chip.

[0138] Optionally, the offset determination module 730 is further configured to:

[0139] The first vertex or the second vertex of the reference chip boundary box is selected as the reference point, and the distance from the reference point to the origin of the coordinate system is determined as the offset.

[0140] Optionally, the second position coordinates include second position sub-coordinates of the first vertex or the second vertex, and the coordinate correction module 740 is further used for:

[0141] When the reference point is the first vertex, the first position sub-coordinate of the first vertex is added with the offset to obtain a corrected second position sub-coordinate of the first vertex;

[0142] When the reference point is the second vertex, the offset is added to the first position sub-coordinate of the second vertex to obtain a corrected second position sub-coordinate of the second vertex.

[0143] Optionally, the ID code determination module 750 is further used to:

[0144] Determine the chip ID coordinate code for each chip according to the following formula:

[0145] ID nX=Die nX0 / width(nX);

[0146] ID nY=Die nY0 / height(nY);

[0147] Among them, the ID coordinate encoding of the nth chip is (ID nX, ID nY), the second position coordinate corresponding to the nth chip is (Die nX0, Die nY0), width(nX) represents the length of the nth chip along the X direction of the layout coordinate system, and height(nY) represents the width of the nth chip along the Y direction of the layout coordinate system.

[0148] The specific details of the method for determining the chip ID layout used in the above-mentioned determination device can be understood by corresponding to the relevant descriptions and effects in the embodiment of the method for determining the chip ID layout shown above, and will not be repeated here.

[0149] Based on the same inventive concept as the above-mentioned method for determining the chip ID layout, the present invention also provides an electronic device, which may include a processor and a memory, wherein the processor and the memory may be connected to each other by bus or other means. The processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above-mentioned various types of chips. The memory, as a non-transient computer-readable storage medium, may be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the method for determining the chip ID layout in the embodiment of the present invention. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, i.e., the determination of the chip ID layout in the above-mentioned method embodiment is realized.

[0150] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required by at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. The one or more modules are stored in the memory, and when executed by the processor, the execution is as follows: Figure 1 The method for determining the chip ID layout in the illustrated embodiment.

[0151] For details of the above electronic equipment, please refer to Figure 1 The corresponding related descriptions and effects in the illustrated embodiments can be understood and will not be repeated here.

[0152] Based on the same inventive concept as the method for determining the chip ID layout, the present invention also provides a computer-readable storage medium, on which computer instructions are stored, and the computer program instructions are used to enable a computer to execute the method for determining the chip ID layout in the above embodiment.

[0153] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0154] The technical solution provided in the above-mentioned embodiment of the present application has at least the following technical effects or advantages: the embodiment of the present invention provides a method, device, equipment and storage medium for determining a chip ID layout, by selecting a non-test chip located within the wafer boundary line from the chip layout layout as the target chip that needs to form a chip ID in the chip layout layout, the target chip is arranged in a manner closer to the arrangement of the chip that needs to generate an ID in the wafer that is actually manufactured, and effectively avoids the problem of inaccurate chip ID layout caused by the inconsistency between the chip layout layout and the chip arrangement that needs to form an ID on the actual manufactured wafer in the traditional method. At the same time, according to the offset of the reference chip relative to the origin of the coordinate system, the position coordinates of each target chip are corrected to ensure the accuracy of the position coordinates of each chip, thereby improving the accuracy of the chip ID layout. Moreover, this method can automatically generate the corresponding chip ID layout according to the arrangement of chips for which IDs need to be generated in the wafer actually manufactured. There is no need to manually adjust the generated chip ID layout according to the arrangement of chips on the wafer actually manufactured, which significantly reduces manufacturing costs and time costs, improves production efficiency, and can well adapt to chips of different sizes and arrangements. There is no need to significantly modify or adjust the method itself, and it can efficiently and accurately generate chip ID layouts for various MEMS products, demonstrating extremely high flexibility and applicability.

[0155] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0156] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the intention that the claimed invention requires more features than those explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0157] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for determining a chip ID layout, characterized in that: Applied to electronic equipment, the method comprises: Selecting a plurality of non-test chips located within a wafer boundary line from a chip layout as target chips, wherein the wafer boundary line is a wafer outer edge contour line with a center point of the chip layout as a midpoint; Determine the first position coordinates of the plurality of target chips based on a pre-established layout coordinate system, wherein the layout coordinate system is a two-dimensional coordinate system established with the center point of the chip arrangement layout as the origin of the coordinate system; Selecting a target chip closest to the origin of the coordinate system from the plurality of target chips as a reference chip, and determining an offset of the reference chip relative to the origin of the coordinate system; Based on the offset, correcting the first position coordinates of the plurality of target chips to obtain corrected second position coordinates; Determine the chip ID coordinate code of each target chip based on the size of each target chip and the corresponding second position coordinate; Based on the first position coordinates of each of the target chips and a preset encoding movement amount, determining the third position coordinates of the chip ID coordinate code of each of the target chips; A chip ID layout is generated based on the chip ID coordinate code of each target chip and the corresponding third position coordinates.

2. The determination method according to claim 1, characterized in that: The first position coordinates of the target chip include first position sub-coordinates of a first vertex and a second vertex of the target chip boundary box, where the first vertex and the second vertex are two diagonal vertices of the target chip boundary box.

3. The determination method according to claim 2, characterized in that: The step of selecting a target chip closest to the origin of the coordinate system from the plurality of target chips as a reference chip comprises: Based on the first position coordinates of each of the target chips, determining the minimum distance from each of the target chips to the origin of the coordinate system; The target chip having the shortest minimum distance to the origin of the coordinate system is selected as the reference chip.

4. The determination method according to claim 3, characterized in that: Determining the offset of the reference chip relative to the origin of the coordinate system includes: The first vertex or the second vertex of the reference chip boundary box is selected as a reference point, and the distance from the reference point to the origin of the coordinate system is determined as the offset.

5. The determination method according to claim 4, characterized in that: The second position coordinates include the second position sub-coordinates of the first vertex or the second vertex, and the first position coordinates of the plurality of target chips are corrected based on the offset to obtain the corrected second position coordinates, including: When the reference point is the first vertex, adding the offset to the first position sub-coordinate of the first vertex to obtain a corrected second position sub-coordinate of the first vertex; When the reference point is the second vertex, the offset is added to the first position sub-coordinate of the second vertex to obtain a corrected second position sub-coordinate of the second vertex.

6. The determination method according to claim 5, characterized in that: The step of determining the chip ID coordinate code of each chip based on the size of each chip and the corresponding second position coordinates includes: Determine the chip ID coordinate code for each chip according to the following formula: ID nX=Die nX0 / width(nX); ID nY=Die nY0 / height(nY); Among them, the ID coordinate encoding of the nth chip is (ID nX, ID nY), the second position coordinate corresponding to the nth chip is (Die nX0, Die nY0), width(nX) represents the length of the nth chip along the X direction of the layout coordinate system, and height(nY) represents the width of the nth chip along the Y direction of the layout coordinate system.

7. The determination method according to claim 1, characterized in that: The step of selecting a plurality of non-test chips located within the wafer boundary line as target chips from the chip layout diagram includes: Extracting a bounding box layout diagram of all valid chips from a preset chip layout layout to obtain a valid chip layout layout, wherein the chip layout layout includes the arrangement of bounding boxes of pre-designed valid chips for exposure and invalid chips for testing; From the effective chip layout, a valid chip whose four vertices of a chip boundary box are all located within the wafer boundary line is selected as the target chip.

8. A device for determining a chip ID layout, characterized in that: include: A chip selection module is used to select a plurality of non-test chips located within a wafer boundary line from a chip layout as target chips, wherein the wafer boundary line is a wafer outer edge contour line with a center point of the chip layout as a midpoint; A coordinate determination module, used to determine the first position coordinates of the plurality of target chips based on a pre-established layout coordinate system, wherein the layout coordinate system is a two-dimensional coordinate system established with the center point of the chip arrangement layout as the origin of the coordinate system; An offset determination module, used for selecting a target chip closest to the origin of the coordinate system from the plurality of target chips as a reference chip, and determining an offset of the reference chip relative to the origin of the coordinate system; A coordinate correction module, used for correcting the first position coordinates of the plurality of target chips based on the offset to obtain corrected second position coordinates; An ID code determination module, configured to determine a chip ID coordinate code of each of the target chips based on the size of each of the target chips and the corresponding second position coordinates; A coding coordinate determination module, used for determining a third position coordinate of the chip ID coordinate code of each of the target chips based on the first position coordinate of each of the target chips and a preset coding movement amount; The ID layout determination module is used to generate a chip ID layout based on the chip ID coordinate code of each target chip and the corresponding third position coordinates.

9. An electronic device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method for determining the chip ID layout as described in any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the method for determining the chip ID layout according to any one of claims 1 to 7.

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