Neural network architecture construction

Abstract

The invention discloses neural network architecture construction, and particularly discloses devices, systems and techniques for constructing neural network architectures. In at least one embodiment, candidate neural components may be selected for a neural network by jointly updating a performance metric mask attached to the candidate neural components and a joint neural network including all candidate neural components.

Description

Technical Field

[0001] At least one embodiment is directed to constructing a neural network architecture according to the various embodiments described herein. Background Art

[0002] The Neural Architecture Search (NAS) process selects neural elements (e.g., neural submodules and / or neural layers) to construct a specific neural network. Traditional NAS processes require multiple stages of pre-training, training, and evaluation of candidate neural elements, followed by a search for neural elements that meet certain performance requirements (e.g., accuracy, latency, etc.). This multi-stage training, evaluation, and search process is inefficient and computationally expensive. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 An example of updating a multi-dimensional performance indicator mask in a NAS process for building a neural network architecture according to at least one embodiment is shown;

[0004] Figure 2 shows the use of at least one embodiment Figure 1 An example of filtering candidate neural network components for building a neural network architecture using the updated multi-dimensional performance indicator mask described in

[15] ;

[0005] Figure 3 shows a calibration according to at least one embodiment Figure 2 An example of a neural network architecture constructed by selecting candidate neural network components as described in [1] to deploy on a target hardware platform;

[0006] Figures 4A-4B An example logical flow diagram illustrating a process for constructing a neural network architecture using multi-dimensional performance metric masks according to at least one embodiment is shown;

[0007] Figure 5 An implementation according to at least one embodiment is shown Figure 1-4B An example of a computing device built with the neural network architecture described in

[15] ;

[0008] Figure 6A illustrates logic according to at least one embodiment;

[0009] Figure 6B illustrates logic according to at least one embodiment;

[0010] Figure 7 illustrates the training and deployment of a neural network according to at least one embodiment;

[0011] Figure 8 An example data center system is shown in accordance with at least one embodiment;

[0012] Figure 9A An example of an autonomous vehicle according to at least one embodiment is shown;

[0013] Figure 9B According to at least one embodiment, Figure 9A Examples of camera positions and fields of view for autonomous vehicles;

[0014] Figure 9C According to at least one embodiment Figure 9A A block diagram of an example system architecture for an autonomous vehicle;

[0015] Figure 9D is a diagram illustrating a method for one or more cloud-based servers and Figure 9A A diagram of a system for communicating between autonomous vehicles;

[0016] Figure 10 is a block diagram illustrating a computer system according to at least one embodiment;

[0017] Figure 11 is a block diagram illustrating a computer system according to at least one embodiment;

[0018] Figure 12 A computer system according to at least one embodiment is shown;

[0019] Figure 13 A computer system according to at least one embodiment is shown;

[0020] Figure 14A A computer system according to at least one embodiment is shown;

[0021] Figure 14B A computer system according to at least one embodiment is shown;

[0022] Figure 14C A computer system according to at least one embodiment is shown;

[0023] Figure 14D A computer system according to at least one embodiment is shown;

[0024] Figure 14E and Figure 14F illustrates a shared programming model according to at least one embodiment;

[0025] Figure 15 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0026] Figures 16A-16B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0027] Figures 17A-17B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0028] Figure 18 A computer system according to at least one embodiment is shown;

[0029] Figure 19A A parallel processor according to at least one embodiment is shown;

[0030] Figure 19B shows a partition unit according to at least one embodiment;

[0031] Figure 19C illustrates a processing cluster according to at least one embodiment;

[0032] Figure 19D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0033] Figure 20 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0034] Figure 21 A graphics processor according to at least one embodiment is shown;

[0035] Figure 22 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0036] Figure 23 A deep learning application processor according to at least one embodiment is shown;

[0037] Figure 24 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0038] Figure 25 is a diagram illustrating at least a portion of a graphics processor according to at least one embodiment;

[0039] Figure 26 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0040] Figure 27 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0041] Figure 28 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0042] Figure 29 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0043] Figures 30A-30B Thread execution logic is shown that includes an array of processing elements of a graphics processor core, in accordance with at least one embodiment.

[0044] Figure 31 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0045] Figure 32 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0046] Figure 33 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0047] Figure 34 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0048] Figure 35 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0049] Figure 36 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0050] Figure 37 includes an example illustration of a high-level computational pipeline 3610A for processing imaging data in accordance with at least one embodiment;

[0051] Figure 38A including an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0052] Figure 38B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0053] Figure 39A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0054] Figure 39B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model, according to at least one embodiment.

[0055] Figure 40 is a system diagram illustrating a system for interfacing with an application program to process data, according to at least one embodiment. DETAILED DESCRIPTION

[0056] Figure 1An example of updating a multi-dimensional performance metric mask in a NAS process for building a neural network architecture according to at least one embodiment is shown. In at least one embodiment, a neural network architecture can be built based on neural components selected for one or more specific tasks (e.g., classification, retrieval, summarization, etc.). In at least one embodiment, the neural components can include various layers, such as attention layers, normalization layers, feedforward layers, projection layers, convolutional layers, recurrent layers, fully connected layers, etc., and the neural network architecture can refer to the specific arrangement and configuration of these layers.

[0057] In at least one embodiment, to construct a desired neural network architecture, a search space representing the space of all possible neural network architectures can be defined based on one or more tasks. In at least one embodiment, the search space can include different types of layers, their arrangements (e.g., connection patterns, network depth and width, etc.), hyperparameters (e.g., number of layers, kernel size, learning rate, etc.), and various other architectural choices. In at least one embodiment, a joint neural network 110, referred to as a "SuperNet," can be constructed that includes a union set of all possible neural network architectures within the search space. In at least one embodiment, for example, the SuperNet 110 can include input and position embedding layers 111, transformer blocks 112, a final projection layer 113, and the like.

[0058] In at least one embodiment, when constructing supernet 110, a conventional neural architecture search (NAS) process may pre-train supernet 110 on a training dataset related to one or more desired tasks. In at least one embodiment, the NAS process may then sample one or more candidate neural network architectures (referred to as "subnets") from the pre-trained supernet 110 during each training iteration. In at least one embodiment, the sampled candidate subnets may be trained during the training iterations. In at least one embodiment, after training is complete (e.g., after multiple training iterations), each candidate subnet may be evaluated to record its respective accuracy, which indicates a performance metric of the particular architecture of the candidate subnet in performing the one or more desired tasks. In at least one embodiment, the NAS process may select subnets that meet predefined performance metrics (e.g., accuracy) to form a neural network architecture. In at least one embodiment, the formed neural network architecture may be further fine-tuned on one or more training datasets to further improve accuracy, as the formed neural network architecture inherits weights from the trained subnets. In at least one embodiment, a conventional NAS process requires multiple stages, namely, pre-training the supernet 110, training the sampled subnets, and fine-tuning the selected subnets, which may be computationally inefficient. In at least one embodiment, a conventional NAS process may evaluate and provide performance metrics for the constructed neural network architecture only on the specific platform used to train and / or fine-tune the subnets, and lacks deployment efficiency across different hardware platforms.

[0059] In at least one embodiment, Figure 1 As shown, for example, when constructing a supernet 110, one or more multidimensional performance indicator masks 108 may be attached to the supernet 110. In at least one embodiment, the multidimensional performance indicator mask may be generated based on one or more performance requirements. In at least one embodiment, for example, when one or more performance requirements include the final accuracy and deployment latency requirements of the constructed neural network architecture, the multidimensional mask 108 may include at least a final accuracy mask 108a and a deployment latency mask 108b. In at least one embodiment, for another example, the multidimensional mask 108 may also include deployment throughput and consumed energy, etc.

[0060] In at least one embodiment, the multi-dimensional performance indicator mask 108 can be attached to each possible neural network architecture (e.g., subnet) within the supernet 110 for joint training. Figure 1As shown, at least a portion of the input and positioning layer 111, a portion of the transformer block 112, and a portion of the final projection layer 113 can affect the final accuracy metric 108a of the neural network architecture. In at least one embodiment, at least a portion of the input and positioning layer 111, a portion of the transformer block 112, and a portion of the final projection layer 113 can affect the deployment latency metric 108b of the neural network architecture. In at least one embodiment, the multi-dimensional performance metric mask 108, including the final accuracy mask 108a and the deployment latency mask 108b, can be updated during training of the supernet 110.

[0061] In at least one embodiment, the supernet 110 can be jointly trained using input images 102 from a training dataset and the performance metric mask 108 can be updated. In at least one embodiment, a random subset of the weights of the supernet 110 can be masked during each training iteration. In at least one embodiment, the supernet 110 can be trained in a mask-based autoencoder (MAE) manner as follows: a random portion of the input image 102 can be masked and input to the supernet 110; the supernet 110 can encode the masked input image and then reconstruct an image including a predicted portion corresponding to the random masked portion of the input image 102; and a training loss 115 can be calculated by comparing the reconstructed image from the supernet 110 with the original input image 102. In at least one embodiment, the training loss 115 can be calculated as a cross-entropy loss between the reconstructed image and the unmasked input image 102.

[0062] In at least one embodiment, the training loss 115 may be used to update the unmasked weights of the supernet 110 during each training iteration. In at least one embodiment, the training loss 115 may be used to update the final accuracy mask 108a attached to each candidate neural network architecture within the supernet 110 because the training loss 115 indicates the difference between the reconstructed image and the unmasked input image 102 and therefore serves as an indicator of accuracy.

[0063] In at least one embodiment, at the end of each training iteration, other performance metrics, such as the deployment delay mask 108 b , may be updated based on simulation results of the updated supernet 110 implemented on the hardware simulator 118 .

[0064] Figure 2 shows the use of at least one embodiment Figure 1 In at least one embodiment, the updated multi-dimensional performance indicator mask described in the embodiment is used to screen candidate neural network components for building a neural network architecture. Figure 1As described in , during joint training of a supernet 110 comprising various candidate neural network architectures (“subnets”) 212a-n, performance metric masks 208a-n respectively attached to the subnet candidates 212a-n may be updated, either based on the training loss 115 computed at each training iteration or based on simulating the updated supernet 110 on a hardware simulator 118 at the end of each training iteration.

[0065] In at least one embodiment, when training of supernet 110 is complete (e.g., a predefined number of training iterations are completed, training loss is less than a predefined threshold, and / or other predefined criteria are met), only subnet candidates that meet desired metric 211 can be selected from subnet candidates 212a-n based on their performance metric masks 208a-n. In at least one embodiment, for example, subnet candidates 213a-b representing neural network architectures that meet desired metric 211 (e.g., final accuracy no less than a predefined accuracy threshold, deployment latency no greater than a predefined latency threshold, etc.) can be selected to construct the final neural network architecture.

[0066] Figure 3 shows a calibration according to at least one embodiment Figure 2 10. The example of a neural network architecture constructed by deploying the selected candidate neural network components described in the embodiment of the present invention on a target hardware platform. In at least one embodiment, the selected subnet candidates (e.g., 213a-b) can be run as a dry run on the target hardware platform to collect actual deployment performance metrics so that any mismatch in performance can be calibrated. In at least one embodiment, for example, although the selected subnet candidates (e.g., 213a-b) can be attached with performance metric masks updated during training, due to cross-layer overhead and / or fusion advantages when jointly trained within the supernet 110, the performance of each selected subnet candidate (e.g., 213a or 213b) when deployed may be different from the performance indicated in its performance metric mask.

[0067] In at least one embodiment, for example, the selected subnet candidate 213a may include input and positioning embedding layers, a transformer block, a final projection layer, and the like. In at least one embodiment, the selected subnet candidate 213a may be placed in a commissioning run 305, during which a test input image 102 may be input to the selected subnet 213a implemented on the target hardware platform 310. In at least one embodiment, the performance metrics (e.g., final accuracy, deployment latency on the target hardware platform 310, etc.) of the selected subnet 213a may be calibrated at a calibration module 320 based on the performance during the commissioning run 305. In at least one embodiment, after calibration 320, the calibrated subnet candidate 213a may be sent for deployment on the target hardware platform 330.

[0068] In at least one embodiment, since different selected subnetwork candidates can be calibrated for different target hardware platforms, the deployment efficiency of the resulting neural network architecture on different target hardware platforms can be improved.

[0069] Figures 4A-4B An example logic flow diagram of a process for constructing a neural network architecture using a multi-dimensional performance indicator mask according to at least one embodiment is provided. In at least one embodiment, it is noted that although reference is made to Figure 1-3 The embodiment described, but process 400 is not limited to Figure 1-3 In at least one embodiment, process 400 may be implemented at least in part in the form of executable code stored on a non-transitory, tangible, machine-readable medium that, when executed by one or more processors, may cause the one or more processors to perform one or more processes. In at least one embodiment, process 400 may correspond to Figure 5 Example operations performed by the neural network building module 530.

[0070] In at least one embodiment, process 400 may begin at step 401, where a joint neural network (e.g., Figure 1 In at least one embodiment, for example, the candidate neural components may include any of a neural layer, a neural block, a neural network architecture, and the like.

[0071] In at least one embodiment, process 400 may proceed to step 403, where the joint neural network may be trained. In at least one embodiment, process 400 may proceed to step 405, where training may include training a joint neural network based at least in part on a network composed of a joint neural network with random masking weights (e.g., Figure 1 The supernet 110 in FIG. 1 is responsive to an input of a random masked image (e.g., Figure 1 The training output generated by the input image 102 in the training image is used to calculate the training loss (e.g., Figure 1 115 in ). In at least one embodiment, a subset of the weights of the joint neural network can be masked in each training iteration. In at least one embodiment, the training loss can be calculated as a MAE loss, such as Figure 1 The training loss is described in 115.

[0072] In at least one embodiment, process 400 may proceed to step 407, where the unmasked weights of the joint neural network may be updated based on the training loss in each training iteration. Additional details of training the neural network based on the loss may be found in at least one embodiment. Figure 8 described in .

[0073] In at least one embodiment, process 400 may proceed to step 409, where a multi-dimensional performance indicator mask (e.g., Figure 1 108) in the network accuracy metrics (e.g., Figure 1 In at least one embodiment, at least one of the one or more performance indicator masks is a multidimensional vector comprising a plurality of performance indicators of at least a portion of the neural network. In at least one embodiment, each performance indicator mask may be associated with one or more neural components (e.g., Figure 2 associated with the subnets 212a-n in FIG.

[0074] In at least one embodiment, process 400 may proceed to step 411 where the training may be performed on a hardware simulator (e.g., Figure 1 118 in ) to run one or more parts of the neural network with updated weights to update one or more performance indicator masks (e.g., Figure 1 108) in other performance indicators (e.g., Figure 1 108b).

[0075] In at least one embodiment, process 400 may proceed to step 413, where process 400 determines whether the training iteration is complete. In at least one embodiment, when the training iteration is not complete, process 400 may continue training at step 403. In at least one embodiment, when the training iteration is not complete, process 400 may proceed to step 414. Figure 4B In step 417, in which one or more performance indicator masks (e.g., Figure 2 208a-n) may be associated with one or more target performance indicators (e.g., Figure 2 211) in for comparison.

[0076] In at least one embodiment, process 400 may proceed to step 419, where process 400 determines whether the target metric is met. In at least one embodiment, when the target metric is not met, process 400 may proceed to step 421, where unsatisfactory neural components may be discarded. In at least one embodiment, when the target metric is met, process 400 may proceed to step 423, where one or more neural components (e.g., Figure 2 The subnetworks 213a-b in the CNN are used as one or more parts of one or more neural networks to generate one or more neural networks.

[0077] In at least one embodiment, process 400 may proceed to step 425 where the one or more constructed neural networks may be run on a target hardware platform (e.g., Figure 3 310) on the test run (for example, Figure 3 In at least one embodiment, for example, one or more constructed neural network inferences can be operated in response to test inputs on a target hardware platform to perform inference, and performance metrics can be collected.

[0078] In at least one embodiment, process 400 may proceed to step 427 where one or more constructed neural networks may be deployed on a target hardware platform.

[0079] Figure 5 An implementation according to at least one embodiment is shown Figure 1-4B In at least one embodiment, for example, Figure 5 As shown, computing device 500 may include a processor 510 coupled to a memory 520. In at least one embodiment, the operation of computing device 500 may be controlled by processor 510.

[0080] In at least one embodiment, it is noted that although Figure 5 The computing device 500 shown in FIG. 5 has only one processor 510. In at least one embodiment, it will be appreciated that the processor 510 may represent one or more central processing units, multi-core processors, microprocessors, microcontrollers, digital signal processors, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), graphics processing units (GPUs), etc., in the computing device 500. In at least one embodiment, the computing device 500 may be implemented as a standalone subsystem, a board added to a computing device, and / or a virtual machine.

[0081] In at least one embodiment, memory 520 may be used to store software executed by computing device 500 and / or one or more data structures used during operation of computing device 500. In at least one embodiment, memory 520 may include one or more types of machine-readable media, such as, but not limited to, a floppy disk, a flexible disk, a hard disk, magnetic tape, any other magnetic medium, a CD-ROM, any other optical medium, punch cards, paper tape, any other physical medium having a pattern of holes, RAM, PROM, EPROM, FLASH-EPROM, any other memory chip or cartridge, and / or any other medium suitable for reading by a processor or computer.

[0082] In at least one embodiment, the memory 520 may include a non-transitory, tangible, machine-readable medium including executable code that, when executed by one or more processors (e.g., processor 510), may cause the one or more processors to perform the methods and / or processes described in further detail herein, e.g. Figure 3 In at least one embodiment, for example, memory 520 may include instructions for a neural network building module 530 that may be used to implement and / or simulate a neural network building module. Figure 1-3 Various embodiments and / or implementations described in Figures 4A-4B Any of the methods and processes 400 described in.

[0083] In at least one embodiment, the neural network construction module 530 may receive input 540 via the data interface 515, such as an input image (e.g., Figure 1 112 in ), and generates an output 550, which can be any training output depending on the training task.

[0084] In at least one embodiment, the data interface 515 may include a communication interface, a user interface (e.g., a voice input interface, a graphical user interface, etc.), etc. In at least one embodiment, for example, the computing device 500 may receive input 540 (e.g., Figure 1 In at least one embodiment, computing device 500 may receive input 540, as another example, by a user uploading a test input image via a user interface, or the like.

[0085] In at least one embodiment, the neural network building module 530 may also include a supernet submodule 531 (e.g., similar to Figure 1 110 in, or Figure 2 210 in) (the supernet submodule also includes subnets 531a-n (similar to Figure 2 212a-n in ), data preprocessing submodule 531, neural network submodule 531 (e.g., similar to Figure 1 110)) and the selection submodule 532, the calibration submodule 533 (e.g., similar to Figure 3 320 in) and so on.

[0086] In at least one embodiment, the supernet submodule 531 may execute Figures 4A-4B At least one or more steps 401-413 of process 400 in FIG. In at least one embodiment, the selection submodule 532 may perform Figures 4A-4B In at least one embodiment, the calibration submodule 533 may perform at least one or more steps 417-423 of the process 400. Figures 4A-4B At least one or more steps 425 of process 400 in.

[0087] logic

[0088] Figure 6A 6 shows logic 615 that can be used in one or more devices to perform operations such as those discussed herein, as described elsewhere herein, in accordance with at least one embodiment. In at least one embodiment, logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic 615 is reasoning and / or training logic. Details regarding logic 615 will be discussed below in conjunction with Figure 6A and / or Figure 6B In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic for providing the functionality or operations described herein, where the logic may collectively or individually be embodied as circuitry forming part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU)).

[0089] In at least one embodiment, logic 615 may include, but is not limited to, code and / or data storage 601 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 615 may include or be coupled to code and / or data storage 601 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 601 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 601 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0090] In at least one embodiment, any portion of code and / or data storage 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 601 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 601 is internal or external to a processor, e.g., or including DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0091] In at least one embodiment, logic 615 may include, but is not limited to, code and / or data storage 605 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 605 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 615 may include or be coupled to code and / or data storage 605 for storing graph code or other software to control the timing and / or sequence in which weight and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0092] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 605 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 605 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 605 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 605 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, can depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0093] In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be separate storage structures. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be the same storage structure. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 601 and code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0094] In at least one embodiment, logic 615 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 610 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 620, which are functions of input / output and / or weight parameter data stored in code and / or data storage 601 and / or code and / or data storage 605. In at least one embodiment, the activations stored in activation storage 620 are generated based on linear algebra and / or matrix-based math performed by ALU 610 in response to executing instructions or other code, with weight values ​​stored in code and / or data storage 605 and / or code and / or data storage 601 used as operands, as well as other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 605 or code and / or data storage 601 or other on-chip or off-chip storage.

[0095] In at least one embodiment, one or more ALUs 610 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 610 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALUs 610 may be included within the execution units of a processor or otherwise included in an ALU bank accessible by the execution units of the processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 601, code and / or data storage 605, and activation storage 620 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 620 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0096] In at least one embodiment, activation storage 620 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 620 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 620 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage on-chip versus off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0097] In at least one embodiment, Figure 6A The logic 615 shown in FIG. 6 may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6A The illustrated logic 615 may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware such as a field programmable gate array ("FPGA").

[0098] Figure 6B Logic 615 is shown in accordance with at least one embodiment. In at least one embodiment, logic 615 is inference and / or training logic. In at least one embodiment, logic 615 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise used exclusively with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 6B The logic 615 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6BThe logic 615 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, logic 615 includes, but is not limited to, code and / or data storage 601 and code and / or data storage 605, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 6B In at least one embodiment shown in FIG, code and / or data storage 601 and code and / or data storage 605 are each associated with dedicated computing resources, such as computing hardware 602 and computing hardware 606, respectively. In at least one embodiment, computing hardware 602 and computing hardware 606 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 601 and code and / or data storage 605, respectively, with the results being stored in activation storage 620.

[0099] In at least one embodiment, each of the code and / or data stores 601 and 605 and the corresponding computing hardware 602 and 606 corresponds to a different layer of a neural network, such that activations from one storage / computation pair 601 / 602 of the code and / or data store 601 and computing hardware 602 are provided as inputs to the next storage / computation pair 605 / 606 of the code and / or data store 605 and computing hardware 606, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 601 / 602 and 605 / 606 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 615 after or in parallel with the storage / computation pairs 601 / 602 and 605 / 606.

[0100] In at least one embodiment, logic 615 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0101] Neural network training and deployment

[0102] Figure 7The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 706 is trained using a training dataset 702. In at least one embodiment, the training framework 704 is the PyTorch framework, while in other embodiments, the training framework 704 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 704 trains the untrained neural network 706 and allows it to be trained using the processing resources described herein to generate a trained neural network 708.

[0103] In at least one embodiment, during the forward propagation of one or more neural networks 706, training data 702 (e.g., input images) is fed into one or more neural networks 706. In at least one embodiment, the training data can flow through multiple layers of the one or more neural networks, where each layer performs calculations based on its weights, biases, and activation functions until the output layer of the one or more neural networks produces an output (e.g., an embedding of the input image). In at least one embodiment, the output generated by the output layer can be used to calculate a loss function.

[0104] In at least one embodiment, given the calculated loss, the negative gradient of the loss can be calculated for each weight of each layer of the one or more neural networks 706. In at least one embodiment, such negative gradients can be calculated one layer at a time, iteratively from the last layer of the neural network back to the input layer of the neural network. In at least one embodiment, these gradients can quantify the sensitivity of the output of the neural network to changes in its parameters. In at least one embodiment, the chain rule of calculus can be applied to efficiently calculate these gradients by backpropagating the gradients from the output layer of the neural network to the input layer of the neural network.

[0105] In at least one embodiment, the parameters of the neural network 706 can be updated backward from the last layer to the input layer (back propagation) using an optimization algorithm based on the calculated negative gradient of the loss to minimize the loss. In at least one embodiment, back propagation from the last layer to the input layer can be performed for multiple training samples in multiple iterative training epochs. In at least one embodiment, the parameters of the neural network can be gradually updated in a direction that results in a smaller loss or minimized loss, indicating that the neural network with the updated parameters has been trained to generate predicted output values ​​that are closer to the target defined by the structure of the specific loss with improved accuracy.

[0106] In at least one embodiment, training can continue until a stopping criterion is met, such as reaching a maximum number of epochs or achieving satisfactory performance on validation data. In at least one embodiment, the trained network 708 can be used to make predictions on new, unseen data.

[0107] In at least one embodiment, the training framework 704 can transform one or more neural networks into one or more "updated" trained neural networks, in which parameters such as weights, activation functions, and biases are updated. In at least one embodiment, the trained neural network can be able to perform tasks that the untrained neural network 706 was unable to perform or achieved only unsatisfactory performance before training (such as, Figure 1 As a result, neural network techniques have improved.

[0108] In at least one embodiment, neural network parameters can be trained in multiple stages. For example, initial training (e.g., pre-training) can be performed on a training dataset, and then additional training stages (e.g., fine-tuning) can be performed using different training datasets. In at least one embodiment, all or part of the parameters of one or more neural network models used together can be frozen, so that the "frozen" parameters are not updated during that training stage. For example, this can allow for training of a smaller subset of parameters without the computational cost of updating all parameters.

[0109] In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, partially supervised, or unsupervised manner.

[0110] In at least one embodiment, untrained neural network 706 is trained using supervised learning, where training dataset 702 includes inputs paired with expected outputs for the inputs, or where training dataset 702 includes inputs with known outputs and the outputs of neural network 706 are manually graded. In at least one embodiment, untrained neural network 706 is trained in a supervised manner, processing inputs from training dataset 702 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through untrained neural network 706. In at least one embodiment, training framework 704 adjusts the weights that control untrained neural network 706. In at least one embodiment, training framework 704 includes tools for monitoring the degree to which untrained neural network 706 converges toward a model (such as trained neural network 708) suitable for generating correct answers (such as results 714) based on input data (such as new dataset 712). In at least one embodiment, the training framework 704 repeatedly trains the untrained neural network 706 while adjusting the weights to refine the output of the untrained neural network 706 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 704 trains the untrained neural network 706 until the untrained neural network 706 reaches a desired accuracy. In at least one embodiment, the trained neural network 708 can then be deployed to implement any number of machine learning operations.

[0111] In at least one embodiment, unsupervised learning is used to train the untrained neural network 706, wherein the untrained neural network 706 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 702 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 706 can learn the groupings within the training dataset 702 and can determine how the individual inputs relate to the untrained dataset 702. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 708, which can perform operations useful for reducing the dimensionality of the new dataset 712. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the new dataset 712 that deviate from the normal pattern of the new dataset 712.

[0112] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 702. In at least one embodiment, the training framework 704 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 708 to adapt to new datasets 712 without forgetting the knowledge that was infused into the trained neural network 708 during initial training.

[0113] In at least one embodiment, the training framework 704 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 615 or uses logic 615 to perform the operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0114] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations (such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof). In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0115] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image restoration, style transfer, action recognition, colorization, and / or their variants.

[0116] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes a neural network model for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's inputs (e.g., resizing the model's inputs), modifying the size of the model's inputs (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalization, standardization, quantization (e.g., converting the model's weights from a first representation, such as floating point, to a second representation, such as integers), and / or variants thereof.

[0117] In at least one embodiment, OpenVINO includes one or more software libraries for reasoning, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to reason about input data. In at least one embodiment, the inference engine implements various classes to reason about input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0118] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (for example, executing a first set of layers on a first device (e.g., a GPU) and executing a second set of layers on a second device (e.g., a CPU)).

[0119] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0120] In at least one embodiment, the training framework 704 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0121] Data Center

[0122] Figure 8 An exemplary data center 800 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 800 includes a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840.

[0123] In at least one embodiment, Figure 8As shown, the data center infrastructure layer 810 may include a resource coordinator 812, grouped computing resources 814, and node computing resources ("node CRs") 816(1)-816(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 816(1)-816(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 818(1)-818(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 816(1)-816(N) may be a server having one or more of the above-mentioned computing resources.

[0124] In at least one embodiment, the grouped computing resources 814 may include separate groups of node CRs housed in one or more racks (not shown), or may be housed in many racks in data centers (also not shown) at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 814 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0125] In at least one embodiment, resource coordinator 812 may configure or otherwise control one or more node CRs 816(1)-816(N) and / or grouped computing resources 814. In at least one embodiment, resource coordinator 812 may comprise a software design infrastructure ("SDI") management entity for data center 800. In at least one embodiment, resource coordinator 812 may comprise hardware, software, or some combination thereof.

[0126] In at least one embodiment, Figure 8As shown, the framework layer 820 includes a job scheduler 822, a configuration manager 824, a resource manager 826, and a distributed file system 828. In at least one embodiment, the framework layer 820 may include a framework that supports software 832 of the software layer 830 and / or one or more applications 842 of the application layer 840. In at least one embodiment, the software 832 or the application 842 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 820 may be, but is not limited to, a type of free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 828 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 822 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 800. In at least one embodiment, the configuration manager 824 may be capable of configuring different layers, such as the software layer 830 and the framework layer 820 including Spark and a distributed file system 828 for supporting large-scale data processing. In at least one embodiment, the resource manager 826 may be capable of managing the mapping or allocation of clustered or grouped computing resources used to support the distributed file system 828 and the job scheduler 822. In at least one embodiment, the clustered or grouped computing resources may include the grouped computing resources 814 at the data center infrastructure layer 810. In at least one embodiment, the resource manager 826 may coordinate with the resource coordinator 812 to manage these mapped or allocated computing resources.

[0127] In at least one embodiment, the software 832 included in the software layer 830 may include software used by at least portions of the node CRs 816(1)-816(N), the grouped computing resources 814, and / or the distributed file system 828 of the framework layer 820. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0128] In at least one embodiment, the one or more applications 842 included in the application layer 840 may include one or more types of applications used by at least portions of the node CRs 816(1)-816(N), the grouped computing resources 814, and / or the distributed file system 828 of the framework layer 820. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0129] In at least one embodiment, any of the configuration manager 824, resource manager 826, and resource coordinator 812 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of the data center 800 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0130] In at least one embodiment, data center 800 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 800. In at least one embodiment, the resources described above with respect to data center 800 may be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks using weight parameters calculated using one or more training techniques described herein.

[0131] In at least one embodiment, the data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0132] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BDetails are provided regarding logic 615. In at least one embodiment, logic 615 can be used in data center 800 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0133] In at least one embodiment, the various components of data center 800 may be used to: Figure 1-5 The neural network architecture described in

[15] is constructed.

[0134] autonomous vehicles

[0135] Figure 9A An example of an autonomous vehicle 900 according to at least one embodiment is shown. In at least one embodiment, autonomous vehicle 900 (alternatively referred to herein as "vehicle 900") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 900 can be a semi-tractor-trailer truck for hauling cargo. In at least one embodiment, vehicle 900 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0136] An autonomous vehicle may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation, “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of the standard). In at least one embodiment, the vehicle 900 may be capable of one or more of Levels 1 to 5 according to the autonomous driving levels. For example, in at least one embodiment, the vehicle 900 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0137] In at least one embodiment, the vehicle 900 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 900 may include, but is not limited to, a propulsion system 950, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 950 may be connected to a drive train of the vehicle 900, which may include, but is not limited to, a transmission, for enabling propulsion of the vehicle 900. In at least one embodiment, the propulsion system 950 may be controlled in response to receiving a signal from a throttle / accelerator 952.

[0138] In at least one embodiment, when propulsion system 950 is operating (e.g., when vehicle 900 is in motion), a steering system 954 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 900 (e.g., along a desired path or route). In at least one embodiment, steering system 954 may receive signals from steering actuator 956. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 946 may be used to operate vehicle brakes in response to signals received from brake actuator 948 and / or brake sensors.

[0139] In at least one embodiment, one or more controllers 936, which may include, but are not limited to, one or more system-on-chips ("SoCs") ( Figure 9A ) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representing commands) to one or more components and / or systems of the vehicle 900. For example, in at least one embodiment, the one or more controllers 936 can send signals to operate vehicle brakes via brake actuator 948, operate steering system 954 via one or more steering actuators 956, and operate propulsion system 950 via one or more throttle / accelerator 952. In at least one embodiment, the one or more controllers 936 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle 900. In at least one embodiment, the one or more controllers 936 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0140] In at least one embodiment, the one or more controllers 936 provide signals for controlling one or more components and / or systems of the vehicle 900 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 958 (e.g., one or more global positioning system sensors), one or more RADAR sensors 960, one or more ultrasonic sensors 962, one or more LIDAR sensors 964, one or more inertial measurement unit (IMU) sensors 966 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 996, one or more stereo cameras 968, one or more wide angle cameras 970 (e.g., fisheye cameras), one or more infrared cameras 972, one or more surround cameras 974 (e.g., 360 degree cameras), long range cameras (e.g., infrared cameras), and / or a combination of these. Figure 9A Not shown), mid-range camera ( Figure 9A ), one or more speed sensors 944 (e.g., for measuring the speed of the vehicle 900), one or more vibration sensors 942, one or more steering sensors 940, one or more brake sensors (e.g., as part of a brake sensor system 946), and / or other sensor types.

[0141] In at least one embodiment, one or more controllers 936 may receive input (e.g., represented by input data) from a dashboard 932 of the vehicle 900 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 934, an audible annunciator, a speaker, and / or via other components of the vehicle 900. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 9A ), location data (e.g., the location of the vehicle 900, such as on a map), directions, the locations of other vehicles (e.g., an occupancy grid), information about objects and the states of objects sensed by the one or more controllers 936, etc. For example, in at least one embodiment, the HMI display 934 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0142] In at least one embodiment, the vehicle 900 further includes a network interface 924 that can communicate over one or more networks using one or more wireless antennas 926 and / or one or more modems. For example, in at least one embodiment, the network interface 924 can be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 926 can also use one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks ("LPWAN") (such as LoRaWAN, SigFox, etc. protocols) to enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.).

[0143] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, logic 615 can be used in vehicle 900 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0144] In at least one embodiment, the various components of vehicle 900 may be used as follows: Figure 1-5 The neural network architecture described in

[15] is constructed.

[0145] Figure 9B According to at least one embodiment, Figure 9A Examples of camera positions and fields of view for autonomous vehicle 900 are shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on vehicle 900.

[0146] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 900. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-clear-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0147] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0148] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to remove stray light and reflected light from within the vehicle 900 (e.g., reflected light from the dashboard reflecting in the windshield mirror), which may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cabin.

[0149] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes portions of the environment in front of the vehicle 900 can be used for surround vision to help identify the path ahead and obstacles, as well as to assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the assistance of one or more controllers 936 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (such as traffic sign recognition).

[0150] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 970 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 9B Only one wide-angle camera 970 is shown, but in other embodiments, there can be any number (including zero) of wide-angle cameras on the vehicle 900. In at least one embodiment, any number of remote cameras 998 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 998 can also be used for object detection and classification and basic object tracking.

[0151] In at least one embodiment, any number of stereo cameras 968 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 968 may include an integrated control unit including an extensible processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a controller area network ("CAN") or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 900, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 968 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 900 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 968 may be used in addition to or in place of those described herein.

[0152] In at least one embodiment, cameras having a field of view of portions of the environment including the sides of the vehicle 900 (e.g., side view cameras) can be used for surround view, which provides information for creating and updating the occupancy grid and generating side impact collision warnings. For example, in at least one embodiment, the surround camera 974 (e.g., Figure 9B The four surround cameras (shown) can be positioned on the vehicle 900. In at least one embodiment, the one or more surround cameras 974 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, the four fisheye cameras can be located on the front, rear, and sides of the vehicle 900. In at least one embodiment, the vehicle 900 can use three surround cameras 974 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0153] In at least one embodiment, a camera having a field of view that includes portions of the environment behind the vehicle 900 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 998 and / or one or more mid-range cameras 976, one or more stereo cameras 968, one or more infrared cameras 972, etc.), as described herein.

[0154] In at least one embodiment, Figure 9B The various components of vehicle 900 shown in FIG. 9 may be used for multi-GPU training of a neural network.

[0155] Figure 9C is a diagram showing a method according to at least one embodiment Figure 9A A block diagram of an exemplary system architecture of an autonomous vehicle 900 is provided. In at least one embodiment, Figure 9CEach of the components, features, and systems of the vehicle 900 is shown as being connected via a bus 902. In at least one embodiment, the bus 902 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, the CAN may be a network internal to the vehicle 900 that assists in controlling various features and functions of the vehicle 900, such as brake actuation, acceleration, braking, steering, wipers, etc. In at least one embodiment, the bus 902 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 902 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, the bus 902 may be a CAN bus that complies with ASIL B.

[0156] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or in place of CAN. In at least one embodiment, any number of buses may form bus 902, including, but not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 902 may communicate with any component of vehicle 900, and two or more buses in bus 902 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chips ("SoCs") 904 (e.g., SoC 904(A) and SoC 904(B)), each of one or more controllers 936, and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors in vehicle 900) and may be connected to a common bus, such as a CAN bus.

[0157] In at least one embodiment, the vehicle 900 may include one or more controllers 936, such as those described herein with respect to Figure 9A In at least one embodiment, the controller 936 can be used for a variety of functions. In at least one embodiment, the controller 936 can be coupled to any of the various other components and systems of the vehicle 900 and can be used to control the vehicle 900, the artificial intelligence of the vehicle 900, the infotainment and / or other functions of the vehicle 900.

[0158] In at least one embodiment, the vehicle 900 may include any number of SoCs 904. In at least one embodiment, each of the SoCs 904 may include, but is not limited to, a central processing unit ("CPU(s)") 906, a graphics processing unit ("GPU(s")) 908, one or more processors 910, one or more caches 912, one or more accelerators 914, one or more data stores 916, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 904 may be used to control the vehicle 900 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 904 may be combined in a system (e.g., a system of the vehicle 900) along with a high-definition ("HD") map 922 that may be downloaded from one or more servers (e.g., a system of the vehicle 900) via a network interface 924. Figure 9C ) to obtain map refreshes and / or updates.

[0159] In at least one embodiment, one or more CPUs 906 may include a CPU cluster or CPU complex (alternatively referred to herein as "CCPLEX"). In at least one embodiment, one or more CPUs 906 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 906 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 906 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 906 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, such that any combination of clusters of one or more CPUs 906 may be active at any given time.

[0160] In at least one embodiment, one or more CPUs 906 may implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware blocks when idle to save dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 906 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein the work is offloaded to the microcode.

[0161] In at least one embodiment, one or more GPUs 908 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 908 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 908 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 908 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 908 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 908 may use one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 908 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0162] In at least one embodiment, one or more GPUs 908 may be power optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 908 may be fabricated on fin field effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler), or a sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for providing efficient execution of workloads using a mix of compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor can include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0163] In at least one embodiment, one or more GPUs 908 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, in some examples configured to provide a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in place of HBM memory.

[0164] In at least one embodiment, one or more GPUs 908 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 908 to directly access one or more CPU 906 page tables. In at least one embodiment, when the memory management unit ("MMU") of a GPU in one or more GPUs 908 experiences a miss, an address translation request may be sent to one or more CPUs 906. In response, in at least one embodiment, two of the one or more CPUs 906 may look up the virtual-to-physical mapping of the address in their page tables and send the translation back to the one or more GPUs 908. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 906 and the one or more GPUs 908, thereby simplifying programming the one or more GPUs 908 and porting applications to the one or more GPUs 908.

[0165] In at least one embodiment, one or more GPUs 908 may include any number of access counters that can track the frequency of accesses to other processors' memory by one or more GPUs 908. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of sharing memory ranges between processors.

[0166] In at least one embodiment, one or more SoCs 904 may include any number of caches 912, including those described herein. For example, in at least one embodiment, one or more caches 912 may include a level 3 ("L3") cache that may be used for both (e.g., connected to) one or more CPUs 906 and one or more GPUs 908. In at least one embodiment, one or more caches 912 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0167] In at least one embodiment, one or more SoCs 904 may include one or more accelerators 914 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 904 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 908 and offload some tasks of one or more GPUs 908 (e.g., to free up more cycles of one or more GPUs 908 to perform other tasks). In at least one embodiment, one or more accelerators 914 may be used for target workloads that are sufficiently stable to withstand acceleration (e.g., perception, convolutional neural networks ("CNN"), recurrent neural networks ("RNN"), etc.). In at least one embodiment, the CNN may include a region-based or region-based convolutional neural network ("RCNN") and a fast RCNN (e.g., as used for object detection) or other types of CNN.

[0168] In at least one embodiment, one or more accelerators 914 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for protection and / or safety related events.

[0169] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 908, and by using an inference accelerator, for example, a designer can target any function to one or more DLAs or one or more GPUs 908. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 908 and / or one or more accelerators 914.

[0170] In at least one embodiment, one or more accelerators 914 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 938, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0171] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0172] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 906. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0173] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as, for example, a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0174] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0175] In at least one embodiment, one or more accelerators 914 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 914. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0176] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may conform to the International Organization for Standardization ("ISO") 26262 or the International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0177] In at least one embodiment, one or more SoCs 904 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0178] In at least one embodiment, one or more accelerators 914 may have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power and low latency is well matched to the domain of algorithms that require predictable processing. In other words, the PVA excels at semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, such as in the vehicle 900, the PVA may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0179] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0180] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used to perform time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0181] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measurement for each object detection. In at least one embodiment, the confidence can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a high confidence detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 966 associated with vehicle 900 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 964 or one or more RADAR sensors 960).

[0182] In at least one embodiment, one or more SoCs 904 may include one or more data stores 916 (e.g., memory). In at least one embodiment, one or more data stores 916 may be on-chip memory of one or more SoCs 904 that may store neural networks to be executed on one or more GPUs 908 and / or DLAs. In at least one embodiment, one or more data stores 916 may have a capacity large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, one or more data stores 916 may include one or more L2 or L3 caches.

[0183] In at least one embodiment, one or more SoCs 904 may include any number of processors 910 (e.g., embedded processors). In at least one embodiment, one or more processors 910 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 904 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low power state transitions, one or more SoCs 904 thermal and temperature sensor management, and / or one or more SoCs 904 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 904 may use the ring oscillator to detect the temperature of one or more CPUs 906, one or more GPUs 908, and / or one or more accelerators 914. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 904 into a lower power state and / or place the vehicle 900 into a driver's safe parking mode (e.g., bringing the vehicle 900 to a safe stop).

[0184] In at least one embodiment, one or more processors 910 may further include a set of embedded processors that can serve as an audio processing engine, which can be an audio subsystem that implements full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0185] In at least one embodiment, one or more processors 910 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0186] In at least one embodiment, one or more processors 910 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 910 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 910 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0187] In at least one embodiment, one or more processors 910 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce a final image for use in a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 970, one or more surround cameras 974, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 904, the neural network being configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode that would otherwise be disabled.

[0188] In at least one embodiment, the video image compositor can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the presence of motion in the video, the noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, in the presence of motion in the image or portion of an image, the temporal noise reduction performed by the video image compositor can use information from previous images to reduce noise in the current image.

[0189] In at least one embodiment, the video image compositor can also be configured to perform stereo rectification on the input stereo footage frames. In at least one embodiment, the video image compositor can also be used for user interface composition when the operating system desktop is being used, and does not require the one or more GPUs 908 to continuously render new surfaces. In at least one embodiment, when the one or more GPUs 908 are powered and active for 3D rendering, the video image compositor can be used to offload the one or more GPUs 908 to improve performance and responsiveness.

[0190] In at least one embodiment, one or more of the SoCs 904 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 904 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0191] In at least one embodiment, one or more of the SoCs 904 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 904 may be configured to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 964, one or more RADAR sensors 960, etc., which may be connected via an Ethernet channel), data from the bus 902 (e.g., vehicle 900 speed, steering wheel position, etc.), data from one or more GNSS sensors 958 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 904 may further include dedicated high-performance large-scale storage controllers, which may include their own DMA engines and may be used to offload one or more of the CPUs 906 from routine data management tasks.

[0192] In at least one embodiment, one or more SoCs 904 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for flexible, reliable driving software stacks and deep learning tools. In at least one embodiment, one or more SoCs 904 can be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 914, when combined with one or more CPUs 906, one or more GPUs 908, and one or more data stores 916, can provide a fast, efficient platform for level 3-5 autonomous vehicles.

[0193] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on various visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles.

[0194] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 920) may include text and word recognition, thereby allowing for the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of signs, and passing this semantic understanding to a path planning module running on the CPU complex.

[0195] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions," along with electric lights, can be interpreted independently or collectively by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 908.

[0196] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 900. In at least one embodiment, an always-on sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 904 provide protection against theft and / or carjacking.

[0197] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 996 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 904 use CNNs to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approaching speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, a CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 958. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 962 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0198] In at least one embodiment, the vehicle 900 may include one or more CPUs 918 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 904 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 918 may include, for example, an X86 processor. The one or more CPUs 918 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the one or more SoCs 904, and / or monitoring the status and health of one or more controllers 936 and / or an infotainment system on a chip ("infotainment SoC") 930. In at least one embodiment, the one or more SoCs 904 include one or more interconnects, and the interconnects may include Peripheral Component Interconnect Express (PCIe).

[0199] In at least one embodiment, the vehicle 900 may include one or more GPUs 920 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 904 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 920 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input from sensors of the vehicle 900 (e.g., sensor data).

[0200] In at least one embodiment, the vehicle 900 may further include a network interface 924, which may include, but is not limited to, one or more wireless antennas 926 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 924 may be used to implement wireless connections to internet cloud services (e.g., to servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between the vehicle 900 and the other vehicle and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide information to the vehicle 900 about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind the vehicle 900). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of the vehicle 900.

[0201] In at least one embodiment, the network interface 924 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 936 to communicate over a wireless network. In at least one embodiment, the network interface 924 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a well-known process and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include a wireless function for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0202] In at least one embodiment, the vehicle 900 may further include one or more data stores 928, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 904) storage. In at least one embodiment, the one or more data stores 928 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0203] In at least one embodiment, the vehicle 900 may further include one or more GNSS sensors 958 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 958 may be used, including, for example, but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0204] In at least one embodiment, the vehicle 900 may further include one or more RADAR sensors 960. In at least one embodiment, the one or more RADAR sensors 960 may be used by the vehicle 900 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, the one or more RADAR sensors 960 may use a CAN bus and / or bus 902 (e.g., for transmitting data generated by the one or more RADAR sensors 960) to control and access object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, the one or more RADAR sensors 960 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 960 are pulse Doppler RADAR sensors.

[0205] In at least one embodiment, one or more RADAR sensors 960 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within a range of 250m). In at least one embodiment, one or more RADAR sensors 960 can help distinguish between static objects and moving objects and can be used by the ADAS system 938 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 960 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, using six antennas, the central four antennas can create a focused beam pattern designed to record the surrounding environment of the vehicle 900 at a higher speed with minimal traffic interference in adjacent lanes. In at least one embodiment, the additional two antennas may extend the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 900 .

[0206] In at least one embodiment, as an example, the medium-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, the short-range RADAR system may include, but is not limited to, any number of RADAR sensors 960 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 938 for blind spot detection and / or lane change assistance.

[0207] In at least one embodiment, the vehicle 900 may further include one or more ultrasonic sensors 962. In at least one embodiment, one or more ultrasonic sensors 962, which may be positioned at the front, rear, and / or side of the vehicle 900, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 962 may be used, and different ultrasonic sensors 962 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 962 may operate at an ASIL B functional safety level.

[0208] In at least one embodiment, the vehicle 900 can include one or more LIDAR sensors 964. In at least one embodiment, the one or more LIDAR sensors 964 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 964 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 900 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 964 that can use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0209] In at least one embodiment, one or more LIDAR sensors 964 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 964 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 964 may comprise a small device that can be embedded in the front, rear, side, and / or corner locations of the vehicle 900. In at least one embodiment, one or more LIDAR sensors 964 may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for low-reflectivity objects, and have a range of 200 meters. In at least one embodiment, the forward-mounted one or more LIDAR sensors 964 may be configured for a horizontal field of view between 45 and 135 degrees.

[0210] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 meters around vehicle 900. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 900 to the object. In at least one embodiment, flash LIDAR can allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 900. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0211] In at least one embodiment, the vehicle 900 may further include one or more IMU sensors 966. In at least one embodiment, the one or more IMU sensors 966 may be located at the center of the rear axle of the vehicle 900. In at least one embodiment, the one or more IMU sensors 966 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 966 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 966 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0212] In at least one embodiment, one or more IMU sensors 966 can be implemented as a miniature, high-performance GPS-assisted inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 966 can enable the vehicle 900 to estimate its heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 966, without the need for input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 966 and one or more GNSS sensors 958 can be combined in a single integrated unit.

[0213] In at least one embodiment, vehicle 900 can include one or more microphones 996 positioned within and / or around vehicle 900. In at least one embodiment, one or more microphones 996 can be used for emergency vehicle detection and identification.

[0214] In at least one embodiment, the vehicle 900 may further include any number of camera types, including one or more stereo cameras 968, one or more wide angle cameras 970, one or more infrared cameras 972, one or more surround cameras 974, one or more long range cameras 998, one or more mid range cameras 976, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 900. In at least one embodiment, the type of camera used depends on the vehicle 900. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 900. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 900 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present disclosure previously referred to herein may provide a plurality of cameras. Figure 9A and Figure 9B Each camera is described in more detail.

[0215] In at least one embodiment, the vehicle 900 can further include one or more vibration sensors 942. In at least one embodiment, the one or more vibration sensors 942 can measure vibrations of a component (e.g., an axle) of the vehicle 900. For example, in at least one embodiment, changes in vibration can indicate changes in the road surface. In at least one embodiment, when two or more vibration sensors 942 are used, the difference between the vibrations can be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0216] In at least one embodiment, the vehicle 900 may include an ADAS system 938. In at least one embodiment, the ADAS system 938 may include, in some examples, but is not limited to, an SoC. In at least one embodiment, the ADAS system 938 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0217] In at least one embodiment, the ACC system may use one or more RADAR sensors 960, one or more LIDAR sensors 964, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 900 and automatically adjusts the speed of the vehicle 900 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 900 change lanes when needed. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0218] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via the network interface 924 and / or one or more wireless antennas 926. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of the vehicle 900 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicle ahead of the vehicle 900, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0219] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 960, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0220] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can use one or more forward-facing cameras and / or one or more RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision approach braking.

[0221] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 900 crosses a lane marking. In at least one embodiment, the LDW system is not activated when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration assembly. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 900 begins to leave its lane, the LKA system provides steering input or braking to correct the vehicle 900.

[0222] In at least one embodiment, the BSW system detects and warns the driver that a vehicle is in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0223] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when the vehicle 900 detects an object outside the range of the rear camera while in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle's brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0224] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take action accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 900 independently decides whether to follow the results of the primary computer or the secondary computer (e.g., the first controller or the second controller in controller 936). For example, in at least one embodiment, the ADAS system 938 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 938 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0225] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU that indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0226] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides a false alarm based, at least in part, on output from the primary computer and output from the auxiliary computer. In at least one embodiment, the one or more neural networks in the supervisory MCU can learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the one or more neural networks in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 904.

[0227] In at least one embodiment, the ADAS system 938 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and the non-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0228] In at least one embodiment, the output of the ADAS system 938 can be fed into the primary computer's perception block and / or the primary computer's dynamic driving task block. For example, in at least one embodiment, if the ADAS system 938 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when the object is identified. In at least one embodiment, the secondary computer can have its own neural network that has been trained, as described herein, to reduce the risk of false positives.

[0229] In at least one embodiment, the vehicle 900 may further include an infotainment SoC 930 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 930 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 930 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / close, air filter information, etc.) to the vehicle 900. For example, the infotainment SoC 930 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, an onboard entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 934, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 930 may be further configured to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 900, such as information from an ADAS system 938, autonomous driving information (e.g., planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0230] In at least one embodiment, the infotainment SoC 930 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 930 can communicate with other devices, systems, and / or components of the vehicle 900 via the bus 902. In at least one embodiment, the infotainment SoC 930 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event that one or more master controllers 936 (e.g., the vehicle 900's main computer and / or backup computer) fail. In at least one embodiment, the infotainment SoC 930 can place the vehicle 900 in a driver-to-safety parking mode, as described herein.

[0231] In at least one embodiment, the vehicle 900 may further include an instrument panel 932 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 932 may include, but is not limited to, a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). In at least one embodiment, the instrument panel 932 may include, but is not limited to, a set of instruments in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine fault lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 930 and the instrument panel 932. In at least one embodiment, the instrument panel 932 may be included as part of the infotainment SoC 930, or vice versa.

[0232] In at least one embodiment, Figure 9C The system architecture of the vehicle 900 shown may be used as follows Figure 1-5 The neural network architecture described in

[15] is constructed.

[0233] Figure 9D In accordance with at least one embodiment, one or more cloud-based servers and Figure 9A900 . In at least one embodiment, the system may include, but is not limited to, one or more servers 978 , one or more networks 990 , and any number and type of vehicles, including vehicle 900 . In at least one embodiment, one or more servers 978 may include, but are not limited to, multiple GPUs 984 (A)-984 (H) (collectively referred to herein as GPUs 984 ), PCIe switches 982 (A)-982 (D) (collectively referred to herein as PCIe switches 982 ), and / or CPUs 980 (A)-980 (B) (collectively referred to herein as CPUs 980 ). In at least one embodiment, GPUs 984 , CPUs 980 , and PCIe switches 982 may be interconnected with a high-speed interconnect, such as, for example, but not limited to, NVLink interface 988 and / or PCIe connection 986 developed by NVIDIA. In at least one embodiment, GPUs 984 are connected via NVLink and / or NVSwitch SoCs, and GPUs 984 and PCIe switches 982 are connected via PCIe interconnects. Although eight GPUs 984, two CPUs 980, and four PCIe switches 982 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 978 may include, but is not limited to, any number of GPUs 984, CPUs 980, and / or PCIe switches 982 in any combination. For example, in at least one embodiment, one or more servers 978 may each include eight, sixteen, thirty-two, and / or more GPUs 984.

[0234] In at least one embodiment, one or more servers 978 may receive image data representing an image from a vehicle via one or more networks 990 that shows unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, one or more servers 978 may send updated neural networks 992 and / or map information 994 to the vehicle via one or more networks 990, including, but not limited to, information regarding traffic and road conditions. In at least one embodiment, updates to map information 994 may include, but are not limited to, updates to HD map 922, such as information regarding construction sites, potholes, service roads, flooding, and / or other obstacles. In at least one embodiment, neural network 992 and / or map information 994 may have been generated by new training and / or experience represented by data received from any number of vehicles in the environment, and / or may be based at least on training performed at a data center (e.g., using one or more servers 978 and / or other servers).

[0235] In at least one embodiment, one or more servers 978 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., sent to the vehicle via one or more networks 990, and / or the machine learning model can be used by one or more servers 978 to remotely monitor the vehicle.

[0236] In at least one embodiment, one or more servers 978 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 978 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 984, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 978 can include the deep learning infrastructure of a data center using CPU power.

[0237] In at least one embodiment, the deep learning infrastructure of one or more servers 978 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in the vehicle 900. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 900, such as a sequence of images and / or objects that the vehicle 900 has located in the sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 900, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 900 is malfunctioning, the one or more servers 978 may send a signal to the vehicle 900 instructing the vehicle's 900 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0238] In at least one embodiment, one or more servers 978 may include one or more GPUs 984 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, such as in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 615 are used to execute one or more embodiments. Figure 6A and / or Figure 6B Details regarding the hardware structure 615 are provided.

[0239] Computer system

[0240] Figure 10 1 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include an execution unit for executing instructions. In at least one embodiment, in accordance with the present disclosure, such as in the embodiments described herein, computer system 1000 may include, but is not limited to, components such as processor 1002 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, computer system 1000 may include a processor such as the Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1000 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0241] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0242] In at least one embodiment, the computer system 1000 may include, but is not limited to, a processor 1002, which may include, but is not limited to, one or more execution units 1008 for performing machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 1000 is a single-processor desktop or server system, but in another embodiment, the computer system 1000 may be a multi-processor system. In at least one embodiment, the processor 1002 may include, but is not limited to, for example, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1002 may be coupled to a processor bus 1010, which may transmit data signals between the processor 1002 and other components in the computer system 1000.

[0243] In at least one embodiment, processor 1002 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1002. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1006 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0244] In at least one embodiment, an execution unit 1008, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1002. In at least one embodiment, the processor 1002 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1008 may include logic for processing a packed instruction set 1009. In at least one embodiment, by including the packed instruction set 1009 in the instruction set of a general-purpose processor and the associated circuitry to execute the instructions, operations used by many multimedia applications can be performed using packed data in the processor 1002. In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which can eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0245] In at least one embodiment, execution unit 1008 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1000 may include, but is not limited to, memory 1020. In at least one embodiment, memory 1020 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1020 may store one or more instructions 1019 and / or data 1021 represented by data signals that may be executed by processor 1002.

[0246] In at least one embodiment, a system logic chip can be coupled to the processor bus 1010 and the memory 1020. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1016, and the processor 1002 can communicate with the MCH 1016 via the processor bus 1010. In at least one embodiment, the MCH 1016 can provide a high-bandwidth memory path 1018 to the memory 1020 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1016 can direct data signals between the processor 1002, the memory 1020, and other components in the computer system 1000, and bridge data signals between the processor bus 1010, the memory 1020, and the system I / O interface 1022. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1016 may be coupled to the memory 1020 via a high-bandwidth memory path 1018 , and the graphics / video card 1012 may be coupled to the MCH 1016 via an accelerated graphics port (“AGP”) interconnect 1014 .

[0247] In at least one embodiment, the computer system 1000 can use the system I / O interface 1022 as a proprietary hub interface bus to couple the MCH 1016 to the I / O controller hub ("ICH") 1030. In at least one embodiment, the ICH 1030 can provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1020, the chipset, and the processor 1002. Examples can include, but are not limited to, an audio controller 1029, a firmware hub ("flash BIOS") 1028, a wireless transceiver 1026, a data store 1024, a traditional I / O controller 1023 including a user input and keyboard interface 1025, a serial expansion port 1027 (such as a universal serial bus ("USB") port), and a network controller 1034. In at least one embodiment, the data store 1024 can include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0248] In at least one embodiment, Figure 10 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 10 An exemplary SoC may be shown. In at least one embodiment, Figure 10The devices shown in FIG. 1 can be interconnected using a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1000 are interconnected using a Compute Express Link (CXL) interconnect.

[0249] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, logic 615 can be used in computer system 1000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0250] In at least one embodiment, processor 1002 may be used to: Figure 1-5 The neural network architecture described in

[15] is constructed.

[0251] Figure 11 1 is a block diagram illustrating an electronic device 1100 for utilizing a processor 1110 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1100 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0252] In at least one embodiment, the electronic device 1100 may include, but is not limited to, a processor 1110 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1110 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, Universal Serial Bus ("USB") (Revision 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 11 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 11 An exemplary SoC may be shown. In at least one embodiment, Figure 11 The devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 11 One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0253] In at least one embodiment, Figure 11 It may include a display 1124, a touch screen 1125, a touchpad 1130, a near field communication unit (“NFC”) 1145, a sensor hub 1140, a thermal sensor 1146, an express chipset (“EC”) 1135, a trusted platform module (“TPM”) 1138, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1122, a DSP 1160, a drive 1120 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1150, a Bluetooth unit 1152, a wireless wide area network unit (“WWAN”) 1156, a global positioning system (GPS) unit 1155, a camera (“USB 3.0 camera”) 1154 (such as a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1115 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0254] In at least one embodiment, other components may be communicatively coupled to processor 1110 via the components described herein. In at least one embodiment, an accelerometer 1141, an ambient light sensor (“ALS”) 1142, a compass 1143, and a gyroscope 1144 may be communicatively coupled to sensor hub 1140. In at least one embodiment, a thermal sensor 1139, a fan 1137, a keyboard 1136, and a touchpad 1130 may be communicatively coupled to EC 1135. In at least one embodiment, a speaker 1163, an earpiece 1164, and a microphone (“mic”) 1165 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 1162, which in turn may be communicatively coupled to DSP 1160. In at least one embodiment, audio unit 1162 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 1157 may be communicatively coupled to WWAN unit 1156. In at least one embodiment, components such as the WLAN unit 1150 and the Bluetooth unit 1152 and the WWAN unit 1156 may be implemented as a next generation form factor ("NGFF").

[0255] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BDetails are provided regarding logic 615. In at least one embodiment, logic 615 may be used in electronic device 1100 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0256] In at least one embodiment, the electronic device 1100 may be used as Figure 1-5 The neural network architecture described in

[15] is constructed.

[0257] Figure 12 A computer system 1200 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1200 is configured to implement the various processes and methods described throughout this disclosure.

[0258] In at least one embodiment, computer system 1200 includes, but is not limited to, at least one central processing unit ("CPU") 1202 connected to a communication bus 1210 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1200 includes, but is not limited to, main memory 1204 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1204, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1222 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using computer system 1200.

[0259] In at least one embodiment, computer system 1200 includes, but is not limited to, input device 1208, parallel processing system 1212, and display device 1206, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1208 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0260] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BDetails are provided regarding logic 615. In at least one embodiment, logic 615 can be used in computer system 1200 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0261] In at least one embodiment, computer system 1200 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0262] Figure 13 A computer system 1300 is shown according to at least one embodiment. In at least one embodiment, computer system 1300 includes, but is not limited to, a computer 1310 and a USB drive 1320. In at least one embodiment, computer 1310 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1310 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0263] In at least one embodiment, the USB disk 1320 includes, but is not limited to, a processing unit 1330, a USB interface 1340, and USB interface logic 1350. In at least one embodiment, the processing unit 1330 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1330 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1330 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1330 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1330 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0264] In at least one embodiment, USB interface 1340 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1340 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1340 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1350 can include any number and type of logic that enables processing unit 1330 to interface with a device (e.g., computer 1310) via USB connector 1340.

[0265] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, logic 615 can be used in computer system 1300 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0266] In at least one embodiment, computer system 1300 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0267] Figure 14A An exemplary architecture is shown in which a plurality of GPUs 1410(1)-1410(N) are communicatively coupled to a plurality of multi-core processors 1405(1)-1405(M) via high-speed links 1440(1)-1440(N) (e.g., a bus, a point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1440(1)-1440(N) support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more of the plurality of GPUs 1410(1)-1410(N) include, for example, Figure 17A and Figure 17B Disclosed are one or more graphics cores (also referred to simply as "cores") 1700. In at least one embodiment, one or more graphics cores 1700 may be referred to as streaming multiprocessors ("SMs"), streaming processors ("SPs"), streaming processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0268] Furthermore, in at least one embodiment, two or more GPUs 1410 are interconnected via high-speed links 1429(1)-1429(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 1440(1)-1440(N). Similarly, two or more multi-core processors 1405 may be connected via high-speed link 1428, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 14A All communications between the various system components shown in .

[0269] In at least one embodiment, each multi-core processor 1405 is communicatively coupled to processor memory 1401(1)-1401(M) via memory interconnects 1426(1)-1426(M), respectively, and each GPU 1410(1)-1410(N) is communicatively coupled to GPU memory 1420(1)-1420(N) via GPU memory interconnects 1450(1)-1450(N), respectively. In at least one embodiment, memory interconnects 1426 and 1450 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1401(1)-1401(M) and GPU memory 1420 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1401 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0270] As described herein, although each multi-core processor 1405 and GPU 1410 can be physically coupled to a specific memory 1401, 1420, respectively, and / or a unified memory architecture can be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1401(1)-1401(M) can each include 64GB of system memory address space, and GPU memories 1420(1)-1420(N) can each include 32GB of system memory address space, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values ​​of N and M are possible.

[0271] Figure 14B Additional details are shown for the interconnection between multi-core processor 1407 and graphics acceleration module 1446 according to an exemplary embodiment. In at least one embodiment, graphics acceleration module 1446 may include one or more GPU chips integrated on a line card that is coupled to processor 1407 via a high-speed link 1440 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1446 may alternatively be integrated on a package or chip with processor 1407.

[0272] In at least one embodiment, the processor 1407 includes a plurality of cores 1460A-1460D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1461A-1461D and one or more caches 1462A-1462D. In at least one embodiment, the cores 1460A-1460D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1462A-1462D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1456 may be included in the caches 1462A-1462D and shared by each group of cores 1460A-1460D. For example, one embodiment of the processor 1407 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1407 and the graphics acceleration module 1446 are connected to the system memory 1414, which may include Figure 14A Processor memory 1401(1)-1401(M) in.

[0273] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1462A-1462D, 1456 and system memory 1414 via inter-core communication over a coherency bus 1464. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate over the coherency bus 1464 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1464 to snoop cache accesses.

[0274] In at least one embodiment, proxy circuitry 1425 communicatively couples graphics acceleration module 1446 to coherence bus 1464, thereby allowing graphics acceleration module 1446 to participate in a cache coherence protocol as a peer of cores 1460A-1460D. In particular, in at least one embodiment, interface 1435 provides connectivity to proxy circuitry 1425 via high-speed link 1440, and interface 1437 connects graphics acceleration module 1446 to high-speed link 1440.

[0275] In at least one embodiment, the accelerator integrated circuit 1436 provides cache management, memory access, context management, and interrupt management services on behalf of the plurality of graphics processing engines 1431(1)-1431(N) of the graphics acceleration module 1446. In at least one embodiment, the plurality of graphics processing engines 1431(1)-1431(N) of the graphics acceleration module 1446 may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1431(1)-1431(N) of the graphics acceleration module 1446 may comprise one or more graphics cores 1700, such as in combination with Figure 17A and Figure 17B As discussed. In at least one embodiment, the graphics processing engines 1431(1)-1431(N) may alternatively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1446 may be a GPU having multiple graphics processing engines 1431(1)-1431(N), or the graphics processing engines 1431(1)-1431(N) may be individual GPUs integrated on a common package, line card, or chip.

[0276] In at least one embodiment, the accelerator integrated circuit 1436 includes a memory management unit (MMU) 1439 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1414. In at least one embodiment, the MMU 1439 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1438 may store commands and data for efficient access by the graphics processing engines 1431(1)-1431(N). In at least one embodiment, a fetch unit 1444 may be used to keep data stored in the cache 1438 and graphics memory 1433(1)-1433(M) consistent with the core caches 1462A-1462D, 1456, and system memory 1414. As previously described, this can be implemented on behalf of cache 1438 and memory 1433(1)-1433(M) via proxy circuitry 1425 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1462A-1462D, 1456 to cache 1438 and receiving updates from cache 1438).

[0277] In at least one embodiment, a set of registers 1445 stores context data for threads executed by graphics processing engines 1431(1)-1431(N), and context management circuitry 1448 manages thread contexts. For example, context management circuitry 1448 can perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1448 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1447 receives and processes interrupts received from system devices.

[0278] In at least one embodiment, the MMU 1439 converts virtual / effective addresses from the graphics processing engine 1431 into real / physical addresses in the system memory 1414. In at least one embodiment, the accelerator integrated circuit 1436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1446 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1446 can be dedicated to a single application executing on the processor 1407, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1431 (1)-1431 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0279] In at least one embodiment, the accelerator integrated circuit 1436 acts as a bridge to the system for the graphics acceleration module 1446 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1436 can provide virtualization facilities to the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1431(1)-1431(N).

[0280] In at least one embodiment, because the hardware resources of graphics processing engines 1431(1)-1431(N) are explicitly mapped into the real address space seen by host processor 1407, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1436 is the physical separation of graphics processing engines 1431(1)-1431(N) so that they appear to the system as independent units.

[0281] In at least one embodiment, one or more graphics memories 1433(1)-1433(M) are coupled to each graphics processing engine 1431(1)-1431(N), respectively, with N=M. In at least one embodiment, graphics memories 1433(1)-1433(M) store instructions and data being processed by each graphics processing engine 1431(1)-1431(N). In at least one embodiment, graphics memories 1433(1)-1433(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0282] In at least one embodiment, to reduce data traffic on high-speed link 1440, a biasing technique may be used to ensure that the data stored in graphics memory 1433(1)-1433(M) is the data most frequently used by graphics processing engines 1431(1)-1431(N), and preferably is data that is not used (at least not frequently) by cores 1460A-1460D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data that is needed by the cores (and preferably not needed by graphics processing engines 1431(1)-1431(N)) in caches 1462A-1462D, 1456, and system memory 1414.

[0283] Figure 14C Another exemplary embodiment is shown in which an accelerator integrated circuit 1436 is integrated within the processor 1407. In this embodiment, the graphics processing engines 1431(1)-1431(N) communicate directly with the accelerator integrated circuit 1436 via interface 1437 and interface 1435 (again, which can be any form of bus or interface protocol) over a high-speed link 1440. In at least one embodiment, the accelerator integrated circuit 1436 can perform operations related to Figure 14B The operations described above are similar to those described above, but may have higher throughput due to its close proximity to the coherence bus 1464 and caches 1462A-1462D, 1456. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1436 and a programming model controlled by the graphics acceleration module 1446.

[0284] In at least one embodiment, graphics processing engines 1431(1)-1431(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1431(1)-1431(N), thereby providing virtualization within a VM / partition.

[0285] In at least one embodiment, graphics processing engines 1431(1)-1431(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1431(1)-1431(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1431(1)-1431(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1431(1)-1431(N) to provide access to each process or application.

[0286] In at least one embodiment, the graphics acceleration module 1446 or the individual graphics processing engines 1431(1)-1431(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1414 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1431(1)-1431(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0287] GPU 1410(1)-1410(N) can be used for example Figure 1-5 The neural network architecture described in

[15] is constructed.

[0288] Figure 14D An exemplary accelerator integrated slice 1490 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1436. In at least one embodiment, the application is an effective address space 1482 in system memory 1414, which stores a process element 1483. In at least one embodiment, the process element 1483 is stored in response to a GPU call 1481 from an application 1480 executing on the processor 1407. In at least one embodiment, the process element 1483 contains the process state of the corresponding application 1480. In at least one embodiment, the work descriptor (WD) 1484 contained in the process element 1483 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1484 is a pointer to a job request queue in the effective address space 1482 of the application.

[0289] In at least one embodiment, the graphics acceleration module 1446 and / or the individual graphics processing engines 1431(1)-1431(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 1484 to the graphics acceleration module 1446 to start a job in a virtualized environment.

[0290] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1446 or an individual graphics processing engine 1431. In at least one embodiment, when a graphics acceleration module 1446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1436 for the owned partition, and when a graphics acceleration module 1446 is assigned, the operating system initializes the accelerator integrated circuit 1436 for the owned process.

[0291] In at least one embodiment, in operation, a WD fetch unit 1491 in the accelerator integrated slice 1490 fetches a next WD 1484, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1446. In at least one embodiment, data from the WD 1484 can be stored in registers 1445 and used by the MMU 1439, interrupt management circuitry 1447, and / or context management circuitry 1448, as shown. For example, one embodiment of the MMU 1439 includes segment / page walk circuitry for accessing segment / page tables 1486 within the OS virtual address space 1485. In at least one embodiment, the interrupt management circuitry 1447 can process interrupt events 1492 received from the graphics acceleration module 1446. In at least one embodiment, when performing graphics operations, effective addresses 1493 generated by the graphics processing engines 1431(1)-1431(N) are converted to real addresses by the MMU 1439.

[0292] In at least one embodiment, registers 1445 are replicated for each graphics processing engine 1431(1)-1431(N) and / or graphics acceleration module 1446, and these registers 1445 can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integration slice 1490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0293] Table 1 - Registers initialized by the hypervisor

[0294]

[0295] Example registers that may be initialized by the operating system are shown in Table 2.

[0296] Table 2 - Registers initialized by the operating system

[0297]

[0298] In at least one embodiment, each WD 1484 is specific to a particular graphics acceleration module 1446 and / or graphics processing engine 1431(1)-1431(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1431(1)-1431(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0299] Figure 14E 1496 virtualizes the graphics acceleration module engine for the operating system 1495.

[0300] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1446. In at least one embodiment, there are two programming models where the graphics acceleration module 1446 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0301] In at least one embodiment, in this model, the hypervisor 1496 owns the graphics acceleration module 1446 and makes its functionality available to all operating systems 1495. In at least one embodiment, for the graphics acceleration module 1446 to support virtualization through the hypervisor 1496, the graphics acceleration module 1446 may adhere to certain requirements, such as (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1446 must provide a context save and restore mechanism, (2) the graphics acceleration module 1446 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1446 provides the ability to preempt job processing, and (3) the graphics acceleration module 1446 must ensure fairness between processes when operating in a directed shared programming model.

[0302] In at least one embodiment, the application 1480 is required to make an operating system 1495 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1446 and can take the form of a graphics acceleration module 1446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 1446.

[0303] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1436 (not shown) and the graphics acceleration module 1446 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1496 may selectively apply the current Authority Mask Override Register (AMOR) value before placing the AMR into the process element 1483. In at least one embodiment, the CSRP is one of the registers 1445 that contains the effective address of an area in the application's effective address space 1482 for the graphics acceleration module 1446 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0304] Upon receiving the system call, the operating system 1495 can verify that the application 1480 has been registered and granted permission to use the graphics acceleration module 1446. Then, in at least one embodiment, the operating system 1495 calls the hypervisor 1496 using the information shown in Table 3.

[0305] Table 3 - OS to hypervisor call parameters

[0306]

[0307] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1496 verifies that operating system 1495 has registered and been granted permission to use graphics acceleration module 1446. Then, in at least one embodiment, hypervisor 1496 places process element 1483 into a linked list of process elements of the corresponding type of graphics acceleration module 1446. In at least one embodiment, the process element may include the information shown in Table 4.

[0308] Table 4 - Process element information

[0309]

[0310] 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer

[0311] 12 Storage Descriptor Register (SDR)

[0312] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1490 registers 1445 .

[0313] like Figure 14F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1401(1)-1401(N) and GPU memory 1420(1)-1420(N). In this implementation, operations executed on GPUs 1410(1)-1410(N) utilize the same virtual / effective memory address space to access processor memory 1401(1)-1401(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1401(1), a second portion is allocated to second processor memory 1401(N), a third portion is allocated to GPU memory 1420(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1401 and GPU memory 1420, thereby allowing any processor or GPU to access any physical memory using a virtual address mapped to that memory.

[0314] In at least one embodiment, bias / coherency management circuitry 1494A-1494E within one or more MMUs 1439A-1439E ensures cache coherency between the caches of one or more host processors (e.g., 1405) and GPU 1410 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. In at least one embodiment, while Figure 14FMultiple instances of bias / coherence management circuits 1494A- 1494E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1405 and / or within an accelerator integrated circuit 1436 .

[0315] One embodiment allows GPU memory 1420 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability to access GPU memory 1420 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1405 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1420 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1410. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0316] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per additional memory page of the GPU. In at least one embodiment, the bias table can be implemented in a stolen memory range of one or more GPU memories 1420, with or without a bias cache in GPU 1410 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0317] In at least one embodiment, the bias table entry associated with each access to GPU-attached memory 1420 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1410 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1420. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 1405 (e.g., via the high-speed link described herein). In at least one embodiment, requests from processor 1405 that find the requested page in the host processor bias complete the request similarly to a normal memory read. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 1410. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in a limited set of cases, a purely hardware-based mechanism.

[0318] In at least one embodiment, a mechanism for changing bias states employs an API call (e.g., OpenCL), which in turn calls a device driver for the GPU, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1405 bias to GPU bias, but not for the reverse migration.

[0319] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1405. In at least one embodiment, to access these pages, processor 1405 may request access from GPU 1410, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1405 and GPU 1410, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the pages required by host processor 1405, and vice versa.

[0320] One or more hardware structures 615 are used to implement one or more embodiments. Figure 6A and / or Figure 6B Details regarding one or more hardware structures 615 are provided.

[0321] Figure 15An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0322] Figure 15 15 is a block diagram illustrating an exemplary system on a chip integrated circuit 1500 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1500 includes one or more application processors 1505 (e.g., CPUs), at least one graphics processor 1510, and may additionally include an image processor 1515 and / or a video processor 1520, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1500 includes peripheral or bus logic including a USB controller 1525, a UART controller 1530, an SPI / SDIO controller 1535, and an I 2 S / I 2 IC controller 1540. In at least one embodiment, integrated circuit 1500 may include a display device 1545 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1550 and a Mobile Industry Processor Interface (MIPI) display interface 1555. In at least one embodiment, storage may be provided by a flash memory subsystem 1560, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1565 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1570.

[0323] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, logic 615 may be used in integrated circuit 1500 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0324] Integrated circuit 1500 may be used, for example, Figure 1-5 The neural network architecture described in

[15] is constructed.

[0325] Figures 16A-16BAn exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0326] Figures 16A-16B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 16A An exemplary graphics processor 1610 of a system-on-chip integrated circuit is shown, which may be fabricated using one or more IP cores, in accordance with at least one embodiment. Figure 16B An additional exemplary graphics processor 1640 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 16A The graphics processor 1610 is a low-power graphics processor core. In at least one embodiment, Figure 16B The graphics processor 1640 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1610, 1640 can be Figure 15 A variant of the graphics processor 1510.

[0327] In at least one embodiment, the graphics processor 1610 includes a vertex processor 1605 and one or more fragment processors 1615A-1615N (e.g., 1615A, 1615B, 1615C, 1615D through 1615N-1 and 1615N). In at least one embodiment, the graphics processor 1610 can execute different shader programs via separate logic, such that the vertex processor 1605 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 1615A-1615N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1605 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1615A-1615N use the primitives and vertex data generated by the vertex processor 1605 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1615A-1615N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0328] In at least one embodiment, graphics processor 1610 additionally includes one or more memory management units (MMUs) 1620A-1620B, one or more caches 1625A-1625B, and one or more circuit interconnects 1630A-1630B. In at least one embodiment, one or more MMUs 1620A-1620B provide virtual to physical address mapping for graphics processor 1610 (including for vertex processor 1605 and / or fragment processors 1615A-1615N), which can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1625A-1625B. In at least one embodiment, one or more MMUs 1620A-1620B can synchronize with other MMUs within the system, including with Figure 15 One or more MMUs associated with one or more application processors 1505, graphics processor 1515, and / or video processor 1520 enable each processor 1505-1520 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1630A-1630B enable graphics processor 1610 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0329] In at least one embodiment, graphics processor 1640 includes: Figure 16B One or more shader cores 1655A-1655N (e.g., 1655A, 1655B, 1655C, 1655D, 1655E, 1655F through 1655N-1 and 1655N) are shown, which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1640 includes an inter-core task manager 1645 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1655A-1655N and a tiling unit 1658 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0330] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BDetails are provided regarding logic 615. In at least one embodiment, logic 615 may be used in graphics processors 1610 and / or 1640 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0331] In at least one embodiment, graphics processor 1610 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0332] Figures 17A-17B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figures 17A-17B shown in or in combination with Figures 17A-17B The components described are integrated into a single system, such as a graphics processing unit (GPU), SoC or other type of processor. In at least one embodiment, Figure 17A Shows that can be included in Figure 15 Graphics core 1700 within graphics processor 1510 of FIG. 1 and, in at least one embodiment, may be such as Figure 16B Unified shader cores 1655A-1655N are shown. Figure 17B A highly parallel general-purpose graphics processing unit ("GPGPU") suitable for deployment on a multi-chip module in at least one embodiment is shown, which may also be referred to as a "graphics processing unit" 1730. In at least one embodiment, graphics processing unit 1730 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 1500 includes graphics core 1700, e.g., forming an integrated circuit and / or forming a SoC, wherein such integrated circuit and / or such SoC performs the operations described herein.

[0333] In at least one embodiment, graphics core 1700 includes a shared instruction cache 1702, texture units 1718, and cache / shared memory 1720 (e.g., including L1, L2, L3, last level cache, or other caches) that are common to execution resources within graphics core 1700. In at least one embodiment, graphics core 1700 may include multiple slices 1701A-1701N, or partitions of each core, and a graphics processor may include multiple instances of graphics core 1700. In at least one embodiment, each slice 1701A-1701N refers to graphics core 1700. In at least one embodiment, slices 1701A-1701N have subslices that are part of slices 1701A-1701N. In at least one embodiment, slices 1701A-1701N may be independent of other slices or dependent on other slices. In at least one embodiment, slices 1701A-1701N may include support logic including a local instruction cache 1704A-1704N, a thread scheduler (sequencer) 1706A-1706N, a thread dispatcher 1707A-1708N, and a set of registers 1710A-1710N. In at least one embodiment, slices 1701A-1701N may include a set of additional function units (AFUs 1712A-1712N), floating point units (FPUs 1714A-1714N), integer arithmetic logic units (ALUs 1716A-1716N), address calculation units (ACUs 1713A-1713N), double-precision floating point units (DPFPUs 1715A-1715N), and matrix processing units (MPUs 1717A-1717N). In at least one embodiment, MPUs 1717A-1717N are referred to as matrix engines.

[0334] In at least one embodiment, each slice 1701A-1701N includes one or more engines for floating-point and integer vector operations, as well as one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large data set workloads. In at least one embodiment, one or more slices 1701A-1701N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating point (also known as "FP16"), 32-bit floating point (also known as "FP32"), or 64-bit floating point (also known as "FP64"). In at least one embodiment, one or more slices 1701A-1701N include 16 vector engines that are paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed via matrix extensions. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, for example, 16 cores and a ray tracing unit or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, graphics core 1700 includes one or more matrix engines for computing matrix operations, for example, when computing tensor operations.

[0335] In at least one embodiment, one or more slices 1701A-1701N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 1701A-1701N). In at least one embodiment, the ray tracing units compute ray traversals, triangle intersections, bounding box intersections, or other ray tracing operations.

[0336] In at least one embodiment, one or more slices 1701A-1701N comprise a media slice that encodes, decodes, and / or transcodes data; scales and / or format converts data; and / or performs video quality operations on video data.

[0337] In at least one embodiment, one or more slices 1701A-1701N are linked to an L2 cache and memory structure, a link connector, a high bandwidth memory (HBM) (e.g., HBM2e, HDM3) stack, and a media engine. In at least one embodiment, one or more slices 1701A-1701N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1701A-1701N have one or more L1 caches. In at least one embodiment, one or more slices 1701A-1701N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data (e.g., corresponding to instructions); one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for caching data; and / or one or more pixel backends. In at least one embodiment, slices 1701A-1701N include memory structures, such as an L2 cache.

[0338] In at least one embodiment, the FPUs 1714A-1714N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1715A-1715N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1716A-1716N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1717A-1717N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1717A-1717N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1712A-1712N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0339] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, logic 615 may be used in graphics core 1700 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0340] In at least one embodiment, graphics core 1700 includes an interconnect and link fabric sublayer attached to switches and GPU-GPU bridges that enable multiple graphics processors 1700 (e.g., eight) to be interconnected without glue using load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1700. In at least one embodiment, the interconnect comprises a standardized interconnect (e.g., PCIe) or some combination thereof.

[0341] In at least one embodiment, graphics core 1700 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where the individual dies can be connected using an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 1700 includes a compute tile, a memory tile (e.g., where the memory tile can be exclusively accessed by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, where all of the tiles are packaged together in graphics core 1700 as part of a GPU. In at least one embodiment, graphics core 1700 can include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile can have eight graphics cores 1700, an L1 cache, and a base tile can have a host interface using PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight links, and eight ports with an embedded switch. In at least one embodiment, each block is connected to a face-to-face (F2F) die bond via fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, graphics core 1700 includes a memory structure that includes memory and is accessible to multiple blocks. In at least one embodiment, graphics core 1700 stores, accesses, or loads its own hardware context in memory, where a hardware context is a set of data loaded from registers before a process resumes, and where the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0342] In at least one embodiment, graphics core 1700 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream to a parallel data stream, or converts a parallel data stream to a serial data stream.

[0343] In at least one embodiment, graphics core 1700 includes a high-speed coherent unified fabric (GPU to GPU), load / store units, large block data transfers and synchronization semantics, and GPUs connected via an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0344] In at least one embodiment, graphics core 1700 executes an API, wherein the API abstracts the hardware of graphics core 1700 and utilizes instructions to access libraries to perform mathematical operations (e.g., a math kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0345] In at least one embodiment, graphics core 1700 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0346] Figure 17B A general purpose processing unit (GPGPU) 1730 is shown in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, GPGPU 1730 can be directly linked to other instances of GPGPU 1730 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1730 includes a host interface 1732 for connecting to a host processor. In at least one embodiment, host interface 1732 is a PCI Express interface. In at least one embodiment, host interface 1732 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1730 receives commands from the host processor and uses a global scheduler 1734 (which can be referred to as a thread sequencer and / or asynchronous compute engine) to assign execution threads associated with those commands to a set of compute clusters 1736A-1736H. In at least one embodiment, compute clusters 1736A-1736H share a cache memory 1738. In at least one embodiment, cache memory 1738 may be used as a higher level cache for cache memory within compute clusters 1736A-1736H. In at least one embodiment, compute clusters 1736A-1736H include slices or are referred to as "slices." In at least one embodiment, GPGPU 1730 is part of a SoC, such as part of integrated circuit 1500 ( Figure 15 ).

[0347] In at least one embodiment, GPGPU 1730 includes memory 1744A-1744B coupled to compute clusters 1736A-1736H via a set of memory controllers 1742A-1742B (e.g., one or more controllers of HBM2e). In at least one embodiment, memory 1744A-1744B may include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0348] In at least one embodiment, computing clusters 1736A-1736H each include a set of graphics cores, such as Figure 17A The graphics core 1700 may include multiple types of integer and floating-point logic units that can perform computational operations across a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1736A-1736H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0349] In at least one embodiment, multiple instances of GPGPU 1730 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 1736A-1736H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1730 communicate via host interface 1732. In at least one embodiment, GPGPU 1730 includes an I / O hub 1739 that couples GPGPU 1730 to a GPU link 1740, which enables direct connections to other instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1730 are located in separate data processing systems and communicate via a network device accessible via host interface 1732. In at least one embodiment, GPU link 1740 may be configured to enable connection to a host processor in addition to or in lieu of host interface 1732 .

[0350] In at least one embodiment, GPGPU 1730 can be configured to train neural networks. In at least one embodiment, GPGPU 1730 can be used within an inference platform. In at least one embodiment, when using GPGPU 1730 for inference, GPGPU 1730 can include fewer compute clusters 1736A-1736H than when using GPGPU 1730 for training a neural network. In at least one embodiment, the memory technology associated with memory 1744A-1744B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 1730 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0351] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, logic 615 may be used in GPGPU 1730 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0352] In at least one embodiment, GPGPU 1730 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0353] Figure 181800 is a block diagram illustrating a computing system 1800 according to at least one embodiment. In at least one embodiment, computing system 1800 includes a processing subsystem 1801 having one or more processors 1802 and system memory 1804 communicating via an interconnect path that may include a memory hub 1805. In at least one embodiment, memory hub 1805 may be a separate component within a chipset assembly or may be integrated within one or more processors 1802. In at least one embodiment, memory hub 1805 is coupled to an I / O subsystem 1811 via a communication link 1806. In at least one embodiment, I / O subsystem 1811 includes an I / O hub 1807, which enables computing system 1800 to receive input from one or more input devices 1808. In at least one embodiment, I / O hub 1807 may enable a display controller, which may be included in one or more processors 1802, to provide output to one or more display devices 1810A. In at least one embodiment, the one or more display devices 1810A coupled to the I / O hub 1807 may include local, internal, or embedded display devices.

[0354] In at least one embodiment, the processing subsystem 1801 includes one or more parallel processors 1812 coupled to the memory hub 1805 via a bus or other communication link 1813. In at least one embodiment, the communication link 1813 can use one of any number of standard based communication link technologies or protocols (such as, but not limited to, PCI Express), or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1812 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as a many-in-one (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 1812 form a graphics processing subsystem that can output pixels to one of one or more display devices 1810A coupled via the I / O hub 1807. In at least one embodiment, the one or more parallel processors 1812 can also include a display controller and display interface (not shown) for enabling direct connection to one or more display devices 1810B. In at least one embodiment, parallel processor 1812 includes one or more cores, such as graphics core 1700 discussed herein.

[0355] In at least one embodiment, a system storage unit 1814 can be connected to the I / O hub 1807 to provide a storage mechanism for the computing system 1800. In at least one embodiment, an I / O switch 1816 can be used to provide an interface mechanism for enabling connections between the I / O hub 1807 and other components, such as a network adapter 1818 and / or a wireless network adapter 1819 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 1820. In at least one embodiment, the network adapter 1818 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1819 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more radio devices.

[0356] In at least one embodiment, computing system 1800 may include other components not explicitly shown that may also be connected to I / O hub 1807, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol). Figure 18 The communication paths between the various components in the system.

[0357] In at least one embodiment, one or more parallel processors 1812 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU), e.g., one or more parallel processors 1812 include graphics core 1700. In at least one embodiment, one or more parallel processors 1812 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 1800 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1812, memory hub 1805, one or more processors 1802, and I / O hub 1807 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1800 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1800 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0358] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, logic 615 can be used in computing system 1800 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0359] In at least one embodiment, computing system 1800 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0360] processor

[0361] Figure 19A 1900 is shown in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 1900 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 1900 is shown in accordance with an exemplary embodiment. Figure 18 A variation of one or more parallel processors 1812 is shown. In at least one embodiment, parallel processor 1900 includes one or more graphics cores 1700.

[0362] In at least one embodiment, parallel processor 1900 includes parallel processing unit 1902. In at least one embodiment, parallel processing unit 1902 includes an I / O unit 1904 that enables communication with other devices, including other instances of parallel processing unit 1902. In at least one embodiment, I / O unit 1904 can be directly connected to other devices. In at least one embodiment, I / O unit 1904 connects to other devices using a hub or switch interface (e.g., memory hub 1905). In at least one embodiment, the connection between memory hub 1905 and I / O unit 1904 forms a communication link 1913. In at least one embodiment, I / O unit 1904 is connected to a host interface 1906 and a memory crossbar switch 1916, where host interface 1906 receives commands for performing processing operations and memory crossbar switch 1916 receives commands for performing memory operations.

[0363] In at least one embodiment, when host interface 1906 receives command buffers via I / O unit 1904, host interface 1906 can direct work operations for executing those commands to front end 1908. In at least one embodiment, front end 1908 is coupled with scheduler 1910 (which can be referred to as a sequencer), which is configured to distribute commands or other work items to processing cluster array 1912. In at least one embodiment, scheduler 1910 ensures that processing cluster array 1912 is properly configured and in a valid state before distributing tasks to clusters within processing cluster array 1912. In at least one embodiment, scheduler 1910 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 1910 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing cluster array 1912. In at least one embodiment, host software can identify workloads for scheduling on processing cluster array 1912 via one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically distributed across the processing cluster array 1912 by scheduler 1910 logic within a microcontroller that includes scheduler 1910 .

[0364] In at least one embodiment, processing cluster array 1912 may include up to "N" processing clusters (e.g., cluster 1914A, cluster 1914B, through cluster 1914N), where "N" represents a positive integer (which may be a different integer "N" than the integers used in other figures). In at least one embodiment, each cluster 1914A-1914N in processing cluster array 1912 may execute a large number of concurrent threads. In at least one embodiment, scheduler 1910 may use various scheduling and / or work distribution algorithms to distribute work to clusters 1914A-1914N in processing cluster array 1912, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 1910 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 1912. In at least one embodiment, different clusters 1914A-1914N in processing cluster array 1912 may be assigned to process different types of programs or to perform different types of computations.

[0365] In at least one embodiment, processing cluster array 1912 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1912 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 1912 can include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0366] In at least one embodiment, processing cluster array 1912 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 1912 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 1912 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 1902 may transfer data from system memory via I / O units 1904 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1922) during processing and then written back to system memory.

[0367] In at least one embodiment, when parallel processing unit 1902 is used to perform graphics processing, scheduler 1910 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1914A-1914N in processing cluster array 1912. In at least one embodiment, different portions of processing cluster array 1912 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1914A-1914N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1914A-1914N for further processing.

[0368] In at least one embodiment, processing cluster array 1912 can receive processing tasks to be executed via scheduler 1910, which receives commands defining the processing tasks from front end 1908. In at least one embodiment, a processing task can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, scheduler 1910 can be configured to obtain an index corresponding to a task, or can receive the index from front end 1908. In at least one embodiment, front end 1908 can be configured to ensure that processing cluster array 1912 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0369] In at least one embodiment, each of one or more instances of parallel processing unit 1902 can be coupled to parallel processor memory 1922. In at least one embodiment, parallel processor memory 1922 can be accessed via memory crossbar 1916, which can receive memory requests from processing cluster array 1912 and I / O unit 1904. In at least one embodiment, memory crossbar 1916 can access parallel processor memory 1922 via memory interface 1918. In at least one embodiment, memory interface 1918 can include a plurality of partition units (e.g., partition unit 1920A, partition unit 1920B, through partition unit 1920N), which can each be coupled to a portion of parallel processor memory 1922 (e.g., a memory unit). In at least one embodiment, the number of partition units 1920A-1920N is configured to be equal to the number of memory cells, such that the first partition unit 1920A has a corresponding first memory cell 1924A, the second partition unit 1920B has a corresponding second memory cell 1924B, and the Nth partition unit 1920N has a corresponding Nth memory cell 1924N. In at least one embodiment, the number of partition units 1920A-1920N may not be equal to the number of memory cells.

[0370] In at least one embodiment, memory units 1924A-1924N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1924A-1924N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, and HDM3. In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 1924A-1924N, allowing partition units 1920A-1920N to write to portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 1922. In at least one embodiment, local instances of parallel processor memory 1922 may be eliminated in favor of a unified memory design that utilizes system memory as well as local cache memory.

[0371] In at least one embodiment, any of the clusters 1914A-1914N in the processing cluster array 1912 can process data to be written to any memory unit 1924A-1924N within the parallel processor memory 1922. In at least one embodiment, the memory crossbar 1916 can be configured to transmit the output of each cluster 1914A-1914N to any partition unit 1920A-1920N or to another cluster 1914A-1914N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 1914A-1914N can communicate with a memory interface 1918 via the memory crossbar 1916 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 1916 has connections to memory interface 1918 for communicating with I / O unit 1904, and connections to local instances of parallel processor memory 1922, which enables processing units within different processing clusters 1914A-1914N to communicate with system memory or other memory that is not local to parallel processing unit 1902. In at least one embodiment, memory crossbar 1916 may use virtual channels to separate traffic flows between clusters 1914A-1914N and partition units 1920A-1920N.

[0372] In at least one embodiment, multiple instances of parallel processing unit 1902 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1902 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1902 can include higher precision floating point units relative to other instances. In at least one embodiment, a system including one or more instances of parallel processing unit 1902 or parallel processor 1900 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0373] Figure 19B is a block diagram of a partition unit 1920 according to at least one embodiment. In at least one embodiment, the partition unit 1920 is Figure 19A 1920N。In at least one embodiment, the partition unit 1920 includes an L2 cache 1921, a frame buffer interface 1925 and an ROP 1926 (raster operation unit). In at least one embodiment, the L2 cache 1921 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 1916 and the ROP 1926. In at least one embodiment, the L2 cache 1921 outputs read misses and urgent write back requests to the frame buffer interface 1925 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 1925 for processing. In at least one embodiment, the frame buffer interface 1925 communicates with memory units in the parallel processor memory (such as Figure 19A One of the memory units 1924A-1924N (e.g., within parallel processor memory 1922)) is coupled.

[0374] In at least one embodiment, ROP 1926 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 1926 then outputs the processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 1926 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 1926 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0375] In at least one embodiment, ROP 1926 is included within each processing cluster (e.g., Figure 19A In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are routed through memory crossbar 1916. In at least one embodiment, the processed graphics data may be displayed on a display device such as a Figure 18 1802 for further processing, or by Figure 19A One of the processing entities within parallel processor 1900 is routed for further processing.

[0376] Figure 19C is a block diagram of a processing cluster 1914 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 19A In at least one embodiment, processing cluster 1914 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0377] In at least one embodiment, the operation of the processing cluster 1914 can be controlled via a pipeline manager 1932 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1932 Figure 19AScheduler 1910 receives instructions and manages the execution of these instructions via graphics multiprocessor 1934 and / or texture unit 1936. In at least one embodiment, graphics multiprocessor 1934 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within processing cluster 1914. In at least one embodiment, one or more instances of graphics multiprocessor 1934 may be included within processing cluster 1914. In at least one embodiment, graphics multiprocessor 1934 may process data, and data crossbar 1940 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, pipeline manager 1932 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via data crossbar 1940.

[0378] In at least one embodiment, each graphics multiprocessor 1934 within a processing cluster 1914 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where a new instruction may be issued before a previous instruction has completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0379] In at least one embodiment, instructions transmitted to processing cluster 1914 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 1934. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 1934. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines can be idle during the processing of a loop within the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 1934. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 1934, processing can be performed within consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 1934.

[0380] In at least one embodiment, the graphics multiprocessor 1934 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1934 can abandon the internal cache and use cache memory within the processing cluster 1914 (e.g., L1 cache 1948). In at least one embodiment, each graphics multiprocessor 1934 can also access a partition unit (e.g., Figure 19A L2 cache within partition units 1920A-1920N) of the graphics multiprocessor 1934, which are shared across all processing clusters 1914 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1934 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1902 can be used as global memory. In at least one embodiment, processing cluster 1914 includes multiple instances of graphics multiprocessor 1934, which can share common instructions and data, which can be stored in L1 cache 1948.

[0381] In at least one embodiment, each processing cluster 1914 may include a memory management unit ("MMU") 1945 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1945 may reside in Figure 19A 1918. In at least one embodiment, the MMU 1945 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 1945 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 1934 or L1 cache 1948 or processing cluster 1914. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0382] In at least one embodiment, processing clusters 1914 can be configured such that each graphics multiprocessor 1934 is coupled to a texture unit 1936 to perform texture mapping operations, which determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1934, and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 1934 outputs processed tasks to a data crossbar 1940 to provide the processed tasks to another processing cluster 1914 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or in system memory via a memory crossbar 1916. In at least one embodiment, a preROP 1942 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 1934 and direct the data to a ROP unit, which can communicate with a partition unit (e.g., a partition unit) as described herein. Figure 19A In at least one embodiment, the PreROP 1942 unit can perform optimizations for color blending, organizing pixel color data, and performing address translation.

[0383] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, logic 615 may be used in graphics processing cluster 1914 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0384] In at least one embodiment, parallel processor 1900 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0385] Figure 19DA graphics multiprocessor 1934 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 1934 is coupled to a pipeline manager 1932 of a processing cluster 1914. In at least one embodiment, the graphics multiprocessor 1934 has an execution pipeline that includes, but is not limited to, an instruction cache 1952, an instruction unit 1954, an address mapping unit 1956, a register file 1958, one or more general purpose graphics processing unit (GPGPU) cores 1962, and one or more load / store units 1966, wherein the one or more load / store units 1966 can perform load / store operations to load / store instructions corresponding to the execution operations. In at least one embodiment, the GPGPU core 1962 and the load / store unit 1966 are coupled to a cache memory 1972 and a shared memory 1970 via a memory and cache interconnect 1968. In at least one embodiment, the GPGPU core 1962 is part of a SoC, such as Figure 15 A portion of integrated circuit 1500.

[0386] In at least one embodiment, the instruction cache 1952 receives a stream of instructions to be executed from the pipeline manager 1932. In at least one embodiment, the instructions are cached in the instruction cache 1952 and dispatched for execution by the instruction unit 1954. In at least one embodiment, the instruction unit 1954 can dispatch instructions as thread groups (e.g., warps, wavefronts, waves), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 1962. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1956 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 1966.

[0387] In at least one embodiment, register file 1958 provides a set of registers for the functional units of graphics multiprocessor 1934. In at least one embodiment, register file 1958 provides temporary storage for operands for data paths connected to the functional units of graphics multiprocessor 1934 (e.g., GPGPU core 1962, load / store unit 1966). In at least one embodiment, register file 1958 is divided between each functional unit such that a dedicated portion of register file 1958 is allocated to each functional unit. In at least one embodiment, register file 1958 is divided between different warps (which may be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 1934.

[0388] In at least one embodiment, each GPGPU core 1962 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1934. In at least one embodiment, the architectures of the various GPGPU cores 1962 may be similar or different. In at least one embodiment, a first portion of a GPGPU core 1962 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-1908 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1934 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1962 may also include fixed-function or special-function logic.

[0389] In at least one embodiment, the GPGPU core 1962 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 1962 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that implement the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0390] In at least one embodiment, memory and cache interconnect 1968 is an interconnect network that connects each functional unit of graphics multiprocessor 1934 to register file 1958 and shared memory 1970. In at least one embodiment, memory and cache interconnect 1968 is a crossbar interconnect that allows load / store unit 1966 to perform load and store operations between shared memory 1970 and register file 1958. In at least one embodiment, register file 1958 can operate at the same frequency as GPGPU core 1962, resulting in very low latency for data transfers between GPGPU core 1962 and register file 1958. In at least one embodiment, shared memory 1970 can be used to facilitate communication between threads executing on functional units within graphics multiprocessor 1934. In at least one embodiment, cache memory 1972 can be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 1936. In at least one embodiment, shared memory 1970 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 1972, threads executing on GPGPU core 1962 may programmatically store data in shared memory.

[0391] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, a SoC includes a parallel processor or GPGPU as described herein, wherein the parallel processor or GPGPU is executed on the SoC. In at least one embodiment, the GPU can be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0392] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BDetails are provided regarding logic 615. In at least one embodiment, logic 615 may be used in graphics multiprocessor 1934 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0393] In at least one embodiment, graphics multiprocessor 1934 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0394] Figure 20 A multi-GPU computing system 2000 is shown in accordance with at least one embodiment. In at least one embodiment, multi-GPU computing system 2000 may include a processor 2002 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2006A-D via a host interface switch 2004. In at least one embodiment, host interface switch 2004 is a PCI Express switch device that couples processor 2002 to a PCI Express bus, over which processor 2002 can communicate with GPGPUs 2006A-D. In at least one embodiment, GPGPUs 2006A-D may be interconnected via a set of high-speed P2P (peer-to-peer) GPU-to-GPU links 2016. In at least one embodiment, GPU-to-GPU links 2016 connect to each of GPGPUs 2006A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 2016 enable direct communication between each GPGPU 2006A-D without requiring communication through host interface bus 2004 to which processor 2002 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU link 2016, host interface bus 2004 remains available for system memory access or communication with other instances of multi-GPU computing system 2000, for example, via one or more network devices. While in at least one embodiment, GPGPUs 2006A-D are connected to processor 2002 via host interface switch 2004, in at least one embodiment, processor 2002 includes direct support for P2P GPU link 2016 and can connect directly to GPGPUs 2006A-D. In at least one embodiment, GPGPUs 2006A-D are part of a SoC (such as a Figure 15 1500), wherein GPGPUs 2006A-D perform the operations described herein.

[0395] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6Aand / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, logic 615 may be used in multi-GPU computing system 2000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0396] In at least one embodiment, multi-GPU computing system 2000 includes one or more graphics cores 1700 .

[0397] In at least one embodiment, the multi-GPU computing system 2000 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0398] Figure 21 2 is a block diagram of a graphics processor 2100 according to at least one embodiment. In at least one embodiment, graphics processor 2100 includes a ring interconnect 2102, a pipeline front end 2104, a media engine 2137, and graphics cores 2180A-2180N. In at least one embodiment, ring interconnect 2102 couples graphics processor 2100 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2100 is one of many processors integrated within a multi-core processing system. In at least one embodiment, graphics processor 2100 includes graphics core 1700.

[0399] In at least one embodiment, the graphics processor 2100 receives batches of commands via a ring interconnect 2102. In at least one embodiment, the incoming commands are interpreted by a command streamer 2103 in a pipeline front end 2104. In at least one embodiment, the graphics processor 2100 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2180A-2180N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2103 provides the commands to a geometry pipeline 2136. In at least one embodiment, for at least some media processing commands, the command streamer 2103 provides the commands to a video front end 2134, which is coupled to a media engine 2137. In at least one embodiment, the media engine 2137 includes a video quality engine (VQE) 2130 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2133 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2136 and the media engine 2137 each generate execution threads for thread execution resources provided by at least one graphics core 2180 .

[0400] In at least one embodiment, the graphics processor 2100 includes scalable thread execution resources featuring graphics cores 2180A-2180N (which may be modular and sometimes referred to as core slices), each of which has multiple sub-cores 2150A-2150N, 2160A-2160N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2100 may have any number of graphics cores 2180A. In at least one embodiment, the graphics processor 2100 includes a graphics core 2180A having at least a first sub-core 2150A and a second sub-core 2160A. In at least one embodiment, the graphics processor 2100 is a low-power processor having a single sub-core (e.g., 2150A). In at least one embodiment, the graphics processor 2100 includes multiple graphics cores 2180A-2180N, each of which includes a set of first sub-cores 2150A-2150N and a set of second sub-cores 2160A-2160N. In at least one embodiment, each of the first sub-cores 2150A-2150N includes at least a first set of execution units 2152A-2152N and media / texture samplers 2154A-2154N. In at least one embodiment, each of the second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In at least one embodiment, each of the sub-cores 2150A-2150N, 2160A-2160N shares a set of shared resources 2170A-2170N. In at least one embodiment, the shared resources include shared cache memory and pixel manipulation logic. In at least one embodiment, the graphics processor 2100 includes a load / store unit in the pipeline front end 2104.

[0401] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, logic 615 may be used in graphics processor 2100 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0402] In at least one embodiment, graphics processor 2100 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0403] Figure 22is a block diagram illustrating a microarchitecture for a processor 2200 that may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2200 may execute instructions including x86 instructions, ARM instructions, specialized instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2200 may include registers for storing packed data, such as 64-bit wide MMX registers in microprocessors implemented with MMX technology from Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in both integer and floating point formats can operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or beyond (commonly referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, processor 2200 can execute instructions that accelerate machine learning or deep learning algorithms, training, or reasoning.

[0404] In at least one embodiment, the processor 2200 includes an in-order front end ("front end") 2201 for fetching instructions to be executed and preparing the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2201 may include several units. In at least one embodiment, an instruction prefetcher 2226 fetches instructions from memory and feeds the instructions to an instruction decoder 2228, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2228 decodes the received instructions into one or more operations called "micro-operations" or "microinstructions" (also known as "micro ops" or "uops" or "μ-ops") that the machine can execute. In at least one embodiment, the instruction decoder 2228 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, the trace cache 2230 can assemble the decoded micro-ops into a program-ordered sequence or trace in the micro-op queue 2234 for execution. In at least one embodiment, when trace cache 2230 encounters a complex instruction, microcode ROM 2232 provides the micro-ops needed to complete the operation.

[0405] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2228 may access the microcode ROM 2232 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2228. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2232. In at least one embodiment, the trace cache 2230 references the entry point programmable logic array ("PLA") to determine the correct microinstruction pointer for reading the microcode sequence from the microcode ROM 2232 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2232 completes serializing the micro-ops for the instruction, the front end 2201 of the machine may resume fetching micro-ops from the trace cache 2230.

[0406] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2203 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as the instruction flow moves down the pipeline and is scheduled for execution. In at least one embodiment, the OOO engine 2203 includes, but is not limited to, an allocator / register renamer 2240, a memory micro-op queue 2242, an integer / floating-point micro-op queue 2244, a memory scheduler 2246, a fast scheduler 2202, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2204, and a simple floating-point scheduler ("simple FP scheduler") 2206. In at least one embodiment, the fast scheduler 2202, the slow / general purpose floating-point scheduler 2204, and the simple floating-point scheduler 2206 are also collectively referred to herein as "micro-op schedulers 2202, 2204, 2206." In at least one embodiment, the allocator / register renamer 2240 allocates the machine buffers and resources required for each micro-op to execute. In at least one embodiment, the allocator / register renamer 2240 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2240 also allocates entries for each micro-op in one of two micro-op queues: the memory micro-op queue 2242 for memory operations and the integer / floating-point micro-op queue 2244 for non-memory operations, preceding the memory scheduler 2246 and the micro-op schedulers 2202, 2204, 2206. In at least one embodiment, the micro-op schedulers 2202, 2204, 2206 determine when a micro-op is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources required for the micro-op to complete its operation. In at least one embodiment, the fast scheduler 2202 can schedule every half of the main clock cycle, while the slow / general floating-point scheduler 2204 and the simple floating-point scheduler 2206 can schedule once per main processor clock cycle. In at least one embodiment, micro-op schedulers 2202, 2204, 2206 arbitrate on dispatch ports to schedule micro-ops for execution.

[0407] In at least one embodiment, execution block 2211 includes, but is not limited to, integer register file / bypass network 2208, floating point register file / bypass network ("FP register file / bypass network") 2210, address generation units ("AGUs") 2212 and 2214, fast arithmetic logic units (ALUs) ("fast ALUs") 2216 and 2218, slow arithmetic logic unit ("slow ALU") 2220, floating point ALU ("FP") 2222, and floating point move unit ("FP move") 2224. In at least one embodiment, integer register file / bypass network 2208 and floating point register file / bypass network 2210 are also referred to herein as "register files 2208, 2210." In at least one embodiment, AGUs 2212 and 2214, fast ALUs 2216 and 2218, slow ALU 2220, floating-point ALU 2222, and floating-point move unit 2224 are also referred to herein as "execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224." In at least one embodiment, execution block 2211 may include, but is not limited to, any number (including zero) and types of register files, bypass networks, address generation units, and execution units in any combination.

[0408] In at least one embodiment, register networks 2208 and 2210 may be arranged between micro-op schedulers 2202, 2204, and 2206 and execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224. In at least one embodiment, integer register file / bypass network 2208 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2210 performs floating-point operations. In at least one embodiment, each of register networks 2208 and 2210 may include, but is not limited to, a bypass network that can bypass recently completed results that have not yet been written to the register file or forward them to new, related micro-ops. In at least one embodiment, register networks 2208 and 2210 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2208 may include, but is not limited to, two separate register files, one for low-order 32-bit data and another for high-order 32-bit data. In at least one embodiment, floating point register file / bypass network 2210 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64-bit to 128-bit wide.

[0409] In at least one embodiment, execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224 may execute instructions. In at least one embodiment, register networks 2208 and 2210 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2200 may include, but is not limited to, any number of execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224, and any combination thereof. In at least one embodiment, floating-point ALU 2222 and floating-point move unit 2224 may execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2222 may include, but is not limited to, a 64-bit by 64-bit floating-point divider for executing divide, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware may be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2216 and 2218. In at least one embodiment, fast ALUs 2216 and 2218 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2220 because slow ALU 2220 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by AGUs 2212 and 2214. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, floating point ALU 2222 and floating point move unit 2224 may be implemented to support a range of operands having bits of various widths, such as supporting 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0410] In at least one embodiment, the micro-operation schedulers 2202, 2204, and 2206 dispatch dependent operations before the parent load has completed execution. In at least one embodiment, since micro-operations can be speculatively scheduled and executed in the processor 2200, the processor 2200 may also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0411] In at least one embodiment, "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0412] In at least one embodiment, the processor 2200 or each core of the processor 2200 includes one or more prefetchers, one or more fetchers, one or more predecoders, one or more decoders for decoding data (e.g., instructions), one or more instruction queues for processing instructions (e.g., instructions corresponding to operations or API calls), one or more micro-operation (μOP) caches for storing μOPs, one or more micro-operation (μOP) queues, an in-order execution engine, one or more load buffers, one or more store buffers, one or more reorder buffers, one or more fill buffers, an out-of-order execution engine, one or more ports, one or more shift and / or shift units, one or more fused multiply-accumulate (FMA) units, one or more load and store units ("LSUs") for performing load / store operations corresponding to load / store data (e.g., instructions) to perform operations (e.g., execute APIs, API calls), one or more matrix multiply-accumulate (MMA) units, and / or one or more shuffle units for performing any functions further described with respect to the processor 2200. In at least one embodiment, processor 2200 may access, use, implement, or execute instructions corresponding to calling an API.

[0413] In at least one embodiment, the processor 2200 includes one or more Ultra Path Interconnects (UPI), for example, which are point-to-point processor interconnects; one or more PCIe; one or more accelerators for accelerating computations or operations; and / or one or more memory controllers. In at least one embodiment, the processor 2200 includes a shared last-level cache (LLC) coupled to one or more memory controllers, which enables shared memory access across processor cores.

[0414] In at least one embodiment, the processor 2200 or the core of the processor 2200 has a mesh structure in which the processor cores, on-chip caches, memory controllers, and I / O controllers are organized into rows and columns, with wires and switches connecting them at each intersection to allow turns. In at least one embodiment, the processor 2200 has one or more higher memory bandwidths (HMBs, e.g., HMBe) for storing data or caching data in, for example, double data rate 5 synchronous dynamic random access memory (DDR5 SDRAM). In at least one embodiment, one or more components of the processor 2200 are interconnected using a compute express link (CXL) interconnect. In at least one embodiment, the memory controller uses a "least recently used" (LRU) approach to determine what is stored in the cache. In at least one embodiment, the processor 2200 includes one or more PCIe (e.g., PCIe 5.0).

[0415] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, some or all of logic 615 may be incorporated into execution block 2211 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more ALUs shown in execution block 2211. Additionally, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALUs of execution block 2211 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0416] In at least one embodiment, the processor 2200 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0417] Figure 23A deep learning application processor 2300 is shown in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2300 uses instructions that, if executed by the deep learning application processor 2300, cause the deep learning application processor 2300 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2300 is an application-specific integrated circuit (ASIC). In at least one embodiment, as a result of executing one or more instructions, or both, the application processor 2300 performs a matrix multiplication operation or is "hardwired" into hardware. In at least one embodiment, the deep learning application processor 2300 includes, but is not limited to, processing clusters 2310(1)-2310(12), inter-chip links (“ICLs”) 2320(1)-2320(12), inter-chip controllers (“ICCs”) 2330(1)-2330(2), second generation high bandwidth memory (“HBM2”) 2340(1)-2340(4), memory controllers (“Mem Ctrlr”) 2342(1)-2342(4), high bandwidth memory physical layer (“HBM PHY”) 2344(1)-2344(4), a management controller central processing unit (“management controller CPU”) 2350, serial peripheral interface, inter-integrated circuit and general purpose input / output blocks (“SPI, I2C, etc.) 2 C, GPIO”) 2360, Peripheral Component Interconnect Express controller and direct memory access block (“PCIe controller and DMA”) 2370, and sixteen-lane Peripheral Component Interconnect Express port (“PCI Express x 16”) 2380.

[0418] In at least one embodiment, the processing cluster 2310 can perform deep learning operations, including inference or prediction operations based on weight parameters calculated based on one or more training techniques (including those described herein). In at least one embodiment, each processing cluster 2310 can include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2300 can include any number and type of processing clusters 2300. In at least one embodiment, the inter-chip link 2320 is bidirectional. In at least one embodiment, the inter-chip link 2320 and the inter-chip controller 2330 enable multiple deep learning application processors 2300 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2300 can include any number (including zero) and type of ICL 2320 and ICC 2330.

[0419] In at least one embodiment, HBM2 2340 provides a total of 32GB of memory. In at least one embodiment, HBM2 2340(i) is associated with both a memory controller 2342(i) and an HBM PHY 2344(i), where "i" is an arbitrary integer. In at least one embodiment, any number of HBM2 2340s can provide any type and total amount of high bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2342 and HBM PHYs 2344. In at least one embodiment, the SPI, I2C, and SPI interfaces can be replaced with any number and type of blocks that implement any number and type of communication standards in any technically feasible manner. 2 C, GPIO 2360, PCIe controller and DMA 2370 and / or PCIe 2380.

[0420] Logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the deep learning application processor 2300. In at least one embodiment, the deep learning application processor 2300 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2300. In at least one embodiment, the processor 2300 can be used to perform one or more of the neural network use cases described herein.

[0421] In at least one embodiment, the deep learning application processor 2300 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0422] Figure 24is a block diagram of a neuromorphic processor 2400 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2400 can receive one or more inputs from a source external to the neuromorphic processor 2400. In at least one embodiment, these inputs can be transmitted to one or more neurons 2402 within the neuromorphic processor 2400. In at least one embodiment, the neurons 2402 and their components can be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2400 can include, but is not limited to, thousands or millions of instances of neurons 2402, although any suitable number of neurons 2402 can be used. In at least one embodiment, each instance of a neuron 2402 can include a neuron input 2404 and a neuron output 2406. In at least one embodiment, a neuron 2402 can generate an output that can be transmitted to the inputs of other instances of the neuron 2402. For example, in at least one embodiment, the neuron input 2404 and the neuron output 2406 can be interconnected via a synapse 2408.

[0423] In at least one embodiment, the neurons 2402 and synapses 2408 can be interconnected so that the neuromorphic processor 2400 operates to process or analyze information received by the neuromorphic processor 2400. In at least one embodiment, the neuron 2402 can send an output pulse (or "fire" or "spike") when the input received through the neuron input 2404 exceeds a threshold. In at least one embodiment, the neuron 2402 can sum or integrate the signals received at the neuron input 2404. For example, in at least one embodiment, the neuron 2402 can be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 2402 can generate an output (or "fire") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, the leaky integrate-and-fire neuron can sum the signals received at the neuron input 2404 into a membrane potential and can also apply an attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron input 2404 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to fire). In at least one embodiment, neuron 2402 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2402 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2406 when the result of applying the transfer function to neuron input 2404 exceeds a threshold. In at least one embodiment, once neuron 2402 fires, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2402 may resume normal operation after a suitable period of time (or refractory period).

[0424] In at least one embodiment, neurons 2402 can be interconnected via synapses 2408. In at least one embodiment, synapses 2408 can be operable to transmit a signal from an output of a first neuron 2402 to an input of a second neuron 2402. In at least one embodiment, a neuron 2402 can transmit information across more than one instance of a synapse 2408. In at least one embodiment, one or more instances of a neuron output 2406 can be connected to an instance of a neuron input 2404 in the same neuron 2402 via an instance of a synapse 2408. In at least one embodiment, an instance of a neuron 2402 that generates an output to be transmitted across an instance of a synapse 2408 can be referred to as a "presynaptic neuron" with respect to an instance of a synapse 2408. In at least one embodiment, an instance of a neuron 2402 that receives an input transmitted across an instance of a synapse 2408 can be referred to as a "postsynaptic neuron" with respect to an instance of a synapse 2408. In at least one embodiment, with respect to individual instances of synapse 2408, because an instance of neuron 2402 can receive input from one or more instances of synapse 2408 and can also transmit output through one or more instances of synapse 2408, a single instance of neuron 2402 can be both a "pre-synaptic neuron" and a "post-synaptic neuron."

[0425] In at least one embodiment, neurons 2402 can be organized into one or more layers. In at least one embodiment, each instance of a neuron 2402 can have a neuron output 2406 that can fan out to one or more neuron inputs 2404 via one or more synapses 2408. In at least one embodiment, the neuron output 2406 of a neuron 2402 in a first layer 2410 can be connected to the neuron input 2404 of a neuron 2402 in a second layer 2412. In at least one embodiment, layers 2410 can be referred to as "feed-forward layers." In at least one embodiment, each instance of a neuron 2402 in an instance of the first layer 2410 can fan out to each instance of a neuron 2402 in a second layer 2412. In at least one embodiment, the first layer 2410 can be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of a neuron 2402 in an instance of the second layer 2412 can fan out to fewer than all instances of a neuron 2402 in a third layer 2414. In at least one embodiment, the second layer 2412 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, neurons 2402 in the second layer 2412 may fan out to neurons 2402 in multiple other layers, including to neurons 2402 also in the second layer 2412. In at least one embodiment, the second layer 2412 may be referred to as a "recurrent layer." In at least one embodiment, the neuromorphic processor 2400 may include, but is not limited to, any suitable combination of recurrent layers and feed-forward layers, including, but not limited to, sparsely connected feed-forward layers and fully connected feed-forward layers.

[0426] In at least one embodiment, the neuromorphic processor 2400 may include, but is not limited to, a reconfigurable interconnect architecture or a dedicated hardwired interconnect for connecting synapses 2408 to neurons 2402. In at least one embodiment, the neuromorphic processor 2400 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2402 as needed based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2408 may be connected to neurons 2402 using an interconnect architecture such as a network on a chip or utilizing dedicated connections. In at least one embodiment, the synaptic interconnect and its components may be implemented using circuitry or logic.

[0427] In at least one embodiment, the neuromorphic processor 2400 may be used to Figure 1-5 The neural network architecture described in

[15] is constructed.

[0428] Figure 252500 is a processing system according to at least one embodiment. In at least one embodiment, system 2500 includes one or more processors 2502 and one or more graphics processors 2508, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2502 or processor cores 2507. In at least one embodiment, system 2500 is a processing platform contained within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, one or more graphics processors 2508 include one or more graphics cores 1700.

[0429] In at least one embodiment, the system 2500 may include or be incorporated into a server-based gaming platform, a gaming console including a gaming and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, the system 2500 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2500 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2500 is a television or set-top box device having one or more processors 2502 and a graphical interface generated by one or more graphics processors 2508.

[0430] In at least one embodiment, each of one or more processors 2502 includes one or more processor cores 2507 for processing instructions, which, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2507 is configured to process a specific instruction sequence 2509. In at least one embodiment, the instruction sequence 2509 can promote complex instruction set computing (CISC), reduced instruction set computing (RISC), or the computing via very long instruction word (VLIW). In at least one embodiment, the processor cores 2507 can each process different instruction sequences 2509, which can include instructions that contribute to emulating other instruction sequences. In at least one embodiment, the processor cores 2507 can also include other processing devices, such as a digital signal processor (DSP).

[0431] In at least one embodiment, the processor 2502 includes a cache memory 2504. In at least one embodiment, the processor 2502 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2502. In at least one embodiment, the processor 2502 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 2507 using known cache coherence techniques. In at least one embodiment, the processor 2502 additionally includes a register file 2506, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, the register file 2506 may include general purpose registers or other registers.

[0432] In at least one embodiment, one or more processors 2502 are coupled to one or more interface buses 2510 to transmit communication signals, such as address, data, or control signals, between the processors 2502 and other components in the system 2500. In at least one embodiment, the interface bus 2510 can be a processor bus, such as a version of a direct media interface (DMI) bus. In at least one embodiment, the interface bus 2510 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the one or more processors 2502 include an integrated memory controller 2516 and a platform controller hub 2530. In at least one embodiment, the memory controller 2516 facilitates communication between memory devices and other components of the system 2500, while the platform controller hub (PCH) 2530 provides connections to I / O devices via a local I / O bus.

[0433] In at least one embodiment, memory device 2520 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance for use as processor memory. In at least one embodiment, memory device 2520 can operate as system memory for system 2500, storing data 2522 and instructions 2521 for use when one or more processors 2502 execute applications or processes. In at least one embodiment, memory controller 2516 is also coupled to an optional external graphics processor 2512, which can communicate with one or more graphics processors 2508 in processors 2502 to perform graphics and media operations. In at least one embodiment, display device 2511 can be connected to one or more processors 2502. In at least one embodiment, display device 2511 can include one or more internal display devices, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2511 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0434] In at least one embodiment, the platform controller hub 2530 enables peripheral devices to be connected to the memory device 2520 and the processor 2502 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2546, a network controller 2534, a firmware interface 2528, a wireless transceiver 2526, a touch sensor 2525, and a data storage device 2524 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2524 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the ...

Claims

1. A processor, comprising: One or more circuits for causing one or more portions of one or more neural networks to be selected based at least in part on one or more performance indicator masks associated with the one or more portions to generate the one or more neural networks.

2. The processor of claim 1 , wherein the one or more circuits further cause constructing a joint neural network comprising the joint set of candidate neural components, and Each of the one or more portions includes one or more candidate neural components selected from the union set of candidate neural components.

3. The processor of claim 2, wherein the one or more circuits further cause training of the joint neural network, and wherein the training comprises: randomly masking a subset of the weights of the joint neural network, calculating a training loss based at least in part on training outputs generated by the joint neural network having randomly masked weights, and Unmasked weights of the joint neural network are updated based on the training loss during at least one training iteration.

4. The processor of claim 1, wherein at least one of the one or more performance indicator masks is a multi-dimensional vector comprising a plurality of performance indicators of at least a portion of the neural network.

5. The processor of claim 4, wherein at least the network accuracy indicator of the plurality of performance indicators is updated during training based at least in part on a training loss calculated during a training iteration.

6. The processor of claim 4, wherein the one or more performance indicator masks associated with the one or more parts are updated during training by running the one or more parts with updated weights on a hardware simulator during training iterations.

7. The processor of claim 2, wherein the one or more portions of the one or more neural networks are selected based at least in part on the one or more performance indicator masks updated according to one or more target performance indicators during training of the joint neural network.

8. A system comprising: One or more processors configured to cause one or more portions of one or more neural networks to be selected based at least in part on one or more performance indicator masks associated with the one or more portions to generate the one or more neural networks.

9. The system of claim 8, wherein the one or more processors further cause construction of a joint neural network comprising the joint set of candidate neural components, and Each of the one or more portions includes one or more candidate neural components selected from the union set of candidate neural components.

10. The system of claim 9, wherein the one or more processors further cause training of the joint neural network, and wherein the training comprises: randomly masking a subset of the weights of the joint neural network, calculating a training loss based at least in part on training outputs generated by the joint neural network having randomly masked weights, and Unmasked weights of the joint neural network are updated based on the training loss during at least one training iteration.

11. The system of claim 8, wherein at least one of the one or more performance indicator masks is a multi-dimensional vector comprising a plurality of performance indicators of at least a portion of the neural network.

12. The system of claim 11, wherein at least the network accuracy metric of the plurality of performance metrics is updated during training based at least in part on a training loss calculated during a training iteration.

13. The system of claim 11, wherein the one or more performance indicator masks associated with the one or more parts are updated during training by running the one or more parts with updated weights on a hardware simulator during training iterations.

14. The system of claim 9, wherein the one or more portions of the one or more neural networks are selected based at least in part on the one or more performance indicator masks updated according to one or more target performance indicators during training of the joint neural network.

15. A machine-readable medium having a set of instructions stored thereon, which, when executed by one or more processors, cause the one or more processors to at least: cause one or more portions of one or more neural networks to be selected to generate one or more neural networks based at least in part on one or more performance indicator masks associated with the one or more portions.

16. The medium of claim 15, wherein the one or more processors are further caused to cause construction of a joint neural network comprising a joint set of candidate neural components, and Each of the one or more portions includes one or more candidate neural components selected from the union set of candidate neural components.

17. The medium of claim 16, wherein the one or more processors are further caused to cause training of the joint neural network, and wherein the training comprises: randomly masking a subset of the weights of the joint neural network, calculating a training loss based at least in part on training outputs generated by the joint neural network having randomly masked weights, and Unmasked weights of the joint neural network are updated based on the training loss during at least one training iteration.

18. The medium of claim 15, wherein at least one of the one or more performance indicator masks is a multi-dimensional vector comprising a plurality of performance indicators of at least a portion of a neural network.

19. The medium of claim 18, wherein at least a network accuracy metric of the plurality of performance metrics is updated during training based at least in part on a training loss calculated during a training iteration, and the one or more performance metric masks associated with the one or more parts are updated during training by running the one or more parts with updated weights on a hardware simulator during a training iteration.

20. The medium of claim 19, wherein the one or more portions of the one or more neural networks are selected based at least in part on the one or more performance indicator masks updated according to one or more target performance indicators during training of the joint neural network.

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